update header files
This commit is contained in:
hathach
File diff suppressed because it is too large
Load Diff
@@ -1,16 +1,16 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm4_simd.h
|
||||
* @brief CMSIS Cortex-M4 SIMD Header File
|
||||
* @version V2.10
|
||||
* @date 19. July 2011
|
||||
* @version V3.01
|
||||
* @date 06. March 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2010-2011 ARM Limited. All rights reserved.
|
||||
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
@@ -23,7 +23,7 @@
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM4_SIMD_H
|
||||
#define __CORE_CM4_SIMD_H
|
||||
@@ -43,7 +43,7 @@
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/
|
||||
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
@@ -118,70 +118,18 @@
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/
|
||||
/* intrinsic __SADD8 see intrinsics.h */
|
||||
/* intrinsic __QADD8 see intrinsics.h */
|
||||
/* intrinsic __SHADD8 see intrinsics.h */
|
||||
/* intrinsic __UADD8 see intrinsics.h */
|
||||
/* intrinsic __UQADD8 see intrinsics.h */
|
||||
/* intrinsic __UHADD8 see intrinsics.h */
|
||||
/* intrinsic __SSUB8 see intrinsics.h */
|
||||
/* intrinsic __QSUB8 see intrinsics.h */
|
||||
/* intrinsic __SHSUB8 see intrinsics.h */
|
||||
/* intrinsic __USUB8 see intrinsics.h */
|
||||
/* intrinsic __UQSUB8 see intrinsics.h */
|
||||
/* intrinsic __UHSUB8 see intrinsics.h */
|
||||
/* intrinsic __SADD16 see intrinsics.h */
|
||||
/* intrinsic __QADD16 see intrinsics.h */
|
||||
/* intrinsic __SHADD16 see intrinsics.h */
|
||||
/* intrinsic __UADD16 see intrinsics.h */
|
||||
/* intrinsic __UQADD16 see intrinsics.h */
|
||||
/* intrinsic __UHADD16 see intrinsics.h */
|
||||
/* intrinsic __SSUB16 see intrinsics.h */
|
||||
/* intrinsic __QSUB16 see intrinsics.h */
|
||||
/* intrinsic __SHSUB16 see intrinsics.h */
|
||||
/* intrinsic __USUB16 see intrinsics.h */
|
||||
/* intrinsic __UQSUB16 see intrinsics.h */
|
||||
/* intrinsic __UHSUB16 see intrinsics.h */
|
||||
/* intrinsic __SASX see intrinsics.h */
|
||||
/* intrinsic __QASX see intrinsics.h */
|
||||
/* intrinsic __SHASX see intrinsics.h */
|
||||
/* intrinsic __UASX see intrinsics.h */
|
||||
/* intrinsic __UQASX see intrinsics.h */
|
||||
/* intrinsic __UHASX see intrinsics.h */
|
||||
/* intrinsic __SSAX see intrinsics.h */
|
||||
/* intrinsic __QSAX see intrinsics.h */
|
||||
/* intrinsic __SHSAX see intrinsics.h */
|
||||
/* intrinsic __USAX see intrinsics.h */
|
||||
/* intrinsic __UQSAX see intrinsics.h */
|
||||
/* intrinsic __UHSAX see intrinsics.h */
|
||||
/* intrinsic __USAD8 see intrinsics.h */
|
||||
/* intrinsic __USADA8 see intrinsics.h */
|
||||
/* intrinsic __SSAT16 see intrinsics.h */
|
||||
/* intrinsic __USAT16 see intrinsics.h */
|
||||
/* intrinsic __UXTB16 see intrinsics.h */
|
||||
/* intrinsic __SXTB16 see intrinsics.h */
|
||||
/* intrinsic __UXTAB16 see intrinsics.h */
|
||||
/* intrinsic __SXTAB16 see intrinsics.h */
|
||||
/* intrinsic __SMUAD see intrinsics.h */
|
||||
/* intrinsic __SMUADX see intrinsics.h */
|
||||
/* intrinsic __SMLAD see intrinsics.h */
|
||||
/* intrinsic __SMLADX see intrinsics.h */
|
||||
/* intrinsic __SMLALD see intrinsics.h */
|
||||
/* intrinsic __SMLALDX see intrinsics.h */
|
||||
/* intrinsic __SMUSD see intrinsics.h */
|
||||
/* intrinsic __SMUSDX see intrinsics.h */
|
||||
/* intrinsic __SMLSD see intrinsics.h */
|
||||
/* intrinsic __SMLSDX see intrinsics.h */
|
||||
/* intrinsic __SMLSLD see intrinsics.h */
|
||||
/* intrinsic __SMLSLDX see intrinsics.h */
|
||||
/* intrinsic __SEL see intrinsics.h */
|
||||
/* intrinsic __QADD see intrinsics.h */
|
||||
/* intrinsic __QSUB see intrinsics.h */
|
||||
/* intrinsic __PKHBT see intrinsics.h */
|
||||
/* intrinsic __PKHTB see intrinsics.h */
|
||||
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
|
||||
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
|
||||
@@ -191,308 +139,308 @@
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
@@ -503,7 +451,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op
|
||||
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
#define __USAT16(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
@@ -511,66 +459,66 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op
|
||||
__RES; \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
@@ -589,34 +537,34 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t o
|
||||
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
@@ -635,15 +583,15 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t o
|
||||
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
@@ -651,10 +599,10 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1,
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
@@ -671,7 +619,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1,
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
if (ARG3 == 0) \
|
||||
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
||||
else \
|
||||
else \
|
||||
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
@@ -1,16 +1,16 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V2.10
|
||||
* @date 26. July 2011
|
||||
* @version V3.01
|
||||
* @date 06. March 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
@@ -26,7 +26,7 @@
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
@@ -47,7 +47,7 @@
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_CONTROL(void)
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
@@ -60,20 +60,20 @@ static __INLINE uint32_t __get_CONTROL(void)
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
static __INLINE void __set_CONTROL(uint32_t control)
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get ISPR Register
|
||||
/** \brief Get IPSR Register
|
||||
|
||||
This function returns the content of the ISPR Register.
|
||||
This function returns the content of the IPSR Register.
|
||||
|
||||
\return ISPR Register value
|
||||
\return IPSR Register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_IPSR(void)
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
@@ -86,7 +86,7 @@ static __INLINE uint32_t __get_IPSR(void)
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_APSR(void)
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
@@ -99,7 +99,7 @@ static __INLINE uint32_t __get_APSR(void)
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_xPSR(void)
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
@@ -112,7 +112,7 @@ static __INLINE uint32_t __get_xPSR(void)
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_PSP(void)
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
@@ -125,7 +125,7 @@ static __INLINE uint32_t __get_PSP(void)
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
static __INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
@@ -138,7 +138,7 @@ static __INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_MSP(void)
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
@@ -151,7 +151,7 @@ static __INLINE uint32_t __get_MSP(void)
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
static __INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
@@ -164,7 +164,7 @@ static __INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
static __INLINE uint32_t __get_PRIMASK(void)
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
@@ -177,12 +177,12 @@ static __INLINE uint32_t __get_PRIMASK(void)
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
static __INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
@@ -208,7 +208,7 @@ static __INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_BASEPRI(void)
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
@@ -221,12 +221,12 @@ static __INLINE uint32_t __get_BASEPRI(void)
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
static __INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xff);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
@@ -234,7 +234,7 @@ static __INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_FAULTMASK(void)
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
@@ -247,7 +247,7 @@ static __INLINE uint32_t __get_FAULTMASK(void)
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1);
|
||||
@@ -264,7 +264,7 @@ static __INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_FPSCR(void)
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
@@ -281,7 +281,7 @@ static __INLINE uint32_t __get_FPSCR(void)
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
static __INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
@@ -297,6 +297,13 @@ static __INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
@@ -305,7 +312,7 @@ static __INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie i");
|
||||
}
|
||||
@@ -316,7 +323,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
|
||||
This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid i");
|
||||
}
|
||||
@@ -328,7 +335,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
@@ -343,19 +350,19 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get ISPR Register
|
||||
/** \brief Get IPSR Register
|
||||
|
||||
This function returns the content of the ISPR Register.
|
||||
This function returns the content of the IPSR Register.
|
||||
|
||||
\return ISPR Register value
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
@@ -370,7 +377,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
@@ -385,7 +392,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
@@ -400,14 +407,14 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
@@ -415,7 +422,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
|
||||
}
|
||||
@@ -427,14 +434,14 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOf
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
@@ -442,7 +449,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
|
||||
}
|
||||
@@ -454,7 +461,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOf
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
@@ -469,11 +476,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
|
||||
}
|
||||
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
@@ -482,7 +489,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t p
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f");
|
||||
}
|
||||
@@ -493,7 +500,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f");
|
||||
}
|
||||
@@ -505,10 +512,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
@@ -520,7 +527,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
|
||||
}
|
||||
@@ -532,10 +539,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t v
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
@@ -547,7 +554,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
|
||||
}
|
||||
@@ -563,7 +570,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
uint32_t result;
|
||||
@@ -582,7 +589,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
|
||||
|
||||
@@ -1,16 +1,16 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V2.10
|
||||
* @date 19. July 2011
|
||||
* @version V3.01
|
||||
* @date 06. March 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
@@ -71,8 +71,8 @@
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
@@ -80,7 +80,7 @@
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
@@ -88,7 +88,7 @@
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
@@ -111,7 +111,7 @@
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
static __INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
@@ -125,13 +125,24 @@ static __INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
static __INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
@@ -247,7 +258,7 @@ static __INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
#define __CLZ __clz
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
@@ -259,6 +270,12 @@ static __INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
@@ -266,7 +283,7 @@ static __INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
|
||||
{
|
||||
__ASM volatile ("nop");
|
||||
}
|
||||
@@ -277,7 +294,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
__ASM volatile ("wfi");
|
||||
}
|
||||
@@ -288,7 +305,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
__ASM volatile ("wfe");
|
||||
}
|
||||
@@ -298,7 +315,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
|
||||
{
|
||||
__ASM volatile ("sev");
|
||||
}
|
||||
@@ -306,11 +323,11 @@ __attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
|
||||
{
|
||||
__ASM volatile ("isb");
|
||||
}
|
||||
@@ -318,10 +335,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
|
||||
{
|
||||
__ASM volatile ("dsb");
|
||||
}
|
||||
@@ -329,10 +346,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
|
||||
{
|
||||
__ASM volatile ("dmb");
|
||||
}
|
||||
@@ -345,10 +362,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
@@ -361,10 +378,10 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
@@ -377,15 +394,31 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t val
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
|
||||
__ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
|
||||
return(op1);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
@@ -395,10 +428,10 @@ __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
@@ -411,10 +444,10 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t valu
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
@@ -427,10 +460,10 @@ __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uin
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
uint16_t result;
|
||||
|
||||
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
@@ -443,10 +476,10 @@ __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile ui
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
@@ -461,11 +494,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile ui
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
|
||||
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
@@ -479,11 +512,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t val
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
|
||||
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
@@ -497,11 +530,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t va
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
|
||||
__ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
@@ -511,7 +544,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t va
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
|
||||
{
|
||||
__ASM volatile ("clrex");
|
||||
}
|
||||
@@ -556,10 +589,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
|
||||
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
@@ -22,7 +22,7 @@
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors’
|
||||
* documentation is hereby granted, under NXP Semiconductors�
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
@@ -41,14 +41,28 @@
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "lpc43xx_uart.h"
|
||||
|
||||
#define KEIL_BOARD 1
|
||||
#define HITEX_BOARD 2
|
||||
|
||||
#ifndef PLATFORM
|
||||
#define PLATFORM KEIL_BOARD
|
||||
#endif
|
||||
|
||||
#if (PLATFORM == HITEX_BOARD)
|
||||
#define USED_UART_DEBUG_PORT 0
|
||||
#endif
|
||||
|
||||
#if (PLATFORM == KEIL_BOARD)
|
||||
#define USED_UART_DEBUG_PORT 3
|
||||
#endif
|
||||
|
||||
#define USED_UART_DEBUG_PORT 1
|
||||
|
||||
#if (USED_UART_DEBUG_PORT==0)
|
||||
#define DEBUG_UART_PORT LPC_UART0
|
||||
#define DEBUG_UART_PORT LPC_USART0
|
||||
#elif (USED_UART_DEBUG_PORT==1)
|
||||
#define DEBUG_UART_PORT LPC_UART1
|
||||
#elif (USED_UART_DEBUG_PORT==3)
|
||||
#define DEBUG_UART_PORT LPC_USART3
|
||||
#endif
|
||||
|
||||
#define _DBG(x) _db_msg((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
|
||||
|
||||
@@ -71,12 +71,29 @@ void EMCFlashInit(void);
|
||||
#define EMC_NOP (3)
|
||||
|
||||
/* The Hitex LPC18xx Evaluation board contains a 64Mb SDRAM with a 16-bit data bus */
|
||||
#if(PLATFORM == HITEX_BOARD)
|
||||
|
||||
#define SDRAM_SIZE_BYTES (1024UL * 1024UL * 8UL)
|
||||
#define SDRAM_WIDTH EMC_SDRAM_WIDTH_16_BITS
|
||||
#define SDRAM_SIZE_MBITS EMC_SDRAM_SIZE_64_MBITS
|
||||
#define SDRAM_DATA_BUS_BITS EMC_SDRAM_DATA_BUS_16_BITS
|
||||
#define SDRAM_COL_ADDR_BITS 8
|
||||
#define CLK0_DELAY 6
|
||||
|
||||
#endif
|
||||
|
||||
#if(PLATFORM == KEIL_BOARD)
|
||||
// TODO adapt these for the MCB4357 !!!!
|
||||
#define SDRAM_SIZE_BYTES (1024UL * 1024UL * 8UL)
|
||||
#define SDRAM_WIDTH EMC_SDRAM_WIDTH_16_BITS
|
||||
#define SDRAM_SIZE_MBITS EMC_SDRAM_SIZE_64_MBITS
|
||||
#define SDRAM_DATA_BUS_BITS EMC_SDRAM_DATA_BUS_16_BITS
|
||||
#define SDRAM_COL_ADDR_BITS 8
|
||||
|
||||
#endif
|
||||
|
||||
// CLK0_DELAY needs to be tuned depending on the external memory bus speed.
|
||||
// For operation at 102 MHz it should be 6 or 7
|
||||
#define CLK0_DELAY 7
|
||||
|
||||
void vEMC_InitSRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits);
|
||||
void emc_WaitUS(volatile uint32_t us);
|
||||
|
||||
@@ -117,6 +117,10 @@
|
||||
/* I2S ------------------------------- */
|
||||
#define _I2S
|
||||
|
||||
/* SDIO ------------------------------ */
|
||||
#define _SDIF
|
||||
#define _SDMMC
|
||||
|
||||
/* USB device ------------------------------- */
|
||||
#define _USBDEV
|
||||
#define _USB_DMA
|
||||
|
||||
@@ -54,18 +54,48 @@ extern "C"
|
||||
/** Pin offset definition */
|
||||
#define PIN_OFFSET 0x04
|
||||
|
||||
/* Pin modes */
|
||||
#define MD_PUP (0x0<<3)
|
||||
#define MD_BUK (0x1<<3)
|
||||
#define MD_PLN (0x2<<3)
|
||||
#define MD_PDN (0x3<<3)
|
||||
#define MD_EHS (0x1<<5)
|
||||
#define MD_EZI (0x1<<6)
|
||||
#define MD_ZI (0x1<<7)
|
||||
#define MD_EHD0 (0x1<<8)
|
||||
#define MD_EHD1 (0x1<<8)
|
||||
/* Pin mode defines, following partly a definition from older chip architectures */
|
||||
#define MD_PUP (0x0 << 3)
|
||||
#define MD_BUK (0x1 << 3)
|
||||
#define MD_PLN (0x2 << 3)
|
||||
#define MD_PDN (0x3 << 3)
|
||||
#define MD_EHS (0x1 << 5)
|
||||
#define MD_EZI (0x1 << 6)
|
||||
#define MD_ZI (0x1 << 7)
|
||||
#define MD_EHD0 (0x1 << 8)
|
||||
#define MD_EHD1 (0x1 << 9)
|
||||
#define MD_EHD2 (0x3 << 8)
|
||||
#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
|
||||
// 0xF0
|
||||
|
||||
|
||||
/* Pin mode defines, more in line with the definitions in the LPC1800/4300 user manual */
|
||||
/* Defines for SFSPx_y pin configuration registers */
|
||||
#define PDN_ENABLE (1 << 3) // Pull-down enable
|
||||
#define PDN_DISABLE (0 << 3) // Pull-down disable
|
||||
#define PUP_ENABLE (0 << 4) // Pull-up enable
|
||||
#define PUP_DISABLE (1 << 4) // Pull-up disable
|
||||
#define SLEWRATE_SLOW (0 << 5) // Slew rate for low noise with medium speed
|
||||
#define SLEWRATE_FAST (1 << 5) // Slew rate for medium noise with fast speed
|
||||
#define INBUF_ENABLE (1 << 6) // Input buffer
|
||||
#define INBUF_DISABLE (0 << 6) // Input buffer
|
||||
#define FILTER_ENABLE (0 << 7) // Glitch filter (for signals below 30MHz)
|
||||
#define FILTER_DISABLE (1 << 7) // No glitch filter (for signals above 30MHz)
|
||||
#define DRIVE_8MA (1 << 8) // Drive strength of 8mA
|
||||
#define DRIVE_14MA (1 << 9) // Drive strength of 14mA
|
||||
#define DRIVE_20MA (3 << 8) // Drive strength of 20mA
|
||||
|
||||
|
||||
/* Configuration examples for various I/O pins */
|
||||
#define EMC_IO (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
#define LCD_PINCONFIG (PUP_DISABLE | PDN_DISABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
#define CLK_IN (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
#define CLK_OUT (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
#define GPIO_PUP (PUP_ENABLE | PDN_DISABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
|
||||
#define GPIO_PDN (PUP_DISABLE | PDN_ENABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
|
||||
#define GPIO_NOPULL (PUP_DISABLE | PDN_DISABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
|
||||
#define UART_RX_TX (PUP_DISABLE | PDN_ENABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
|
||||
#define SSP_IO (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
|
||||
|
||||
/* Pin function */
|
||||
#define FUNC0 0x0 /** Function 0 */
|
||||
|
||||
@@ -0,0 +1,301 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc43xx_sdif.h 2012-Aug-15
|
||||
*//**
|
||||
* @file lpc43xx_sdif.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for SDIO firmware library on LPC43xx
|
||||
* @version 1.0
|
||||
* @date 15. Aug. 2012
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup SDIF SDIF (SD Card Interface)
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
#ifndef LPC43XX_SDIF_H
|
||||
#define LPC43XX_SDIF_H
|
||||
|
||||
#include "LPC43xx.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup SDIF_Private_Macros SDIF Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** \brief SDIO chained DMA descriptor
|
||||
*/
|
||||
typedef struct {
|
||||
volatile uint32_t des0; /*!< Control and status */
|
||||
volatile uint32_t des1; /*!< Buffer size(s) */
|
||||
volatile uint32_t des2; /*!< Buffer address pointer 1 */
|
||||
volatile uint32_t des3; /*!< Buffer address pointer 2 */
|
||||
} LPC_SDMMC_DMA_Type;
|
||||
|
||||
/** \brief SDIO DMA descriptor control (des0) register defines
|
||||
*/
|
||||
#define MCI_DMADES0_OWN (1UL << 31) /*!< DMA owns descriptor bit */
|
||||
#define MCI_DMADES0_CES (1 << 30) /*!< Card Error Summary bit */
|
||||
#define MCI_DMADES0_ER (1 << 5) /*!< End of descriptopr ring bit */
|
||||
#define MCI_DMADES0_CH (1 << 4) /*!< Second address chained bit */
|
||||
#define MCI_DMADES0_FS (1 << 3) /*!< First descriptor bit */
|
||||
#define MCI_DMADES0_LD (1 << 2) /*!< Last descriptor bit */
|
||||
#define MCI_DMADES0_DIC (1 << 1) /*!< Disable interrupt on completion bit */
|
||||
|
||||
/** \brief SDIO DMA descriptor size (des1) register defines
|
||||
*/
|
||||
#define MCI_DMADES1_BS1(x) (x) /*!< Size of buffer 1 */
|
||||
#define MCI_DMADES1_BS2(x) ((x) << 13) /*!< Size of buffer 2 */
|
||||
#define MCI_DMADES1_MAXTR 4096 /*!< Max transfer size per buffer */
|
||||
|
||||
|
||||
/** \brief SDIO control register defines
|
||||
*/
|
||||
#define MCI_CTRL_USE_INT_DMAC (1 << 25) /*!< Use internal DMA */
|
||||
#define MCI_CTRL_CARDV_MASK (0x7 << 16) /*!< SD_VOLT[2:0} pins output state mask */
|
||||
#define MCI_CTRL_CEATA_INT_EN (1 << 11) /*!< Enable CE-ATA interrupts */
|
||||
#define MCI_CTRL_SEND_AS_CCSD (1 << 10) /*!< Send auto-stop */
|
||||
#define MCI_CTRL_SEND_CCSD (1 << 9) /*!< Send CCSD */
|
||||
#define MCI_CTRL_ABRT_READ_DATA (1 << 8) /*!< Abort read data */
|
||||
#define MCI_CTRL_SEND_IRQ_RESP (1 << 7) /*!< Send auto-IRQ response */
|
||||
#define MCI_CTRL_READ_WAIT (1 << 6) /*!< Assert read-wait for SDIO */
|
||||
#define MCI_CTRL_INT_ENABLE (1 << 4) /*!< Global interrupt enable */
|
||||
#define MCI_CTRL_DMA_RESET (1 << 2) /*!< Reset internal DMA */
|
||||
#define MCI_CTRL_FIFO_RESET (1 << 1) /*!< Reset data FIFO pointers */
|
||||
#define MCI_CTRL_RESET (1 << 0) /*!< Reset controller */
|
||||
|
||||
/** \brief SDIO Power Enable register defines
|
||||
*/
|
||||
#define MCI_POWER_ENABLE 0x1 /*!< Enable slot power signal (SD_POW) */
|
||||
|
||||
/** \brief SDIO Clock divider register defines
|
||||
*/
|
||||
#define MCI_CLOCK_DIVIDER(dn, d2) ((d2) << ((dn) * 8)) /*!< Set cklock divider */
|
||||
|
||||
/** \brief SDIO Clock source register defines
|
||||
*/
|
||||
#define MCI_CLKSRC_CLKDIV0 0
|
||||
#define MCI_CLKSRC_CLKDIV1 1
|
||||
#define MCI_CLKSRC_CLKDIV2 2
|
||||
#define MCI_CLKSRC_CLKDIV3 3
|
||||
#define MCI_CLK_SOURCE(clksrc) (clksrc) /*!< Set cklock divider source */
|
||||
|
||||
/** \brief SDIO Clock Enable register defines
|
||||
*/
|
||||
#define MCI_CLKEN_LOW_PWR (1 << 16) /*!< Enable clock idle for slot */
|
||||
#define MCI_CLKEN_ENABLE (1 << 0) /*!< Enable slot clock */
|
||||
|
||||
/** \brief SDIO time-out register defines
|
||||
*/
|
||||
#define MCI_TMOUT_DATA(clks) ((clks) << 8) /*!< Data timeout clocks */
|
||||
#define MCI_TMOUT_DATA_MSK 0xFFFFFF00
|
||||
#define MCI_TMOUT_RESP(clks) ((clks) & 0xFF) /*!< Response timeout clocks */
|
||||
#define MCI_TMOUT_RESP_MSK 0xFF
|
||||
|
||||
/** \brief SDIO card-type register defines
|
||||
*/
|
||||
#define MCI_CTYPE_8BIT (1 << 16) /*!< Enable 4-bit mode */
|
||||
#define MCI_CTYPE_4BIT (1 << 0) /*!< Enable 8-bit mode */
|
||||
|
||||
/** \brief SDIO Interrupt status & mask register defines
|
||||
*/
|
||||
#define MCI_INT_SDIO (1 << 16) /*!< SDIO interrupt */
|
||||
#define MCI_INT_EBE (1 << 15) /*!< End-bit error */
|
||||
#define MCI_INT_ACD (1 << 14) /*!< Auto command done */
|
||||
#define MCI_INT_SBE (1 << 13) /*!< Start bit error */
|
||||
#define MCI_INT_HLE (1 << 12) /*!< Hardware locked error */
|
||||
#define MCI_INT_FRUN (1 << 11) /*!< FIFO overrun/underrun error */
|
||||
#define MCI_INT_HTO (1 << 10) /*!< Host data starvation error */
|
||||
#define MCI_INT_DTO (1 << 9) /*!< Data timeout error */
|
||||
#define MCI_INT_RTO (1 << 8) /*!< Response timeout error */
|
||||
#define MCI_INT_DCRC (1 << 7) /*!< Data CRC error */
|
||||
#define MCI_INT_RCRC (1 << 6) /*!< Response CRC error */
|
||||
#define MCI_INT_RXDR (1 << 5) /*!< RX data ready */
|
||||
#define MCI_INT_TXDR (1 << 4) /*!< TX data needed */
|
||||
#define MCI_INT_DATA_OVER (1 << 3) /*!< Data transfer over */
|
||||
#define MCI_INT_CMD_DONE (1 << 2) /*!< Command done */
|
||||
#define MCI_INT_RESP_ERR (1 << 1) /*!< Command response error */
|
||||
#define MCI_INT_CD (1 << 0) /*!< Card detect */
|
||||
|
||||
/** \brief SDIO Command register defines
|
||||
*/
|
||||
#define MCI_CMD_START (1UL << 31) /*!< Start command */
|
||||
#define MCI_CMD_VOLT_SWITCH (1 << 28) /*!< Voltage switch bit */
|
||||
#define MCI_CMD_BOOT_MODE (1 << 27) /*!< Boot mode */
|
||||
#define MCI_CMD_DISABLE_BOOT (1 << 26) /*!< Disable boot */
|
||||
#define MCI_CMD_EXPECT_BOOT_ACK (1 << 25) /*!< Expect boot ack */
|
||||
#define MCI_CMD_ENABLE_BOOT (1 << 24) /*!< Enable boot */
|
||||
#define MCI_CMD_CCS_EXP (1 << 23) /*!< CCS expected */
|
||||
#define MCI_CMD_CEATA_RD (1 << 22) /*!< CE-ATA read in progress */
|
||||
#define MCI_CMD_UPD_CLK (1 << 21) /*!< Update clock register only */
|
||||
#define MCI_CMD_INIT (1 << 15) /*!< Send init sequence */
|
||||
#define MCI_CMD_STOP (1 << 14) /*!< Stop/abort command */
|
||||
#define MCI_CMD_PRV_DAT_WAIT (1 << 13) /*!< Wait before send */
|
||||
#define MCI_CMD_SEND_STOP (1 << 12) /*!< Send auto-stop */
|
||||
#define MCI_CMD_STRM_MODE (1 << 11) /*!< Stream transfer mode */
|
||||
#define MCI_CMD_DAT_WR (1 << 10) /*!< Read(0)/Write(1) selection */
|
||||
#define MCI_CMD_DAT_EXP (1 << 9) /*!< Data expected */
|
||||
#define MCI_CMD_RESP_CRC (1 << 8) /*!< Check response CRC */
|
||||
#define MCI_CMD_RESP_LONG (1 << 7) /*!< Response length */
|
||||
#define MCI_CMD_RESP_EXP (1 << 6) /*!< Response expected */
|
||||
#define MCI_CMD_INDX(n) ((n) & 0x1F)
|
||||
|
||||
/** \brief SDIO status register definess
|
||||
*/
|
||||
#define MCI_STS_GET_FCNT(x) (((x) >> 17) & 0x1FF)
|
||||
|
||||
/** \brief SDIO FIFO threshold defines
|
||||
*/
|
||||
#define MCI_FIFOTH_TX_WM(x) ((x) & 0xFFF)
|
||||
#define MCI_FIFOTH_RX_WM(x) (((x) & 0xFFF) << 16)
|
||||
#define MCI_FIFOTH_DMA_MTS_1 (0UL << 28)
|
||||
#define MCI_FIFOTH_DMA_MTS_4 (1UL << 28)
|
||||
#define MCI_FIFOTH_DMA_MTS_8 (2UL << 28)
|
||||
#define MCI_FIFOTH_DMA_MTS_16 (3UL << 28)
|
||||
#define MCI_FIFOTH_DMA_MTS_32 (4UL << 28)
|
||||
#define MCI_FIFOTH_DMA_MTS_64 (5UL << 28)
|
||||
#define MCI_FIFOTH_DMA_MTS_128 (6UL << 28)
|
||||
#define MCI_FIFOTH_DMA_MTS_256 (7UL << 28)
|
||||
|
||||
/** \brief Bus mode register defines
|
||||
*/
|
||||
#define MCI_BMOD_PBL1 (0 << 8) /*!< Burst length = 1 */
|
||||
#define MCI_BMOD_PBL4 (1 << 8) /*!< Burst length = 4 */
|
||||
#define MCI_BMOD_PBL8 (2 << 8) /*!< Burst length = 8 */
|
||||
#define MCI_BMOD_PBL16 (3 << 8) /*!< Burst length = 16 */
|
||||
#define MCI_BMOD_PBL32 (4 << 8) /*!< Burst length = 32 */
|
||||
#define MCI_BMOD_PBL64 (5 << 8) /*!< Burst length = 64 */
|
||||
#define MCI_BMOD_PBL128 (6 << 8) /*!< Burst length = 128 */
|
||||
#define MCI_BMOD_PBL256 (7 << 8) /*!< Burst length = 256 */
|
||||
#define MCI_BMOD_DE (1 << 7) /*!< Enable internal DMAC */
|
||||
#define MCI_BMOD_DSL(len) ((len) << 2) /*!< Descriptor skip length */
|
||||
#define MCI_BMOD_FB (1 << 1) /*!< Fixed bursts */
|
||||
#define MCI_BMOD_SWR (1 << 0) /*!< Software reset of internal registers */
|
||||
|
||||
/** \brief Commonly used definitions
|
||||
*/
|
||||
#define SD_FIFO_SZ 32 /*!< Size of SDIO FIFOs (32-bit wide) */
|
||||
|
||||
/***********************************************************************
|
||||
* MCI device structure and it defines
|
||||
**********************************************************************/
|
||||
|
||||
/* Function prototype for SD interface IRQ callback */
|
||||
typedef uint32_t (*MCI_IRQ_CB_FUNC_T)(uint32_t);
|
||||
|
||||
/* Function prototype for SD detect and write protect status check */
|
||||
typedef int32_t (*PSCHECK_FUNC_T) (void);
|
||||
|
||||
/* Function prototype for SD slot power enable or slot reset */
|
||||
typedef void (*PS_POWER_FUNC_T) (int32_t enable);
|
||||
|
||||
/* Card specific setup data */
|
||||
struct _mci_card_struct
|
||||
{
|
||||
uint32_t response[4]; /*!< Most recent response */
|
||||
uint32_t cid[4]; /*!< CID of acquired card */
|
||||
uint32_t csd[4]; /*!< CSD of acquired card */
|
||||
uint32_t ext_csd[512 / 4];
|
||||
uint32_t card_type;
|
||||
uint32_t rca; /*!< Relative address assigned to card */
|
||||
uint32_t speed;
|
||||
uint32_t block_len;
|
||||
uint32_t device_size;
|
||||
uint32_t blocknr;
|
||||
PSCHECK_FUNC_T sdck_det;
|
||||
PSCHECK_FUNC_T sdck_wp;
|
||||
PS_POWER_FUNC_T sd_setpow;
|
||||
PS_POWER_FUNC_T sd_setrst;
|
||||
};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup SDIO_Public_Functions SDIO Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Setup DMA descriptors */
|
||||
void sdif_dma_setup(uint32_t addr, uint32_t size);
|
||||
|
||||
/* Send a command on the SD bus */
|
||||
int32_t sdif_send_cmd(uint32_t cmd, uint32_t arg);
|
||||
|
||||
/* Read the response from the last command */
|
||||
void sdif_get_response(uint32_t *resp);
|
||||
|
||||
/* Sets the SD bus clock speed */
|
||||
void sdif_set_clock(uint32_t speed);
|
||||
|
||||
/* Detect if an SD card is inserted
|
||||
(uses SD_CD pin, returns 0 on card detect) */
|
||||
int32_t sdif_card_ndetect(void);
|
||||
|
||||
/* Detect if write protect is enabled
|
||||
(uses SD_WP pin, returns 1 if card is write protected) */
|
||||
int32_t sdif_card_wp_on(void);
|
||||
|
||||
/* Enable or disable slot power, !0 = enable slot power
|
||||
(Uses SD_POW pin, set to high or low based on enable parameter state) */
|
||||
void sdif_power_onoff(int32_t enable);
|
||||
|
||||
/* Reset card in slot, must manually de-assert reset after assertion
|
||||
(Uses SD_RST pin, set per reset parameter state) */
|
||||
void sdif_reset(int32_t reset);
|
||||
|
||||
/* Set block size for transfer */
|
||||
void sdif_set_blksize(uint32_t bytes);
|
||||
|
||||
/* Enter or exit low power mode. */
|
||||
void sdif_set_lowpower_mode(int32_t lpmode);
|
||||
|
||||
/* Initialize the SD controller */
|
||||
void sdif_init(uint32_t sdio_clock, MCI_IRQ_CB_FUNC_T irq_callback);
|
||||
|
||||
/* Close the SD controller */
|
||||
void sdif_deinit(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end LPC43XX_SDIF_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@@ -0,0 +1,124 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc43xx_sdmmc.h 2012-Aug-15
|
||||
*//**
|
||||
* @file lpc43xx_sdmmc.h
|
||||
* @brief SD/MMC card access and data driver
|
||||
* @version 1.0
|
||||
* @date 15. Aug. 2012
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup SDMMC SDMMC (SDMMC Card Interface)
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
#ifndef LPC43XX_SDMMC_H
|
||||
#define LPC43XX_SDMMC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup SDMMC_Private_Macros SDMMC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** \brief card type defines
|
||||
*/
|
||||
#define CARD_TYPE_SD (1 << 0)
|
||||
#define CARD_TYPE_4BIT (1 << 1)
|
||||
#define CARD_TYPE_8BIT (1 << 2)
|
||||
#define CARD_TYPE_HC (OCR_HC_CCS) /*!< high capacity card > 2GB */
|
||||
|
||||
#define MMC_SECTOR_SIZE 512
|
||||
|
||||
/** \brief Setup options for the SDIO driver
|
||||
*/
|
||||
#define US_TIMEOUT 1000000 /*!< give 1 atleast 1 sec for the card to respond */
|
||||
#define MS_ACQUIRE_DELAY (10) /*!< inter-command acquire oper condition delay in msec*/
|
||||
#define INIT_OP_RETRIES 50 /*!< initial OP_COND retries */
|
||||
#define SET_OP_RETRIES 1000 /*!< set OP_COND retries */
|
||||
#define SDIO_BUS_WIDTH 4 /*!< Max bus width supported */
|
||||
#define SD_MMC_ENUM_CLOCK 400000 /*!< Typical enumeration clock rate */
|
||||
#define MMC_MAX_CLOCK 20000000 /*!< Max MMC clock rate */
|
||||
#define MMC_LOW_BUS_MAX_CLOCK 26000000 /*!< Type 0 MMC card max clock rate */
|
||||
#define MMC_HIGH_BUS_MAX_CLOCK 52000000 /*!< Type 1 MMC card max clock rate */
|
||||
#define SD_MAX_CLOCK 25000000 /*!< Max SD clock rate */
|
||||
|
||||
/* Function prototype for event setup function */
|
||||
typedef void (*MCI_EVSETUP_FUNC_T)(uint32_t);
|
||||
|
||||
/* Function prototype for wait (for IRQ) function */
|
||||
typedef uint32_t (*MCI_WAIT_CB_FUNC_T)(uint32_t);
|
||||
|
||||
/* Function prototype for milliSecond delay function */
|
||||
typedef void (*MCI_MSDELAY_FUNC_T)(uint32_t);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup SDMMC_Public_Functions SDMMC Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Attempt to enumerate an SDMMC card */
|
||||
int32_t sdmmc_acquire(MCI_EVSETUP_FUNC_T evsetup_cb,
|
||||
MCI_WAIT_CB_FUNC_T waitfunc_cb, MCI_MSDELAY_FUNC_T msdelay_func,
|
||||
struct _mci_card_struct *pcardinfo);
|
||||
|
||||
/* Get card's current state (idle, transfer, program, etc.) */
|
||||
int32_t sdmmc_get_state(void);
|
||||
|
||||
/* Get card's size */
|
||||
int32_t sdmmc_get_device_size(void);
|
||||
|
||||
/* SDMMC read function - reads data from a card */
|
||||
int32_t sdmmc_read_blocks(void *buffer, int32_t start_block,
|
||||
int32_t end_block);
|
||||
|
||||
/* SDMMC write function - writes data to a card. After calling this
|
||||
function, do not use read or write until the card state has
|
||||
left the program state. */
|
||||
int32_t sdmmc_write_blocks(void *buffer, int32_t start_block,
|
||||
int32_t end_block);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end LPC43XX_SDMMC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@@ -163,9 +163,9 @@ extern "C"
|
||||
* SSP DMA defines
|
||||
**********************************************************************/
|
||||
/** SSP bit for enabling RX DMA */
|
||||
#define SSP_DMA_TX SSP_DMA_RXDMA_EN
|
||||
#define SSP_DMA_RX SSP_DMA_RXDMA_EN
|
||||
/** SSP bit for enabling TX DMA */
|
||||
#define SSP_DMA_RX SSP_DMA_TXDMA_EN
|
||||
#define SSP_DMA_TX SSP_DMA_TXDMA_EN
|
||||
|
||||
/* SSP Status Implementation definitions */
|
||||
#define SSP_STAT_DONE (1UL<<8) /**< Done */
|
||||
|
||||
Reference in New Issue
Block a user