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MMU works

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This commit is contained in:
Scott Shawcroft
2021-09-24 16:14:01 -07:00
parent 829f92d00f
commit 0a6ca65e3f
5 changed files with 177 additions and 7 deletions
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hw/mcu/broadcom/bcm2711/io.c
+2
View File
@@ -3,6 +3,8 @@
// GPIO
// Pi 4 base address: 0xFE000000
// Pi 3 base address: 0x3F000000
enum {
PERIPHERAL_BASE = 0xFE000000,
GPFSEL0 = PERIPHERAL_BASE + 0x200000,
hw/mcu/broadcom/bcm2711/mmu.c
+8 -4
View File
@@ -5,7 +5,7 @@
#include "mmu.h"
// Each entry is a gig.
volatile uint64_t level_1_table[32] __attribute__((aligned(4096)));
volatile uint64_t level_1_table[512] __attribute__((aligned(4096)));
// Third gig has peripherals
uint64_t level_2_0x0_c000_0000_to_0x1_0000_0000[512] __attribute__((aligned(4096)));
@@ -14,9 +14,10 @@ void setup_mmu_flat_map(void) {
// Set the first gig to regular access.
level_1_table[0] = 0x0000000000000000 |
MM_DESCRIPTOR_MAIR_INDEX(MT_NORMAL_NC) |
MM_DESCRIPTOR_ACCESS_FLAG |
MM_DESCRIPTOR_BLOCK |
MM_DESCRIPTOR_VALID;
level_1_table[2] = ((uint64_t) level_2_0x0_c000_0000_to_0x1_0000_0000) |
level_1_table[3] = ((uint64_t) level_2_0x0_c000_0000_to_0x1_0000_0000) |
MM_DESCRIPTOR_TABLE |
MM_DESCRIPTOR_VALID;
// Set peripherals to register access.
@@ -24,6 +25,7 @@ void setup_mmu_flat_map(void) {
level_2_0x0_c000_0000_to_0x1_0000_0000[i] = (0x00000000c0000000 + (i << 21)) |
MM_DESCRIPTOR_EXECUTE_NEVER |
MM_DESCRIPTOR_MAIR_INDEX(MT_DEVICE_nGnRnE) |
MM_DESCRIPTOR_ACCESS_FLAG |
MM_DESCRIPTOR_BLOCK |
MM_DESCRIPTOR_VALID;
}
@@ -47,12 +49,14 @@ void setup_mmu_flat_map(void) {
// Set [M] bit and enable the MMU.
"MSR SCTLR_EL2, %[sctlr]\n\t"
// The ISB forces these changes to be seen by the next instruction
"ISB"
"ISB\n\t"
// "AT S1EL2R %[ttbr0]"
: /* No outputs. */
: [mair] "r" (mair),
[tcr] "r" (tcr),
[ttbr0] "r" (ttbr0),
[sctlr] "r" (sctlr)
);
while (true) {}
//__asm__ ("brk #123");
//while (true) {}
}
hw/mcu/broadcom/bcm2711/mmu.h
+3 -2
View File
@@ -13,11 +13,11 @@
#define MT_DEVICE_nGnRnE 0x0
#define MT_NORMAL_NC 0x1
#define MT_DEVICE_nGnRnE_FLAGS 0x00
#define MT_NORMAL_NC_FLAGS 0x44
#define MT_NORMAL_NC_FLAGS 0xff
#define MAIR_VALUE (MT_DEVICE_nGnRnE_FLAGS << (8 * MT_DEVICE_nGnRnE)) | (MT_NORMAL_NC_FLAGS << (8 * MT_NORMAL_NC))
#define TCR_T0SZ (64 - 35)
#define TCR_T0SZ (64 - 36)
#define TCR_PS (0x01 << 16) // 36-bit physical address
#define TCR_TG0_4K (0 << 14)
#define TCR_SH0_OUTER_SHAREABLE (0x2 << 12)
@@ -36,6 +36,7 @@
// Block attributes
#define MM_DESCRIPTOR_EXECUTE_NEVER (0x1ull << 54)
#define MM_DESCRIPTOR_CONTIGUOUS (0x1ull << 52)
#define MM_DESCRIPTOR_ACCESS_FLAG (0x1ull << 10)
#define MM_DESCRIPTOR_MAIR_INDEX(index) (index << 2)