better qspi

hw/bsp/pca10056/board_pca10056.c

@@ -80,6 +80,17 @@ uint32_t tusb_hal_millis(void)
 #define QSPI_STD_CMD_RST    0x99
 #define QSPI_STD_CMD_WRSR   0x01
 
+extern void qspi_flash_complete (void);
+
+void qflash_hdl (nrfx_qspi_evt_t event, void * p_context)
+{
+  (void) p_context;
+  (void) event;
+
+  qspi_flash_complete();
+}
+
+
 /* tinyusb function that handles power event (detected, ready, removed)
  * We must call it within SD's SOC event handler, or set it as power event handler if SD is not enabled.
  */
@@ -104,42 +115,41 @@ void board_init(void)
 
 // 64 Mbit qspi flash
 #ifdef BOARD_MSC_FLASH_QSPI
-  nrfx_qspi_config_t qspi_cfg =
-  {
-    .xip_offset  = 0,
+  nrfx_qspi_config_t qspi_cfg = {
+    .xip_offset = 0,
     .pins = {
-       .sck_pin     = 19,
-       .csn_pin     = 17,
-       .io0_pin     = 20,
-       .io1_pin     = 21,
-       .io2_pin     = 22,
-       .io3_pin     = 23,
+       .sck_pin = 19,
+       .csn_pin = 17,
+       .io0_pin = 20,
+       .io1_pin = 21,
+       .io2_pin = 22,
+       .io3_pin = 23,
     },
     .prot_if = {
-        .readoc     = NRF_QSPI_READOC_FASTREAD,
-        .writeoc    = NRF_QSPI_WRITEOC_PP,
-        .addrmode   = NRF_QSPI_ADDRMODE_24BIT,
-        .dpmconfig  = false, // deep power down
+      .readoc    = NRF_QSPI_READOC_READ4IO,
+      .writeoc   = NRF_QSPI_WRITEOC_PP,
+      .addrmode  = NRF_QSPI_ADDRMODE_24BIT,
+      .dpmconfig = false,  // deep power down
     },
     .phy_if = {
-        .sck_freq   = NRF_QSPI_FREQ_32MDIV16,
-        .sck_delay  = 1,
-        .spi_mode   = NRF_QSPI_MODE_0,
-        .dpmen      = false
+      .sck_freq  = NRF_QSPI_FREQ_32MDIV4,
+      .sck_delay = 1,
+      .spi_mode  = NRF_QSPI_MODE_0,
+      .dpmen     = false
     },
     .irq_priority   = 7,
   };
 
-  // callback = NULL --> blocking
   nrfx_qspi_init(&qspi_cfg, NULL, NULL);
+//  nrfx_qspi_init(&qspi_cfg, qflash_hdl, NULL);
 
   nrf_qspi_cinstr_conf_t cinstr_cfg = {
-      .opcode = 0,
-      .length = 0,
-      .io2_level = true,
-      .io3_level = true,
-      .wipwait   = true,
-      .wren      = true
+    .opcode    = 0,
+    .length    = 0,
+    .io2_level = true,
+    .io3_level = true,
+    .wipwait   = true,
+    .wren      = true
   };
 
   // Send reset enable