refractor qhd_xfer_error_isr (omit xfer_type para)

add accumulated total xferred byte for an endpoint until transfer with IOC set
- control xfer will have length of data phase in usbh_xfer_isr callback
This commit is contained in:
hathach
2013-07-06 14:52:02 +07:00
parent 68da489c2e
commit 25304d142f
5 changed files with 42 additions and 16 deletions
@@ -209,11 +209,12 @@ void test_bulk_xfer_complete_isr(void)
ehci_qtd_t* p_head = p_qhd_bulk->p_qtd_list_head;
ehci_qtd_t* p_tail = p_qhd_bulk->p_qtd_list_tail;
usbh_xfer_isr_Expect(pipe_hdl_bulk, TUSB_CLASS_MSC, TUSB_EVENT_XFER_COMPLETE, sizeof(data2));
usbh_xfer_isr_Expect(pipe_hdl_bulk, TUSB_CLASS_MSC, TUSB_EVENT_XFER_COMPLETE, sizeof(data2)+sizeof(xfer_data));
//------------- Code Under Test -------------//
ehci_controller_run(hostid);
TEST_ASSERT_EQUAL(0, p_qhd_bulk->total_xferred_bytes);
TEST_ASSERT_TRUE(p_qhd_bulk->qtd_overlay.next.terminate);
TEST_ASSERT_FALSE(p_head->used);
TEST_ASSERT_FALSE(p_tail->used);
@@ -155,6 +155,7 @@ void test_control_addr0_xfer_get_check_qhd_qtd_mapping(void)
p_data = &ehci_data.addr0_qtd[1];
p_status = &ehci_data.addr0_qtd[2];
TEST_ASSERT_EQUAL(0 , p_qhd->total_xferred_bytes);
TEST_ASSERT_EQUAL_HEX( p_setup, p_qhd->qtd_overlay.next.address );
TEST_ASSERT_EQUAL_HEX( p_setup , p_qhd->p_qtd_list_head);
TEST_ASSERT_EQUAL_HEX( p_data , p_setup->next.address);
@@ -227,11 +228,12 @@ void test_control_xfer_complete_isr(void)
{
TEST_ASSERT_STATUS( hcd_pipe_control_xfer(dev_addr, &request_get_dev_desc, xfer_data) );
usbh_xfer_isr_Expect(((pipe_handle_t){.dev_addr = dev_addr}), 0, TUSB_EVENT_XFER_COMPLETE, 0);
usbh_xfer_isr_Expect(((pipe_handle_t){.dev_addr = dev_addr}), 0, TUSB_EVENT_XFER_COMPLETE, 18);
//------------- Code Under TEST -------------//
ehci_controller_run(hostid);
TEST_ASSERT_EQUAL(0, p_control_qhd->total_xferred_bytes);
TEST_ASSERT_NULL(p_control_qhd->p_qtd_list_head);
TEST_ASSERT_NULL(p_control_qhd->p_qtd_list_tail);
@@ -249,6 +251,8 @@ void test_control_xfer_error_isr(void)
//------------- Code Under TEST -------------//
ehci_controller_run_error(hostid);
TEST_ASSERT_EQUAL(0, p_control_qhd->total_xferred_bytes);
}
void test_control_xfer_error_stall(void)
@@ -259,4 +263,6 @@ void test_control_xfer_error_stall(void)
//------------- Code Under TEST -------------//
ehci_controller_run_stall(hostid);
TEST_ASSERT_EQUAL(0, p_control_qhd->total_xferred_bytes);
}
@@ -201,7 +201,7 @@ void test_interrupt_xfer_complete_isr_interval_less_than_1ms(void)
TEST_ASSERT_STATUS( hcd_pipe_xfer(pipe_hdl_interrupt, data2, sizeof(data2), true) );
usbh_xfer_isr_Expect(pipe_hdl_interrupt, TUSB_CLASS_HID, TUSB_EVENT_XFER_COMPLETE, sizeof(data2));
usbh_xfer_isr_Expect(pipe_hdl_interrupt, TUSB_CLASS_HID, TUSB_EVENT_XFER_COMPLETE, sizeof(xfer_data)+sizeof(data2));
ehci_qtd_t* p_head = p_qhd_interrupt->p_qtd_list_head;
ehci_qtd_t* p_tail = p_qhd_interrupt->p_qtd_list_tail;
@@ -209,6 +209,7 @@ void test_interrupt_xfer_complete_isr_interval_less_than_1ms(void)
//------------- Code Under Test -------------//
ehci_controller_run(hostid);
TEST_ASSERT_EQUAL(0, p_qhd_interrupt->total_xferred_bytes);
check_qhd_after_complete(p_qhd_interrupt);
TEST_ASSERT_FALSE(p_head->used);
TEST_ASSERT_FALSE(p_tail->used);
@@ -230,6 +231,7 @@ void test_interrupt_xfer_complete_isr_interval_2ms(void)
//------------- Code Under Test -------------//
ehci_controller_run(hostid);
TEST_ASSERT_EQUAL(0, p_qhd_interrupt->total_xferred_bytes);
check_qhd_after_complete(p_qhd_2ms);
TEST_ASSERT_FALSE(p_head->used);
TEST_ASSERT_FALSE(p_tail->used);
@@ -244,6 +246,8 @@ void test_interrupt_xfer_error_isr(void)
//------------- Code Under TEST -------------//
ehci_controller_run_error(hostid);
TEST_ASSERT_EQUAL(0, p_qhd_interrupt->total_xferred_bytes);
}
void test_interrupt_xfer_error_stall(void)
@@ -254,5 +258,7 @@ void test_interrupt_xfer_error_stall(void)
//------------- Code Under TEST -------------//
ehci_controller_run_stall(hostid);
TEST_ASSERT_EQUAL(0, p_qhd_interrupt->total_xferred_bytes);
}