adding lpc40xx support
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hathach
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/*
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* @brief Basic CMSIS include file for LPC40xx
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2014
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CMSIS_40XX_H_
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#define __CMSIS_40XX_H_
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#include "lpc_types.h"
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#include "sys_config.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup CMSIS_40XX CHIP: LPC40xx CMSIS include file
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* @ingroup CHIP_17XX_40XX_Drivers
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* @{
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*/
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#if defined(__ARMCC_VERSION)
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// Kill warning "#pragma push with no matching #pragma pop"
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#pragma diag_suppress 2525
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#pragma push
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#pragma anon_unions
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#elif defined(__CWCC__)
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#pragma push
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#pragma cpp_extensions on
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__IAR_SYSTEMS_ICC__)
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// #pragma push // FIXME not usable for IAR
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#pragma language=extended
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#else
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#error Not supported compiler type
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#endif
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/*
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* ==========================================================================
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* ---------- Interrupt Number Definition -----------------------------------
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* ==========================================================================
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*/
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#if !defined(CHIP_LPC40XX)
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#error Incorrect or missing device variant (CHIP_LPC40XX)
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#endif
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/** @defgroup CMSIS_40XX_IRQ CHIP_40XX: LPC40xx peripheral interrupt numbers
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* @{
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*/
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typedef enum {
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/* ------------------------- Cortex-M4 Processor Exceptions Numbers ----------------------------- */
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Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
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NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
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HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
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MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
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BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
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UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
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SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
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DebugMonitor_IRQn = -4, /*!< 12 CDebug Monitor */
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PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
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SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
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/* --------------------------- LPC40xx Specific Interrupt Numbers ------------------------------- */
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WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
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TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
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TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
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TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
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TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
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UART0_IRQn = 5, /*!< UART0 Interrupt */
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UART_IRQn = UART0_IRQn, /*!< Alias for UART0 Interrupt */
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UART1_IRQn = 6, /*!< UART1 Interrupt */
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UART2_IRQn = 7, /*!< UART2 Interrupt */
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UART3_IRQn = 8, /*!< UART3 Interrupt */
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PWM1_IRQn = 9, /*!< PWM1 Interrupt */
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I2C0_IRQn = 10, /*!< I2C0 Interrupt */
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I2C_IRQn = I2C0_IRQn, /*!< Alias for I2C0 Interrupt */
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I2C1_IRQn = 11, /*!< I2C1 Interrupt */
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I2C2_IRQn = 12, /*!< I2C2 Interrupt */
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Reserved0_IRQn = 13, /*!< Reserved */
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SSP0_IRQn = 14, /*!< SSP0 Interrupt */
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SSP_IRQn = SSP0_IRQn, /*!< Alias for SSP0 Interrupt */
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SSP1_IRQn = 15, /*!< SSP1 Interrupt */
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PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
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RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
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EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
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EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
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EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
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EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
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ADC_IRQn = 22, /*!< A/D Converter Interrupt */
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BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
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USB_IRQn = 24, /*!< USB Interrupt */
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CAN_IRQn = 25, /*!< CAN Interrupt */
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DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
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I2S_IRQn = 27, /*!< I2S Interrupt */
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ETHERNET_IRQn = 28, /*!< Ethernet Interrupt */
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SDC_IRQn = 29, /*!< SD/MMC card I/F Interrupt */
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MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
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QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
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PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
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USBActivity_IRQn = 33, /*!< USB Activity interrupt */
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CANActivity_IRQn = 34, /*!< CAN Activity interrupt */
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UART4_IRQn = 35, /*!< UART4 Interrupt */
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SSP2_IRQn = 36, /*!< SSP2 Interrupt */
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LCD_IRQn = 37, /*!< LCD Interrupt */
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GPIO_IRQn = 38, /*!< GPIO Interrupt */
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PWM0_IRQn = 39, /*!< PWM0 Interrupt */
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EEPROM_IRQn = 40, /*!< EEPROM Interrupt */
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} LPC40XX_IRQn_Type;
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/**
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* @}
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*/
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/** @defgroup CMSIS_40XX_COMMON CHIP: LPC40xx Cortex CMSIS definitions
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* @{
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*/
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#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */
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#define __MPU_PRESENT 1 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#ifndef __FPU_PRESENT
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#define __FPU_PRESENT 1 /*!< FPU present or not */
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#endif
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CMSIS_40XX_H_ */
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