adding lpc40xx support
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@@ -54,9 +54,14 @@
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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#define QHD_MAX 12
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#define QTD_NEXT_INVALID 0x01
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typedef struct {
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dcd_qhd_t qhd[DCD_QHD_MAX] ATTR_ALIGNED(64); ///< Must be at 2K alignment
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dcd_qtd_t qtd[DCD_QTD_MAX] ATTR_ALIGNED(32);
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// Must be at 2K alignment
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dcd_qhd_t qhd[QHD_MAX] ATTR_ALIGNED(64);
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dcd_qtd_t qtd[QHD_MAX] ATTR_ALIGNED(32);
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}dcd_data_t;
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#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
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@@ -229,7 +234,6 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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{
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// TODO USB1 only has 4 non-control enpoint (USB0 has 5)
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// TODO not support ISO yet
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TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
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@@ -237,6 +241,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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uint8_t const dir = edpt_dir(p_endpoint_desc->bEndpointAddress);
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uint8_t const ep_idx = 2*epnum + dir;
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// USB0 has 5, USB1 has 3 non-control endpoints
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TU_ASSERT( epnum <= (rhport ? 3 : 5) );
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//------------- Prepare Queue Head -------------//
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dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
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tu_memclr(p_qhd, sizeof(dcd_qhd_t));
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@@ -351,7 +358,7 @@ void hal_dcd_isr(uint8_t rhport)
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if ( edpt_complete )
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{
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for(uint8_t ep_idx = 0; ep_idx < DCD_QHD_MAX; ep_idx++)
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for(uint8_t ep_idx = 0; ep_idx < QHD_MAX; ep_idx++)
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{
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if ( BIT_TEST_(edpt_complete, ep_idx2bit(ep_idx)) )
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{
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@@ -52,10 +52,6 @@
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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#define DCD_QHD_MAX 12
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#define DCD_QTD_MAX 12
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#define QTD_NEXT_INVALID 0x01
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/*---------- ENDPTCTRL ----------*/
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enum {
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