rename bit_* helper to tu_bit_*, BIT_* to TU_BIT_* for consistency
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+28
-28
@@ -65,10 +65,10 @@ enum {
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enum {
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OHCI_CONTROL_CONTROL_BULK_RATIO = 3, ///< This specifies the service ratio between Control and Bulk EDs. 0 = 1:1, 3 = 4:1
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OHCI_CONTROL_LIST_PERIODIC_ENABLE_MASK = BIT_(2),
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OHCI_CONTROL_LIST_ISOCHRONOUS_ENABLE_MASK = BIT_(3),
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OHCI_CONTROL_LIST_CONTROL_ENABLE_MASK = BIT_(4),
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OHCI_CONTROL_LIST_BULK_ENABLE_MASK = BIT_(5),
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OHCI_CONTROL_LIST_PERIODIC_ENABLE_MASK = TU_BIT(2),
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OHCI_CONTROL_LIST_ISOCHRONOUS_ENABLE_MASK = TU_BIT(3),
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OHCI_CONTROL_LIST_CONTROL_ENABLE_MASK = TU_BIT(4),
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OHCI_CONTROL_LIST_BULK_ENABLE_MASK = TU_BIT(5),
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};
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enum {
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@@ -81,33 +81,33 @@ enum {
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};
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enum {
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OHCI_INT_SCHEDULING_OVERUN_MASK = BIT_(0),
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OHCI_INT_WRITEBACK_DONEHEAD_MASK = BIT_(1),
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OHCI_INT_SOF_MASK = BIT_(2),
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OHCI_INT_RESUME_DETECTED_MASK = BIT_(3),
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OHCI_INT_UNRECOVERABLE_ERROR_MASK = BIT_(4),
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OHCI_INT_FRAME_OVERFLOW_MASK = BIT_(5),
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OHCI_INT_RHPORT_STATUS_CHANGE_MASK = BIT_(6),
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OHCI_INT_SCHEDULING_OVERUN_MASK = TU_BIT(0),
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OHCI_INT_WRITEBACK_DONEHEAD_MASK = TU_BIT(1),
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OHCI_INT_SOF_MASK = TU_BIT(2),
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OHCI_INT_RESUME_DETECTED_MASK = TU_BIT(3),
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OHCI_INT_UNRECOVERABLE_ERROR_MASK = TU_BIT(4),
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OHCI_INT_FRAME_OVERFLOW_MASK = TU_BIT(5),
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OHCI_INT_RHPORT_STATUS_CHANGE_MASK = TU_BIT(6),
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OHCI_INT_OWNERSHIP_CHANGE_MASK = BIT_(30),
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OHCI_INT_MASTER_ENABLE_MASK = BIT_(31),
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OHCI_INT_OWNERSHIP_CHANGE_MASK = TU_BIT(30),
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OHCI_INT_MASTER_ENABLE_MASK = TU_BIT(31),
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};
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enum {
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OHCI_RHPORT_CURRENT_CONNECT_STATUS_MASK = BIT_(0),
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OHCI_RHPORT_PORT_ENABLE_STATUS_MASK = BIT_(1),
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OHCI_RHPORT_PORT_SUSPEND_STATUS_MASK = BIT_(2),
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OHCI_RHPORT_PORT_OVER_CURRENT_INDICATOR_MASK = BIT_(3),
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OHCI_RHPORT_PORT_RESET_STATUS_MASK = BIT_(4), ///< write '1' to reset port
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OHCI_RHPORT_CURRENT_CONNECT_STATUS_MASK = TU_BIT(0),
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OHCI_RHPORT_PORT_ENABLE_STATUS_MASK = TU_BIT(1),
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OHCI_RHPORT_PORT_SUSPEND_STATUS_MASK = TU_BIT(2),
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OHCI_RHPORT_PORT_OVER_CURRENT_INDICATOR_MASK = TU_BIT(3),
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OHCI_RHPORT_PORT_RESET_STATUS_MASK = TU_BIT(4), ///< write '1' to reset port
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OHCI_RHPORT_PORT_POWER_STATUS_MASK = BIT_(8),
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OHCI_RHPORT_LOW_SPEED_DEVICE_ATTACHED_MASK = BIT_(9),
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OHCI_RHPORT_PORT_POWER_STATUS_MASK = TU_BIT(8),
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OHCI_RHPORT_LOW_SPEED_DEVICE_ATTACHED_MASK = TU_BIT(9),
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OHCI_RHPORT_CONNECT_STATUS_CHANGE_MASK = BIT_(16),
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OHCI_RHPORT_PORT_ENABLE_CHANGE_MASK = BIT_(17),
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OHCI_RHPORT_PORT_SUSPEND_CHANGE_MASK = BIT_(18),
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OHCI_RHPORT_OVER_CURRENT_CHANGE_MASK = BIT_(19),
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OHCI_RHPORT_PORT_RESET_CHANGE_MASK = BIT_(20),
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OHCI_RHPORT_CONNECT_STATUS_CHANGE_MASK = TU_BIT(16),
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OHCI_RHPORT_PORT_ENABLE_CHANGE_MASK = TU_BIT(17),
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OHCI_RHPORT_PORT_SUSPEND_CHANGE_MASK = TU_BIT(18),
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OHCI_RHPORT_OVER_CURRENT_CHANGE_MASK = TU_BIT(19),
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OHCI_RHPORT_PORT_RESET_CHANGE_MASK = TU_BIT(20),
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OHCI_RHPORT_ALL_CHANGE_MASK = OHCI_RHPORT_CONNECT_STATUS_CHANGE_MASK | OHCI_RHPORT_PORT_ENABLE_CHANGE_MASK |
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OHCI_RHPORT_PORT_SUSPEND_CHANGE_MASK | OHCI_RHPORT_OVER_CURRENT_CHANGE_MASK | OHCI_RHPORT_PORT_RESET_CHANGE_MASK
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@@ -131,7 +131,7 @@ enum {
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enum {
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OHCI_INT_ON_COMPLETE_YES = 0,
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OHCI_INT_ON_COMPLETE_NO = BIN8(111)
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OHCI_INT_ON_COMPLETE_NO = TU_BIN8(111)
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};
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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@@ -300,7 +300,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
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gtd_init(p_setup, (void*) setup_packet, 8);
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p_setup->index = dev_addr;
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p_setup->pid = OHCI_PID_SETUP;
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p_setup->data_toggle = BIN8(10); // DATA0
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p_setup->data_toggle = TU_BIN8(10); // DATA0
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p_setup->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
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//------------- Attach TDs list to Control Endpoint -------------//
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@@ -328,7 +328,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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p_data->index = dev_addr;
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p_data->pid = dir ? OHCI_PID_IN : OHCI_PID_OUT;
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p_data->data_toggle = BIN8(11); // DATA1
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p_data->data_toggle = TU_BIN8(11); // DATA1
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p_data->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
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p_ed->td_head.address = (uint32_t) p_data;
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