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rename bit_* helper to tu_bit_*, BIT_* to TU_BIT_* for consistency

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This commit is contained in:
hathach
2018-12-14 15:28:38 +07:00
parent a3713f801d
commit 2a60427bdc
29 changed files with 264 additions and 292 deletions
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src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+14 -14
View File
@@ -148,7 +148,7 @@ static inline uint8_t ep_addr2idx(uint8_t ep_addr)
static void set_ep_size(uint8_t ep_id, uint16_t max_packet_size)
{
// follows example in 11.10.4.2
LPC_USB->ReEp |= BIT_(ep_id);
LPC_USB->ReEp |= TU_BIT(ep_id);
LPC_USB->EpInd = ep_id; // select index before setting packet size
LPC_USB->MaxPSize = max_packet_size;
@@ -419,15 +419,15 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t t
if ( ep_id % 2 )
{
// Clear EP interrupt before Enable DMA
LPC_USB->EpIntEn &= ~BIT_(ep_id);
LPC_USB->EpDMAEn = BIT_(ep_id);
LPC_USB->EpIntEn &= ~TU_BIT(ep_id);
LPC_USB->EpDMAEn = TU_BIT(ep_id);
// endpoint IN need to actively raise DMA request
LPC_USB->DMARSet = BIT_(ep_id);
LPC_USB->DMARSet = TU_BIT(ep_id);
}else
{
// Enable DMA
LPC_USB->EpDMAEn = BIT_(ep_id);
LPC_USB->EpDMAEn = TU_BIT(ep_id);
}
return true;
@@ -442,11 +442,11 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t t
static void control_xfer_isr(uint8_t rhport, uint32_t ep_int_status)
{
// Control out complete
if ( ep_int_status & BIT_(0) )
if ( ep_int_status & TU_BIT(0) )
{
bool is_setup = sie_read(SIE_CMDCODE_ENDPOINT_SELECT+0) & SIE_SELECT_ENDPOINT_SETUP_RECEIVED_MASK;
LPC_USB->EpIntClr = BIT_(0);
LPC_USB->EpIntClr = TU_BIT(0);
if (is_setup)
{
@@ -472,9 +472,9 @@ static void control_xfer_isr(uint8_t rhport, uint32_t ep_int_status)
}
// Control In complete
if ( ep_int_status & BIT_(1) )
if ( ep_int_status & TU_BIT(1) )
{
LPC_USB->EpIntClr = BIT_(1);
LPC_USB->EpIntClr = TU_BIT(1);
dcd_event_xfer_complete(rhport, TUSB_DIR_IN_MASK, _dcd.control.in_bytes, XFER_RESULT_SUCCESS, true);
}
}
@@ -546,12 +546,12 @@ void hal_dcd_isr(uint8_t rhport)
{
for ( uint8_t ep_id = 3; ep_id < DCD_ENDPOINT_MAX; ep_id += 2 )
{
if ( BIT_TEST_(ep_int_status, ep_id) )
if ( TU_BIT_TEST(ep_int_status, ep_id) )
{
LPC_USB->EpIntClr = BIT_(ep_id);
LPC_USB->EpIntClr = TU_BIT(ep_id);
// Clear Ep interrupt for next DMA
LPC_USB->EpIntEn &= ~BIT_(ep_id);
LPC_USB->EpIntEn &= ~TU_BIT(ep_id);
dd_complete_isr(rhport, ep_id);
}
@@ -569,12 +569,12 @@ void hal_dcd_isr(uint8_t rhport)
for ( uint8_t ep_id = 2; ep_id < DCD_ENDPOINT_MAX; ep_id++ )
{
if ( BIT_TEST_(eot, ep_id) )
if ( TU_BIT_TEST(eot, ep_id) )
{
if ( ep_id & 0x01 )
{
// IN enable EpInt for end of usb transfer
LPC_USB->EpIntEn |= BIT_(ep_id);
LPC_USB->EpIntEn |= TU_BIT(ep_id);
}else
{
// OUT
src/portable/nxp/lpc17_40/dcd_lpc17_40.h
+39 -39
View File
@@ -51,45 +51,45 @@
//------------- USB Interrupt USBIntSt -------------//
//enum {
// DCD_USB_REQ_LOW_PRIO_MASK = BIT_(0),
// DCD_USB_REQ_HIGH_PRIO_MASK = BIT_(1),
// DCD_USB_REQ_DMA_MASK = BIT_(2),
// DCD_USB_REQ_NEED_CLOCK_MASK = BIT_(8),
// DCD_USB_REQ_ENABLE_MASK = BIT_(31)
// DCD_USB_REQ_LOW_PRIO_MASK = TU_BIT(0),
// DCD_USB_REQ_HIGH_PRIO_MASK = TU_BIT(1),
// DCD_USB_REQ_DMA_MASK = TU_BIT(2),
// DCD_USB_REQ_NEED_CLOCK_MASK = TU_BIT(8),
// DCD_USB_REQ_ENABLE_MASK = TU_BIT(31)
//};
//------------- Device Interrupt USBDevInt -------------//
enum {
DEV_INT_FRAME_MASK = BIT_(0),
DEV_INT_ENDPOINT_FAST_MASK = BIT_(1),
DEV_INT_ENDPOINT_SLOW_MASK = BIT_(2),
DEV_INT_DEVICE_STATUS_MASK = BIT_(3),
DEV_INT_COMMAND_CODE_EMPTY_MASK = BIT_(4),
DEV_INT_COMMAND_DATA_FULL_MASK = BIT_(5),
DEV_INT_RX_ENDPOINT_PACKET_MASK = BIT_(6),
DEV_INT_TX_ENDPOINT_PACKET_MASK = BIT_(7),
DEV_INT_ENDPOINT_REALIZED_MASK = BIT_(8),
DEV_INT_ERROR_MASK = BIT_(9)
DEV_INT_FRAME_MASK = TU_BIT(0),
DEV_INT_ENDPOINT_FAST_MASK = TU_BIT(1),
DEV_INT_ENDPOINT_SLOW_MASK = TU_BIT(2),
DEV_INT_DEVICE_STATUS_MASK = TU_BIT(3),
DEV_INT_COMMAND_CODE_EMPTY_MASK = TU_BIT(4),
DEV_INT_COMMAND_DATA_FULL_MASK = TU_BIT(5),
DEV_INT_RX_ENDPOINT_PACKET_MASK = TU_BIT(6),
DEV_INT_TX_ENDPOINT_PACKET_MASK = TU_BIT(7),
DEV_INT_ENDPOINT_REALIZED_MASK = TU_BIT(8),
DEV_INT_ERROR_MASK = TU_BIT(9)
};
//------------- DMA Interrupt USBDMAInt-------------//
enum {
DMA_INT_END_OF_XFER_MASK = BIT_(0),
DMA_INT_NEW_DD_REQUEST_MASK = BIT_(1),
DMA_INT_ERROR_MASK = BIT_(2)
DMA_INT_END_OF_XFER_MASK = TU_BIT(0),
DMA_INT_NEW_DD_REQUEST_MASK = TU_BIT(1),
DMA_INT_ERROR_MASK = TU_BIT(2)
};
//------------- USBCtrl -------------//
enum {
USBCTRL_READ_ENABLE_MASK = BIT_(0),
USBCTRL_WRITE_ENABLE_MASK = BIT_(1),
USBCTRL_READ_ENABLE_MASK = TU_BIT(0),
USBCTRL_WRITE_ENABLE_MASK = TU_BIT(1),
};
//------------- USBRxPLen -------------//
enum {
USBRXPLEN_PACKET_LENGTH_MASK = (BIT_(10)-1),
USBRXPLEN_DATA_VALID_MASK = BIT_(10),
USBRXPLEN_PACKET_READY_MASK = BIT_(11),
USBRXPLEN_PACKET_LENGTH_MASK = (TU_BIT(10)-1),
USBRXPLEN_DATA_VALID_MASK = TU_BIT(10),
USBRXPLEN_PACKET_READY_MASK = TU_BIT(11),
};
//------------- SIE Command Code -------------//
@@ -121,30 +121,30 @@ enum {
//------------- SIE Device Status (get/set from SIE_CMDCODE_DEVICE_STATUS) -------------//
enum {
SIE_DEV_STATUS_CONNECT_STATUS_MASK = BIT_(0),
SIE_DEV_STATUS_CONNECT_CHANGE_MASK = BIT_(1),
SIE_DEV_STATUS_SUSPEND_MASK = BIT_(2),
SIE_DEV_STATUS_SUSPEND_CHANGE_MASK = BIT_(3),
SIE_DEV_STATUS_RESET_MASK = BIT_(4)
SIE_DEV_STATUS_CONNECT_STATUS_MASK = TU_BIT(0),
SIE_DEV_STATUS_CONNECT_CHANGE_MASK = TU_BIT(1),
SIE_DEV_STATUS_SUSPEND_MASK = TU_BIT(2),
SIE_DEV_STATUS_SUSPEND_CHANGE_MASK = TU_BIT(3),
SIE_DEV_STATUS_RESET_MASK = TU_BIT(4)
};
//------------- SIE Select Endpoint Command -------------//
enum {
SIE_SELECT_ENDPOINT_FULL_EMPTY_MASK = BIT_(0), // 0: empty, 1 full. IN endpoint checks empty, OUT endpoint check full
SIE_SELECT_ENDPOINT_STALL_MASK = BIT_(1),
SIE_SELECT_ENDPOINT_SETUP_RECEIVED_MASK = BIT_(2), // clear by SIE_CMDCODE_ENDPOINT_SELECT_CLEAR_INTERRUPT
SIE_SELECT_ENDPOINT_PACKET_OVERWRITTEN_MASK = BIT_(3), // previous packet is overwritten by a SETUP packet
SIE_SELECT_ENDPOINT_NAK_MASK = BIT_(4), // last packet response is NAK (auto clear by an ACK)
SIE_SELECT_ENDPOINT_BUFFER1_FULL_MASK = BIT_(5),
SIE_SELECT_ENDPOINT_BUFFER2_FULL_MASK = BIT_(6)
SIE_SELECT_ENDPOINT_FULL_EMPTY_MASK = TU_BIT(0), // 0: empty, 1 full. IN endpoint checks empty, OUT endpoint check full
SIE_SELECT_ENDPOINT_STALL_MASK = TU_BIT(1),
SIE_SELECT_ENDPOINT_SETUP_RECEIVED_MASK = TU_BIT(2), // clear by SIE_CMDCODE_ENDPOINT_SELECT_CLEAR_INTERRUPT
SIE_SELECT_ENDPOINT_PACKET_OVERWRITTEN_MASK = TU_BIT(3), // previous packet is overwritten by a SETUP packet
SIE_SELECT_ENDPOINT_NAK_MASK = TU_BIT(4), // last packet response is NAK (auto clear by an ACK)
SIE_SELECT_ENDPOINT_BUFFER1_FULL_MASK = TU_BIT(5),
SIE_SELECT_ENDPOINT_BUFFER2_FULL_MASK = TU_BIT(6)
};
typedef enum
{
SIE_SET_ENDPOINT_STALLED_MASK = BIT_(0),
SIE_SET_ENDPOINT_DISABLED_MASK = BIT_(5),
SIE_SET_ENDPOINT_RATE_FEEDBACK_MASK = BIT_(6),
SIE_SET_ENDPOINT_CONDITION_STALLED_MASK = BIT_(7),
SIE_SET_ENDPOINT_STALLED_MASK = TU_BIT(0),
SIE_SET_ENDPOINT_DISABLED_MASK = TU_BIT(5),
SIE_SET_ENDPOINT_RATE_FEEDBACK_MASK = TU_BIT(6),
SIE_SET_ENDPOINT_CONDITION_STALLED_MASK = TU_BIT(7),
}sie_endpoint_set_status_mask_t;
//------------- DMA Descriptor Status -------------//