rename bit_* helper to tu_bit_*, BIT_* to TU_BIT_* for consistency

This commit is contained in:
hathach
2018-12-14 15:28:38 +07:00
parent a3713f801d
commit 2a60427bdc
29 changed files with 264 additions and 292 deletions
+5 -5
View File
@@ -94,7 +94,7 @@ static dcd_data_t* const dcd_data_ptr[2] =
//--------------------------------------------------------------------+
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
{
LPC_USB[rhport]->DEVICEADDR = (dev_addr << 25) | BIT_(24);
LPC_USB[rhport]->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
}
void dcd_set_config(uint8_t rhport, uint8_t config_num)
@@ -158,7 +158,7 @@ bool dcd_init(uint8_t rhport)
lpc_usb->USBINTR_D = INT_MASK_USB | INT_MASK_ERROR | INT_MASK_PORT_CHANGE | INT_MASK_RESET | INT_MASK_SUSPEND | INT_MASK_SOF;
lpc_usb->USBCMD_D &= ~0x00FF0000; // Interrupt Threshold Interval = 0
lpc_usb->USBCMD_D |= BIT_(0); // connect
lpc_usb->USBCMD_D |= TU_BIT(0); // connect
return true;
}
@@ -284,7 +284,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
{
// follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
// wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
while(LPC_USB[rhport]->ENDPTSETUPSTAT & BIT_(0)) {}
while(LPC_USB[rhport]->ENDPTSETUPSTAT & TU_BIT(0)) {}
}
dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
@@ -296,7 +296,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
// start transfer
LPC_USB[rhport]->ENDPTPRIME = BIT_( ep_idx2bit(ep_idx) ) ;
LPC_USB[rhport]->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
return true;
}
@@ -363,7 +363,7 @@ void hal_dcd_isr(uint8_t rhport)
{
for(uint8_t ep_idx = 0; ep_idx < QHD_MAX; ep_idx++)
{
if ( BIT_TEST_(edpt_complete, ep_idx2bit(ep_idx)) )
if ( TU_BIT_TEST(edpt_complete, ep_idx2bit(ep_idx)) )
{
// 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
+18 -18
View File
@@ -55,37 +55,37 @@
/*---------- ENDPTCTRL ----------*/
enum {
ENDPTCTRL_MASK_STALL = BIT_(0),
ENDPTCTRL_MASK_TOGGLE_INHIBIT = BIT_(5), ///< used for test only
ENDPTCTRL_MASK_TOGGLE_RESET = BIT_(6),
ENDPTCTRL_MASK_ENABLE = BIT_(7)
ENDPTCTRL_MASK_STALL = TU_BIT(0),
ENDPTCTRL_MASK_TOGGLE_INHIBIT = TU_BIT(5), ///< used for test only
ENDPTCTRL_MASK_TOGGLE_RESET = TU_BIT(6),
ENDPTCTRL_MASK_ENABLE = TU_BIT(7)
};
/*---------- USBCMD ----------*/
enum {
USBCMD_MASK_RUN_STOP = BIT_(0),
USBCMD_MASK_RESET = BIT_(1),
USBCMD_MASK_SETUP_TRIPWIRE = BIT_(13),
USBCMD_MASK_ADD_QTD_TRIPWIRE = BIT_(14) ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoints linked list. This bit is set and cleared by software during the process of adding a new dTD
USBCMD_MASK_RUN_STOP = TU_BIT(0),
USBCMD_MASK_RESET = TU_BIT(1),
USBCMD_MASK_SETUP_TRIPWIRE = TU_BIT(13),
USBCMD_MASK_ADD_QTD_TRIPWIRE = TU_BIT(14) ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoints linked list. This bit is set and cleared by software during the process of adding a new dTD
};
// Interrupt Threshold bit 23:16
/*---------- USBSTS, USBINTR ----------*/
enum {
INT_MASK_USB = BIT_(0),
INT_MASK_ERROR = BIT_(1),
INT_MASK_PORT_CHANGE = BIT_(2),
INT_MASK_RESET = BIT_(6),
INT_MASK_SOF = BIT_(7),
INT_MASK_SUSPEND = BIT_(8),
INT_MASK_NAK = BIT_(16)
INT_MASK_USB = TU_BIT(0),
INT_MASK_ERROR = TU_BIT(1),
INT_MASK_PORT_CHANGE = TU_BIT(2),
INT_MASK_RESET = TU_BIT(6),
INT_MASK_SOF = TU_BIT(7),
INT_MASK_SUSPEND = TU_BIT(8),
INT_MASK_NAK = TU_BIT(16)
};
//------------- PORTSC -------------//
enum {
PORTSC_CURRENT_CONNECT_STATUS_MASK = BIT_(0),
PORTSC_FORCE_PORT_RESUME_MASK = BIT_(6),
PORTSC_SUSPEND_MASK = BIT_(7)
PORTSC_CURRENT_CONNECT_STATUS_MASK = TU_BIT(0),
PORTSC_FORCE_PORT_RESUME_MASK = TU_BIT(6),
PORTSC_SUSPEND_MASK = TU_BIT(7)
};
typedef struct