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move board and mcu into hw folder

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hathach
2018-03-02 13:41:35 +07:00
parent 2580b4c6a7
commit 349fa2aed8
250 changed files with 47186 additions and 47134 deletions
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hw/mcu/lpc13uxx/CMSIS_CORE_LPC13Uxx/history.txt
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History of updates to CMSIS_CORE_LPC13Uxx
===========================================
18 July 2013
------------
CMSIS library project using ARM Cortex-M0 CMSIS files as
supplied in ARM's CMSIS 3.20 March 2013 release, together
with NXP's device specific files taken from old
CMSISv2p10_LPC13Uxx project.
Note files are built -Os for both Debug and Release
History of updates to CMSISv2p10_LPC13Uxx
=========================================
17 February 2012
----------------
CMSIS 2.1 library project using ARM Cortex-M3 CMSIS
files as supplied in ARM's CMSIS 2.1 July 2011 release,
together with device/board specific files from NXP for
LPC1300 (12bit ADC) parts (ie LPC1315/16/17/45/46/47).
hw/mcu/lpc13uxx/CMSIS_CORE_LPC13Uxx/inc/LPC13Uxx.h
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/****************************************************************************************************//**
* @file LPC13Uxx.h
*
*
*
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
* default LPC13Uxx Device Series
*
* @version V0.1
* @date 18. Jan 2012
*
* @note Generated with SFDGen V2.6 Build 4f on Tuesday, 17.01.2012 13:39:52
*
* from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
* created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
*
*******************************************************************************************************/
/** @addtogroup NXP
* @{
*/
/** @addtogroup LPC13Uxx
* @{
*/
#ifndef __LPC13UXX_H__
#define __LPC13UXX_H__
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/* Interrupt Number Definition */
typedef enum {
// ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
// ---------------------------- LPC13Uxx Specific Interrupt Numbers --------------------------------
PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
GINT0_IRQn = 8, /*!< 8 GINT0 */
GINT1_IRQn = 9, /*!< 9 GINT1 */
Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
SSP1_IRQn = 14, /*!< 14 SSP1 */
I2C_IRQn = 15, /*!< 15 I2C */
CT16B0_IRQn = 16, /*!< 16 CT16B0 */
CT16B1_IRQn = 17, /*!< 17 CT16B1 */
CT32B0_IRQn = 18, /*!< 18 CT32B0 */
CT32B1_IRQn = 19, /*!< 19 CT32B1 */
SSP0_IRQn = 20, /*!< 20 SSP0 */
USART_IRQn = 21, /*!< 21 USART */
USB_IRQ_IRQn = 22, /*!< 22 USB_IRQ */
USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
ADC_IRQn = 24, /*!< 24 ADC */
WDT_IRQn = 25, /*!< 25 WDT */
BOD_IRQn = 26, /*!< 26 BOD */
FMC_IRQn = 27, /*!< 27 FMC */
Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
} IRQn_Type;
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
#define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/** @} */ /* End of group Configuration_of_CMSIS */
#include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
#include "system_LPC13Uxx.h" /*!< LPC13Uxx System */
/** @addtogroup Device_Peripheral_Registers
* @{
*/
// ------------------------------------------------------------------------------------------------
// ----- I2C -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40000000) I2C Structure */
__IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
__I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
__IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
__IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
__IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
__IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
__O uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
__IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register. */
union{
__IO uint32_t ADR[3]; /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
struct{
__IO uint32_t ADR1;
__IO uint32_t ADR2;
__IO uint32_t ADR3;
};
};
__I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
union{
__IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
struct{
__IO uint32_t MASK0;
__IO uint32_t MASK1;
__IO uint32_t MASK2;
__IO uint32_t MASK3;
};
};
} LPC_I2C_Type;
// ------------------------------------------------------------------------------------------------
// ----- WWDT -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40004000) WWDT Structure */
__IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
__IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
__O uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
__I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
__IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
__IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
__IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
} LPC_WWDT_Type;
// ------------------------------------------------------------------------------------------------
// ----- USART -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40008000) USART Structure */
union {
__IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
__O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
__I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
};
union {
__IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
__IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
};
union {
__O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
__I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
};
__IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
__IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
__I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
__I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
__IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
__IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
__IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
__IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
__IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
__IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
__I uint32_t RESERVED0[3];
__IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
__I uint32_t RESERVED1;
__IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
__IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
__IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
__IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
__IO uint32_t SYNCCTRL; /*!< (@ 0x40008058) Synchronous mode control register. */
} LPC_USART_Type;
// ------------------------------------------------------------------------------------------------
// ----- CT16B0 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x4000C000) CT16B0 Structure */
__IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union {
__IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
__IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
__IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
__IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
};
};
__IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
struct{
__I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
__I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
__I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
__I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
};
};
__IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
} LPC_CT16B0_Type;
// ------------------------------------------------------------------------------------------------
// ----- CT16B1 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40010000) CT16B1 Structure */
__IO uint32_t IR; /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union {
__IO uint32_t MR[4]; /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IO uint32_t MR0; /*!< (@ 0x40010018) Match Register. MR0 */
__IO uint32_t MR1; /*!< (@ 0x4001001C) Match Register. MR1 */
__IO uint32_t MR2; /*!< (@ 0x40010020) Match Register. MR2 */
__IO uint32_t MR3; /*!< (@ 0x40010024) Match Register. MR3 */
};
};
__IO uint32_t CCR; /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__I uint32_t CR[4]; /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
struct{
__I uint32_t CR0; /*!< (@ 0x4001002C) Capture Register. CR 0 */
__I uint32_t CR1; /*!< (@ 0x40010030) Capture Register. CR 1 */
__I uint32_t CR2; /*!< (@ 0x40010034) Capture Register. CR 2 */
__I uint32_t CR3; /*!< (@ 0x40010038) Capture Register. CR 3 */
};
};
__IO uint32_t EMR; /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IO uint32_t PWMC; /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
} LPC_CT16B1_Type;
// ------------------------------------------------------------------------------------------------
// ----- CT32B0 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
__IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union {
__IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IO uint32_t MR0; /*!< (@ 0x40014018) Match Register. MR0 */
__IO uint32_t MR1; /*!< (@ 0x4001401C) Match Register. MR1 */
__IO uint32_t MR2; /*!< (@ 0x40014020) Match Register. MR2 */
__IO uint32_t MR3; /*!< (@ 0x40014024) Match Register. MR3 */
};
};
__IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
struct{
__I uint32_t CR0; /*!< (@ 0x4001402C) Capture Register. CR 0 */
__I uint32_t CR1; /*!< (@ 0x40014030) Capture Register. CR 1 */
__I uint32_t CR2; /*!< (@ 0x40014034) Capture Register. CR 2 */
__I uint32_t CR3; /*!< (@ 0x40014038) Capture Register. CR 3 */
};
};
__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
} LPC_CT32B0_Type;
// ------------------------------------------------------------------------------------------------
// ----- CT32B1 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40018000) CT32B1 Structure */
__IO uint32_t IR; /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union {
__IO uint32_t MR[4]; /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
__IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
__IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
__IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
};
};
__IO uint32_t CCR; /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__I uint32_t CR[4]; /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
struct{
__I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
__I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
__I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
__I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
};
};
__IO uint32_t EMR; /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IO uint32_t PWMC; /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
} LPC_CT32B1_Type;
// ------------------------------------------------------------------------------------------------
// ----- ADC -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x4001C000) ADC Structure */
__IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
__IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
__I uint32_t RESERVED0[1];
__IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
union{
__I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
struct{
__I uint32_t DR0; /*!< (@ 0x4001C010) A/D Channel Data Register 0*/
__I uint32_t DR1; /*!< (@ 0x4001C014) A/D Channel Data Register 1*/
__I uint32_t DR2; /*!< (@ 0x4001C018) A/D Channel Data Register 2*/
__I uint32_t DR3; /*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
__I uint32_t DR4; /*!< (@ 0x4001C020) A/D Channel Data Register 4*/
__I uint32_t DR5; /*!< (@ 0x4001C024) A/D Channel Data Register 5*/
__I uint32_t DR6; /*!< (@ 0x4001C028) A/D Channel Data Register 6*/
__I uint32_t DR7; /*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
};
};
__I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
} LPC_ADC_Type;
// ------------------------------------------------------------------------------------------------
// ----- PMU -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40038000) PMU Structure */
__IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
union{
__IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
struct{
__IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
__IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
__IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
__IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
};
};
__IO uint32_t GPREG4; /*!< (@ 0x40038014) General purpose register 4 */
} LPC_PMU_Type;
// ------------------------------------------------------------------------------------------------
// ----- FLASHCTRL -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
__I uint32_t RESERVED0[4];
__IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
__I uint32_t RESERVED1[3];
__IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
__IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
__I uint32_t RESERVED2[1];
__I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
__I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
__I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
__I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
__I uint32_t RESERVED3[1001];
__I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
__I uint32_t RESERVED4[1];
__O uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
} LPC_FLASHCTRL_Type;
// ------------------------------------------------------------------------------------------------
// ----- SSP0 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
__IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
__IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
__IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
__I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
__IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
__IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
__I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
__I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
__O uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
} LPC_SSP0_Type;
// ------------------------------------------------------------------------------------------------
// ----- IOCON -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40044000) IOCON Structure */
__IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
__IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
__IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
__IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
__IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
__IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
__IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
__IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
__IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/SWO */
__IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/TRACECLK */
__IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
__IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
__IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
__IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
__IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
__IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
__IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
__IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
__IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
__IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
__IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
__IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
__IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
__IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
__IO uint32_t PIO1_0; /*!< (@ 0x40044060) I/O configuration for pin PIO1_0/CT32B1_MAT0 */
__IO uint32_t PIO1_1; /*!< (@ 0x40044064) I/O configuration for pin PIO1_1/CT32B1_MAT1 */
__IO uint32_t PIO1_2; /*!< (@ 0x40044068) I/O configuration for pin PIO1_2/CT32B1_MAT2 */
__IO uint32_t PIO1_3; /*!< (@ 0x4004406C) I/O configuration for pin PIO1_3/CT32B1_MAT3 */
__IO uint32_t PIO1_4; /*!< (@ 0x40044070) I/O configuration for pin PIO1_4/CT32B1_CAP0 */
__IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
__IO uint32_t PIO1_6; /*!< (@ 0x40044078) I/O configuration for pin PIO1_6 */
__IO uint32_t PIO1_7; /*!< (@ 0x4004407C) I/O configuration for pin PIO1_7 */
__IO uint32_t PIO1_8; /*!< (@ 0x40044080) I/O configuration for pin PIO1_8 */
__IO uint32_t PIO1_9; /*!< (@ 0x40044084) I/O configuration for pin PIO1_9 */
__IO uint32_t PIO1_10; /*!< (@ 0x40044088) I/O configuration for pin PIO1_10 */
__IO uint32_t PIO1_11; /*!< (@ 0x4004408C) I/O configuration for pin PIO1_11 */
__IO uint32_t PIO1_12; /*!< (@ 0x40044090) I/O configuration for pin PIO1_12 */
__IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD */
__IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD */
__IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
__IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
__IO uint32_t PIO1_17; /*!< (@ 0x400440A4) I/O configuration for PIO1_17/CT16B0_CAP1/RXD */
__IO uint32_t PIO1_18; /*!< (@ 0x400440A8) I/O configuration for PIO1_18/CT16B1_CAP1/TXD */
__IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
__IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
__IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
__IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
__IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
__IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
__IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
__IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
__IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
__IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
__IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
__IO uint32_t PIO1_30; /*!< (@ 0x400440D8) I/O configuration for pin PIO1_30 */
__IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
} LPC_IOCON_Type;
// ------------------------------------------------------------------------------------------------
// ----- SYSCON -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
__IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
__IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
__IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
__I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
__IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
__I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
__I uint32_t RESERVED0[2];
__IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
__IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
__I uint32_t RESERVED1[2];
__IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
__I uint32_t RESERVED2[3];
__IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
__I uint32_t RESERVED3;
__IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
__I uint32_t RESERVED4[9];
__IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
__I uint32_t RESERVED5;
__IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
__I uint32_t RESERVED6;
__IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
__I uint32_t RESERVED7[4];
__IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
__IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
__IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
__I uint32_t RESERVED8[3];
__IO uint32_t TRACECLKDIV; /*!< (@ 0x400480AC) ARM trace clock divider */
__IO uint32_t SYSTICKCLKDIV; /*!< (@ 0x400480B0) SYSTICK clock divder */
__I uint32_t RESERVED9[3];
__IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
__I uint32_t RESERVED10;
__IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
__I uint32_t RESERVED11[5];
__IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
__I uint32_t RESERVED12;
__IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
__I uint32_t RESERVED13[5];
__I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
__I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
__I uint32_t RESERVED14[18];
__IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
__IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
__I uint32_t RESERVED15[6];
__IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
__IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
__IO uint32_t PINSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register */
__IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
__I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
__I uint32_t RESERVED16[25];
__IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
__I uint32_t RESERVED17[3];
__IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
__I uint32_t RESERVED18[6];
__IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
__IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
__IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
__I uint32_t RESERVED19[111];
__I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
} LPC_SYSCON_Type;
// ------------------------------------------------------------------------------------------------
// ----- GPIO_PIN_INT -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
__IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
__IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
__O uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
__O uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
__IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
__O uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
__O uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
__IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
__IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
__IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
} LPC_GPIO_PIN_INT_Type;
// ------------------------------------------------------------------------------------------------
// ----- SSP1 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40058000) SSP1 Structure */
__IO uint32_t CR0; /*!< (@ 0x40058000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
__IO uint32_t CR1; /*!< (@ 0x40058004) Control Register 1. Selects master/slave and other modes. */
__IO uint32_t DR; /*!< (@ 0x40058008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
__I uint32_t SR; /*!< (@ 0x4005800C) Status Register */
__IO uint32_t CPSR; /*!< (@ 0x40058010) Clock Prescale Register */
__IO uint32_t IMSC; /*!< (@ 0x40058014) Interrupt Mask Set and Clear Register */
__I uint32_t RIS; /*!< (@ 0x40058018) Raw Interrupt Status Register */
__I uint32_t MIS; /*!< (@ 0x4005801C) Masked Interrupt Status Register */
__O uint32_t ICR; /*!< (@ 0x40058020) SSPICR Interrupt Clear Register */
} LPC_SSP1_Type;
// ------------------------------------------------------------------------------------------------
// ----- GPIO_GROUP_INT0 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
__IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
__I uint32_t RESERVED0[7];
__IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
__I uint32_t RESERVED1[6];
__IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
} LPC_GPIO_GROUP_INT0_Type;
// ------------------------------------------------------------------------------------------------
// ----- GPIO_GROUP_INT1 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40060000) GPIO_GROUP_INT1 Structure */
__IO uint32_t CTRL; /*!< (@ 0x40060000) GPIO grouped interrupt control register */
__I uint32_t RESERVED0[7];
__IO uint32_t PORT_POL[2]; /*!< (@ 0x40060020) GPIO grouped interrupt port 0 polarity register */
__I uint32_t RESERVED1[6];
__IO uint32_t PORT_ENA[2]; /*!< (@ 0x40060040) GPIO grouped interrupt port 0/1 enable register */
} LPC_GPIO_GROUP_INT1_Type;
// ------------------------------------------------------------------------------------------------
// ----- Repetitive Interrupt Timer (RIT) -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40064000) RITIMER Structure */
__IO uint32_t COMPVAL; /*!< (@ 0x40064000) RITIMER compare register */
__IO uint32_t MASK; /*!< (@ 0x40064004) RITIMER mask register */
__IO uint32_t CTRL; /*!< (@ 0x40064008) RITIMER control register */
__IO uint32_t COUNTER; /*!< (@ 0x4006400C) RITIMER counter register */
__IO uint32_t COMPVAL_H; /*!< (@ 0x40064010) RITIMER compare upper register */
__IO uint32_t MASK_H; /*!< (@ 0x40064014) RITIMER mask upper register */
__I uint32_t RESERVED0[1];
__IO uint32_t COUNTER_H; /*!< (@ 0x4006401C) RITIMER counter upper register */
} LPC_RITIMER_Type;
// ------------------------------------------------------------------------------------------------
// ----- USB -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40020000) USB Structure */
__IO uint32_t DEVCMDSTAT; /*!< (@ 0x40020000) USB Device Command/Status register */
__IO uint32_t INFO; /*!< (@ 0x40020004) USB Info register */
__IO uint32_t EPLISTSTART; /*!< (@ 0x40020008) USB EP Command/Status List start address */
__IO uint32_t DATABUFSTART; /*!< (@ 0x4002000C) USB Data buffer start address */
__IO uint32_t LPM; /*!< (@ 0x40020010) Link Power Management register */
__IO uint32_t EPSKIP; /*!< (@ 0x40020014) USB Endpoint skip */
__IO uint32_t EPINUSE; /*!< (@ 0x40020018) USB Endpoint Buffer in use */
__IO uint32_t EPBUFCFG; /*!< (@ 0x4002001C) USB Endpoint Buffer Configuration register */
__IO uint32_t INTSTAT; /*!< (@ 0x40020020) USB interrupt status register */
__IO uint32_t INTEN; /*!< (@ 0x40020024) USB interrupt enable register */
__IO uint32_t INTSETSTAT; /*!< (@ 0x40020028) USB set interrupt status register */
__IO uint32_t INTROUTING; /*!< (@ 0x4002002C) USB interrupt routing register */
__I uint32_t RESERVED0[1];
__I uint32_t EPTOGGLE; /*!< (@ 0x40020034) USB Endpoint toggle register */
} LPC_USB_Type;
// ------------------------------------------------------------------------------------------------
// ----- GPIO_PORT -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x50000000) GPIO_PORT Structure */
union {
struct {
__IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
__IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
};
__IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
};
__I uint32_t RESERVED0[1008];
union {
struct {
__IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
__IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
};
__IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
};
__I uint32_t RESERVED1[960];
__IO uint32_t DIR[2]; /*!< (@ 0x50002000) Direction registers port 0/1 */
__I uint32_t RESERVED2[30];
__IO uint32_t MASK[2]; /*!< (@ 0x50002080) Mask register port 0/1 */
__I uint32_t RESERVED3[30];
__IO uint32_t PIN[2]; /*!< (@ 0x50002100) Portpin register port 0 */
__I uint32_t RESERVED4[30];
__IO uint32_t MPIN[2]; /*!< (@ 0x50002180) Masked port register port 0/1 */
__I uint32_t RESERVED5[30];
__IO uint32_t SET[2]; /*!< (@ 0x50002200) Write: Set register for port 0/1 Read: output bits for port 0/1 */
__I uint32_t RESERVED6[30];
__O uint32_t CLR[2]; /*!< (@ 0x50002280) Clear port 0/1 */
__I uint32_t RESERVED7[30];
__O uint32_t NOT[2]; /*!< (@ 0x50002300) Toggle port 0/1 */
} LPC_GPIO_Type;
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
// ------------------------------------------------------------------------------------------------
// ----- Peripheral memory map -----
// ------------------------------------------------------------------------------------------------
#define LPC_I2C_BASE (0x40000000)
#define LPC_WWDT_BASE (0x40004000)
#define LPC_USART_BASE (0x40008000)
#define LPC_CT16B0_BASE (0x4000C000)
#define LPC_CT16B1_BASE (0x40010000)
#define LPC_CT32B0_BASE (0x40014000)
#define LPC_CT32B1_BASE (0x40018000)
#define LPC_ADC_BASE (0x4001C000)
#define LPC_PMU_BASE (0x40038000)
#define LPC_FLASHCTRL_BASE (0x4003C000)
#define LPC_SSP0_BASE (0x40040000)
#define LPC_IOCON_BASE (0x40044000)
#define LPC_SYSCON_BASE (0x40048000)
#define LPC_GPIO_PIN_INT_BASE (0x4004C000)
#define LPC_SSP1_BASE (0x40058000)
#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
#define LPC_RITIMER_BASE (0x40064000)
#define LPC_USB_BASE (0x40080000)
#define LPC_GPIO_BASE (0x50000000)
// ------------------------------------------------------------------------------------------------
// ----- Peripheral declaration -----
// ------------------------------------------------------------------------------------------------
#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
#define LPC_CT16B0 ((LPC_CT16B0_Type *) LPC_CT16B0_BASE)
#define LPC_CT16B1 ((LPC_CT16B1_Type *) LPC_CT16B1_BASE)
#define LPC_CT32B0 ((LPC_CT32B0_Type *) LPC_CT32B0_BASE)
#define LPC_CT32B1 ((LPC_CT32B1_Type *) LPC_CT32B1_BASE)
#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
#define LPC_SSP0 ((LPC_SSP0_Type *) LPC_SSP0_BASE)
#define LPC_SSP1 ((LPC_SSP1_Type *) LPC_SSP1_BASE)
#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)
#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)
#define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)
#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
/** @} */ /* End of group Device_Peripheral_Registers */
/** @} */ /* End of group (null) */
/** @} */ /* End of group h1usf */
#ifdef __cplusplus
}
#endif
#endif // __LPC13UXX_H__
hw/mcu/lpc13uxx/CMSIS_CORE_LPC13Uxx/inc/core_cm3.h
+1627
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hw/mcu/lpc13uxx/CMSIS_CORE_LPC13Uxx/inc/core_cmFunc.h
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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */
hw/mcu/lpc13uxx/CMSIS_CORE_LPC13Uxx/inc/core_cmInstr.h
+688
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@@ -0,0 +1,688 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.20
* @date 05. March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */
hw/mcu/lpc13uxx/CMSIS_CORE_LPC13Uxx/inc/power_api.h
+88
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/****************************************************************************
* $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267 $
* Project: NXP LPC13Uxx software example
*
* Description:
* Power API Header File for NXP LPC13Uxx Device Series
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __LPC13UXX_POWER_API_H__
#define __LPC13UXX_POWER_API_H__
#ifdef __cplusplus
extern "C" {
#endif
#define PWRROMD_PRESENT
#define USBROMD_PRESENT
#ifdef USBROMD_PRESENT
#include "mw_usbd_rom_api.h"
#endif
typedef struct _PWRD {
void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
void (*set_power)(unsigned int cmd[], unsigned int resp[]);
} PWRD;
typedef struct _ROM {
#ifdef USBROMD_PRESENT
const USBD_API_T * pUSBD;
#else
const unsigned p_usbd;
#endif /* USBROMD_PRESENT */
const unsigned p_clib;
const unsigned p_cand;
#ifdef PWRROMD_PRESENT
const PWRD * pPWRD;
#else
const unsigned p_pwrd;
#endif /* PWRROMD_PRESENT */
const unsigned p_dev1;
const unsigned p_dev2;
const unsigned p_dev3;
const unsigned p_dev4;
} ROM;
//PLL setup related definitions
#define CPU_FREQ_EQU 0 //main PLL freq must be equal to the specified
#define CPU_FREQ_LTE 1 //main PLL freq must be less than or equal the specified
#define CPU_FREQ_GTE 2 //main PLL freq must be greater than or equal the specified
#define CPU_FREQ_APPROX 3 //main PLL freq must be as close as possible the specified
#define PLL_CMD_SUCCESS 0 //PLL setup successfully found
#define PLL_INVALID_FREQ 1 //specified freq out of range (either input or output)
#define PLL_INVALID_MODE 2 //invalid mode (see above for valid) specified
#define PLL_FREQ_NOT_FOUND 3 //specified freq not found under specified conditions
#define PLL_NOT_LOCKED 4 //PLL not locked => no changes to the PLL setup
//power setup elated definitions
#define PARAM_DEFAULT 0 //default power settings (voltage regulator, flash interface)
#define PARAM_CPU_PERFORMANCE 1 //setup for maximum CPU performance (higher current, more computation)
#define PARAM_EFFICIENCY 2 //balanced setting (power vs CPU performance)
#define PARAM_LOW_CURRENT 3 //lowest active current, lowest CPU performance
#define PARAM_CMD_SUCCESS 0 //power setting successfully found
#define PARAM_INVALID_FREQ 1 //specified freq out of range (=0 or > 50 MHz)
#define PARAM_INVALID_MODE 2 //specified mode not valid (see above for valid)
#define MAX_CLOCK_KHZ_PARAM 50000
#ifdef __cplusplus
}
#endif
#endif /* __LPC13UXX_POWER_API_H__ */
hw/mcu/lpc13uxx/CMSIS_CORE_LPC13Uxx/inc/system_LPC13Uxx.h
+64
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/**************************************************************************//**
* @file system_LPC13Uxx.h
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
* for the NXP LPC13Uxx Device Series
* @version V1.10
* @date 24. November 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __SYSTEM_LPC13Uxx_H
#define __SYSTEM_LPC13Uxx_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_LPC13Uxx_H */
hw/mcu/lpc13uxx/CMSIS_CORE_LPC13Uxx/liblinks.xml
+32
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<!-- liblinks.xml
LPCXpresso "Smart update wizard" script file
When executed on a particular application project, will
add appropriate links to the specified library project.
Note that this script assumes that the application project
contains the standard 'Debug' and 'Release' build
configurations.
-->
<project name="" update="true">
<setting id="all.compiler.inc">
<value>${workspace_loc:/CMSIS_CORE_LPC13Uxx/inc}</value>
</setting>
<setting id="all.compiler.def">
<value>__USE_CMSIS=CMSIS_CORE_LPC13Uxx</value>
</setting>
<setting id="linker.libs">
<value>CMSIS_CORE_LPC13Uxx</value>
</setting>
<setting id="linker.paths" buildType="Debug">
<value>${workspace_loc:/CMSIS_CORE_LPC13Uxx/Debug}</value>
</setting>
<setting id="linker.paths" buildType="Release">
<value>${workspace_loc:/CMSIS_CORE_LPC13Uxx/Release}</value>
</setting>
<requires msg="Library project `CMSIS_CORE_LPC13Uxx` not found">
<value>CMSIS_CORE_LPC13Uxx</value>
</requires>
</project>
hw/mcu/lpc13uxx/CMSIS_CORE_LPC13Uxx/src/system_LPC13Uxx.c
+437
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/******************************************************************************
* @file system_LPC13Uxx.c
* @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File
* for the NXP LPC13xx Device Series
* @version V1.10
* @date 24. November 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include "LPC13Uxx.h"
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
// <e> Clock Configuration
// <h> System Oscillator Control Register (SYSOSCCTRL)
// <o1.0> BYPASS: System Oscillator Bypass Enable
// <i> If enabled then PLL input (sys_osc_clk) is fed
// <i> directly from XTALIN and XTALOUT pins.
// <o1.9> FREQRANGE: System Oscillator Frequency Range
// <i> Determines frequency range for Low-power oscillator.
// <0=> 1 - 20 MHz
// <1=> 15 - 25 MHz
// </h>
//
// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
// <o2.0..4> DIVSEL: Select Divider for Fclkana
// <i> wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
// <0-31>
// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
// <0=> Undefined
// <1=> 0.5 MHz
// <2=> 0.8 MHz
// <3=> 1.1 MHz
// <4=> 1.4 MHz
// <5=> 1.6 MHz
// <6=> 1.8 MHz
// <7=> 2.0 MHz
// <8=> 2.2 MHz
// <9=> 2.4 MHz
// <10=> 2.6 MHz
// <11=> 2.7 MHz
// <12=> 2.9 MHz
// <13=> 3.1 MHz
// <14=> 3.2 MHz
// <15=> 3.4 MHz
// </h>
//
// <h> System PLL Control Register (SYSPLLCTRL)
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
// <o3.0..4> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o3.5..6> PSEL: Post Divider Selection
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
//
// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
// <o4.0..1> SEL: System PLL Clock Source
// <0=> IRC Oscillator
// <1=> System Oscillator
// <2=> Reserved
// <3=> Reserved
// </h>
//
// <h> Main Clock Source Select Register (MAINCLKSEL)
// <o5.0..1> SEL: Clock Source for Main Clock
// <0=> IRC Oscillator
// <1=> Input Clock to System PLL
// <2=> WDT Oscillator
// <3=> System PLL Clock Out
// </h>
//
// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
// <o6.0..7> DIV: System AHB Clock Divider
// <i> Divides main clock to provide system clock to core, memories, and peripherals.
// <i> 0 = is disabled
// <0-255>
// </h>
//
// <h> USB PLL Control Register (USBPLLCTRL)
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
// <o7.0..4> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o7.5..6> PSEL: Post Divider Selection
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
//
// <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
// <o8.0..1> SEL: USB PLL Clock Source
// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
// <0=> IRC Oscillator
// <1=> System Oscillator
// <2=> Reserved
// <3=> Reserved
// </h>
//
// <h> USB Clock Source Select Register (USBCLKSEL)
// <o9.0..1> SEL: System PLL Clock Source
// <0=> USB PLL out
// <1=> Main clock
// <2=> Reserved
// <3=> Reserved
// </h>
//
// <h> USB Clock Divider Register (USBCLKDIV)
// <o10.0..7> DIV: USB Clock Divider
// <i> Divides USB clock to 48 MHz.
// <i> 0 = is disabled
// <0-255>
// </h>
// </e>
*/
#define CLOCK_SETUP 1
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
#define SYSPLLCTRL_Val 0x00000025 // Reset: 0x000
#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
#define USBPLLCTRL_Val 0x00000023 // Reset: 0x000
#define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000
#define USBCLKSEL_Val 0x00000000 // Reset: 0x000
#define USBCLKDIV_Val 0x00000001 // Reset: 0x001
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
Check the register settings
*----------------------------------------------------------------------------*/
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
#define CHECK_RSVD(val, mask) (val & mask)
/* Clock Configuration -------------------------------------------------------*/
#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
#error "SYSOSCCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
#error "WDTOSCCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
#error "SYSPLLCLKSEL: Value out of range!"
#endif
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
#error "SYSPLLCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
#error "MAINCLKSEL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
#error "SYSAHBCLKDIV: Value out of range!"
#endif
#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
#error "USBPLLCLKSEL: Value out of range!"
#endif
#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
#error "USBPLLCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
#error "USBCLKSEL: Value out of range!"
#endif
#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
#error "USBCLKDIV: Value out of range!"
#endif
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __XTAL (12000000UL) /* Oscillator frequency */
#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
#if (CLOCK_SETUP) /* Clock Setup */
#if (__FREQSEL == 0)
#define __WDT_OSC_CLK ( 0) /* undefined */
#elif (__FREQSEL == 1)
#define __WDT_OSC_CLK ( 500000 / __DIVSEL)
#elif (__FREQSEL == 2)
#define __WDT_OSC_CLK ( 800000 / __DIVSEL)
#elif (__FREQSEL == 3)
#define __WDT_OSC_CLK (1100000 / __DIVSEL)
#elif (__FREQSEL == 4)
#define __WDT_OSC_CLK (1400000 / __DIVSEL)
#elif (__FREQSEL == 5)
#define __WDT_OSC_CLK (1600000 / __DIVSEL)
#elif (__FREQSEL == 6)
#define __WDT_OSC_CLK (1800000 / __DIVSEL)
#elif (__FREQSEL == 7)
#define __WDT_OSC_CLK (2000000 / __DIVSEL)
#elif (__FREQSEL == 8)
#define __WDT_OSC_CLK (2200000 / __DIVSEL)
#elif (__FREQSEL == 9)
#define __WDT_OSC_CLK (2400000 / __DIVSEL)
#elif (__FREQSEL == 10)
#define __WDT_OSC_CLK (2600000 / __DIVSEL)
#elif (__FREQSEL == 11)
#define __WDT_OSC_CLK (2700000 / __DIVSEL)
#elif (__FREQSEL == 12)
#define __WDT_OSC_CLK (2900000 / __DIVSEL)
#elif (__FREQSEL == 13)
#define __WDT_OSC_CLK (3100000 / __DIVSEL)
#elif (__FREQSEL == 14)
#define __WDT_OSC_CLK (3200000 / __DIVSEL)
#else
#define __WDT_OSC_CLK (3400000 / __DIVSEL)
#endif
/* sys_pllclkin calculation */
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
#else
#define __SYS_PLLCLKIN (0)
#endif
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
/* main clock calculation */
#if ((MAINCLKSEL_Val & 0x03) == 0)
#define __MAIN_CLOCK (__IRC_OSC_CLK)
#elif ((MAINCLKSEL_Val & 0x03) == 1)
#define __MAIN_CLOCK (__SYS_PLLCLKIN)
#elif ((MAINCLKSEL_Val & 0x03) == 2)
#if (__FREQSEL == 0)
#error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
#else
#define __MAIN_CLOCK (__WDT_OSC_CLK)
#endif
#elif ((MAINCLKSEL_Val & 0x03) == 3)
#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
#else
#define __MAIN_CLOCK (0)
#endif
#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
#else
#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
#endif // CLOCK_SETUP
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
uint32_t wdt_osc = 0;
/* Determine clock frequency according to clock register values */
switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
case 0: wdt_osc = 0; break;
case 1: wdt_osc = 500000; break;
case 2: wdt_osc = 800000; break;
case 3: wdt_osc = 1100000; break;
case 4: wdt_osc = 1400000; break;
case 5: wdt_osc = 1600000; break;
case 6: wdt_osc = 1800000; break;
case 7: wdt_osc = 2000000; break;
case 8: wdt_osc = 2200000; break;
case 9: wdt_osc = 2400000; break;
case 10: wdt_osc = 2600000; break;
case 11: wdt_osc = 2700000; break;
case 12: wdt_osc = 2900000; break;
case 13: wdt_osc = 3100000; break;
case 14: wdt_osc = 3200000; break;
case 15: wdt_osc = 3400000; break;
}
wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK;
break;
case 1: /* Input Clock to System PLL */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK;
break;
case 1: /* System oscillator */
SystemCoreClock = __SYS_OSC_CLK;
break;
case 2: /* Reserved */
case 3: /* Reserved */
SystemCoreClock = 0;
break;
}
break;
case 2: /* WDT Oscillator */
SystemCoreClock = wdt_osc;
break;
case 3: /* System PLL Clock Out */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
SystemCoreClock = __IRC_OSC_CLK;
} else {
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
}
break;
case 1: /* System oscillator */
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
SystemCoreClock = __SYS_OSC_CLK;
} else {
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
}
break;
case 2: /* Reserved */
case 3: /* Reserved */
SystemCoreClock = 0;
break;
}
break;
}
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void) {
volatile uint32_t i;
#if (CLOCK_SETUP) /* Clock Setup */
#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
for (i = 0; i < 200; i++) __NOP();
#endif
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
#endif
#if (((MAINCLKSEL_Val & 0x03) == 2) )
LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
for (i = 0; i < 200; i++) __NOP();
#endif
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
#if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */
LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
/* Regardless USB PLL is used as USB clock or not, USB PLL needs to be configured. */
LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
#else /* USB clock is not used */
LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
#endif
#endif
/* System clock to the IOCON needs to be enabled or
most of the I/O related peripherals won't work. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
}
hw/mcu/lpc13uxx/LPC13Uxx_DriverLib/inc/clkconfig.h
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/****************************************************************************
* $Id:: clkconfig.h 6172 2011-01-13 18:22:51Z usb00423 $
* Project: NXP LPC13Uxx software example
*
* Description:
* This file contains definition and prototype for clock configuration.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __CLKCONFIG_H
#define __CLKCONFIG_H
#define SYSPLL_SRC_IRC_OSC 0
#define SYSPLL_SRC_SYS_OSC 1
#define MAINCLK_SRC_IRC_OSC 0
#define MAINCLK_SRC_SYSPLL_IN 1
#define MAINCLK_SRC_WDT_OSC 2
#define MAINCLK_SRC_SYS_PLL 3
#define WDTCLK_SRC_IRC_OSC 0
#define WDTCLK_SRC_WDT_OSC 1
#define CLKOUTCLK_SRC_IRC_OSC 0
#define CLKOUTCLK_SRC_SYS_OSC 1
#define CLKOUTCLK_SRC_WDT_OSC 2
#define CLKOUTCLK_SRC_MAIN_CLK 3
void WDT_CLK_Setup(uint32_t timer_num);
void CLKOUT_Setup(uint32_t timer_num);
#endif /* end __CLKCONFIG_H */
/*****************************************************************************
** End Of File
******************************************************************************/
hw/mcu/lpc13uxx/LPC13Uxx_DriverLib/inc/gpio.h
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/****************************************************************************
* $Id:: gpio.h 6172 2011-01-13 18:22:51Z usb00423 $
* Project: NXP LPC13Uxx software example
*
* Description:
* This file contains definition and prototype for GPIO.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __GPIO_H
#define __GPIO_H
#define CHANNEL0 0
#define CHANNEL1 1
#define CHANNEL2 2
#define CHANNEL3 3
#define CHANNEL4 4
#define CHANNEL5 5
#define CHANNEL6 6
#define CHANNEL7 7
#define PORT0 0
#define PORT1 1
#define GROUP0 0
#define GROUP1 1
void PIN_INT0_IRQHandler(void);
void PIN_INT1_IRQHandler(void);
void PIN_INT2_IRQHandler(void);
void PIN_INT3_IRQHandler(void);
void PIN_INT4_IRQHandler(void);
void PIN_INT5_IRQHandler(void);
void PIN_INT6_IRQHandler(void);
void PIN_INT7_IRQHandler(void);
void GINT0_IRQHandler(void);
void GINT1_IRQHandler(void);
void GPIOInit( void );
void GPIOSetPinInterrupt( uint32_t channelNum, uint32_t portNum, uint32_t bitPosi,
uint32_t sense, uint32_t event );
void GPIOPinIntEnable( uint32_t channelNum, uint32_t event );
void GPIOPinIntDisable( uint32_t channelNum, uint32_t event );
uint32_t GPIOPinIntStatus( uint32_t channelNum );
void GPIOPinIntClear( uint32_t channelNum );
void GPIOSetGroupedInterrupt( uint32_t groupNum, uint32_t *bitPattern, uint32_t logic,
uint32_t sense, uint32_t *eventPattern );
uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi );
void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal );
void GPIOSetDir( uint32_t portNum, uint32_t bitPosi, uint32_t dir );
#endif /* end __GPIO_H */
/*****************************************************************************
** End Of File
******************************************************************************/
hw/mcu/lpc13uxx/LPC13Uxx_DriverLib/inc/nmi.h
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/****************************************************************************
* $Id:: nmi.h 6172 2011-01-13 18:22:51Z usb00423 $
* Project: NXP LPC13Uxx NMI software example
*
* Description:
* This file contains definition and prototype for NMI interrupt.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __NMI_H
#define __NMI_H
#define NMI_ENABLED 1
#define MAX_NMI_NUM 32
void NMI_Init( uint32_t NMI_num );
void NMI_Handler(void);
#endif /* end __NMI_H */
/*****************************************************************************
** End Of File
******************************************************************************/
hw/mcu/lpc13uxx/LPC13Uxx_DriverLib/inc/power_api.h
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/****************************************************************************
* $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267 $
* Project: NXP LPC13Uxx software example
*
* Description:
* Power API Header File for NXP LPC13Uxx Device Series
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __LPC13UXX_POWER_API_H__
#define __LPC13UXX_POWER_API_H__
#ifdef __cplusplus
extern "C" {
#endif
#define PWRROMD_PRESENT
#define USBROMD_PRESENT
#ifdef USBROMD_PRESENT
#include "mw_usbd_rom_api.h"
#endif
typedef struct _PWRD {
void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
void (*set_power)(unsigned int cmd[], unsigned int resp[]);
} PWRD;
typedef struct _ROM {
#ifdef USBROMD_PRESENT
const USBD_API_T * pUSBD;
#else
const unsigned p_usbd;
#endif /* USBROMD_PRESENT */
const unsigned p_clib;
const unsigned p_cand;
#ifdef PWRROMD_PRESENT
const PWRD * pPWRD;
#else
const unsigned p_pwrd;
#endif /* PWRROMD_PRESENT */
const unsigned p_dev1;
const unsigned p_dev2;
const unsigned p_dev3;
const unsigned p_dev4;
} ROM;
//PLL setup related definitions
#define CPU_FREQ_EQU 0 //main PLL freq must be equal to the specified
#define CPU_FREQ_LTE 1 //main PLL freq must be less than or equal the specified
#define CPU_FREQ_GTE 2 //main PLL freq must be greater than or equal the specified
#define CPU_FREQ_APPROX 3 //main PLL freq must be as close as possible the specified
#define PLL_CMD_SUCCESS 0 //PLL setup successfully found
#define PLL_INVALID_FREQ 1 //specified freq out of range (either input or output)
#define PLL_INVALID_MODE 2 //invalid mode (see above for valid) specified
#define PLL_FREQ_NOT_FOUND 3 //specified freq not found under specified conditions
#define PLL_NOT_LOCKED 4 //PLL not locked => no changes to the PLL setup
//power setup elated definitions
#define PARAM_DEFAULT 0 //default power settings (voltage regulator, flash interface)
#define PARAM_CPU_PERFORMANCE 1 //setup for maximum CPU performance (higher current, more computation)
#define PARAM_EFFICIENCY 2 //balanced setting (power vs CPU performance)
#define PARAM_LOW_CURRENT 3 //lowest active current, lowest CPU performance
#define PARAM_CMD_SUCCESS 0 //power setting successfully found
#define PARAM_INVALID_FREQ 1 //specified freq out of range (=0 or > 50 MHz)
#define PARAM_INVALID_MODE 2 //specified mode not valid (see above for valid)
#define MAX_CLOCK_KHZ_PARAM 50000
#ifdef __cplusplus
}
#endif
#endif /* __LPC13UXX_POWER_API_H__ */
hw/mcu/lpc13uxx/LPC13Uxx_DriverLib/inc/timer16.h
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/****************************************************************************
* $Id:: timer16.h 6956 2011-03-23 23:03:25Z usb00423 $
* Project: NXP LPC13Uxx software example
*
* Description:
* This file contains definition and prototype for 16-bit timer
* configuration.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __TIMER16_H
#define __TIMER16_H
/* The test is either MAT_OUT or CAP_IN. Default is MAT_OUT. */
#define TIMER_MATCH 0
#define EMC0 4
#define EMC1 6
#define EMC2 8
#define EMC3 10
#define MATCH0 (1<<0)
#define MATCH1 (1<<1)
#define MATCH2 (1<<2)
#define MATCH3 (1<<3)
///* For 16-bit timer, make sure that TIME_INTERVAL should be no
//greater than 0xFFFF. */
#ifndef TIME_INTERVAL
#define TIME_INTERVAL (SystemCoreClock/1000 - 1)
#endif
void delayMs(uint8_t timer_num, uint32_t delayInMs);
void CT16B0_IRQHandler(void);
void CT16B1_IRQHandler(void);
void enable_timer16(uint8_t timer_num);
void disable_timer16(uint8_t timer_num);
void reset_timer16(uint8_t timer_num);
void set_timer16_capture(uint8_t timer_num, uint8_t location );
void set_timer16_match(uint8_t timer_num, uint8_t match_enable, uint8_t location);
void init_timer16(uint8_t timer_num, uint32_t timerInterval);
void init_timer16PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable, uint8_t cap_enabled);
void setMatch_timer16PWM (uint8_t timer_num, uint8_t match_nr, uint32_t value);
#endif /* end __TIMER16_H */
/*****************************************************************************
** End Of File
******************************************************************************/
hw/mcu/lpc13uxx/LPC13Uxx_DriverLib/inc/timer32.h
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/****************************************************************************
* $Id:: timer32.h 7146 2011-04-19 19:48:01Z nxp28548 $
* Project: NXP LPC13Uxx software example
*
* Description:
* This file contains definition and prototype for 32-bit timer
* configuration.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __TIMER32_H
#define __TIMER32_H
/* The test is either MAT_OUT or CAP_IN. Default is CAP_IN. */
#ifndef TIMER_MATCH
#define TIMER_MATCH 0
#endif//TIMER_MATCH
#define EMC0 4
#define EMC1 6
#define EMC2 8
#define EMC3 10
#define MATCH0 (1<<0)
#define MATCH1 (1<<1)
#define MATCH2 (1<<2)
#define MATCH3 (1<<3)
#ifndef TIME_INTERVAL
#define TIME_INTERVAL (SystemCoreClock/100 - 1)
#endif
void delay32Ms(uint8_t timer_num, uint32_t delayInMs);
void CT32B0_IRQHandler(void);
void CT32B1_IRQHandler(void);
void enable_timer32(uint8_t timer_num);
void disable_timer32(uint8_t timer_num);
void reset_timer32(uint8_t timer_num);
void set_timer32_capture(uint8_t timer_num, uint8_t location );
void set_timer32_match(uint8_t timer_num, uint8_t match_enable, uint8_t location);
void init_timer32(uint8_t timer_num, uint32_t timerInterval);
void init_timer32PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable);
void setMatch_timer32PWM (uint8_t timer_num, uint8_t match_nr, uint32_t value);
#endif /* end __TIMER32_H */
/*****************************************************************************
** End Of File
******************************************************************************/
hw/mcu/lpc13uxx/LPC13Uxx_DriverLib/inc/type.h
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/****************************************************************************
* $Id:: type.h 6172 2011-01-13 18:22:51Z usb00423 $
* Project: NXP LPC13Uxx software example
*
* Description:
* This file contains different type definition.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __TYPE_H__
#define __TYPE_H__
#if defined (__GNUC__)
#include <stdint.h>
#else
/* exact-width signed integer types */
typedef signed char int8_t;
typedef signed short int int16_t;
typedef signed int int32_t;
//typedef signed __int64 int64_t;
/* exact-width unsigned integer types */
typedef unsigned char uint8_t;
typedef unsigned short int uint16_t;
typedef unsigned int uint32_t;
//typedef unsigned __int64 uint64_t;
#endif
#ifndef NULL
#define NULL ((void *)0)
#endif
#ifndef FALSE
#define FALSE (0)
#endif
#ifndef TRUE
#define TRUE (1)
#endif
#endif /* __TYPE_H__ */
hw/mcu/lpc13uxx/LPC13Uxx_DriverLib/inc/uart.h
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/****************************************************************************
* $Id:: uart.h 6172 2011-01-13 18:22:51Z usb00423 $
* Project: NXP LPC13Uxx software example
*
* Description:
* This file contains definition and prototype for UART configuration.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __UART_H
#define __UART_H
#define AUTOBAUD_ENABLE 0
#define FDR_CALIBRATION 0
#define RS485_ENABLED 0
#define TX_INTERRUPT 0 /* 0 if TX uses polling, 1 interrupt driven. */
#define MODEM_TEST 0
#define IER_RBR (0x01<<0)
#define IER_THRE (0x01<<1)
#define IER_RLS (0x01<<2)
#define IER_ABEO (0x01<<8)
#define IER_ABTO (0x01<<9)
#define IIR_PEND 0x01
#define IIR_RLS 0x03
#define IIR_RDA 0x02
#define IIR_CTI 0x06
#define IIR_THRE 0x01
#define IIR_ABEO (0x01<<8)
#define IIR_ABTO (0x01<<9)
#define LSR_RDR (0x01<<0)
#define LSR_OE (0x01<<1)
#define LSR_PE (0x01<<2)
#define LSR_FE (0x01<<3)
#define LSR_BI (0x01<<4)
#define LSR_THRE (0x01<<5)
#define LSR_TEMT (0x01<<6)
#define LSR_RXFE (0x01<<7)
#define BUFSIZE 0x40
/* RS485 mode definition. */
#define RS485_NMMEN (0x1<<0)
#define RS485_RXDIS (0x1<<1)
#define RS485_AADEN (0x1<<2)
#define RS485_SEL (0x1<<3)
#define RS485_DCTRL (0x1<<4)
#define RS485_OINV (0x1<<5)
void ModemInit( void );
void UARTInit(uint32_t Baudrate);
void USART_IRQHandler(void);
void UARTSend(uint8_t *BufferPtr, uint32_t Length);
void print_string( uint8_t *str_ptr );
uint8_t get_key( void );
#endif /* end __UART_H */
/*****************************************************************************
** End Of File
******************************************************************************/
hw/mcu/lpc13uxx/LPC13Uxx_DriverLib/inc/usart.h
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/****************************************************************************
* $Id:: usart.h 6172 2011-01-13 18:22:51Z usb00423 $
* Project: NXP LPC13Uxx software example
*
* Description:
* This file contains definition and prototype for UART configuration.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __USART_H
#define __USART_H
/* Synchronous mode control register definition. */
#define SYNC_ON (0x1<<0)
#define SYNC_OFF (0x0<<0)
#define SYNC_MASTER (0x1<<1)
#define SYNC_SLAVE (0x0<<1)
#define SYNC_RE (0x0<<2)
#define SYNC_FE (0x1<<2)
#define SYNC_CONT_CLK_EN (0x1<<4)
#define SYNC_CONT_CLK_DIS (0x0<<4)
#define SYNC_STARTSTOPOFF (0x1<<5)
#define SYNC_STARTSTOPON (0x0<<5)
#define SYNC_CON_CLK_CLR (0x1<<6)
#endif /* end __USART_H */
/*****************************************************************************
** End Of File
******************************************************************************/
hw/mcu/lpc13uxx/LPC13Uxx_DriverLib/src/Serial.c
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/******************************************************************************/
/* SERIAL.C: Low Level Serial Routines */
/******************************************************************************/
/* This file is part of the uVision/ARM development tools. */
/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
/* This software may only be used under the terms of a valid, current, */
/* end user licence from KEIL for a compatible version of KEIL software */
/* development tools. Nothing else gives you the right to use this software. */
/******************************************************************************/
#include "LPC13Uxx.h" /* LPC13Uxx definitions */
#include "uart.h"
#define CR 0x0D
/* implementation of putchar (also used by printf function to output data) */
int sendchar (int ch) { /* Write character to Serial Port */
if (ch == '\n') {
while (!(LPC_USART->LSR & 0x20));
LPC_USART->THR = CR; /* output CR */
}
while (!(LPC_USART->LSR & 0x20));
return (LPC_USART->THR = ch);
}
int getkey (void) { /* Read character from Serial Port */
while (!(LPC_USART->LSR & 0x01));
return (LPC_USART->RBR);
}
hw/mcu/lpc13uxx/LPC13Uxx_DriverLib/src/clkconfig.c
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/****************************************************************************
* $Id:: clkconfig.c 6874 2011-03-22 01:58:31Z usb00423 $
* Project: NXP LPC13Uxx Clock Configuration example
*
* Description:
* This file contains clock configuration code example which include
* watchdog setup and debug clock out setup.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
****************************************************************************/
#include "LPC13Uxx.h"
#include "clkconfig.h"
/*****************************************************************************
** Function name: WDT_CLK_Setup
**
** Descriptions: Configure WDT clock.
** parameters: clock source: irc_osc(0), main_clk(1), wdt_osc(2).
**
** Returned value: None
**
*****************************************************************************/
void WDT_CLK_Setup ( uint32_t clksrc )
{
/* Freq = 0.5Mhz, div_sel is 0x1F, divided by 64. WDT_OSC should be 7.8125khz */
LPC_SYSCON->WDTOSCCTRL = (0x1<<5)|0x1F;
LPC_SYSCON->PDRUNCFG &= ~(0x1<<6); /* Let WDT clock run */
/* Enables clock for WDT */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<15);
LPC_WWDT->CLKSEL = clksrc; /* Select clock source */
return;
}
/*****************************************************************************
** Function name: CLKOUT_Setup
**
** Descriptions: Configure CLKOUT for reference clock check.
** parameters: clock source: irc_osc(0), sys_osc(1), wdt_osc(2),
** main_clk(3).
**
** Returned value: None
**
*****************************************************************************/
void CLKOUT_Setup ( uint32_t clksrc )
{
/* debug PLL after configuration. */
LPC_SYSCON->CLKOUTSEL = clksrc; /* Select Main clock */
LPC_SYSCON->CLKOUTDIV = 1; /* Divided by 1 */
return;
}
hw/mcu/lpc13uxx/LPC13Uxx_DriverLib/src/gpio.c
+838
View File
@@ -0,0 +1,838 @@
/****************************************************************************
* $Id:: gpio.c 6874 2011-03-22 01:58:31Z usb00423 $
* Project: NXP LPC13Uxx GPIO example
*
* Description:
* This file contains GPIO code example which include GPIO
* initialization, GPIO interrupt handler, and related APIs for
* GPIO access.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
****************************************************************************/
#include "LPC13Uxx.h" /* LPC13Uxx Peripheral Registers */
#include "gpio.h"
volatile uint32_t pin_int0_counter = 0;
volatile uint32_t pin_int1_counter = 0;
volatile uint32_t pin_int2_counter = 0;
volatile uint32_t pin_int3_counter = 0;
volatile uint32_t pin_int4_counter = 0;
volatile uint32_t pin_int5_counter = 0;
volatile uint32_t pin_int6_counter = 0;
volatile uint32_t pin_int7_counter = 0;
volatile uint32_t gint0_counter = 0;
volatile uint32_t gint1_counter = 0;
volatile uint32_t pin_int0_level_counter = 0;
volatile uint32_t pin_int0_rising_edge_counter = 0;
volatile uint32_t pin_int0_falling_edge_counter = 0;
volatile uint32_t pin_int1_level_counter = 0;
volatile uint32_t pin_int1_rising_edge_counter = 0;
volatile uint32_t pin_int1_falling_edge_counter = 0;
volatile uint32_t pin_int2_level_counter = 0;
volatile uint32_t pin_int2_rising_edge_counter = 0;
volatile uint32_t pin_int2_falling_edge_counter = 0;
volatile uint32_t pin_int3_level_counter = 0;
volatile uint32_t pin_int3_rising_edge_counter = 0;
volatile uint32_t pin_int3_falling_edge_counter = 0;
volatile uint32_t pin_int4_level_counter = 0;
volatile uint32_t pin_int4_rising_edge_counter = 0;
volatile uint32_t pin_int4_falling_edge_counter = 0;
volatile uint32_t pin_int5_level_counter = 0;
volatile uint32_t pin_int5_rising_edge_counter = 0;
volatile uint32_t pin_int5_falling_edge_counter = 0;
volatile uint32_t pin_int6_level_counter = 0;
volatile uint32_t pin_int6_rising_edge_counter = 0;
volatile uint32_t pin_int6_falling_edge_counter = 0;
volatile uint32_t pin_int7_level_counter = 0;
volatile uint32_t pin_int7_rising_edge_counter = 0;
volatile uint32_t pin_int7_falling_edge_counter = 0;
volatile uint32_t gint0_level_counter = 0;
volatile uint32_t gint0_edge_counter = 0;
volatile uint32_t gint1_level_counter = 0;
volatile uint32_t gint1_edge_counter = 0;
/*****************************************************************************
** Function name: PIN_INT0_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void PIN_INT0_IRQHandler(void)
{
pin_int0_counter++;
if ( LPC_GPIO_PIN_INT->IST & (0x1<<0) )
{
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<0) )
{
pin_int0_level_counter++;
}
else
{
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<0) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<0) ) )
{
pin_int0_rising_edge_counter++;
LPC_GPIO_PIN_INT->RISE = 0x1<<0;
}
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<0) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<0) ) )
{
pin_int0_falling_edge_counter++;
LPC_GPIO_PIN_INT->FALL = 0x1<<0;
}
LPC_GPIO_PIN_INT->IST = 0x1<<0;
}
}
return;
}
/*****************************************************************************
** Function name: PIN_INT1_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void PIN_INT1_IRQHandler(void)
{
pin_int1_counter++;
if ( LPC_GPIO_PIN_INT->IST & (0x1<<1) )
{
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<1) )
{
pin_int1_level_counter++;
}
else
{
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<1) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<1) ) )
{
pin_int1_rising_edge_counter++;
LPC_GPIO_PIN_INT->RISE = 0x1<<1;
}
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<1) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<1) ) )
{
pin_int1_falling_edge_counter++;
LPC_GPIO_PIN_INT->FALL = 0x1<<1;
}
LPC_GPIO_PIN_INT->IST = 0x1<<1;
}
}
return;
}
/*****************************************************************************
** Function name: PIN_INT2_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void PIN_INT2_IRQHandler(void)
{
pin_int2_counter++;
if ( LPC_GPIO_PIN_INT->IST & (0x1<<2) )
{
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<2) )
{
pin_int2_level_counter++;
}
else
{
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<2) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<2) ) )
{
pin_int2_rising_edge_counter++;
LPC_GPIO_PIN_INT->RISE = 0x1<<2;
}
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<2) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<2) ) )
{
pin_int2_falling_edge_counter++;
LPC_GPIO_PIN_INT->FALL = 0x1<<2;
}
LPC_GPIO_PIN_INT->IST = 0x1<<2;
}
}
return;
}
/*****************************************************************************
** Function name: PIN_INT3_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void PIN_INT3_IRQHandler(void)
{
pin_int3_counter++;
if ( LPC_GPIO_PIN_INT->IST & (0x1<<3) )
{
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<3) )
{
pin_int3_level_counter++;
}
else
{
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<3) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<3) ) )
{
pin_int3_rising_edge_counter++;
LPC_GPIO_PIN_INT->RISE = 0x1<<3;
}
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<3) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<3) ) )
{
pin_int3_falling_edge_counter++;
LPC_GPIO_PIN_INT->FALL = 0x1<<3;
}
LPC_GPIO_PIN_INT->IST = 0x1<<3;
}
}
return;
}
/*****************************************************************************
** Function name: PIN_INT4_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void PIN_INT4_IRQHandler(void)
{
pin_int4_counter++;
if ( LPC_GPIO_PIN_INT->IST & (0x1<<4) )
{
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<4) )
{
pin_int4_level_counter++;
}
else
{
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<4) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<4) ) )
{
pin_int4_rising_edge_counter++;
LPC_GPIO_PIN_INT->RISE = 0x1<<4;
}
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<4) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<4) ) )
{
pin_int4_falling_edge_counter++;
LPC_GPIO_PIN_INT->FALL = 0x1<<4;
}
LPC_GPIO_PIN_INT->IST = 0x1<<4;
}
}
return;
}
/*****************************************************************************
** Function name: PIN_INT5_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void PIN_INT5_IRQHandler(void)
{
pin_int5_counter++;
if ( LPC_GPIO_PIN_INT->IST & (0x1<<5) )
{
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<5) )
{
pin_int5_level_counter++;
}
else
{
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<5) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<5) ) )
{
pin_int5_rising_edge_counter++;
LPC_GPIO_PIN_INT->RISE = 0x1<<5;
}
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<5) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<5) ) )
{
pin_int5_falling_edge_counter++;
LPC_GPIO_PIN_INT->FALL = 0x1<<5;
}
LPC_GPIO_PIN_INT->IST = 0x1<<5;
}
}
return;
}
/*****************************************************************************
** Function name: PIN_INT6_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void PIN_INT6_IRQHandler(void)
{
pin_int6_counter++;
if ( LPC_GPIO_PIN_INT->IST & (0x1<<6) )
{
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<6) )
{
pin_int6_level_counter++;
}
else
{
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<6) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<6) ) )
{
pin_int6_rising_edge_counter++;
LPC_GPIO_PIN_INT->RISE = 0x1<<6;
}
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<6) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<6) ) )
{
pin_int6_falling_edge_counter++;
LPC_GPIO_PIN_INT->FALL = 0x1<<6;
}
LPC_GPIO_PIN_INT->IST = 0x1<<6;
}
}
return;
}
/*****************************************************************************
** Function name: PIN_INT7_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void PIN_INT7_IRQHandler(void)
{
pin_int7_counter++;
if ( LPC_GPIO_PIN_INT->IST & (0x1<<7) )
{
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<7) )
{
pin_int7_level_counter++;
}
else
{
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<7) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<7) ) )
{
pin_int7_rising_edge_counter++;
LPC_GPIO_PIN_INT->RISE = 0x1<<7;
}
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<7) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<7) ) )
{
pin_int7_falling_edge_counter++;
LPC_GPIO_PIN_INT->FALL = 0x1<<7;
}
LPC_GPIO_PIN_INT->IST = 0x1<<7;
}
}
return;
}
/*****************************************************************************
** Function name: GINT0_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void GINT0_IRQHandler(void)
{
gint0_counter++;
if ( LPC_GPIO_GROUP_INT0->CTRL & (0x1<<0) )
{
if ( LPC_GPIO_GROUP_INT0->CTRL & (0x1<<2) )
{
gint0_level_counter++;
}
else
{
gint0_edge_counter++;
}
LPC_GPIO_GROUP_INT0->CTRL |= (0x1<<0);
}
return;
}
/*****************************************************************************
** Function name: GINT1_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void GINT1_IRQHandler(void)
{
gint1_counter++;
if ( LPC_GPIO_GROUP_INT1->CTRL & (0x1<<0) )
{
if ( LPC_GPIO_GROUP_INT1->CTRL & (0x1<<2) )
{
gint1_level_counter++;
}
else
{
gint1_edge_counter++;
}
LPC_GPIO_GROUP_INT1->CTRL |= (0x1<<0);
}
return;
}
/*****************************************************************************
** Function name: GPIOInit
**
** Descriptions: Initialize GPIO, install the
** GPIO interrupt handler
**
** parameters: None
**
** Returned value: true or false, return false if the VIC table
** is full and GPIO interrupt handler can be
** installed.
**
*****************************************************************************/
void GPIOInit( void )
{
/* Enable AHB clock to the GPIO domain. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
/* Enable AHB clock to the PinInt, GroupedInt domain. */
LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24));
return;
}
/*****************************************************************************
** Function name: GPIOSetPinInterrupt
**
** Descriptions: Set interrupt sense, event, etc.
** sense: edge or level, 0 is edge, 1 is level
** event/polarity: 0 is active low/falling, 1 is high/rising.
**
** parameters: channel #, port #, bit position, sense, event(polarity)
**
** Returned value: None
**
*****************************************************************************/
void GPIOSetPinInterrupt( uint32_t channelNum, uint32_t portNum, uint32_t bitPosi,
uint32_t sense, uint32_t event )
{
switch ( channelNum )
{
case CHANNEL0:
if ( portNum )
{
LPC_SYSCON->PINSEL[0] = bitPosi + 24;
}
else
{
LPC_SYSCON->PINSEL[0] = bitPosi;
}
NVIC_EnableIRQ(PIN_INT0_IRQn);
break;
case CHANNEL1:
if ( portNum )
{
LPC_SYSCON->PINSEL[1] = bitPosi + 24;
}
else
{
LPC_SYSCON->PINSEL[1] = bitPosi;
}
NVIC_EnableIRQ(PIN_INT1_IRQn);
break;
case CHANNEL2:
if ( portNum )
{
LPC_SYSCON->PINSEL[2] = bitPosi + 24;
}
else
{
LPC_SYSCON->PINSEL[2] = bitPosi;
}
NVIC_EnableIRQ(PIN_INT2_IRQn);
break;
case CHANNEL3:
if ( portNum )
{
LPC_SYSCON->PINSEL[3] = bitPosi + 24;
}
else
{
LPC_SYSCON->PINSEL[3] = bitPosi;
}
NVIC_EnableIRQ(PIN_INT3_IRQn);
break;
case CHANNEL4:
if ( portNum )
{
LPC_SYSCON->PINSEL[4] = bitPosi + 24;
}
else
{
LPC_SYSCON->PINSEL[4] = bitPosi;
}
NVIC_EnableIRQ(PIN_INT4_IRQn);
break;
case CHANNEL5:
if ( portNum )
{
LPC_SYSCON->PINSEL[5] = bitPosi + 24;
}
else
{
LPC_SYSCON->PINSEL[5] = bitPosi;
}
NVIC_EnableIRQ(PIN_INT5_IRQn);
break;
case CHANNEL6:
if ( portNum )
{
LPC_SYSCON->PINSEL[6] = bitPosi + 24;
}
else
{
LPC_SYSCON->PINSEL[6] = bitPosi;
}
NVIC_EnableIRQ(PIN_INT6_IRQn);
break;
case CHANNEL7:
if ( portNum )
{
LPC_SYSCON->PINSEL[7] = bitPosi + 24;
}
else
{
LPC_SYSCON->PINSEL[7] = bitPosi;
}
NVIC_EnableIRQ(PIN_INT7_IRQn);
break;
default:
break;
}
if ( sense == 0 )
{
LPC_GPIO_PIN_INT->ISEL &= ~(0x1<<channelNum); /* Edge trigger */
if ( event == 0 )
{
LPC_GPIO_PIN_INT->IENF |= (0x1<<channelNum); /* faling edge */
}
else
{
LPC_GPIO_PIN_INT->IENR |= (0x1<<channelNum); /* Rising edge */
}
}
else
{
LPC_GPIO_PIN_INT->ISEL |= (0x1<<channelNum); /* Level trigger. */
LPC_GPIO_PIN_INT->IENR |= (0x1<<channelNum); /* Level enable */
if ( event == 0 )
{
LPC_GPIO_PIN_INT->IENF &= ~(0x1<<channelNum); /* active-low */
}
else
{
LPC_GPIO_PIN_INT->IENF |= (0x1<<channelNum); /* active-high */
}
}
return;
}
/*****************************************************************************
** Function name: GPIOPinIntEnable
**
** Descriptions: Enable Interrupt
**
** parameters: channel num, event(0 is falling edge, 1 is rising edge)
** Returned value: None
**
*****************************************************************************/
void GPIOPinIntEnable( uint32_t channelNum, uint32_t event )
{
if ( !( LPC_GPIO_PIN_INT->ISEL & (0x1<<channelNum) ) )
{
if ( event == 0 )
{
LPC_GPIO_PIN_INT->SIENF |= (0x1<<channelNum); /* faling edge */
}
else
{
LPC_GPIO_PIN_INT->SIENR |= (0x1<<channelNum); /* Rising edge */
}
}
else
{
LPC_GPIO_PIN_INT->SIENR |= (0x1<<channelNum); /* Level */
}
return;
}
/*****************************************************************************
** Function name: GPIOPinIntDisable
**
** Descriptions: Disable Interrupt
**
** parameters: channel num, event(0 is falling edge, 1 is rising edge)
**
** Returned value: None
**
*****************************************************************************/
void GPIOPinIntDisable( uint32_t channelNum, uint32_t event )
{
if ( !( LPC_GPIO_PIN_INT->ISEL & (0x1<<channelNum) ) )
{
if ( event == 0 )
{
LPC_GPIO_PIN_INT->CIENF |= (0x1<<channelNum); /* faling edge */
}
else
{
LPC_GPIO_PIN_INT->CIENR |= (0x1<<channelNum); /* Rising edge */
}
}
else
{
LPC_GPIO_PIN_INT->CIENR |= (0x1<<channelNum); /* Level */
}
return;
}
/*****************************************************************************
** Function name: GPIOPinIntStatus
**
** Descriptions: Get Interrupt status
**
** parameters: channel num
**
** Returned value: None
**
*****************************************************************************/
uint32_t GPIOPinIntStatus( uint32_t channelNum )
{
if ( LPC_GPIO_PIN_INT->IST & (0x1<<channelNum) )
{
return( 1 );
}
else
{
return( 0 );
}
}
/*****************************************************************************
** Function name: GPIOPinIntClear
**
** Descriptions: Clear Interrupt
**
** parameters: channel num
**
** Returned value: None
**
*****************************************************************************/
void GPIOPinIntClear( uint32_t channelNum )
{
if ( !( LPC_GPIO_PIN_INT->ISEL & (0x1<<channelNum) ) )
{
LPC_GPIO_PIN_INT->IST = (1<<channelNum);
}
return;
}
/*****************************************************************************
** Function name: GPIOSetGroupedInterrupt
**
** Descriptions: Set interrupt logic, sense, eventPattern, etc.
** logic: AND or OR, 0 is OR, 1 is AND
** sensePattern: edge or level, 0 is edge, 1 is level
** event/polarity: 0 is active low/falling, 1 is high/rising.
**
** parameters: group #, bit pattern, logic, sense, event(polarity) pattern
**
** Returned value: None
**
*****************************************************************************/
void GPIOSetGroupedInterrupt( uint32_t groupNum, uint32_t *bitPattern, uint32_t logic,
uint32_t sense, uint32_t *eventPattern )
{
switch ( groupNum )
{
case GROUP0:
if ( sense == 0 )
{
LPC_GPIO_GROUP_INT0->CTRL &= ~(0x1<<2); /* Edge trigger */
}
else
{
LPC_GPIO_GROUP_INT0->CTRL |= (0x1<<2); /* Level trigger. */
}
if ( logic == 0 )
{
LPC_GPIO_GROUP_INT0->CTRL &= ~(0x1<<1); /* OR */
}
else
{
LPC_GPIO_GROUP_INT0->CTRL |= (0x1<<1); /* AND */
}
LPC_GPIO_GROUP_INT0->PORT_POL[0] = *((uint32_t *)(eventPattern + 0));
LPC_GPIO_GROUP_INT0->PORT_POL[1] = *((uint32_t *)(eventPattern + 1));
LPC_GPIO_GROUP_INT0->PORT_ENA[0] = *((uint32_t *)(bitPattern + 0));
LPC_GPIO_GROUP_INT0->PORT_ENA[1] = *((uint32_t *)(bitPattern + 1));
/* as soon as enabled, an edge may be generated */
/* clear interrupt flag and NVIC pending interrupt to */
/* workaround the potential edge generated as enabled */
LPC_GPIO_GROUP_INT0->CTRL |= (1<<0);
NVIC_ClearPendingIRQ(GINT0_IRQn);
NVIC_EnableIRQ(GINT0_IRQn);
break;
case GROUP1:
if ( sense == 0 )
{
LPC_GPIO_GROUP_INT1->CTRL &= ~(0x1<<2); /* Edge trigger */
}
else
{
LPC_GPIO_GROUP_INT1->CTRL |= (0x1<<2); /* Level trigger. */
}
if ( logic == 0 )
{
LPC_GPIO_GROUP_INT1->CTRL &= ~(0x1<<1); /* OR */
}
else
{
LPC_GPIO_GROUP_INT1->CTRL |= (0x1<<1); /* AND */
}
LPC_GPIO_GROUP_INT1->PORT_POL[0] = *((uint32_t *)(eventPattern + 0));
LPC_GPIO_GROUP_INT1->PORT_POL[1] = *((uint32_t *)(eventPattern + 1));
LPC_GPIO_GROUP_INT1->PORT_ENA[0] = *((uint32_t *)(bitPattern + 0));
LPC_GPIO_GROUP_INT1->PORT_ENA[1] = *((uint32_t *)(bitPattern + 1));
/* as soon as enabled, an edge may be generated */
/* clear interrupt flag and NVIC pending interrupt to */
/* workaround the potential edge generated as enabled */
LPC_GPIO_GROUP_INT1->CTRL |= (1<<0);
NVIC_ClearPendingIRQ(GINT1_IRQn);
NVIC_EnableIRQ(GINT1_IRQn);
break;
default:
break;
}
return;
}
/*****************************************************************************
** Function name: GPIOGetPinValue
**
** Descriptions: Read Current state of port pin, PIN register value
**
** parameters: port num, bit position
** Returned value: None
**
*****************************************************************************/
uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi )
{
uint32_t regVal = 0;
if( bitPosi < 0x20 )
{
if ( LPC_GPIO->PIN[portNum] & (0x1<<bitPosi) )
{
regVal = 1;
}
}
else if( bitPosi == 0xFF )
{
regVal = LPC_GPIO->PIN[portNum];
}
return ( regVal );
}
/*****************************************************************************
** Function name: GPIOSetBitValue
**
** Descriptions: Set/clear a bit in a specific position
**
** parameters: port num, bit position, bit value
**
** Returned value: None
**
*****************************************************************************/
void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal )
{
if ( bitVal )
{
LPC_GPIO->SET[portNum] = 1<<bitPosi;
}
else
{
LPC_GPIO->CLR[portNum] = 1<<bitPosi;
}
return;
}
/*****************************************************************************
** Function name: GPIOSetDir
**
** Descriptions: Set the direction in GPIO port
**
** parameters: portNum, bit position, direction (1 out, 0 input)
**
** Returned value: None
**
*****************************************************************************/
void GPIOSetDir( uint32_t portNum, uint32_t bitPosi, uint32_t dir )
{
if( dir )
{
LPC_GPIO->DIR[portNum] |= (1<<bitPosi);
}
else
{
LPC_GPIO->DIR[portNum] &= ~(1<<bitPosi);
}
return;
}
/******************************************************************************
** End Of File
******************************************************************************/
hw/mcu/lpc13uxx/LPC13Uxx_DriverLib/src/nmi.c
+95
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@@ -0,0 +1,95 @@
/****************************************************************************
* $Id:: nmi.c 7227 2011-04-27 20:20:38Z usb01267 $
* Project: NXP LPC13Uxx NMI interrupt example
*
* Description:
* This file contains NMI interrupt handler code example.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
****************************************************************************/
#include "LPC13Uxx.h"
#include "nmi.h"
#if NMI_ENABLED
volatile uint32_t NMI_Counter[MAX_NMI_NUM];
/*****************************************************************************
** Function name: NMI_Handler
**
** Descriptions: NMI interrupt handler
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void NMI_Handler( void )
{
uint32_t regVal;
regVal = LPC_SYSCON->NMISRC;
regVal &= ~0x80000000;
if ( regVal < MAX_NMI_NUM )
{
if ( regVal == CT16B0_IRQn )
{
/* Use TIMER16_0_IRQHandler as example for real application. */
LPC_CT16B0->IR = 0xFF; /* Clear timer16_0 interrupt */
}
else if ( regVal == CT16B1_IRQn )
{
/* Use TIMER16_1_IRQHandler as example for real application. */
LPC_CT16B1->IR = 0xFF; /* Clear timer16_1 interrupt */
}
else if ( regVal == CT32B0_IRQn )
{
/* Use TIMER32_0_IRQHandler as example for real application. */
LPC_CT32B0->IR = 0xFF; /* Clear timer32_0 interrupt */
}
else if ( regVal == CT32B1_IRQn )
{
/* Use TIMER32_0_IRQHandler as example for real application. */
LPC_CT32B1->IR = 0xFF; /* Clear timer32_1 interrupt */
}
NMI_Counter[regVal]++;
}
return;
}
/*****************************************************************************
** Function name: NMI_Init
**
** Descriptions: NMI initialization
** parameters: NMI number
**
** Returned value: None
**
*****************************************************************************/
void NMI_Init( uint32_t NMI_num )
{
uint32_t i;
for ( i = 0; i < MAX_NMI_NUM; i++ )
{
NMI_Counter[i] = 0x0;
}
LPC_SYSCON->NMISRC = 0x80000000|NMI_num;
return;
}
#endif
hw/mcu/lpc13uxx/LPC13Uxx_DriverLib/src/timer16.c
+628
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@@ -0,0 +1,628 @@
/****************************************************************************
* $Id:: timer16.c 6950 2011-03-23 22:09:44Z usb00423 $
* Project: NXP LPC13Uxx 16-bit timer example
*
* Description:
* This file contains 16-bit timer code example which include timer
* initialization, timer interrupt handler, and related APIs for
* timer setup.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
****************************************************************************/
#include "LPC13Uxx.h"
#include "timer16.h"
#include "nmi.h"
volatile uint32_t timer16_0_counter[4] = {0,0,0,0};
volatile uint32_t timer16_1_counter[4] = {0,0,0,0};
volatile uint32_t timer16_0_capture[4] = {0,0,0,0};
volatile uint32_t timer16_1_capture[4] = {0,0,0,0};
volatile uint32_t timer16_0_period = 0;
volatile uint32_t timer16_1_period = 0;
/*****************************************************************************
** Function name: delayMs
**
** Descriptions: Start the timer delay in milo seconds
** until elapsed
**
** parameters: timer number, Delay value in milo second
**
** Returned value: None
**
*****************************************************************************/
void delayMs(uint8_t timer_num, uint32_t delayInMs)
{
if (timer_num == 0)
{
/*
* setup timer #0 for delay
*/
LPC_CT16B0->TCR = 0x02; /* reset timer */
LPC_CT16B0->PR = 0x00; /* set prescaler to zero */
LPC_CT16B0->MR0 = delayInMs * (SystemCoreClock / 1000);
LPC_CT16B0->IR = 0xff; /* reset all interrrupts */
LPC_CT16B0->MCR = 0x04; /* stop timer on match */
LPC_CT16B0->TCR = 0x01; /* start timer */
/* wait until delay time has elapsed */
while (LPC_CT16B0->TCR & 0x01);
}
else if (timer_num == 1)
{
/*
* setup timer #1 for delay
*/
LPC_CT16B1->TCR = 0x02; /* reset timer */
LPC_CT16B1->PR = 0x00; /* set prescaler to zero */
LPC_CT16B1->MR0 = delayInMs * (SystemCoreClock / 1000);
LPC_CT16B1->IR = 0xff; /* reset all interrrupts */
LPC_CT16B1->MCR = 0x04; /* stop timer on match */
LPC_CT16B1->TCR = 0x01; /* start timer */
/* wait until delay time has elapsed */
while (LPC_CT16B1->TCR & 0x01);
}
return;
}
/******************************************************************************
** Function name: CT16B0_IRQHandler
**
** Descriptions: Timer/CounterX and CaptureX interrupt handler
**
** parameters: None
** Returned value: None
**
******************************************************************************/
void CT16B0_IRQHandler(void)
{
if ( LPC_CT16B0->IR & (0x1<<0) )
{
LPC_CT16B0->IR = 0x1<<0; /* clear interrupt flag */
timer16_0_counter[0]++;
}
if ( LPC_CT16B0->IR & (0x1<<1) )
{
LPC_CT16B0->IR = 0x1<<1; /* clear interrupt flag */
timer16_0_counter[1]++;
}
if ( LPC_CT16B0->IR & (0x1<<2) )
{
LPC_CT16B0->IR = 0x1<<2; /* clear interrupt flag */
timer16_0_counter[2]++;
}
if ( LPC_CT16B0->IR & (0x1<<3) )
{
LPC_CT16B0->IR = 0x1<<3; /* clear interrupt flag */
timer16_0_counter[3]++;
}
if ( LPC_CT16B0->IR & (0x1<<4) )
{
LPC_CT16B0->IR = 0x1<<4; /* clear interrupt flag */
timer16_0_capture[0]++;
}
if ( LPC_CT16B0->IR & (0x1<<5) )
{
LPC_CT16B0->IR = 0x1<<5; /* clear interrupt flag */
timer16_0_capture[1]++;
}
if ( LPC_CT16B0->IR & (0x1<<6) )
{
LPC_CT16B0->IR = 0x1<<6; /* clear interrupt flag */
timer16_0_capture[2]++;
}
if ( LPC_CT16B0->IR & (0x1<<7) )
{
LPC_CT16B0->IR = 0x1<<7; /* clear interrupt flag */
timer16_0_capture[3]++;
}
return;
}
/******************************************************************************
** Function name: CT16B1_IRQHandler
**
** Descriptions: Timer/CounterX and CaptureX interrupt handler
**
** parameters: None
** Returned value: None
**
******************************************************************************/
void CT16B1_IRQHandler(void)
{
if ( LPC_CT16B1->IR & (0x1<<0) )
{
LPC_CT16B1->IR = 0x1<<0; /* clear interrupt flag */
timer16_1_counter[0]++;
}
if ( LPC_CT16B1->IR & (0x1<<1) )
{
LPC_CT16B1->IR = 0x1<<1; /* clear interrupt flag */
timer16_1_counter[1]++;
}
if ( LPC_CT16B1->IR & (0x1<<2) )
{
LPC_CT16B1->IR = 0x1<<2; /* clear interrupt flag */
timer16_1_counter[2]++;
}
if ( LPC_CT16B1->IR & (0x1<<3) )
{
LPC_CT16B1->IR = 0x1<<3; /* clear interrupt flag */
timer16_1_counter[3]++;
}
if ( LPC_CT16B1->IR & (0x1<<4) )
{
LPC_CT16B1->IR = 0x1<<4; /* clear interrupt flag */
timer16_1_capture[0]++;
}
if ( LPC_CT16B1->IR & (0x1<<5) )
{
LPC_CT16B1->IR = 0x1<<5; /* clear interrupt flag */
timer16_1_capture[1]++;
}
if ( LPC_CT16B1->IR & (0x1<<6) )
{
LPC_CT16B1->IR = 0x1<<6; /* clear interrupt flag */
timer16_1_capture[2]++;
}
if ( LPC_CT16B1->IR & (0x1<<7) )
{
LPC_CT16B1->IR = 0x1<<7; /* clear interrupt flag */
timer16_1_capture[3]++;
}
return;
}
/******************************************************************************
** Function name: enable_timer
**
** Descriptions: Enable timer
**
** parameters: timer number: 0 or 1
** Returned value: None
**
******************************************************************************/
void enable_timer16(uint8_t timer_num)
{
if ( timer_num == 0 )
{
LPC_CT16B0->TCR = 1;
}
else
{
LPC_CT16B1->TCR = 1;
}
return;
}
/******************************************************************************
** Function name: disable_timer
**
** Descriptions: Disable timer
**
** parameters: timer number: 0 or 1
** Returned value: None
**
******************************************************************************/
void disable_timer16(uint8_t timer_num)
{
if ( timer_num == 0 )
{
LPC_CT16B0->TCR = 0;
}
else
{
LPC_CT16B1->TCR = 0;
}
return;
}
/******************************************************************************
** Function name: reset_timer
**
** Descriptions: Reset timer
**
** parameters: timer number: 0 or 1
** Returned value: None
**
******************************************************************************/
void reset_timer16(uint8_t timer_num)
{
uint32_t regVal;
if ( timer_num == 0 )
{
regVal = LPC_CT16B0->TCR;
regVal |= 0x02;
LPC_CT16B0->TCR = regVal;
}
else
{
regVal = LPC_CT16B1->TCR;
regVal |= 0x02;
LPC_CT16B1->TCR = regVal;
}
return;
}
/******************************************************************************
** Function name: Set_timer_capture
**
** Descriptions: set timer capture based on LOC number.
**
** parameters: timer number and location number
** Returned value: None
**
******************************************************************************/
void set_timer16_capture(uint8_t timer_num, uint8_t location )
{
if ( timer_num == 0 )
{
/* Timer0_16 I/O config */
if ( location == 0 )
{
LPC_IOCON->PIO1_16 &= ~0x07;
LPC_IOCON->PIO1_16 |= 0x02; /* Timer0_16 CAP0 */
LPC_IOCON->PIO1_17 &= ~0x07;
LPC_IOCON->PIO1_17 |= 0x01; /* Timer0_16 CAP2 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO0_2 &= ~0x07;
LPC_IOCON->PIO0_2 |= 0x02; /* Timer0_16 CAP0 */
}
else
{
while ( 1 ); /* Fatal location number error */
}
}
else
{
/* Timer1_16 I/O config */
if ( location == 0 )
{
LPC_IOCON->PIO0_20 &= ~0x07; /* Timer1_16 I/O config */
LPC_IOCON->PIO0_20 |= 0x01; /* Timer1_16 CAP0 */
LPC_IOCON->PIO1_18 &= ~0x07;
LPC_IOCON->PIO1_18 |= 0x01; /* Timer1_16 CAP1 */
}
else
{
while ( 1 ); /* Fatal location number error */
}
}
return;
}
/******************************************************************************
** Function name: Set_timer_match
**
** Descriptions: set timer match based on LOC number.
**
** parameters: timer number, match enable, and location number
** Returned value: None
**
******************************************************************************/
void set_timer16_match(uint8_t timer_num, uint8_t match_enable, uint8_t location)
{
if ( timer_num == 0 )
{
if ( match_enable & 0x01 )
{
/* Timer0_16 I/O config */
if ( location == 0 )
{
LPC_IOCON->PIO0_8 &= ~0x07;
LPC_IOCON->PIO0_8 |= 0x02; /* Timer0_16 MAT0 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO1_13 &= ~0x07;
LPC_IOCON->PIO1_13 |= 0x02; /* Timer0_16 MAT0 */
}
}
if ( match_enable & 0x02 )
{
/* Timer0_16 I/O config */
if ( location == 0 )
{
LPC_IOCON->PIO0_9 &= ~0x07;
LPC_IOCON->PIO0_9 |= 0x02; /* Timer0_16 MAT1 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO1_14 &= ~0x07;
LPC_IOCON->PIO1_14 |= 0x02; /* Timer0_16 MAT1 */
}
}
if ( match_enable & 0x04 )
{
/* Timer0_16 I/O config */
if ( location == 0 )
{
#ifdef __SWD_DISABLED
LPC_IOCON->SWCLK_PIO0_10 &= ~0x07;
LPC_IOCON->SWCLK_PIO0_10 |= 0x03; /* Timer0_16 MAT2 */
#endif
}
else if ( location == 1 )
{
LPC_IOCON->PIO1_15 &= ~0x07;
LPC_IOCON->PIO1_15 |= 0x02; /* Timer0_16 MAT2 */
}
}
}
else if ( timer_num == 1 )
{
if ( match_enable & 0x01 )
{
/* Timer1_16 I/O config */
if ( location == 0 )
{
LPC_IOCON->PIO0_21 &= ~0x07;
LPC_IOCON->PIO0_21 |= 0x01; /* Timer1_16 MAT0 */
}
}
if ( match_enable & 0x02 )
{
/* Timer1_16 I/O config */
if ( location == 0 )
{
LPC_IOCON->PIO0_22 &= ~0x07;
LPC_IOCON->PIO0_22 |= 0x02; /* Timer1_16 MAT1 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO1_23 &= ~0x07;
LPC_IOCON->PIO1_23 |= 0x01; /* Timer1_16 MAT1 */
}
}
}
return;
}
/******************************************************************************
** Function name: init_timer
**
** Descriptions: Initialize timer, set timer interval, reset timer,
** install timer interrupt handler
**
** parameters: timer number and timer interval
** Returned value: None
**
******************************************************************************/
void init_timer16(uint8_t timer_num, uint32_t TimerInterval)
{
uint32_t i;
if ( timer_num == 0 )
{
/* Some of the I/O pins need to be clearfully planned if
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<7);
LPC_CT16B0->MR0 = TimerInterval;
LPC_CT16B0->MR1 = TimerInterval;
#if TIMER_MATCH
for ( i = 0; i < 4; i++ )
{
timer16_0_counter[i] = 0;
}
set_timer16_match(timer_num, 0x07, 0);
LPC_CT16B0->EMR &= ~(0xFF<<4);
LPC_CT16B0->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8));
#else
for ( i = 0; i < 4; i++ )
{
timer16_0_capture[i] = 0;
}
set_timer16_capture(timer_num, 0);
/* Capture 0 and 2 on rising edge, interrupt enable. */
LPC_CT16B0->CCR = (0x5<<0)|(0x5<<6);
#endif
LPC_CT16B0->MCR = (0x3<<0)|(0x3<<3); /* Interrupt and Reset on MR0 and MR1 */
/* Enable the TIMER0 Interrupt */
#if NMI_ENABLED
NVIC_DisableIRQ(CT16B0_IRQn);
NMI_Init( CT16B0_IRQn );
#else
NVIC_EnableIRQ(CT16B0_IRQn);
#endif
}
else if ( timer_num == 1 )
{
/* Some of the I/O pins need to be clearfully planned if
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<8);
LPC_CT16B1->MR0 = TimerInterval;
LPC_CT16B1->MR1 = TimerInterval;
#if TIMER_MATCH
for ( i = 0; i < 4; i++ )
{
timer16_1_counter[i] = 0;
}
set_timer16_match(timer_num, 0x07, 0);
LPC_CT16B1->EMR &= ~(0xFF<<4);
LPC_CT16B1->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8));
#else
for ( i = 0; i < 4; i++ )
{
timer16_1_capture[i] = 0;
}
set_timer16_capture(timer_num, 0);
/* Capture 0 and 1 on rising edge, interrupt enable. */
LPC_CT16B1->CCR = (0x5<<0)|(0x5<<3);
#endif
LPC_CT16B1->MCR = (0x3<<0)|(0x3<<3); /* Interrupt and Reset on MR0 and MR1 */
/* Enable the TIMER1 Interrupt */
#if NMI_ENABLED
NVIC_DisableIRQ(CT16B1_IRQn);
NMI_Init( CT16B1_IRQn );
#else
NVIC_EnableIRQ(CT16B1_IRQn);
#endif
}
return;
}
/******************************************************************************
** Function name: init_timer16PWM
**
** Descriptions: Initialize timer as PWM
**
** parameters: timer number, period and match enable:
** match_enable[0] = PWM for MAT0
** match_enable[1] = PWM for MAT1
** match_enable[2] = PWM for MAT2
**
** Returned value: None
**
******************************************************************************/
void init_timer16PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable, uint8_t cap_enabled)
{
disable_timer16(timer_num);
if (timer_num == 1)
{
/* Some of the I/O pins need to be clearfully planned if
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<8);
/* Setup the external match register */
LPC_CT16B1->EMR = (1<<EMC3)|(1<<EMC2)|(1<<EMC1)|(2<<EMC0)|(1<<3)|(match_enable);
/* Setup the outputs */
/* If match0 is enabled, set the output */
set_timer16_match(timer_num, match_enable, 0 );
/* Enable the selected PWMs and enable Match3 */
LPC_CT16B1->PWMC = (1<<3)|(match_enable);
/* Setup the match registers */
/* set the period value to a global variable */
timer16_1_period = period;
LPC_CT16B1->MR3 = timer16_1_period;
LPC_CT16B1->MR0 = timer16_1_period/2;
LPC_CT16B1->MR1 = timer16_1_period/2;
LPC_CT16B1->MR2 = timer16_1_period/2;
/* Set match control register */
LPC_CT16B1->MCR = 1<<10;// | 1<<9; /* Reset on MR3 */
if (cap_enabled)
{
/* Use location 0 for test. */
set_timer16_capture( timer_num, 0 );
LPC_CT16B1->IR = 0xF; /* clear interrupt flag */
/* Set the capture control register */
LPC_CT16B1->CCR = 7;
}
/* Enable the TIMER1 Interrupt */
NVIC_EnableIRQ(CT16B1_IRQn);
}
else
{
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<7);
/* Setup the external match register */
LPC_CT16B0->EMR = (1<<EMC3)|(1<<EMC2)|(1<<EMC1)|(1<<EMC0)|(1<<3)|(match_enable);
/* Setup the outputs */
/* If match0 is enabled, set the output */
set_timer16_match(timer_num, match_enable, 0 );
/* Enable the selected PWMs and enable Match3 */
LPC_CT16B0->PWMC = (1<<3)|(match_enable);
/* Setup the match registers */
/* set the period value to a global variable */
timer16_0_period = period;
LPC_CT16B0->MR3 = timer16_0_period;
LPC_CT16B0->MR0 = timer16_0_period/2;
LPC_CT16B0->MR1 = timer16_0_period/2;
LPC_CT16B0->MR2 = timer16_0_period/2;
/* Set the match control register */
LPC_CT16B0->MCR = 1<<10; /* Reset on MR3 */
/* Enable the TIMER1 Interrupt */
NVIC_EnableIRQ(CT16B0_IRQn);
}
}
/******************************************************************************
** Function name: pwm16_setMatch
**
** Descriptions: Set the pwm16 match values
**
** parameters: timer number, match numner and the value
**
** Returned value: None
**
******************************************************************************/
void setMatch_timer16PWM (uint8_t timer_num, uint8_t match_nr, uint32_t value)
{
if (timer_num)
{
switch (match_nr)
{
case 0:
LPC_CT16B1->MR0 = value;
break;
case 1:
LPC_CT16B1->MR1 = value;
break;
case 2:
LPC_CT16B1->MR2 = value;
break;
case 3:
LPC_CT16B1->MR3 = value;
break;
default:
break;
}
}
else
{
switch (match_nr)
{
case 0:
LPC_CT16B0->MR0 = value;
break;
case 1:
LPC_CT16B0->MR1 = value;
break;
case 2:
LPC_CT16B0->MR2 = value;
break;
case 3:
LPC_CT16B0->MR3 = value;
break;
default:
break;
}
}
}
/******************************************************************************
** End Of File
******************************************************************************/
hw/mcu/lpc13uxx/LPC13Uxx_DriverLib/src/timer32.c
+646
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@@ -0,0 +1,646 @@
/****************************************************************************
* $Id:: timer32.c 6951 2011-03-23 22:11:07Z usb00423 $
* Project: NXP LPC13Uxx 32-bit timer example
*
* Description:
* This file contains 32-bit timer code example which include timer
* initialization, timer interrupt handler, and related APIs for
* timer setup.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
****************************************************************************/
#include "LPC13Uxx.h"
#include "timer32.h"
#include "nmi.h"
volatile uint32_t timer32_0_counter[4] = {0,0,0,0};
volatile uint32_t timer32_1_counter[4] = {0,0,0,0};
volatile uint32_t timer32_0_capture[4] = {0,0,0,0};
volatile uint32_t timer32_1_capture[4] = {0,0,0,0};
volatile uint32_t timer32_0_period = 0;
volatile uint32_t timer32_1_period = 0;
/*****************************************************************************
** Function name: delay32Ms
**
** Descriptions: Start the timer delay in milo seconds
** until elapsed
**
** parameters: timer number, Delay value in milo second
**
** Returned value: None
**
*****************************************************************************/
void delay32Ms(uint8_t timer_num, uint32_t delayInMs)
{
if (timer_num == 0)
{
/* setup timer #0 for delay */
LPC_CT32B0->TCR = 0x02; /* reset timer */
LPC_CT32B0->PR = 0x00; /* set prescaler to zero */
LPC_CT32B0->MR0 = delayInMs * (SystemCoreClock / 1000);
LPC_CT32B0->IR = 0xff; /* reset all interrrupts */
LPC_CT32B0->MCR = 0x04; /* stop timer on match */
LPC_CT32B0->TCR = 0x01; /* start timer */
/* wait until delay time has elapsed */
while (LPC_CT32B0->TCR & 0x01);
}
else if (timer_num == 1)
{
/* setup timer #1 for delay */
LPC_CT32B1->TCR = 0x02; /* reset timer */
LPC_CT32B1->PR = 0x00; /* set prescaler to zero */
LPC_CT32B1->MR0 = delayInMs * (SystemCoreClock / 1000);
LPC_CT32B1->IR = 0xff; /* reset all interrrupts */
LPC_CT32B1->MCR = 0x04; /* stop timer on match */
LPC_CT32B1->TCR = 0x01; /* start timer */
/* wait until delay time has elapsed */
while (LPC_CT32B1->TCR & 0x01);
}
return;
}
/******************************************************************************
** Function name: CT32B0_IRQHandler
**
** Descriptions: Timer/CounterX and captureX interrupt handler
**
** parameters: None
** Returned value: None
**
******************************************************************************/
void CT32B0_IRQHandler(void)
{
if ( LPC_CT32B0->IR & (0x01<<0) )
{
LPC_CT32B0->IR = 0x1<<0; /* clear interrupt flag */
timer32_0_counter[0]++;
}
if ( LPC_CT32B0->IR & (0x01<<1) )
{
LPC_CT32B0->IR = 0x1<<1; /* clear interrupt flag */
timer32_0_counter[1]++;
}
if ( LPC_CT32B0->IR & (0x01<<2) )
{
LPC_CT32B0->IR = 0x1<<2; /* clear interrupt flag */
timer32_0_counter[2]++;
}
if ( LPC_CT32B0->IR & (0x01<<3) )
{
LPC_CT32B0->IR = 0x1<<3; /* clear interrupt flag */
timer32_0_counter[3]++;
}
if ( LPC_CT32B0->IR & (0x1<<4) )
{
LPC_CT32B0->IR = 0x1<<4; /* clear interrupt flag */
timer32_0_capture[0]++;
}
if ( LPC_CT32B0->IR & (0x1<<5) )
{
LPC_CT32B0->IR = 0x1<<5; /* clear interrupt flag */
timer32_0_capture[1]++;
}
if ( LPC_CT32B0->IR & (0x1<<6) )
{
LPC_CT32B0->IR = 0x1<<6; /* clear interrupt flag */
timer32_0_capture[2]++;
}
if ( LPC_CT32B0->IR & (0x1<<7) )
{
LPC_CT32B0->IR = 0x1<<7; /* clear interrupt flag */
timer32_0_capture[3]++;
}
return;
}
/******************************************************************************
** Function name: CT32B1_IRQHandler
**
** Descriptions: Timer/CounterX and captureX interrupt handler
**
** parameters: None
** Returned value: None
**
******************************************************************************/
void CT32B1_IRQHandler(void)
{
if ( LPC_CT32B1->IR & (0x01<<0) )
{
LPC_CT32B1->IR = 0x1<<0; /* clear interrupt flag */
timer32_1_counter[0]++;
}
if ( LPC_CT32B1->IR & (0x01<<1) )
{
LPC_CT32B1->IR = 0x1<<1; /* clear interrupt flag */
timer32_1_counter[1]++;
}
if ( LPC_CT32B1->IR & (0x01<<2) )
{
LPC_CT32B1->IR = 0x1<<2; /* clear interrupt flag */
timer32_1_counter[2]++;
}
if ( LPC_CT32B1->IR & (0x01<<3) )
{
LPC_CT32B1->IR = 0x1<<3; /* clear interrupt flag */
timer32_1_counter[3]++;
}
if ( LPC_CT32B1->IR & (0x1<<4) )
{
LPC_CT32B1->IR = 0x1<<4; /* clear interrupt flag */
timer32_1_capture[0]++;
}
if ( LPC_CT32B1->IR & (0x1<<5) )
{
LPC_CT32B1->IR = 0x1<<5; /* clear interrupt flag */
timer32_1_capture[1]++;
}
if ( LPC_CT32B1->IR & (0x1<<6) )
{
LPC_CT32B1->IR = 0x1<<6; /* clear interrupt flag */
timer32_1_capture[2]++;
}
if ( LPC_CT32B1->IR & (0x1<<7) )
{
LPC_CT32B1->IR = 0x1<<7; /* clear interrupt flag */
timer32_1_capture[3]++;
}
return;
}
/******************************************************************************
** Function name: enable_timer
**
** Descriptions: Enable timer
**
** parameters: timer number: 0 or 1
** Returned value: None
**
******************************************************************************/
void enable_timer32(uint8_t timer_num)
{
if ( timer_num == 0 )
{
LPC_CT32B0->TCR = 1;
}
else
{
LPC_CT32B1->TCR = 1;
}
return;
}
/******************************************************************************
** Function name: disable_timer
**
** Descriptions: Disable timer
**
** parameters: timer number: 0 or 1
** Returned value: None
**
******************************************************************************/
void disable_timer32(uint8_t timer_num)
{
if ( timer_num == 0 )
{
LPC_CT32B0->TCR = 0;
}
else
{
LPC_CT32B1->TCR = 0;
}
return;
}
/******************************************************************************
** Function name: reset_timer
**
** Descriptions: Reset timer
**
** parameters: timer number: 0 or 1
** Returned value: None
**
******************************************************************************/
void reset_timer32(uint8_t timer_num)
{
uint32_t regVal;
if ( timer_num == 0 )
{
regVal = LPC_CT32B0->TCR;
regVal |= 0x02;
LPC_CT32B0->TCR = regVal;
}
else
{
regVal = LPC_CT32B1->TCR;
regVal |= 0x02;
LPC_CT32B1->TCR = regVal;
}
return;
}
/******************************************************************************
** Function name: set_timer_capture
**
** Descriptions: Set timer capture based on location
**
** parameters: timer number: 0~1, location 0~2
** Returned value: None
**
******************************************************************************/
void set_timer32_capture(uint8_t timer_num, uint8_t location )
{
if ( timer_num == 0 )
{
/* Timer0_32 I/O config */
if ( location == 0 )
{
LPC_IOCON->PIO1_28 &= ~0x07;
LPC_IOCON->PIO1_28 |= 0x01; /* Timer0_32 CAP0 */
LPC_IOCON->PIO1_29 &= ~0x07;
LPC_IOCON->PIO1_29 |= 0x02; /* Timer0_32 CAP2 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO0_17 &= ~0x07;
LPC_IOCON->PIO0_17 |= 0x02; /* Timer0_32 CAP0 */
}
else
{
while ( 1 ); /* Fatal location number error */
}
}
else
{
/* Timer1_32 I/O config */
if ( location == 0 )
{
LPC_IOCON->PIO1_4 &= ~0x07; /* Timer1_32 I/O config */
LPC_IOCON->PIO1_4 |= 0x01; /* Timer1_32 CAP0 */
LPC_IOCON->PIO1_5 &= ~0x07;
LPC_IOCON->PIO1_5 |= 0x01; /* Timer1_32 CAP1 */
}
else if ( location == 1 )
{
LPC_IOCON->TMS_PIO0_12 &= ~0x07;
LPC_IOCON->TMS_PIO0_12 |= 0x03; /* Timer1_32 CAP0 */
}
else
{
while ( 1 ); /* Fatal location number error */
}
}
return;
}
/******************************************************************************
** Function name: set_timer_match
**
** Descriptions: Set timer match based on location
**
** parameters: timer number: 0~1, location 0~2
** Returned value: None
**
******************************************************************************/
void set_timer32_match(uint8_t timer_num, uint8_t match_enable, uint8_t location)
{
if ( timer_num == 0 )
{
if ( match_enable & 0x01 )
{
if ( location == 0 )
{
LPC_IOCON->PIO0_18 &= ~0x07;
LPC_IOCON->PIO0_18 |= 0x02; /* Timer0_32 MAT0 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO1_24 &= ~0x07;
LPC_IOCON->PIO1_24 |= 0x01; /* Timer0_32 MAT0 */
}
}
if ( match_enable & 0x02 )
{
if ( location == 0 )
{
LPC_IOCON->PIO0_19 &= ~0x07;
LPC_IOCON->PIO0_19 |= 0x02; /* Timer0_32 MAT1 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO1_25 &= ~0x07;
LPC_IOCON->PIO1_25 |= 0x01; /* Timer0_32 MAT1 */
}
}
if ( match_enable & 0x04 )
{
if ( location == 0 )
{
LPC_IOCON->PIO0_1 &= ~0x07;
LPC_IOCON->PIO0_1 |= 0x02; /* Timer0_32 MAT2 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO1_26 &= ~0x07;
LPC_IOCON->PIO1_26 |= 0x01; /* Timer0_32 MAT2 */
}
}
if ( match_enable & 0x08 )
{
if ( location == 0 )
{
LPC_IOCON->TDI_PIO0_11 &= ~0x07;
LPC_IOCON->TDI_PIO0_11 |= 0x03; /* Timer0_32 MAT3 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO1_27 &= ~0x07;
LPC_IOCON->PIO1_27 |= 0x01; /* Timer0_32 MAT3 */
}
}
}
else if ( timer_num == 1 )
{
if ( match_enable & 0x01 )
{
if ( location == 0 )
{
LPC_IOCON->PIO1_0 &= ~0x07;
LPC_IOCON->PIO1_0 |= 0x01; /* Timer1_32 MAT0 */
}
else if ( location == 1 )
{
LPC_IOCON->TDO_PIO0_13 &= ~0x07;
LPC_IOCON->TDO_PIO0_13 |= 0x03; /* Timer1_32 MAT0 */
}
}
if ( match_enable & 0x02 )
{
if ( location == 0 )
{
LPC_IOCON->PIO1_1 &= ~0x07;
LPC_IOCON->PIO1_1 |= 0x01; /* Timer1_32 MAT1 */
}
else if ( location == 1 )
{
LPC_IOCON->TRST_PIO0_14 &= ~0x07;
LPC_IOCON->TRST_PIO0_14 |= 0x03; /* Timer1_32 MAT1 */
}
}
if ( match_enable & 0x04 )
{
if ( location == 0 )
{
LPC_IOCON->PIO1_2 &= ~0x07;
LPC_IOCON->PIO1_2 |= 0x01; /* Timer1_32 MAT2 */
}
else if ( location == 1 )
{
#if __SWD_DISABLED
LPC_IOCON->SWDIO_PIO0_15 &= ~0x07;
LPC_IOCON->SWDIO_PIO0_15 |= 0x03; /* Timer1_32 MAT2 */
#endif
}
}
if ( match_enable & 0x08 )
{
if ( location == 0 )
{
LPC_IOCON->PIO1_3 &= ~0x07;
LPC_IOCON->PIO1_3 |= 0x01; /* Timer1_32 MAT3 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO0_16 &= ~0x07;
LPC_IOCON->PIO0_16 |= 0x02; /* Timer1_32 MAT3 */
}
}
}
return;
}
/******************************************************************************
** Function name: init_timer
**
** Descriptions: Initialize timer, set timer interval, reset timer,
** install timer interrupt handler
**
** parameters: timer number and timer interval
** Returned value: None
**
******************************************************************************/
void init_timer32(uint8_t timer_num, uint32_t TimerInterval)
{
uint32_t i;
if ( timer_num == 0 )
{
/* Some of the I/O pins need to be clearfully planned if
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<9);
LPC_CT32B0->MR0 = TimerInterval;
#if TIMER_MATCH
for ( i = 0; i < 4; i++ )
{
timer32_0_counter[i] = 0;
}
set_timer32_match(timer_num, 0x0F, 0);
LPC_CT32B0->EMR &= ~(0xFF<<4);
LPC_CT32B0->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8)|(0x3<<10)); /* MR0/1/2/3 Toggle */
#else
for ( i = 0; i < 4; i++ )
{
timer32_0_capture[i] = 0;
}
set_timer32_capture(timer_num, 0 );
/* Capture 0 on rising edge, interrupt enable. */
LPC_CT32B0->CCR = (0x5<<0)|(0x5<<6);
#endif
LPC_CT32B0->MCR = 3; /* Interrupt and Reset on MR0 */
/* Enable the TIMER0 Interrupt */
#if NMI_ENABLED
NVIC_DisableIRQ( CT32B0_IRQn );
NMI_Init( CT32B0_IRQn );
#else
NVIC_EnableIRQ(CT32B0_IRQn);
#endif
}
else if ( timer_num == 1 )
{
/* Some of the I/O pins need to be clearfully planned if
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10);
LPC_CT32B1->MR0 = TimerInterval;
#if TIMER_MATCH
for ( i = 0; i < 4; i++ )
{
timer32_1_counter[i] = 0;
}
set_timer32_match(timer_num, 0x0F, 0);
LPC_CT32B1->EMR &= ~(0xFF<<4);
LPC_CT32B1->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8)|(0x3<<10)); /* MR0/1/2 Toggle */
#else
for ( i = 0; i < 4; i++ )
{
timer32_1_capture[i] = 0;
}
set_timer32_capture(timer_num, 0 );
/* Capture 0 on rising edge, interrupt enable. */
LPC_CT32B1->CCR = (0x5<<0)|(0x5<<3);
#endif
LPC_CT32B1->MCR = 3; /* Interrupt and Reset on MR0 */
/* Enable the TIMER1 Interrupt */
#if NMI_ENABLED
NVIC_DisableIRQ( CT32B1_IRQn );
NMI_Init( CT32B1_IRQn );
#else
NVIC_EnableIRQ(CT32B1_IRQn);
#endif
}
return;
}
/******************************************************************************
** Function name: init_timer32PWM
**
** Descriptions: Initialize timer as PWM
**
** parameters: timer number, period and match enable:
** match_enable[0] = PWM for MAT0
** match_enable[1] = PWM for MAT1
** match_enable[2] = PWM for MAT2
** Returned value: None
**
******************************************************************************/
void init_timer32PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable)
{
disable_timer32(timer_num);
if (timer_num == 1)
{
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10);
/* Setup the external match register */
LPC_CT32B1->EMR = (1<<EMC3)|(1<<EMC2)|(2<<EMC1)|(1<<EMC0)|MATCH3|(match_enable);
/* Setup the outputs */
/* If match0 is enabled, set the output, use location 0 for test. */
set_timer32_match( timer_num, match_enable, 0 );
/* Enable the selected PWMs and enable Match3 */
LPC_CT32B1->PWMC = MATCH3|(match_enable);
/* Setup the match registers */
/* set the period value to a global variable */
timer32_1_period = period;
LPC_CT32B1->MR3 = timer32_1_period;
LPC_CT32B1->MR0 = timer32_1_period/2;
LPC_CT32B1->MR1 = timer32_1_period/2;
LPC_CT32B1->MR2 = timer32_1_period/2;
LPC_CT32B1->MCR = 1<<10; /* Reset on MR3 */
}
else
{
/* Some of the I/O pins need to be clearfully planned if
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<9);
/* Setup the external match register */
LPC_CT32B0->EMR = (1<<EMC3)|(2<<EMC2)|(1<<EMC1)|(1<<EMC0)|MATCH3|(match_enable);
/* Setup the outputs */
/* If match0 is enabled, set the output, use location 0 for test. */
set_timer32_match( timer_num, match_enable, 0 );
/* Enable the selected PWMs and enable Match3 */
LPC_CT32B0->PWMC = MATCH3|(match_enable);
/* Setup the match registers */
/* set the period value to a global variable */
timer32_0_period = period;
LPC_CT32B0->MR3 = timer32_0_period;
LPC_CT32B0->MR0 = timer32_0_period/2;
LPC_CT32B0->MR1 = timer32_0_period/2;
LPC_CT32B0->MR2 = timer32_0_period/2;
LPC_CT32B0->MCR = 1<<10; /* Reset on MR3 */
}
}
/******************************************************************************
** Function name: pwm32_setMatch
**
** Descriptions: Set the pwm32 match values
**
** parameters: timer number, match numner and the value
**
** Returned value: None
**
******************************************************************************/
void setMatch_timer32PWM (uint8_t timer_num, uint8_t match_nr, uint32_t value)
{
if (timer_num)
{
switch (match_nr)
{
case 0:
LPC_CT32B1->MR0 = value;
break;
case 1:
LPC_CT32B1->MR1 = value;
break;
case 2:
LPC_CT32B1->MR2 = value;
break;
case 3:
LPC_CT32B1->MR3 = value;
break;
default:
break;
}
}
else
{
switch (match_nr)
{
case 0:
LPC_CT32B0->MR0 = value;
break;
case 1:
LPC_CT32B0->MR1 = value;
break;
case 2:
LPC_CT32B0->MR2 = value;
break;
case 3:
LPC_CT32B0->MR3 = value;
break;
default:
break;
}
}
}
/******************************************************************************
** End Of File
******************************************************************************/
hw/mcu/lpc13uxx/LPC13Uxx_DriverLib/src/uart.c
+437
View File
@@ -0,0 +1,437 @@
/****************************************************************************
* $Id:: uart.c 7125 2011-04-15 00:22:12Z usb01267 $
* Project: NXP LPC13Uxx UART example
*
* Description:
* This file contains UART code example which include UART
* initialization, UART interrupt handler, and related APIs for
* UART access.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
****************************************************************************/
#include "LPC13Uxx.h"
#include "type.h"
#include "uart.h"
volatile uint32_t UARTStatus;
volatile uint8_t UARTTxEmpty = 1;
volatile uint8_t UARTBuffer[BUFSIZE];
volatile uint32_t UARTCount = 0;
#if AUTOBAUD_ENABLE
volatile uint32_t UARTAutoBaud = 0, AutoBaudTimeout = 0;
#endif
/*****************************************************************************
** Function name: USART_IRQHandler
**
** Descriptions: USART interrupt handler
**
** parameters: None
** Returned value: None
**
*****************************************************************************/
void USART_IRQHandler(void)
{
uint8_t IIRValue, LSRValue;
uint8_t Dummy = Dummy;
IIRValue = LPC_USART->IIR;
IIRValue >>= 1; /* skip pending bit in IIR */
IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
if (IIRValue == IIR_RLS) /* Receive Line Status */
{
LSRValue = LPC_USART->LSR;
/* Receive Line Status */
if (LSRValue & (LSR_OE | LSR_PE | LSR_FE | LSR_RXFE | LSR_BI))
{
/* There are errors or break interrupt */
/* Read LSR will clear the interrupt */
UARTStatus = LSRValue;
Dummy = LPC_USART->RBR; /* Dummy read on RX to clear
interrupt, then bail out */
return;
}
if (LSRValue & LSR_RDR) /* Receive Data Ready */
{
/* If no error on RLS, normal ready, save into the data buffer. */
/* Note: read RBR will clear the interrupt */
UARTBuffer[UARTCount++] = LPC_USART->RBR;
if (UARTCount == BUFSIZE)
{
UARTCount = 0; /* buffer overflow */
}
}
}
else if (IIRValue == IIR_RDA) /* Receive Data Available */
{
/* Receive Data Available */
UARTBuffer[UARTCount++] = LPC_USART->RBR;
if (UARTCount == BUFSIZE)
{
UARTCount = 0; /* buffer overflow */
}
}
else if (IIRValue == IIR_CTI) /* Character timeout indicator */
{
/* Character Time-out indicator */
UARTStatus |= 0x100; /* Bit 9 as the CTI error */
}
else if (IIRValue == IIR_THRE) /* THRE, transmit holding register empty */
{
/* THRE interrupt */
LSRValue = LPC_USART->LSR; /* Check status in the LSR to see if
valid data in U0THR or not */
if (LSRValue & LSR_THRE)
{
UARTTxEmpty = 1;
}
else
{
UARTTxEmpty = 0;
}
}
#if AUTOBAUD_ENABLE
if (LPC_USART->IIR & IIR_ABEO) /* End of Auto baud */
{
LPC_USART->IER &= ~IIR_ABEO;
/* clear bit ABEOInt in the IIR by set ABEOIntClr in the ACR register */
LPC_USART->ACR |= IIR_ABEO;
UARTAutoBaud = 1;
}
else if (LPC_USART->IIR & IIR_ABTO)/* Auto baud time out */
{
LPC_USART->IER &= ~IIR_ABTO;
AutoBaudTimeout = 1;
/* clear bit ABTOInt in the IIR by set ABTOIntClr in the ACR register */
LPC_USART->ACR |= IIR_ABTO;
}
#endif
return;
}
#if MODEM_TEST
/*****************************************************************************
** Function name: ModemInit
**
** Descriptions: Initialize UART0 port as modem, setup pin select.
**
** parameters: None
** Returned value: None
**
*****************************************************************************/
void ModemInit( void )
{
LPC_IOCON->PIO0_7 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO0_7 |= 0x01; /* UART CTS */
LPC_IOCON->PIO0_17 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO0_17 |= 0x01; /* UART RTS */
#if 1
LPC_IOCON->PIO1_13 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_13 |= 0x01; /* UART DTR */
LPC_IOCON->PIO1_14 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_14 |= 0x01; /* UART DSR */
LPC_IOCON->PIO1_15 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_15 |= 0x01; /* UART DCD */
LPC_IOCON->PIO1_16 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_16 |= 0x01; /* UART RI */
#else
LPC_IOCON->PIO1_19 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_19 |= 0x01; /* UART DTR */
LPC_IOCON->PIO1_20 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_20 |= 0x01; /* UART DSR */
LPC_IOCON->PIO1_21 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_21 |= 0x01; /* UART DCD */
LPC_IOCON->PIO1_22 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_22 |= 0x01; /* UART RI */
#endif
LPC_USART->MCR = 0xC0; /* Enable Auto RTS and Auto CTS. */
return;
}
#endif
/***********************************************************************
*
* Function: uart_set_divisors
*
* Purpose: Determines best dividers to get a target clock rate
*
* Processing:
* See function.
*
* Parameters:
* UARTClk : UART clock
* baudrate : Desired UART baud rate
*
* Outputs:
* baudrate : Sets the estimated buadrate value in DLL, DLM, and FDR.
*
* Returns: Error status.
*
* Notes: None
*
**********************************************************************/
uint32_t uart_set_divisors(uint32_t UARTClk, uint32_t baudrate)
{
uint32_t uClk;
uint32_t calcBaudrate = 0;
uint32_t temp = 0;
uint32_t mulFracDiv, dividerAddFracDiv;
uint32_t diviser = 0 ;
uint32_t mulFracDivOptimal = 1;
uint32_t dividerAddOptimal = 0;
uint32_t diviserOptimal = 0;
uint32_t relativeError = 0;
uint32_t relativeOptimalError = 100000;
/* get UART block clock */
uClk = UARTClk >> 4; /* div by 16 */
/* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
* The formula is :
* BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
* It involves floating point calculations. That's the reason the formulae are adjusted with
* Multiply and divide method.*/
/* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
* 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
for (mulFracDiv = 1; mulFracDiv <= 15; mulFracDiv++)
{
for (dividerAddFracDiv = 0; dividerAddFracDiv <= 15; dividerAddFracDiv++)
{
temp = (mulFracDiv * uClk) / ((mulFracDiv + dividerAddFracDiv));
diviser = temp / baudrate;
if ((temp % baudrate) > (baudrate / 2))
diviser++;
if (diviser > 2 && diviser < 65536)
{
calcBaudrate = temp / diviser;
if (calcBaudrate <= baudrate)
relativeError = baudrate - calcBaudrate;
else
relativeError = calcBaudrate - baudrate;
if ((relativeError < relativeOptimalError))
{
mulFracDivOptimal = mulFracDiv ;
dividerAddOptimal = dividerAddFracDiv;
diviserOptimal = diviser;
relativeOptimalError = relativeError;
if (relativeError == 0)
break;
}
} /* End of if */
} /* end of inner for loop */
if (relativeError == 0)
break;
} /* end of outer for loop */
if (relativeOptimalError < (baudrate / 30))
{
/* Set the `Divisor Latch Access Bit` and enable so the DLL/DLM access*/
/* Initialise the `Divisor latch LSB` and `Divisor latch MSB` registers */
LPC_USART->DLM = (diviserOptimal >> 8) & 0xFF;
LPC_USART->DLL = diviserOptimal & 0xFF;
/* Initialise the Fractional Divider Register */
LPC_USART->FDR = ((mulFracDivOptimal & 0xF) << 4) | (dividerAddOptimal & 0xF);
return( TRUE );
}
return ( FALSE );
}
/*****************************************************************************
** Function name: UARTInit
**
** Descriptions: Initialize UART0 port, setup pin select,
** clock, parity, stop bits, FIFO, etc.
**
** parameters: UART baudrate
** Returned value: None
**
*****************************************************************************/
void UARTInit(uint32_t baudrate)
{
#if !AUTOBAUD_ENABLE
uint32_t Fdiv;
#endif
volatile uint32_t regVal;
UARTTxEmpty = 1;
UARTCount = 0;
NVIC_DisableIRQ(USART_IRQn);
/* Select only one location from below. */
#if 1
LPC_IOCON->PIO0_18 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO0_18 |= 0x01; /* UART RXD */
LPC_IOCON->PIO0_19 &= ~0x07;
LPC_IOCON->PIO0_19 |= 0x01; /* UART TXD */
#endif
#if 0
LPC_IOCON->PIO1_14 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_14 |= 0x03; /* UART RXD */
LPC_IOCON->PIO1_13 &= ~0x07;
LPC_IOCON->PIO1_13 |= 0x03; /* UART TXD */
#endif
#if 0
LPC_IOCON->PIO1_17 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_17 |= 0x02; /* UART RXD */
LPC_IOCON->PIO1_18 &= ~0x07;
LPC_IOCON->PIO1_18 |= 0x02; /* UART TXD */
#endif
#if 0
LPC_IOCON->PIO1_26 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_26 |= 0x02; /* UART RXD */
LPC_IOCON->PIO1_27 &= ~0x07;
LPC_IOCON->PIO1_27 |= 0x02; /* UART TXD */
#endif
/* Enable UART clock */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
LPC_SYSCON->UARTCLKDIV = 0x1; /* divided by 1 */
LPC_USART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
#if !AUTOBAUD_ENABLE
#if FDR_CALIBRATION
if ( uart_set_divisors(SystemCoreClock/LPC_SYSCON->UARTCLKDIV, baudrate) != TRUE )
{
Fdiv = ((SystemCoreClock/LPC_SYSCON->UARTCLKDIV)/16)/baudrate ; /*baud rate */
LPC_USART->DLM = Fdiv / 256;
LPC_USART->DLL = Fdiv % 256;
LPC_USART->FDR = 0x10; /* Default */
}
#else
Fdiv = ((SystemCoreClock/LPC_SYSCON->UARTCLKDIV)/16)/baudrate ; /*baud rate */
LPC_USART->DLM = Fdiv / 256;
LPC_USART->DLL = Fdiv % 256;
LPC_USART->FDR = 0x10; /* Default */
#endif
#endif
LPC_USART->LCR = 0x03; /* DLAB = 0 */
LPC_USART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
/* Read to clear the line status. */
regVal = LPC_USART->LSR;
/* Ensure a clean start, no data in either TX or RX FIFO. */
while (( LPC_USART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
while ( LPC_USART->LSR & LSR_RDR )
{
regVal = LPC_USART->RBR; /* Dump data from RX FIFO */
}
/* Enable the UART Interrupt */
NVIC_EnableIRQ(USART_IRQn);
#if TX_INTERRUPT
LPC_USART->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */
#else
LPC_USART->IER = IER_RBR | IER_RLS; /* Enable UART interrupt */
#endif
#if AUTOBAUD_ENABLE
LPC_USART->IER |= IER_ABEO | IER_ABTO;
#endif
return;
}
/*****************************************************************************
** Function name: UARTSend
**
** Descriptions: Send a block of data to the UART 0 port based
** on the data length
**
** parameters: buffer pointer, and data length
** Returned value: None
**
*****************************************************************************/
void UARTSend(uint8_t *BufferPtr, uint32_t Length)
{
while ( Length != 0 )
{
/* THRE status, contain valid data */
#if !TX_INTERRUPT
while ( !(LPC_USART->LSR & LSR_THRE) );
LPC_USART->THR = *BufferPtr;
#else
/* Below flag is set inside the interrupt handler when THRE occurs. */
while ( !(UARTTxEmpty & 0x01) );
LPC_USART->THR = *BufferPtr;
UARTTxEmpty = 0; /* not empty in the THR until it shifts out */
#endif
BufferPtr++;
Length--;
}
return;
}
/*****************************************************************************
** Function name: print_string
**
** Descriptions: print out string on the terminal
**
** parameters: pointer to the string end with NULL char.
** Returned value: none.
**
*****************************************************************************/
void print_string( uint8_t *str_ptr )
{
while(*str_ptr != 0x00)
{
while((LPC_USART->LSR & 0x60) != 0x60);
LPC_USART->THR = *str_ptr;
str_ptr++;
}
return;
}
/*****************************************************************************
** Function name: get_key
**
** Descriptions: Get a character from the terminal
**
** parameters: None
** Returned value: character, zero is none.
**
*****************************************************************************/
uint8_t get_key( void )
{
uint8_t dummy;
while ( !(LPC_USART->LSR & 0x01) );
dummy = LPC_USART->RBR;
if ((dummy>=65) && (dummy<=90))
{
/* convert capital to non-capital character, A2a, B2b, C2c. */
dummy +=32;
}
/* echo */
LPC_USART->THR = dummy;
return(dummy);
}
/******************************************************************************
** End Of File
******************************************************************************/
hw/mcu/lpc13uxx/iar/startup_lpc13xx.s
+168
View File
@@ -0,0 +1,168 @@
/**************************************************
*
* Part one of the system initialization code, contains low-level
* initialization, plain thumb variant.
*
* Copyright 2012 IAR Systems. All rights reserved.
*
* $Revision: 50057 $
*
**************************************************/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD __iar_program_start ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
__vector_table_0x1c
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
DCD FLEX_INT0_IRQHandler ; GPIO pin interrupt 0
DCD FLEX_INT1_IRQHandler ; GPIO pin interrupt 1
DCD FLEX_INT2_IRQHandler ; GPIO pin interrupt 2
DCD FLEX_INT3_IRQHandler ; GPIO pin interrupt 3
DCD FLEX_INT4_IRQHandler ; GPIO pin interrupt 4
DCD FLEX_INT5_IRQHandler ; GPIO pin interrupt 5
DCD FLEX_INT6_IRQHandler ; GPIO pin interrupt 6
DCD FLEX_INT7_IRQHandler ; GPIO pin interrupt 7
DCD GINT0_IRQHandler ; GPIO GROUP0 interrupt
DCD GINT1_IRQHandler ; GPIO GROUP1 interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SSP1_IRQHandler ; SSP1 interrupt
DCD I2C_IRQHandler ; I2C interrupt
DCD CT16B0_IRQHandler ; CT16B0 Match 0-3, Capture 0
DCD CT16B1_IRQHandler ; CT16B1 Match 0-3, Capture 0
DCD CT32B0_IRQHandler ; CT32B0 Match 0-3, Capture 0
DCD CT32B1_IRQHandler ; CT32B1 Match 0-3, Capture 0
DCD SSP0_IRQHandler ; SSP0 interrupt
DCD USART_IRQHandler ; USART interrupt
DCD USB_IRQHandler ; USB_IRQ interrupt
DCD USB_FIQHandler ; USB_FIQ interrupt
DCD ADC_IRQHandler ; ADC interrupt
DCD WWDT_IRQHandler ; WWDT interrupt
DCD BOD_IRQHandler ; BOD interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD USBWakeup_IRQHandler ; USB_WAKEUP interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
PUBWEAK NMI_Handler
PUBWEAK HardFault_Handler
PUBWEAK MemManage_Handler
PUBWEAK BusFault_Handler
PUBWEAK UsageFault_Handler
PUBWEAK SVC_Handler
PUBWEAK DebugMon_Handler
PUBWEAK PendSV_Handler
PUBWEAK SysTick_Handler
PUBWEAK FLEX_INT0_IRQHandler
PUBWEAK FLEX_INT1_IRQHandler
PUBWEAK FLEX_INT2_IRQHandler
PUBWEAK FLEX_INT3_IRQHandler
PUBWEAK FLEX_INT4_IRQHandler
PUBWEAK FLEX_INT5_IRQHandler
PUBWEAK FLEX_INT6_IRQHandler
PUBWEAK FLEX_INT7_IRQHandler
PUBWEAK GINT0_IRQHandler
PUBWEAK GINT1_IRQHandler
PUBWEAK SSP1_IRQHandler
PUBWEAK I2C_IRQHandler
PUBWEAK CT16B0_IRQHandler
PUBWEAK CT16B1_IRQHandler
PUBWEAK CT32B0_IRQHandler
PUBWEAK CT32B1_IRQHandler
PUBWEAK SSP0_IRQHandler
PUBWEAK USART_IRQHandler
PUBWEAK USB_IRQHandler
PUBWEAK USB_FIQHandler
PUBWEAK ADC_IRQHandler
PUBWEAK WWDT_IRQHandler
PUBWEAK BOD_IRQHandler
PUBWEAK USBWakeup_IRQHandler
SECTION .text:CODE:REORDER(1)
THUMB
NMI_Handler
HardFault_Handler
MemManage_Handler
BusFault_Handler
UsageFault_Handler
SVC_Handler
DebugMon_Handler
PendSV_Handler
SysTick_Handler
FLEX_INT0_IRQHandler
FLEX_INT1_IRQHandler
FLEX_INT2_IRQHandler
FLEX_INT3_IRQHandler
FLEX_INT4_IRQHandler
FLEX_INT5_IRQHandler
FLEX_INT6_IRQHandler
FLEX_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
SSP1_IRQHandler
I2C_IRQHandler
CT16B0_IRQHandler
CT16B1_IRQHandler
CT32B0_IRQHandler
CT32B1_IRQHandler
SSP0_IRQHandler
USART_IRQHandler
USB_IRQHandler
USB_FIQHandler
ADC_IRQHandler
WWDT_IRQHandler
BOD_IRQHandler
USBWakeup_IRQHandler
Default_Handler
B Default_Handler
END
hw/mcu/lpc13uxx/keil/lpc13uxx.sct
+18
View File
@@ -0,0 +1,18 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00010000 { ; load region size_region
ER_IROM1 0x00000000 0x00010000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x10000000 0x00002000 { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM2 0x20004000 0x00000800 {
*(USBRAM_SECTION)
}
}
hw/mcu/lpc13uxx/keil/startup_LPC13Uxx.s
+279
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@@ -0,0 +1,279 @@
;/**************************************************************************//**
; * @file startup_LPC13Uxx.s
; * @brief CMSIS Cortex-M3 Core Device Startup File
; * for the NXP LPC13Uxx Device Series
; * @version V1.10
; * @date 24. November 2010
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * @note
; * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PIN_INT0_IRQHandler ; All GPIO pin can be routed to PIN_INTx
DCD PIN_INT1_IRQHandler
DCD PIN_INT2_IRQHandler
DCD PIN_INT3_IRQHandler
DCD PIN_INT4_IRQHandler
DCD PIN_INT5_IRQHandler
DCD PIN_INT6_IRQHandler
DCD PIN_INT7_IRQHandler
DCD GINT0_IRQHandler
DCD GINT1_IRQHandler ; PIO0 (0:7)
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler
DCD OSTIMER_IRQHandler
DCD Reserved_IRQHandler
DCD SSP1_IRQHandler ; SSP1
DCD I2C_IRQHandler ; I2C
DCD CT16B0_IRQHandler ; 16-bit Timer0
DCD CT16B1_IRQHandler ; 16-bit Timer1
DCD CT32B0_IRQHandler ; 32-bit Timer0
DCD CT32B1_IRQHandler ; 32-bit Timer1
DCD SSP0_IRQHandler ; SSP0
DCD USART_IRQHandler ; USART
DCD USB_IRQHandler ; USB IRQ
DCD USB_FIQHandler ; USB FIQ
DCD ADC_IRQHandler ; A/D Converter
DCD WDT_IRQHandler ; Watchdog timer
DCD BOD_IRQHandler ; Brown Out Detect
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
DCD OSCFAIL_IRQHandler ; OSC FAIL
DCD PVTCIRCUIT_IRQHandler ; PVT CIRCUIT
DCD USBWakeup_IRQHandler ; USB wake up
DCD Reserved_IRQHandler ; Reserved
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
; for particular peripheral.
;NMI_Handler PROC
; EXPORT NMI_Handler [WEAK]
; B .
; ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Reserved_IRQHandler PROC
EXPORT Reserved_IRQHandler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT NMI_Handler [WEAK]
EXPORT PIN_INT0_IRQHandler [WEAK]
EXPORT PIN_INT1_IRQHandler [WEAK]
EXPORT PIN_INT2_IRQHandler [WEAK]
EXPORT PIN_INT3_IRQHandler [WEAK]
EXPORT PIN_INT4_IRQHandler [WEAK]
EXPORT PIN_INT5_IRQHandler [WEAK]
EXPORT PIN_INT6_IRQHandler [WEAK]
EXPORT PIN_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT OSTIMER_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CT16B0_IRQHandler [WEAK]
EXPORT CT16B1_IRQHandler [WEAK]
EXPORT CT32B0_IRQHandler [WEAK]
EXPORT CT32B1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT USART_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT USB_FIQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT OSCFAIL_IRQHandler [WEAK]
EXPORT PVTCIRCUIT_IRQHandler [WEAK]
EXPORT USBWakeup_IRQHandler [WEAK]
NMI_Handler
PIN_INT0_IRQHandler
PIN_INT1_IRQHandler
PIN_INT2_IRQHandler
PIN_INT3_IRQHandler
PIN_INT4_IRQHandler
PIN_INT5_IRQHandler
PIN_INT6_IRQHandler
PIN_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
OSTIMER_IRQHandler
SSP1_IRQHandler
I2C_IRQHandler
CT16B0_IRQHandler
CT16B1_IRQHandler
CT32B0_IRQHandler
CT32B1_IRQHandler
SSP0_IRQHandler
USART_IRQHandler
USB_IRQHandler
USB_FIQHandler
ADC_IRQHandler
WDT_IRQHandler
BOD_IRQHandler
FMC_IRQHandler
OSCFAIL_IRQHandler
PVTCIRCUIT_IRQHandler
USBWakeup_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
hw/mcu/lpc13uxx/lpcxpresso/cr_startup_lpc13u.c
+354
View File
@@ -0,0 +1,354 @@
//*****************************************************************************
// +--+
// | ++----+
// +-++ |
// | |
// +-+--+ |
// | +--+--+
// +----+ Copyright (c) 2012 Code Red Technologies Ltd.
//
// NXP LPC13U Microcontroller Startup code for use with Red Suite
//
// Version : 120202
//
// Software License Agreement
//
// The software is owned by Code Red Technologies and/or its suppliers, and is
// protected under applicable copyright laws. All rights are reserved. Any
// use in violation of the foregoing restrictions may subject the user to criminal
// sanctions under applicable laws, as well as to civil liability for the breach
// of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
// CODE RED TECHNOLOGIES LTD.
//
//*****************************************************************************
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
// Code Red - if CMSIS is being used, then SystemInit() routine
// will be called by startup code rather than in application's main()
#if defined (__USE_CMSIS)
#include "LPC13Uxx.h"
#endif
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
//
// Forward declaration of the default handlers. These are aliased.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
WEAK void BusFault_Handler(void);
WEAK void UsageFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void DebugMon_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
//*****************************************************************************
//
// Forward declaration of the specific IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the application
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//
//*****************************************************************************
void PIN_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void OSTIMER_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C_IRQHandler(void) ALIAS(IntDefaultHandler);
void CT16B0_IRQHandler(void) ALIAS(IntDefaultHandler);
void CT16B1_IRQHandler(void) ALIAS(IntDefaultHandler);
void CT32B0_IRQHandler(void) ALIAS(IntDefaultHandler);
void CT32B1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
void USART_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB_FIQHandler(void) ALIAS(IntDefaultHandler);
void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
void FMC_IRQHandler(void) ALIAS(IntDefaultHandler);
void OSCFAIL_IRQHandler(void) ALIAS(IntDefaultHandler);
void PVTCIRCUIT_IRQHandler(void) ALIAS(IntDefaultHandler);
void USBWakeup_IRQHandler(void) ALIAS(IntDefaultHandler);
//*****************************************************************************
//
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
//
// The vector table. Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000.
//
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM3
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// LPC13U External Interrupts
PIN_INT0_IRQHandler, // All GPIO pin can be routed to PIN_INTx
PIN_INT1_IRQHandler,
PIN_INT2_IRQHandler,
PIN_INT3_IRQHandler,
PIN_INT4_IRQHandler,
PIN_INT5_IRQHandler,
PIN_INT6_IRQHandler,
PIN_INT7_IRQHandler,
GINT0_IRQHandler,
GINT1_IRQHandler, // PIO0 (0:7)
0,
0,
OSTIMER_IRQHandler,
0,
SSP1_IRQHandler, // SSP1
I2C_IRQHandler, // I2C
CT16B0_IRQHandler, // 16-bit Timer0
CT16B1_IRQHandler, // 16-bit Timer1
CT32B0_IRQHandler, // 32-bit Timer0
CT32B1_IRQHandler, // 32-bit Timer1
SSP0_IRQHandler, // SSP0
USART_IRQHandler, // USART
USB_IRQHandler, // USB IRQ
USB_FIQHandler, // USB FIQ
ADC_IRQHandler, // A/D Converter
WDT_IRQHandler, // Watchdog timer
BOD_IRQHandler, // Brown Out Detect
FMC_IRQHandler, // IP2111 Flash Memory Controller
OSCFAIL_IRQHandler, // OSC FAIL
PVTCIRCUIT_IRQHandler, // PVT CIRCUIT
USBWakeup_IRQHandler, // USB wake up
0,
};
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
__attribute__ ((section(".after_vectors")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void
ResetISR(void) {
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#ifdef __USE_CMSIS
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
//*****************************************************************************
// Default exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void NMI_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void HardFault_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void MemManage_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void BusFault_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void UsageFault_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void SVC_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void DebugMon_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void PendSV_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void SysTick_Handler(void) {
while (1) {
}
}
//*****************************************************************************
//
// Processor ends up here if an unexpected interrupt occurs or a handler
// is not present in the application code.
//
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void IntDefaultHandler(void) {
//
// Go into an infinite loop.
//
while (1) {
}
}