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move board and mcu into hw folder

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hathach
2018-03-02 13:41:35 +07:00
parent 2580b4c6a7
commit 349fa2aed8
250 changed files with 47186 additions and 47134 deletions
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hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/LCDTerm.h
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/**********************************************************************
* $Id$ LCDTerm.h.c 2011-12-06
*//**
* @file LCDTerm.h.c
* @brief This is a library that can be used to display text on the LCD of Hitex 1800 board
* @version 1.0
* @date 06. Dec. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors’
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
#include "lpc43xx_ssp.h"
#ifndef HITEX_LCD_TERM
#define HITEX_LCD_TERM 2
#endif
#define Highlight 1
#define NoHighlight 0
SSP_DATA_SETUP_Type *InitLCDTerm(void);
void WriteChar(char ch, SSP_DATA_SETUP_Type *xferConfig, uint8_t nHighlight);
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/LPC43xx.h
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hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/core_cm4.h
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hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/core_cm4_simd.h
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/**************************************************************************//**
* @file core_cm4_simd.h
* @brief CMSIS Cortex-M4 SIMD Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM4_SIMD_H
#define __CORE_CM4_SIMD_H
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32) ) >> 32))
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#include <cmsis_iar.h>
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#include <cmsis_ccs.h>
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SSAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SMLALD(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
#define __SMLALDX(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SMLSLD(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
#define __SMLSLDX(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#define __PKHBT(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
/* not yet supported */
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CORE_CM4_SIMD_H */
#ifdef __cplusplus
}
#endif
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/core_cmFunc.h
+636
View File
@@ -0,0 +1,636 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/core_cmInstr.h
+688
View File
@@ -0,0 +1,688 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.20
* @date 05. March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/debug_frmwrk.h
+109
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/**********************************************************************
* $Id$ debug_frmwrk.h 2011-06-02
*//**
* @file debug_frmwrk.h
* @brief Contains some utilities that used for debugging through UART
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup DEBUG_FRMWRK DEBUG FRAMEWORK
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef DEBUG_FRMWRK_H_
#define DEBUG_FRMWRK_H_
/* Includes ------------------------------------------------------------------- */
#include "lpc43xx_uart.h"
#define KEIL_BOARD 1
#define HITEX_BOARD 2
#ifndef PLATFORM
#define PLATFORM KEIL_BOARD
#endif
#if (PLATFORM == HITEX_BOARD)
#define USED_UART_DEBUG_PORT 0
#endif
#if (PLATFORM == KEIL_BOARD)
#define USED_UART_DEBUG_PORT 3
#endif
#if (USED_UART_DEBUG_PORT==0)
#define DEBUG_UART_PORT LPC_USART0
#elif (USED_UART_DEBUG_PORT==1)
#define DEBUG_UART_PORT LPC_UART1
#elif (USED_UART_DEBUG_PORT==3)
#define DEBUG_UART_PORT LPC_USART3
#endif
#define _DBG(x) _db_msg((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBG_(x) _db_msg_((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBC(x) _db_char((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBD(x) _db_dec((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBD16(x) _db_dec_16((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBD32(x) _db_dec_32((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBH(x) _db_hex((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBH16(x) _db_hex_16((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBH32(x) _db_hex_32((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DG _db_get_char((LPC_USARTn_Type*)DEBUG_UART_PORT)
void lpc_printf (const char *format, ...);
extern void (*_db_msg)(LPC_USARTn_Type *UARTx, const void *s);
extern void (*_db_msg_)(LPC_USARTn_Type *UARTx, const void *s);
extern void (*_db_char)(LPC_USARTn_Type *UARTx, uint8_t ch);
extern void (*_db_dec)(LPC_USARTn_Type *UARTx, uint8_t decn);
extern void (*_db_dec_16)(LPC_USARTn_Type *UARTx, uint16_t decn);
extern void (*_db_dec_32)(LPC_USARTn_Type *UARTx, uint32_t decn);
extern void (*_db_hex)(LPC_USARTn_Type *UARTx, uint8_t hexn);
extern void (*_db_hex_16)(LPC_USARTn_Type *UARTx, uint16_t hexn);
extern void (*_db_hex_32)(LPC_USARTn_Type *UARTx, uint32_t hexn);
extern uint8_t (*_db_get_char)(LPC_USARTn_Type *UARTx);
void UARTPutChar (LPC_USARTn_Type *UARTx, uint8_t ch);
void UARTPuts(LPC_USARTn_Type *UARTx, const void *str);
void UARTPuts_(LPC_USARTn_Type *UARTx, const void *str);
void UARTPutDec(LPC_USARTn_Type *UARTx, uint8_t decnum);
void UARTPutDec16(LPC_USARTn_Type *UARTx, uint16_t decnum);
void UARTPutDec32(LPC_USARTn_Type *UARTx, uint32_t decnum);
void UARTPutHex (LPC_USARTn_Type *UARTx, uint8_t hexnum);
void UARTPutHex16 (LPC_USARTn_Type *UARTx, uint16_t hexnum);
void UARTPutHex32 (LPC_USARTn_Type *UARTx, uint32_t hexnum);
uint8_t UARTGetChar (LPC_USARTn_Type *UARTx);
#define debug_frmwrk_init() debug_frmwrk_init_clk(0)
void debug_frmwrk_init_clk(uint32_t Clock_Speed);
#endif /* DEBUG_FRMWRK_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/fpu_enable.h
+33
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/***********************************************************************
* $Id: fpu_enable.h
*
* Project: LPC43xx
*
* Description: fpu initialization routine header
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __FPU_ENABLE_H
#define __FPU_ENABLE_H
#if defined(__ARMCC_VERSION)
void fpuEnable(void) __attribute__ ((section("BOOTSTRAP_CODE")));
#else
extern void fpuEnable(void);
#endif
#endif /* __FPU_ENABLE_H */
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/fpu_init.h
+29
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/***********************************************************************
* $Id: fpu_init.h
*
* Project: LPC43xx
*
* Description: fpu initialization routine header
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __FPU_INIT_H
#define __FPU_INIT_H
void fpuInit(void);
#endif /* __FPU_INIT_H */
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_adc.h
+300
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/**********************************************************************
* $Id$ lpc43xx_adc.h 2011-06-02
*//**
* @file lpc43xx_adc.h
* @brief Contains all macro definitions and function prototypes
* support for ADC firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup ADC ADC (Analog to Digital Converter)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_ADC_H_
#define lpc43xx_ADC_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private macros ------------------------------------------------------------- */
/** @defgroup ADC_Private_Macros ADC Private Macros
* @{
*/
/* -------------------------- BIT DEFINITIONS ----------------------------------- */
/*********************************************************************//**
* Macro defines for ADC control register
**********************************************************************/
/** Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
#define ADC_CR_CH_SEL(n) ((1UL << n))
/** The APB clock (PCLK) is divided by (this value plus one)
* to produce the clock for the A/D */
#define ADC_CR_CLKDIV(n) ((n<<8))
/** Repeated conversions A/D enable bit */
#define ADC_CR_BURST ((1UL<<16))
/** number of accuracy bits */
#define ADC_CR_BITACC(n) (((n)<<17))
/** ADC convert in power down mode */
#define ADC_CR_PDN ((1UL<<21))
/** Start mask bits */
#define ADC_CR_START_MASK ((7UL<<24))
/** Select Start Mode */
#define ADC_CR_START_MODE_SEL(SEL) ((SEL<<24))
/** Start conversion now */
#define ADC_CR_START_NOW ((1UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
#define ADC_CR_START_CTOUT15 ((2UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
#define ADC_CR_START_CTOUT8 ((3UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
#define ADC_CR_START_ADCTRIG0 ((4UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
#define ADC_CR_START_ADCTRIG1 ((5UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
#define ADC_CR_START_MCOA2 ((6UL<<24))
/** Start conversion on a falling edge on the selected CAP/MAT signal */
#define ADC_CR_EDGE ((1UL<<27))
/*********************************************************************//**
* Macro defines for ADC Global Data register
**********************************************************************/
/** When DONE is 1, this field contains result value of ADC conversion */
#define ADC_GDR_RESULT(n) (((n>>4)&0xFFF))
/** These bits contain the channel from which the LS bits were converted */
#define ADC_GDR_CH(n) (((n>>24)&0x7))
/** This bit is 1 in burst mode if the results of one or
* more conversions was (were) lost */
#define ADC_GDR_OVERRUN_FLAG ((1UL<<30))
/** This bit is set to 1 when an A/D conversion completes */
#define ADC_GDR_DONE_FLAG ((1UL<<31))
/** This bits is used to mask for Channel */
#define ADC_GDR_CH_MASK ((7UL<<24))
/*********************************************************************//**
* Macro defines for ADC Interrupt register
**********************************************************************/
/** These bits allow control over which A/D channels generate
* interrupts for conversion completion */
#define ADC_INTEN_CH(n) ((1UL<<n))
/** When 1, enables the global DONE flag in ADDR to generate an interrupt */
#define ADC_INTEN_GLOBAL ((1UL<<8))
/*********************************************************************//**
* Macro defines for ADC Data register
**********************************************************************/
/** When DONE is 1, this field contains result value of ADC conversion */
#define ADC_DR_RESULT(n) (((n>>6)&0x3FF))
/** These bits mirror the OVERRRUN status flags that appear in the
* result register for each A/D channel */
#define ADC_DR_OVERRUN_FLAG ((1UL<<30))
/** This bit is set to 1 when an A/D conversion completes. It is cleared
* when this register is read */
#define ADC_DR_DONE_FLAG ((1UL<<31))
/*********************************************************************//**
* Macro defines for ADC Status register
**********************************************************************/
/** These bits mirror the DONE status flags that appear in the result
* register for each A/D channel */
#define ADC_STAT_CH_DONE_FLAG(n) ((n&0xFF))
/** These bits mirror the OVERRRUN status flags that appear in the
* result register for each A/D channel */
#define ADC_STAT_CH_OVERRUN_FLAG(n) (((n>>8)&0xFF))
/** This bit is the A/D interrupt flag */
#define ADC_STAT_INT_FLAG ((1UL<<16))
/*********************************************************************//**
* Macro defines for ADC Trim register
**********************************************************************/
/** Offset trim bits for ADC operation */
#define ADC_ADCOFFS(n) (((n&0xF)<<4))
/** Written to boot code*/
#define ADC_TRIM(n) (((n&0xF)<<8))
/* ------------------- CHECK PARAM DEFINITIONS ------------------------- */
/** Check ADC parameter */
#define PARAM_ADCx(n) (((uint32_t *)n)==((uint32_t *)LPC_ADC0) || ((uint32_t *)n)==((uint32_t *)LPC_ADC1))
/** Check ADC state parameter */
#define PARAM_ADC_START_ON_EDGE_OPT(OPT) ((OPT == ADC_START_ON_RISING)||(OPT == ADC_START_ON_FALLING))
/** Check ADC state parameter */
#define PARAM_ADC_DATA_STATUS(OPT) ((OPT== ADC_DATA_BURST)||(OPT== ADC_DATA_DONE))
/** Check ADC rate parameter */
#define PARAM_ADC_RATE(rate) ((rate>0)&&(rate<=200000))
/** Check ADC bits accuracy parameter */
#define PARAM_ADC_BITSACC(x) ((x>=3)&&(x<=10))
/** Check ADC channel selection parameter */
#define PARAM_ADC_CHANNEL_SELECTION(SEL) ((SEL == ADC_CHANNEL_0)||(ADC_CHANNEL_1)\
||(SEL == ADC_CHANNEL_2)|(ADC_CHANNEL_3)\
||(SEL == ADC_CHANNEL_4)||(ADC_CHANNEL_5)\
||(SEL == ADC_CHANNEL_6)||(ADC_CHANNEL_7))
/** Check ADC start option parameter */
#define PARAM_ADC_START_OPT(OPT) ((OPT == ADC_START_CONTINUOUS)||(OPT == ADC_START_NOW)\
||(OPT == ADC_START_ON_CTOUT15)||(OPT == ADC_START_ON_CTOUT8)\
||(OPT == ADC_START_ON_ADCTRIG0)||(OPT == ADC_START_ON_ADCTRIG1)\
||(OPT == ADC_START_ON_MCOA2))
/** Check ADC interrupt type parameter */
#define PARAM_ADC_TYPE_INT_OPT(OPT) ((OPT == ADC_ADINTEN0)||(OPT == ADC_ADINTEN1)\
||(OPT == ADC_ADINTEN2)||(OPT == ADC_ADINTEN3)\
||(OPT == ADC_ADINTEN4)||(OPT == ADC_ADINTEN5)\
||(OPT == ADC_ADINTEN6)||(OPT == ADC_ADINTEN7)\
||(OPT == ADC_ADGINTEN))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup ADC_Public_Types ADC Public Types
* @{
*/
/*********************************************************************//**
* @brief ADC enumeration
**********************************************************************/
/** @brief Channel Selection */
typedef enum
{
ADC_CHANNEL_0 = 0, /*!< Channel 0 */
ADC_CHANNEL_1, /*!< Channel 1 */
ADC_CHANNEL_2, /*!< Channel 2 */
ADC_CHANNEL_3, /*!< Channel 3 */
ADC_CHANNEL_4, /*!< Channel 4 */
ADC_CHANNEL_5, /*!< Channel 5 */
ADC_CHANNEL_6, /*!< Channel 6 */
ADC_CHANNEL_7 /*!< Channel 7 */
}ADC_CHANNEL_SELECTION;
/** @brief Type of start option */
typedef enum
{
ADC_START_CONTINUOUS =0, /*!< Continuous mode */
ADC_START_NOW, /*!< Start conversion now */
ADC_START_ON_CTOUT15, /*!< Start conversion when the edge selected
* by bit 27 occurs on CTOUT_15 */
ADC_START_ON_CTOUT8, /*!< Start conversion when the edge selected
* by bit 27 occurs on CTOUT_8 */
ADC_START_ON_ADCTRIG0, /*!< Start conversion when the edge selected
* by bit 27 occurs on ADCTRIG0 */
ADC_START_ON_ADCTRIG1, /*!< Start conversion when the edge selected
* by bit 27 occurs on ADCTRIG1 */
ADC_START_ON_MCOA2 /*!< Start conversion when the edge selected
* by bit 27 occurs on Motocon PWM output MCOA2 */
} ADC_START_OPT;
/** @brief Type of edge when start conversion on the selected CAP/MAT signal */
typedef enum
{
ADC_START_ON_RISING = 0, /*!< Start conversion on a rising edge
*on the selected CAP/MAT signal */
ADC_START_ON_FALLING /*!< Start conversion on a falling edge
*on the selected CAP/MAT signal */
} ADC_START_ON_EDGE_OPT;
/** @brief* ADC type interrupt enum */
typedef enum
{
ADC_ADINTEN0 = 0, /*!< Interrupt channel 0 */
ADC_ADINTEN1, /*!< Interrupt channel 1 */
ADC_ADINTEN2, /*!< Interrupt channel 2 */
ADC_ADINTEN3, /*!< Interrupt channel 3 */
ADC_ADINTEN4, /*!< Interrupt channel 4 */
ADC_ADINTEN5, /*!< Interrupt channel 5 */
ADC_ADINTEN6, /*!< Interrupt channel 6 */
ADC_ADINTEN7, /*!< Interrupt channel 7 */
ADC_ADGINTEN /*!< Individual channel/global flag done generate an interrupt */
}ADC_TYPE_INT_OPT;
/** @brief ADC Data status */
typedef enum
{
ADC_DATA_BURST = 0, /*Burst bit*/
ADC_DATA_DONE /*Done bit*/
}ADC_DATA_STATUS;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup ADC_Public_Functions ADC Public Functions
* @{
*/
/* Init/DeInit ADC peripheral ----------------*/
void ADC_Init(LPC_ADCn_Type *ADCx, uint32_t rate, uint8_t bits_accuracy);
void ADC_DeInit(LPC_ADCn_Type *ADCx);
/* Enable/Disable ADC functions --------------*/
void ADC_BurstCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState);
void ADC_PowerdownCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState);
void ADC_StartCmd(LPC_ADCn_Type *ADCx, uint8_t start_mode);
void ADC_ChannelCmd (LPC_ADCn_Type *ADCx, uint8_t Channel, FunctionalState NewState);
/* Configure ADC functions -------------------*/
void ADC_EdgeStartConfig(LPC_ADCn_Type *ADCx, uint8_t EdgeOption);
void ADC_IntConfig (LPC_ADCn_Type *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState);
/* Get ADC information functions -------------------*/
uint16_t ADC_ChannelGetData(LPC_ADCn_Type *ADCx, uint8_t channel);
FlagStatus ADC_ChannelGetStatus(LPC_ADCn_Type *ADCx, uint8_t channel, uint32_t StatusType);
uint32_t ADC_GlobalGetData(LPC_ADCn_Type *ADCx);
FlagStatus ADC_GlobalGetStatus(LPC_ADCn_Type *ADCx, uint32_t StatusType);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_ADC_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_atimer.h
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/**********************************************************************
* $Id$ lpc43xx_atimer.h 2011-06-02
*//**
* @file lpc43xx_atimer.h
* @brief Contains all functions support for Alarm Timer firmware
* library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup ATIMER ATIMER (Alarm Timer)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef __lpc43xx_ATIMER_H_
#define __lpc43xx_ATIMER_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup ATIMER_Private_Macros ALARM Timer Private Macros
* @{
*/
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/** Macro to determine if it is valid ALARM TIMER peripheral */
#define PARAM_ATIMERx(n) (((uint32_t *)n)==((uint32_t *)LPC_ATIMER))
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup ATIMER_Public_Functions ATIMER Public Functions
* @{
*/
/* Init/DeInit ATIMER functions -----------*/
void ATIMER_Init(LPC_ATIMER_Type *ATIMERx, uint32_t PresetValue);
void ATIMER_DeInit(LPC_ATIMER_Type *ATIMERx);
/* ATIMER interrupt functions -------------*/
void ATIMER_IntEnable(LPC_ATIMER_Type *ATIMERx);
void ATIMER_IntDisable(LPC_ATIMER_Type *ATIMERx);
void ATIMER_ClearIntStatus(LPC_ATIMER_Type *ATIMERx);
void ATIMER_SetIntStatus(LPC_ATIMER_Type *ATIMERx);
/* ATIMER configuration functions --------*/
void ATIMER_UpdatePresetValue(LPC_ATIMER_Type *ATIMERx,uint32_t PresetValue);
uint32_t ATIMER_GetPresetValue(LPC_ATIMER_Type *ATIMERx);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __lpc43xx_ATIMER_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_can.h
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/**********************************************************************
* $Id$ lpc43xx_can.h 2011-06-02
*//**
* @file lpc43xx_can.h
* @brief Contains all macro definitions and function prototypes
* support for CAN firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup C_CAN C_CAN (Controller Area Network)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef __lpc43xx_CAN_H
#define __lpc43xx_CAN_H
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup C_CAN_Public_Macros C_CAN Public Macros
* @{
*/
/** In BASIC_MODE IF1 registers are used directly as TX buffer, IF2 registers are used as RX buffer.
* If not BASIC_MODE use message objects and IF registers to communicate with message buffers
*/
#define BASIC_MODE 0
/** In Silent Mode, the CAN controller is able to receive valid data frames and valid remote
* frames, but it sends only recessive bits on the CAN bus, and it cannot start a transmission
*/
#define SILENT_MODE 0
/** In Loop-back Mode, the CAN Core treats its own transmitted messages as received messages
* and stores them (if they pass acceptance filtering) into a Receive Buffer.
*/
#define LOOPBACK_MODE 0
/** Enables receiving remote frame requests */
#define REMOTE_ENABLE 1
/**
* @}
*/
/* Private Macros -------------------------------------------------------------- */
/** @defgroup C_CAN_Private_Macros C_CAN Private Macros
* @{
*/
/** MAX CAN message obj */
#define CAN_MSG_OBJ_MAX 0x0020
/** MAX data length */
#define CAN_DLC_MAX 8
/********************************************************************//**
* BRP+1 = Fpclk/(CANBitRate * QUANTAValue)
* QUANTAValue = 1 + (Tseg1+1) + (Tseg2+1)
* QUANTA value varies based on the Fpclk and sample point
* e.g. (1) sample point is 87.5%, Fpclk is 48Mhz
* the QUANTA should be 16
* (2) sample point is 90%, Fpclk is 12.5Mhz
* the QUANTA should be 10
* Fpclk = Fclk /APBDIV
* or
* BitRate = Fcclk/(APBDIV * (BRP+1) * ((Tseg1+1)+(Tseg2+1)+1))
*/
/*********************************************************************//**
* @brief CAN Bit Timing Values definitions at 8Mhz
**********************************************************************/
/** Bitrate: 100K */
#define CAN_BITRATE100K12MHZ 0x00004509
/** Bitrate: 125K */
#define CAN_BITRATE125K12MHZ 0x00004507
/** Bitrate: 250K */
#define CAN_BITRATE250K12MHZ 0x00004503
/** Bitrate: 500K */
#define CAN_BITRATE500K12MHZ 0x00004501
/** Bitrate: 1000K */
#define CAN_BITRATE1000K12MHZ 0x00004500
/*********************************************************************//**
* @brief CAN Bit Timing Values definitions at 16Mhz
**********************************************************************/
/** Bitrate: 100K */
#define CAN_BITRATE100K16MHZ 0x00005809
/** Bitrate: 125K */
#define CAN_BITRATE125K16MHZ 0x00005807
/** Bitrate: 250K */
#define CAN_BITRATE250K16MHZ 0x00005803
/** Bitrate: 500K */
#define CAN_BITRATE500K16MHZ 0x00005801
/*********************************************************************//**
* @brief CAN Bit Timing Values definitions at 24Mhz
**********************************************************************/
/** Bitrate: 100K */
#define CAN_BITRATE100K24MHZ 0x00007E09
/** Bitrate: 125K */
#define CAN_BITRATE125K24MHZ 0x0000450F
/** Bitrate: 250K */
#define CAN_BITRATE250K24MHZ 0x00004507
/** Bitrate: 500K */
#define CAN_BITRATE500K24MHZ 0x00004503
/** Bitrate: 1000K */
#define CAN_BITRATE1000K24MHZ 0x00004501
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup CAN_Public_Types CAN Public Types
* @{
*/
/*********************************************************************//**
* @brief CAN enumeration
**********************************************************************/
/**
* @brief CAN interface register type definition
*/
typedef enum CCAN_IFREG
{
CMDREQ = 0, /**< Command request */
CMDMSK = 1, /**< Command mask */
MSK1 = 2, /**< Mask 1 */
MSK2 = 3, /**< Mask 2 */
ARB1 = 4, /**< Arbitration 1 */
ARB2 = 5, /**< Arbitration 2 */
MCTRL = 6, /**< Message control */
DA1 = 7, /**< Data A1 */
DA2 = 8, /**< Data A2 */
DB1 = 9, /**< Data B1 */
DB2 = 10 /**< Data B2 */
}CCAN_IFREG_Type;
/**
* @brief CAN Clock division rate type definition
*/
typedef enum CCAN_CLKDIV
{
CLKDIV1 = 0,
CLKDIV2 = 1,
CLKDIV3 = 2,
CLKDIV5 = 3,
CLKDIV9 = 4,
CLKDIV17 = 5,
CLKDIV33 = 6,
CLKDIV65 = 7
}CCAN_CLKDIV_Type;
/********************************************************************//**
* @brief Data structure definition for a CAN message
**********************************************************************/
/**
* @brief CAN message object structure
*/
typedef struct
{
uint32_t id; /**< ID of message, if bit 30 is set then this is extended frame */
uint32_t dlc; /**< Message data length */
uint8_t data[8]; /**< Message data */
} message_object;
/**
* @brief CAN call-back function
*/
typedef void (*MSG_CB)(uint32_t msg_no);
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup CAN_Public_Functions CAN Public Functions
* @{
*/
void CAN_IRQHandler (void);
void CAN_Init( uint32_t BitClk, CCAN_CLKDIV_Type ClkDiv , MSG_CB Tx_cb, MSG_CB Rx_cb);
void CAN_ConfigureRxMessageObjects( void );
void CAN_RxInt_MessageProcess( uint8_t MsgObjNo );
void CAN_TxInt_MessageProcess( uint8_t MsgObjNo );
void CAN_Send(uint8_t msg_no, uint32_t *msg_ptr );
void CAN_Recv(uint8_t msg_no, uint32_t *msg_ptr, Bool RemoteEnable);
void CAN_ReadMsg(uint32_t msg_no, message_object* buff);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __lpc43xx_CAN_H */
/**
* @}
*/
/*****************************************************************************
** End Of File
******************************************************************************/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_cgu.h
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/**********************************************************************
* $Id$ lpc43xx_cgu.h 2011-06-02
*//**
* @file llpc43xx_cgu.h
* @brief Contains all macro definitions and function prototypes
* support for Clock Generation and Clock Control firmware
* library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup CGU CGU (Clock Generation Unit)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_CGU_H_
#define lpc43xx_CGU_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros -------------------------------------------------------------- */
/** @defgroup CGU_Private_Macros CGU Private Macros
* @{
*/
/** Branch clocks from CGU_BASE_SAFE */
#define CGU_ENTITY_NONE CGU_ENTITY_NUM
/** Check bit at specific position is clear or not */
#define ISBITCLR(x,bit) ((x&(1<<bit))^(1<<bit))
/** Check bit at specific position is set or not */
#define ISBITSET(x,bit) (x&(1<<bit))
/** Set mask */
#define ISMASKSET(x,mask) (x&mask)
/** CGU number of clock source */
#define CGU_CLKSRC_NUM (CGU_CLKSRC_IDIVE+1)
/*********************************************************************//**
* Macro defines for CGU control mask bit definitions
**********************************************************************/
/** CGU control enable mask bit */
#define CGU_CTRL_EN_MASK 1
/** CGU control clock-source mask bit */
#define CGU_CTRL_SRC_MASK (0xF<<24)
/** CGU control auto block mask bit */
#define CGU_CTRL_AUTOBLOCK_MASK (1<<11)
/*********************************************************************//**
* Macro defines for CGU PLL1 mask bit definitions
**********************************************************************/
/** CGU PLL1 feedback select mask bit */
#define CGU_PLL1_FBSEL_MASK (1<<6)
/** CGU PLL1 Input clock bypass control mask bit */
#define CGU_PLL1_BYPASS_MASK (1<<1)
/** CGU PLL1 direct CCO output mask bit */
#define CGU_PLL1_DIRECT_MASK (1<<7)
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup CGU_Public_Types CGU Public Types
* @{
*/
/*********************************************************************//**
* @brief CGU enumeration
**********************************************************************/
/*
* @brief CGU clock source enumerate definition
*/
typedef enum {
/* Clock Source */
CGU_CLKSRC_32KHZ_OSC = 0, /**< 32KHz oscillator clock source */
CGU_CLKSRC_IRC, /**< IRC 12 Mhz clock source */
CGU_CLKSRC_ENET_RX_CLK, /**< Ethernet receive clock source */
CGU_CLKSRC_ENET_TX_CLK, /**< Ethernet transmit clock source */
CGU_CLKSRC_GP_CLKIN, /**< General purpose clock source */
CGU_CLKSRC_TCK, /**< TCK clock source */
CGU_CLKSRC_XTAL_OSC, /**< Crystal oscillator clock source*/
CGU_CLKSRC_PLL0, /**< PLL0 (USB0) clock source */
CGU_CLKSRC_PLL0_AUDIO,
CGU_CLKSRC_PLL1, /**< PLL1 clock source */
CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3, /**< IDIVA clock source */
CGU_CLKSRC_IDIVB, /**< IDIVB clock source */
CGU_CLKSRC_IDIVC, /**< IDIVC clock source */
CGU_CLKSRC_IDIVD, /**< IDIVD clock source */
CGU_CLKSRC_IDIVE, /**< IDIVE clock source */
/* Base */
CGU_BASE_SAFE, /**< Base save clock (always on) for WDT */
CGU_BASE_USB0, /**< USB0 base clock */
CGU_BASE_PERIPH, /** Peripheral bus (SGPIO) */
CGU_BASE_USB1, /**< USB1 base clock */
CGU_BASE_M4, /**< ARM Cortex-M4 Core base clock */
CGU_BASE_SPIFI, /**< SPIFI base clock */
CGU_BASE_PHY_RX = CGU_BASE_SPIFI + 2, /**< Ethernet PHY Rx base clock */
CGU_BASE_PHY_TX, /**< Ethernet PHY Tx base clock */
CGU_BASE_APB1, /**< APB peripheral block #1 base clock */
CGU_BASE_APB3, /**< APB peripheral block #3 base clock */
CGU_BASE_LCD, /**< LCD base clock */
CGU_BASE_ENET_CSR,
CGU_BASE_SDIO, /**< SDIO base clock */
CGU_BASE_SSP0, /**< SSP0 base clock */
CGU_BASE_SSP1, /**< SSP1 base clock */
CGU_BASE_UART0, /**< UART0 base clock */
CGU_BASE_UART1, /**< UART1 base clock */
CGU_BASE_UART2, /**< UART2 base clock */
CGU_BASE_UART3, /**< UART3 base clock */
CGU_BASE_CLKOUT, /**< CLKOUT base clock */
CGU_BASE_APLL = CGU_BASE_CLKOUT + 5,
CGU_BASE_OUT0,
CGU_BASE_OUT1,
CGU_ENTITY_NUM /**< Number or clock source entity */
} CGU_ENTITY_T;
/*
* @brief CGU PPL0 mode enumerate definition
*/
typedef enum {
CGU_PLL0_MODE_1d = 0,
CGU_PLL0_MODE_1c,
CGU_PLL0_MODE_1b,
CGU_PLL0_MODE_1a
}CGU_PLL0_MODE;
/*
* @brief CGU peripheral enumerate definition
*/
typedef enum {
CGU_PERIPHERAL_ADC0 = 0, /**< ADC0 */
CGU_PERIPHERAL_ADC1, /**< ADC1 */
CGU_PERIPHERAL_AES, /**< AES */
// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
CGU_PERIPHERAL_APB1_BUS, /**< APB1 bus */
CGU_PERIPHERAL_APB3_BUS, /**< APB3 bus */
CGU_PERIPHERAL_CAN, /**< CAN */
CGU_PERIPHERAL_CREG, /**< CREG */
CGU_PERIPHERAL_DAC, /**< DAC */
CGU_PERIPHERAL_DMA, /**< DMA */
CGU_PERIPHERAL_EMC, /**< EMC */
CGU_PERIPHERAL_ETHERNET, /**< Ethernet */
CGU_PERIPHERAL_ETHERNET_TX, //HIDE /**< Ethernet transmit */
CGU_PERIPHERAL_GPIO, /**< GPIO */
CGU_PERIPHERAL_I2C0, /**< I2C0 */
CGU_PERIPHERAL_I2C1, /**< I2C1 */
CGU_PERIPHERAL_I2S, /**< I2S */
CGU_PERIPHERAL_LCD, /**< LCD */
CGU_PERIPHERAL_M4CORE, /**< ARM Cortex-M4 Core */
CGU_PERIPHERAL_M4_BUS, /**< ARM Cortex-M4 Bus */
CGU_PERIPHERAL_MOTOCON, /**< Motor Control */
CGU_PERIPHERAL_QEI, /**< QEI */
CGU_PERIPHERAL_RITIMER, /**< RIT Timer */
CGU_PERIPHERAL_SCT, /**< SCT */
CGU_PERIPHERAL_SCU, /**< SCU */
CGU_PERIPHERAL_SDIO, /**< SDIO */
CGU_PERIPHERAL_SPIFI, /**< SPIFI */
CGU_PERIPHERAL_SSP0, /**< SSP0 */
CGU_PERIPHERAL_SSP1, /**< SSP1 */
CGU_PERIPHERAL_TIMER0, /**< TIMER 0 */
CGU_PERIPHERAL_TIMER1, /**< TIMER 1 */
CGU_PERIPHERAL_TIMER2, /**< TIMER 2 */
CGU_PERIPHERAL_TIMER3, /**< TIMER 3 */
CGU_PERIPHERAL_UART0, /**< UART0 */
CGU_PERIPHERAL_UART1, /**< UART1 */
CGU_PERIPHERAL_UART2, /**< UART2 */
CGU_PERIPHERAL_UART3, /**< UART3 */
CGU_PERIPHERAL_USB0, /**< USB0 */
CGU_PERIPHERAL_USB1, /**< USB1 */
CGU_PERIPHERAL_WWDT, /**< WWDT */
CGU_PERIPHERAL_NUM
} CGU_PERIPHERAL_T;
/**
* @brief CGU error status enumerate definition
*/
typedef enum {
CGU_ERROR_SUCCESS = 0,
CGU_ERROR_CONNECT_TOGETHER,
CGU_ERROR_INVALID_ENTITY,
CGU_ERROR_INVALID_CLOCK_SOURCE,
CGU_ERROR_INVALID_PARAM,
CGU_ERROR_FREQ_OUTOF_RANGE
} CGU_ERROR;
/********************************************************************//**
* @brief CGU structure definitions
**********************************************************************/
/*
* @brief CGU peripheral clock structure
*/
typedef struct {
uint8_t RegBaseEntity; /**< Base register address */
uint16_t RegBranchOffset; /**< Branch register offset */
uint8_t PerBaseEntity; /**< Base peripheral address */
uint16_t PerBranchOffset; /**< Base peripheral offset */
uint8_t next; /**< Pointer to next structure */
} CGU_PERIPHERAL_S;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup CGU_Public_Functions CGU Public Functions
* @{
*/
/** Clock generate initialize/de-initialize */
uint32_t CGU_Init(void);
uint32_t CGU_DeInit(void);
/** Clock Generator and Clock Control */
uint32_t CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en);
uint32_t CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock);
/** Clock Source and Base Clock operation */
uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency);
uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor);
uint32_t CGU_SetPLL0(void);
uint32_t CGU_SetPLL0audio(void);
uint32_t CGU_SetPLL1(uint32_t mult);
uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en);
uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity);
uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base);
void CGU_UpdateClock(void);
uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_CGU_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_dac.h
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/**********************************************************************
* $Id$ lpc43xx_dac.h 2011-06-02
*//**
* @file lpc43xx_dac.h
* @brief Contains all macro definitions and function prototypes
* support for DAC firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup DAC DAC (Digital to Analog Converter)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_DAC_H_
#define lpc43xx_DAC_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup DAC_Private_Macros DAC Private Macros
* @{
*/
/** After the selected settling time after this field is written with a
new VALUE, the voltage on the AOUT pin (with respect to VSSA)
is VALUE/1024 � VREF */
#define DAC_VALUE(n) ((uint32_t)((n&0x3FF)<<6))
/** If this bit = 0: The settling time of the DAC is 1 microsecond max,
* and the maximum current is 700 microAmpere
* If this bit = 1: The settling time of the DAC is 2.5 microsecond
* and the maximum current is 350 microAmpere */
#define DAC_BIAS_EN ((uint32_t)(1<<16))
/** Value to reload interrupt DMA counter */
#define DAC_CCNT_VALUE(n) ((uint32_t)(n&0xffff))
/** DCAR double buffering */
#define DAC_DBLBUF_ENA ((uint32_t)(1<<1))
/** DCAR Time out count enable */
#define DAC_CNT_ENA ((uint32_t)(1<<2))
/** DCAR DMA access */
#define DAC_DMA_ENA ((uint32_t)(1<<3))
/** DCAR DACCTRL mask bit */
#define DAC_DACCTRL_MASK ((uint32_t)(0x0F))
/** Macro to determine if it is valid DAC peripheral */
#define PARAM_DACx(n) (((uint32_t *)n)==((uint32_t *)LPC_DAC))
/** Macro to check DAC current optional parameter */
#define PARAM_DAC_CURRENT_OPT(OPTION) ((OPTION == DAC_MAX_CURRENT_700uA)\
||(OPTION == DAC_MAX_CURRENT_350uA))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup DAC_Public_Types DAC Public Types
* @{
*/
/**
* @brief Current option in DAC configuration option */
typedef enum
{
DAC_MAX_CURRENT_700uA = 0, /*!< The settling time of the DAC is 1 us max,
and the maximum current is 700 uA */
DAC_MAX_CURRENT_350uA /*!< The settling time of the DAC is 2.5 us
and the maximum current is 350 uA */
} DAC_CURRENT_OPT;
/**
* @brief Configuration for DAC converter control register */
typedef struct
{
uint8_t DBLBUF_ENA; /**<
-0: Disable DACR double buffering
-1: when bit CNT_ENA, enable DACR double buffering feature
*/
uint8_t CNT_ENA; /*!<
-0: Time out counter is disable
-1: Time out conter is enable
*/
uint8_t DMA_ENA; /*!<
-0: DMA access is disable
-1: DMA burst request
*/
uint8_t RESERVED;
} DAC_CONVERTER_CFG_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup DAC_Public_Functions DAC Public Functions
* @{
*/
void DAC_Init(LPC_DAC_Type *DACx);
void DAC_UpdateValue (LPC_DAC_Type *DACx, uint32_t dac_value);
void DAC_SetBias (LPC_DAC_Type *DACx,uint32_t bias);
void DAC_ConfigDAConverterControl (LPC_DAC_Type *DACx,DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct);
void DAC_SetDMATimeOut(LPC_DAC_Type *DACx,uint32_t time_out);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_DAC_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_emc.h
+101
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/**********************************************************************
* $Id: lpc43xx_emc.h 8765 2011-12-08 00:51:21Z nxp21346 $ lpc43xx_emc.h 2011-12-07
*//**
* @file lpc43xx_emc.h
* @brief Contains all functions support for Clock Generation and Control
* firmware library on lpc43xx
* @version 1.0
* @date 07. December. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors’
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
#define __CRYSTAL (12000000UL) /* Crystal Oscillator frequency */
#define __PLLMULT (15)
#define __PLLOUTHZ (__CRYSTAL * __PLLMULT)
#define __EMCDIV (2)
#define __EMCHZ (__PLLOUTHZ / __EMCDIV)
void MemoryPinInit(void);
void EMCFlashInit(void);
/* SDRAM Address Base for DYCS0*/
#define SDRAM_BASE_ADDR 0x28000000
#define FLASH_BASE_ADDR 0x1C000000
#define EMC_SDRAM_WIDTH_8_BITS 0
#define EMC_SDRAM_WIDTH_16_BITS 1
#define EMC_SDRAM_WIDTH_32_BITS 2
#define EMC_SDRAM_SIZE_16_MBITS 0
#define EMC_SDRAM_SIZE_64_MBITS 1
#define EMC_SDRAM_SIZE_128_MBITS 2
#define EMC_SDRAM_SIZE_256_MBITS 3
#define EMC_SDRAM_SIZE_512_MBITS 4
#define EMC_SDRAM_DATA_BUS_16_BITS 0
#define EMC_SDRAM_DATA_BUS_32_BITS 1
#define EMC_B_ENABLE (1 << 19)
#define EMC_ENABLE (1 << 0)
#define EMC_CE_ENABLE (1 << 0)
#define EMC_CS_ENABLE (1 << 1)
#define EMC_CLOCK_DELAYED_STRATEGY (0 << 0)
#define EMC_COMMAND_DELAYED_STRATEGY (1 << 0)
#define EMC_COMMAND_DELAYED_STRATEGY2 (2 << 0)
#define EMC_COMMAND_DELAYED_STRATEGY3 (3 << 0)
#define EMC_INIT(i) ((i) << 7)
#define EMC_NORMAL (0)
#define EMC_MODE (1)
#define EMC_PRECHARGE_ALL (2)
#define EMC_NOP (3)
/* The Hitex LPC18xx Evaluation board contains a 64Mb SDRAM with a 16-bit data bus */
#if(PLATFORM == HITEX_BOARD)
#define SDRAM_SIZE_BYTES (1024UL * 1024UL * 8UL)
#define SDRAM_WIDTH EMC_SDRAM_WIDTH_16_BITS
#define SDRAM_SIZE_MBITS EMC_SDRAM_SIZE_64_MBITS
#define SDRAM_DATA_BUS_BITS EMC_SDRAM_DATA_BUS_16_BITS
#define SDRAM_COL_ADDR_BITS 8
#endif
#if(PLATFORM == KEIL_BOARD)
// TODO adapt these for the MCB4357 !!!!
#define SDRAM_SIZE_BYTES (1024UL * 1024UL * 8UL)
#define SDRAM_WIDTH EMC_SDRAM_WIDTH_16_BITS
#define SDRAM_SIZE_MBITS EMC_SDRAM_SIZE_64_MBITS
#define SDRAM_DATA_BUS_BITS EMC_SDRAM_DATA_BUS_16_BITS
#define SDRAM_COL_ADDR_BITS 8
#endif
// CLK0_DELAY needs to be tuned depending on the external memory bus speed.
// For operation at 102 MHz it should be 6 or 7
#define CLK0_DELAY 7
void vEMC_InitSRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits);
void emc_WaitUS(volatile uint32_t us);
void emc_WaitMS(uint32_t ms);
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_evrt.h
+151
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/**********************************************************************
* $Id$ lpc43xx_evrt.h 2011-06-02
*//**
* @file lpc43xx_evrt.h
* @brief Contains all macro definitions and function prototypes
* support for Event Router firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup EVRT EVRT (Event Router)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_EVRT_H_
#define lpc43xx_EVRT_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup EVRT_Private_Macros EVRT Private Macros
* @{
*/
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/** Macro to determine if it is valid EVRT peripheral */
#define PARAM_EVRTx(x) (((uint32_t *)x)==((uint32_t *)LPC_EVENTROUTER))
/* Macro check EVRT source */
#define PARAM_EVRT_SOURCE(n) ((n==EVRT_SRC_WAKEUP0) || (n==EVRT_SRC_WAKEUP1) \
|| (n==EVRT_SRC_WAKEUP2) || (n==EVRT_SRC_WAKEUP3) \
|| (n==EVRT_SRC_ATIMER) || (n==EVRT_SRC_RTC) \
|| (n==EVRT_SRC_BOD1) || (n==EVRT_SRC_WWDT) \
|| (n==EVRT_SRC_ETHERNET) || (n==EVRT_SRC_USB0) \
|| (n==EVRT_SRC_USB1) || (n==EVRT_SRC_CCAN) || (n==EVRT_SRC_SDIO) \
|| (n==EVRT_SRC_COMBINE_TIMER2) || (n==EVRT_SRC_COMBINE_TIMER6) \
|| (n==EVRT_SRC_QEI) || (n==EVRT_SRC_COMBINE_TIMER14) \
|| (n==EVRT_SRC_RESET)) \
/* Macro check EVRT source active type*/
#define PARAM_EVRT_SOURCE_ACTIVE_TYPE(n) ((n==EVRT_SRC_ACTIVE_LOW_LEVEL) || (n==EVRT_SRC_ACTIVE_HIGH_LEVEL) \
|| (n==EVRT_SRC_ACTIVE_FALLING_EDGE) || (n==EVRT_SRC_ACTIVE_RISING_EDGE))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup EVRT_Public_Types EVRT Public Types
* @{
*/
/** @brief EVRT input sources */
typedef enum {
EVRT_SRC_WAKEUP0, /**< WAKEUP0 event router source */
EVRT_SRC_WAKEUP1, /**< WAKEUP1 event router source */
EVRT_SRC_WAKEUP2, /**< WAKEUP2 event router source */
EVRT_SRC_WAKEUP3, /**< WAKEUP3 event router source */
EVRT_SRC_ATIMER, /**< Alarm timer event router source */
EVRT_SRC_RTC, /**< RTC event router source */
EVRT_SRC_BOD1, /**< BOD event router source */
EVRT_SRC_WWDT, /**< WWDT event router source */
EVRT_SRC_ETHERNET, /**< Ethernet event router source */
EVRT_SRC_USB0, /**< USB0 event router source */
EVRT_SRC_USB1, /**< USB1 event router source */
EVRT_SRC_SDIO, /**< Reserved */
EVRT_SRC_CCAN, /**< C_CAN event router source */
EVRT_SRC_COMBINE_TIMER2, /**< Combined timer 2 event router source */
EVRT_SRC_COMBINE_TIMER6, /**< Combined timer 6 event router source */
EVRT_SRC_QEI, /**< QEI event router source */
EVRT_SRC_COMBINE_TIMER14, /**< Combined timer 14 event router source */
EVRT_SRC_RESERVED1, /**< Reserved */
EVRT_SRC_RESERVED2, /**< Reserved */
EVRT_SRC_RESET /**< Reset event router source */
} EVRT_SRC_ENUM;
/** @brief EVRT input sources detecting type */
typedef enum {
EVRT_SRC_ACTIVE_LOW_LEVEL, /**< Active low level */
EVRT_SRC_ACTIVE_HIGH_LEVEL, /**< Active high level */
EVRT_SRC_ACTIVE_FALLING_EDGE, /**< Active falling edge */
EVRT_SRC_ACTIVE_RISING_EDGE /**< Active rising edge */
}EVRT_SRC_ACTIVE_TYPE;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup EVRT_Public_Functions EVRT Public Functions
* @{
*/
void EVRT_Init (LPC_EVENTROUTER_Type *EVRTx);
void EVRT_DeInit(LPC_EVENTROUTER_Type *EVRTx);
void EVRT_ConfigIntSrcActiveType(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src, EVRT_SRC_ACTIVE_TYPE type);
void EVRT_SetUpIntSrc(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src, FunctionalState state);
Bool EVRT_IsSourceInterrupting(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src);
void EVRT_ClrPendIntSrc(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_EVRT_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_gpdma.h
+473
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/**********************************************************************
* $Id$ lpc43xx_gpdma.h 2011-06-02
*//**
* @file lpc43xx_gpdma.h
* @brief Contains all macro definitions and function prototypes
* support for GPDMA firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup GPDMA GPDMA (General Purpose DMA)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_GPDMA_H_
#define lpc43xx_GPDMA_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup GPDMA_Public_Macros GPDMA Public Macros
* @{
*/
/** DMA Connection number definitions */
#define GPDMA_CONN_RESERVED ((0UL))
#define GPDMA_CONN_MAT0_0 ((1UL)) /**< MAT0.0 */
#define GPDMA_CONN_UART0_Tx ((2UL)) /**< UART0 Tx */
#define GPDMA_CONN_MAT0_1 ((3UL)) /**< MAT0.1 */
#define GPDMA_CONN_UART0_Rx ((4UL)) /**< UART0 Rx */
#define GPDMA_CONN_MAT1_0 ((5UL)) /**< MAT1.0 */
#define GPDMA_CONN_UART1_Tx ((6UL)) /**< UART1 Tx */
#define GPDMA_CONN_MAT1_1 ((7UL)) /**< MAT1.1 */
#define GPDMA_CONN_UART1_Rx ((8UL)) /**< UART1 Rx */
#define GPDMA_CONN_MAT2_0 ((9UL)) /**< MAT2.0 */
#define GPDMA_CONN_UART2_Tx ((10UL)) /**< UART2 Tx */
#define GPDMA_CONN_MAT2_1 ((11UL)) /**< MAT2.1 */
#define GPDMA_CONN_UART2_Rx ((12UL)) /**< UART2 Rx */
#define GPDMA_CONN_MAT3_0 ((13UL)) /**< MAT3.0 */
#define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */
#define GPDMA_CONN_SCT_0 ((15UL)) /**< SCT timer channel 0*/
#define GPDMA_CONN_MAT3_1 ((16UL)) /**< MAT3.1 */
#define GPDMA_CONN_UART3_Rx ((17UL)) /**< UART3 Rx */
#define GPDMA_CONN_SCT_1 ((18UL)) /**< SCT timer channel 1*/
#define GPDMA_CONN_SSP0_Rx ((19UL)) /**< SSP0 Rx */
#define GPDMA_CONN_I2S_Channel_0 ((20UL)) /**< I2S channel 0 */
#define GPDMA_CONN_SSP0_Tx ((21UL)) /**< SSP0 Tx */
#define GPDMA_CONN_I2S_Channel_1 ((22UL)) /**< I2S channel 1 */
#define GPDMA_CONN_SSP1_Rx ((23UL)) /**< SSP1 Rx */
#define GPDMA_CONN_SSP1_Tx ((24UL)) /**< SSP1 Tx */
#define GPDMA_CONN_ADC_0 ((25UL)) /**< ADC 0 */
#define GPDMA_CONN_ADC_1 ((26UL)) /**< ADC 1 */
#define GPDMA_CONN_DAC ((27UL)) /**< DAC */
/** GPDMA Transfer type definitions */
#define GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA ((0UL)) /**< Memory to memory - DMA control */
#define GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA ((1UL)) /**< Memory to peripheral - DMA control */
#define GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA ((2UL)) /**< Peripheral to memory - DMA control */
#define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA ((3UL)) /**< Source peripheral to destination peripheral - DMA control */
#define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL ((4UL)) /**< Source peripheral to destination peripheral - destination peripheral control */
#define GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL ((5UL)) /**< Memory to peripheral - peripheral control */
#define GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL ((6UL)) /**< Peripheral to memory - peripheral control */
#define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL ((7UL)) /**< Source peripheral to destination peripheral - source peripheral control */
/** Burst size in Source and Destination definitions */
#define GPDMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */
#define GPDMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */
#define GPDMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */
#define GPDMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */
#define GPDMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */
#define GPDMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */
#define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
#define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
/** Width in Source transfer width and Destination transfer width definitions */
#define GPDMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */
#define GPDMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */
#define GPDMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */
/** LPC_GPDMA base addresses */
#define LPC_GPDMACH0_BASE 0x40002100
#define LPC_GPDMACH1_BASE 0x40002120
#define LPC_GPDMACH2_BASE 0x40002140
#define LPC_GPDMACH3_BASE 0x40002160
#define LPC_GPDMACH4_BASE 0x40002180
#define LPC_GPDMACH5_BASE 0x400021A0
#define LPC_GPDMACH6_BASE 0x400021C0
#define LPC_GPDMACH7_BASE 0x400021E0
/* LPC_GPDMA channels definitions */
#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
/**
* @}
*/
/* Private Macros ------------------------------------------------------------- */
/** @defgroup GPDMA_Private_Macros GPDMA Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*********************************************************************//**
* Macro defines for DMA Interrupt Status register
**********************************************************************/
#define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACIntStat_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Interrupt Terminal Count Request Status register
**********************************************************************/
#define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACIntTCStat_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Interrupt Terminal Count Request Clear register
**********************************************************************/
#define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACIntTCClear_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Interrupt Error Status register
**********************************************************************/
#define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACIntErrStat_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Interrupt Error Clear register
**********************************************************************/
#define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACIntErrClr_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Raw Interrupt Terminal Count Status register
**********************************************************************/
#define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Raw Error Interrupt Status register
**********************************************************************/
#define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Enabled Channel register
**********************************************************************/
#define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACEnbldChns_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Software Burst Request register
**********************************************************************/
#define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF))
#define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF))
/*********************************************************************//**
* Macro defines for DMA Software Single Request register
**********************************************************************/
#define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF))
#define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF))
/*********************************************************************//**
* Macro defines for DMA Software Last Burst Request register
**********************************************************************/
#define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF))
#define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF))
/*********************************************************************//**
* Macro defines for DMA Software Last Single Request register
**********************************************************************/
#define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF))
#define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF))
/*********************************************************************//**
* Macro defines for DMA Configuration register
**********************************************************************/
#define GPDMA_DMACConfig_E ((0x01)) /**< DMA Controller enable*/
#define GPDMA_DMACConfig_M0 ((0x02)) /**< AHB Master 0 endianness configuration*/
#define GPDMA_DMACConfig_M1 ((0x04)) /**< AHB Master 1 endianness configuration*/
#define GPDMA_DMACConfig_BITMASK ((0x07))
/*********************************************************************//**
* Macro defines for DMA Synchronization register
**********************************************************************/
#define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF))
#define GPDMA_DMACSync_BITMASK ((0xFFFF))
/*********************************************************************//**
* Macro defines for DMA Channel Linked List Item registers
**********************************************************************/
/** DMA Channel Linked List Item registers bit mask*/
#define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC))
/*********************************************************************//**
* Macro defines for DMA channel control registers
**********************************************************************/
#define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0)) /**< Transfer size*/
#define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12)) /**< Source burst size*/
#define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15)) /**< Destination burst size*/
#define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18)) /**< Source transfer width*/
#define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21)) /**< Destination transfer width*/
#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 ((1UL<<24)) /**< Source AHB master select*/
#define GPDMA_DMACCxControl_DestTransUseAHBMaster1 ((1UL<<25)) /**< Destination AHB master select*/
#define GPDMA_DMACCxControl_SI ((1UL<<26)) /**< Source increment*/
#define GPDMA_DMACCxControl_DI ((1UL<<27)) /**< Destination increment*/
#define GPDMA_DMACCxControl_Prot1 ((1UL<<28)) /**< Indicates that the access is in user mode or privileged mode*/
#define GPDMA_DMACCxControl_Prot2 ((1UL<<29)) /**< Indicates that the access is bufferable or not bufferable*/
#define GPDMA_DMACCxControl_Prot3 ((1UL<<30)) /**< Indicates that the access is cacheable or not cacheable*/
#define GPDMA_DMACCxControl_I ((1UL<<31)) /**< Terminal count interrupt enable bit */
/** DMA channel control registers bit mask */
#define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF))
/*********************************************************************//**
* Macro defines for DMA Channel Configuration registers
**********************************************************************/
#define GPDMA_DMACCxConfig_E ((1UL<<0)) /**< DMA control enable*/
#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1)) /**< Source peripheral*/
#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6)) /**< Destination peripheral*/
#define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11)) /**< This value indicates the type of transfer*/
#define GPDMA_DMACCxConfig_IE ((1UL<<14)) /**< Interrupt error mask*/
#define GPDMA_DMACCxConfig_ITC ((1UL<<15)) /**< Terminal count interrupt mask*/
#define GPDMA_DMACCxConfig_L ((1UL<<16)) /**< Lock*/
#define GPDMA_DMACCxConfig_A ((1UL<<17)) /**< Active*/
#define GPDMA_DMACCxConfig_H ((1UL<<18)) /**< Halt*/
/** DMA Channel Configuration registers bit mask */
#define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF))
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/* Macros check GPDMA channel */
#define PARAM_GPDMA_CHANNEL(n) (n<=7)
/* Macros check GPDMA connection type */
#define PARAM_GPDMA_CONN(n) ((n==GPDMA_CONN_RESERVED) || (n==GPDMA_CONN_DAC) \
|| (n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \
|| (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \
|| (n==GPDMA_CONN_ADC_0) || (n==GPDMA_CONN_ADC_1) \
|| (n==GPDMA_CONN_I2S_Channel_0) || (n==GPDMA_CONN_I2S_Channel_1) \
|| (n==GPDMA_CONN_SCT_0) || (n==GPDMA_CONN_SCT_1) \
|| (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \
|| (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \
|| (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \
|| (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \
|| (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \
|| (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \
|| (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \
|| (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1))
/* Macros check GPDMA burst size type */
#define PARAM_GPDMA_BSIZE(n) ((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \
|| (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \
|| (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \
|| (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256))
/* Macros check GPDMA width type */
#define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \
|| (n==GPDMA_WIDTH_WORD))
/* Macros check GPDMA status type */
#define PARAM_GPDMA_STAT(n) ((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \
|| (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \
|| (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH))
/* Macros check GPDMA transfer type */
#define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA)||(n==GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA) \
||(n==GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA)||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA)\
||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL)||(n==GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL)\
||(n==GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL)||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL))
/* Macros check GPDMA state clear type */
#define PARAM_GPDMA_STATCLR(n) ((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup GPDMA_Public_Types GPDMA Public Types
* @{
*/
/**
* @brief GPDMA Channel Registers
*/
typedef struct
{
__IO uint32_t CSrcAddr;
__IO uint32_t CDestAddr;
__IO uint32_t CLLI;
__IO uint32_t CControl;
__IO uint32_t CConfig;
} LPC_GPDMACH_TypeDef;
/**
* @brief GPDMA Status enumeration
*/
typedef enum {
GPDMA_STAT_INT, /**< GPDMA Interrupt Status */
GPDMA_STAT_INTTC, /**< GPDMA Interrupt Terminal Count Request Status */
GPDMA_STAT_INTERR, /**< GPDMA Interrupt Error Status */
GPDMA_STAT_RAWINTTC, /**< GPDMA Raw Interrupt Terminal Count Status */
GPDMA_STAT_RAWINTERR, /**< GPDMA Raw Error Interrupt Status */
GPDMA_STAT_ENABLED_CH /**< GPDMA Enabled Channel Status */
} GPDMA_Status_Type;
/**
* @brief GPDMA Interrupt clear status enumeration
*/
typedef enum{
GPDMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */
GPDMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */
}GPDMA_StateClear_Type;
/**
* @brief GPDMA Channel configuration structure type definition
*/
typedef struct {
uint32_t ChannelNum; /**< DMA channel number, should be in
range from 0 to 7.
Note: DMA channel 0 has the highest priority
and DMA channel 7 the lowest priority.
*/
uint32_t TransferSize; /**< Length/Size of transfer */
uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as
GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as
GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
uint32_t TransferType; /**< Transfer Type, should be one of the following:
- GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA: Memory to memory - DMA control
- GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA: Memory to peripheral - DMA control
- GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA: Peripheral to memory - DMA control
- GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA: Source peripheral to destination peripheral - DMA control
- GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL: Source peripheral to destination peripheral - destination peripheral control
- GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL: Memory to peripheral - peripheral control
- GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL: Peripheral to memory - peripheral control
- GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL: Source peripheral to destination peripheral - source peripheral control
*/
uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as
GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
following:
- GPDMA_CONN_SSP0_Tx: SSP0, Tx
- GPDMA_CONN_SSP0_Rx: SSP0, Rx
- GPDMA_CONN_SSP1_Tx: SSP1, Tx
- GPDMA_CONN_SSP1_Rx: SSP1, Rx
- GPDMA_CONN_ADC_0: ADC0
- GPDMA_CONN_ADC_1: ADC1
- GPDMA_CONN_SCT_0: SCT0
- GPDMA_CONN_SCT_1: SCT1
- GPDMA_CONN_I2S_Channel_0: I2S Channel 0
- GPDMA_CONN_I2S_Channel_1: I2S Channel 1
- GPDMA_CONN_DAC: DAC
- GPDMA_CONN_RESERVED:
- GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
- GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
- GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
- GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
- GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
- GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
- GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
- GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
*/
uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as
GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
following:
- GPDMA_CONN_SSP0_Tx: SSP0, Tx
- GPDMA_CONN_SSP0_Rx: SSP0, Rx
- GPDMA_CONN_SSP1_Tx: SSP1, Tx
- GPDMA_CONN_SSP1_Rx: SSP1, Rx
- GPDMA_CONN_ADC_0: ADC0
- GPDMA_CONN_ADC_1: ADC1
- GPDMA_CONN_SCT_0: SCT0
- GPDMA_CONN_SCT_1: SCT1
- GPDMA_CONN_I2S_Channel_0: I2S Channel 0
- GPDMA_CONN_I2S_Channel_1: I2S Channel 1
- GPDMA_CONN_DAC: DAC
- GPDMA_CONN_RESERVED:
- GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
- GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
- GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
- GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
- GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
- GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
- GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
- GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
*/
uint32_t DMALLI; /**< Linker List Item structure data address
if there's no Linker List, set as '0'
*/
} GPDMA_Channel_CFG_Type;
/**
* @brief GPDMA Linker List Item structure type definition
*/
typedef struct {
uint32_t SrcAddr; /**< Source Address */
uint32_t DstAddr; /**< Destination address */
uint32_t NextLLI; /**< Next LLI address, otherwise set to '0' */
uint32_t Control; /**< GPDMA Control of this LLI */
} GPDMA_LLI_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup GPDMA_Public_Functions GPDMA Public Functions
* @{
*/
void GPDMA_Init(void);
Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);
IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);
void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);
void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_GPDMA_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_gpio.h
+116
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@@ -0,0 +1,116 @@
/**********************************************************************
* $Id$ lpc43xx_gpio.h 2011-06-02
*//**
* @file lpc43xx_gpio.h
* @brief Contains all macro definitions and function prototypes
* support for GPIO firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup GPIO GPIO (General Purpose I/O)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_GPIO_H_
#define lpc43xx_GPIO_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup GPIO_Public_Macros GPIO Public Macros
* @{
*/
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup GPIO_Public_Types GPIO Public Types
* @{
*/
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup GPIO_Public_Functions GPIO Public Functions
* @{
*/
/* GPIO style ------------------------------- */
void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
void GPIO_SetValue(uint8_t portNum, uint32_t bitValue);
void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue);
uint32_t GPIO_ReadValue(uint8_t portNum);
#ifdef GPIO_INT
void GPIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
FunctionalState GPIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
void GPIO_ClearInt(uint8_t portNum, uint32_t bitValue);
#endif
/* FIO (word-accessible) style ------------------------------- */
void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
void FIO_SetValue(uint8_t portNum, uint32_t bitValue);
void FIO_ClearValue(uint8_t portNum, uint32_t bitValue);
uint32_t FIO_ReadValue(uint8_t portNum);
void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue);
#ifdef GPIO_INT
void FIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
FunctionalState FIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
void FIO_ClearInt(uint8_t portNum, uint32_t pinNum);
#endif
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_GPIO_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_i2c.h
+388
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@@ -0,0 +1,388 @@
/**********************************************************************
* $Id$ lpc43xx_i2c.h 2011-06-02
*//**
* @file lpc43xx_i2c.h
* @brief Contains all macro definitions and function prototypes
* support for I2C firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup I2C I2C (Inter-Integrated Circuit)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_I2C_H_
#define lpc43xx_I2C_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup I2C_Private_Macros I2C Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*******************************************************************//**
* I2C Control Set register description
*********************************************************************/
#define I2C_I2CONSET_AA ((0x04)) /*!< Assert acknowledge flag */
#define I2C_I2CONSET_SI ((0x08)) /*!< I2C interrupt flag */
#define I2C_I2CONSET_STO ((0x10)) /*!< STOP flag */
#define I2C_I2CONSET_STA ((0x20)) /*!< START flag */
#define I2C_I2CONSET_I2EN ((0x40)) /*!< I2C interface enable */
/*******************************************************************//**
* I2C Control Clear register description
*********************************************************************/
/** Assert acknowledge Clear bit */
#define I2C_I2CONCLR_AAC ((1<<2))
/** I2C interrupt Clear bit */
#define I2C_I2CONCLR_SIC ((1<<3))
/** START flag Clear bit */
#define I2C_I2CONCLR_STAC ((1<<5))
/** I2C interface Disable bit */
#define I2C_I2CONCLR_I2ENC ((1<<6))
/********************************************************************//**
* I2C Status Code definition (I2C Status register)
*********************************************************************/
/* Return Code in I2C status register */
#define I2C_STAT_CODE_BITMASK ((0xF8))
/* I2C return status code definitions ----------------------------- */
/** No relevant information */
#define I2C_I2STAT_NO_INF ((0xF8))
/* Master transmit mode -------------------------------------------- */
/** A start condition has been transmitted */
#define I2C_I2STAT_M_TX_START ((0x08))
/** A repeat start condition has been transmitted */
#define I2C_I2STAT_M_TX_RESTART ((0x10))
/** SLA+W has been transmitted, ACK has been received */
#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))
/** SLA+W has been transmitted, NACK has been received */
#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))
/** Data has been transmitted, ACK has been received */
#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))
/** Data has been transmitted, NACK has been received */
#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))
/** Arbitration lost in SLA+R/W or Data bytes */
#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))
/* Master receive mode -------------------------------------------- */
/** A start condition has been transmitted */
#define I2C_I2STAT_M_RX_START ((0x08))
/** A repeat start condition has been transmitted */
#define I2C_I2STAT_M_RX_RESTART ((0x10))
/** Arbitration lost */
#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))
/** SLA+R has been transmitted, ACK has been received */
#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))
/** SLA+R has been transmitted, NACK has been received */
#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))
/** Data has been received, ACK has been returned */
#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))
/** Data has been received, NACK has been return */
#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))
/* Slave receive mode -------------------------------------------- */
/** Own slave address has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))
/** Arbitration lost in SLA+R/W as master */
#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))
/** Own SLA+W has been received, ACK returned */
//#define I2C_I2STAT_S_RX_SLAW_ACK ((0x68))
/** General call address has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))
/** Arbitration lost in SLA+R/W (GENERAL CALL) as master */
#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))
/** General call address has been received, ACK has been returned */
//#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78))
/** Previously addressed with own SLV address;
* Data has been received, ACK has been return */
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))
/** Previously addressed with own SLA;
* Data has been received and NOT ACK has been return */
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))
/** Previously addressed with General Call;
* Data has been received and ACK has been return */
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))
/** Previously addressed with General Call;
* Data has been received and NOT ACK has been return */
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))
/** A STOP condition or repeated START condition has
* been received while still addressed as SLV/REC
* (Slave Receive) or SLV/TRX (Slave Transmit) */
#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))
/** Slave transmit mode */
/** Own SLA+R has been received, ACK has been returned */
#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))
/** Arbitration lost in SLA+R/W as master */
#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))
/** Own SLA+R has been received, ACK has been returned */
//#define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0))
/** Data has been transmitted, ACK has been received */
#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))
/** Data has been transmitted, NACK has been received */
#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))
/** Last data byte in I2DAT has been transmitted (AA = 0);
ACK has been received */
#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))
/** Time out in case of using I2C slave mode */
#define I2C_SLAVE_TIME_OUT 0x10000UL
/********************************************************************//**
* I2C Data register definition
*********************************************************************/
/** Mask for I2DAT register*/
#define I2C_I2DAT_BITMASK ((0xFF))
/** Idle data value will be send out in slave mode in case of the actual
* expecting data requested from the master is greater than its sending data
* length that can be supported */
#define I2C_I2DAT_IDLE_CHAR (0xFF)
/********************************************************************//**
* I2C Monitor mode control register description
*********************************************************************/
#define I2C_I2MMCTRL_MM_ENA ((1<<0)) /**< Monitor mode enable */
#define I2C_I2MMCTRL_ENA_SCL ((1<<1)) /**< SCL output enable */
#define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) /**< Select interrupt register match */
#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */
/********************************************************************//**
* I2C Data buffer register description
*********************************************************************/
/** I2C Data buffer register bit mask */
#define I2DATA_BUFFER_BITMASK ((0xFF))
/********************************************************************//**
* I2C Slave Address registers definition
*********************************************************************/
/** General Call enable bit */
#define I2C_I2ADR_GC ((1<<0))
/** I2C Slave Address registers bit mask */
#define I2C_I2ADR_BITMASK ((0xFF))
/********************************************************************//**
* I2C Mask Register definition
*********************************************************************/
/** I2C Mask Register mask field */
#define I2C_I2MASK_MASK(n) ((n&0xFE))
/********************************************************************//**
* I2C SCL HIGH duty cycle Register definition
*********************************************************************/
/** I2C SCL HIGH duty cycle Register bit mask */
#define I2C_I2SCLH_BITMASK ((0xFFFF))
/********************************************************************//**
* I2C SCL LOW duty cycle Register definition
*********************************************************************/
/** I2C SCL LOW duty cycle Register bit mask */
#define I2C_I2SCLL_BITMASK ((0xFFFF))
/* I2C status values */
#define I2C_SETUP_STATUS_ARBF (1<<8) /**< Arbitration false */
#define I2C_SETUP_STATUS_NOACKF (1<<9) /**< No ACK returned */
#define I2C_SETUP_STATUS_DONE (1<<10) /**< Status DONE */
/*********************************************************************//**
* I2C monitor control configuration defines
**********************************************************************/
#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */
#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/* Macros check I2C slave address */
#define PARAM_I2C_SLAVEADDR_CH(n) (n<=3)
/** Macro to determine if it is valid SSP port number */
#define PARAM_I2Cx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \
|| (((uint32_t *)n)==((uint32_t *)LPC_I2C1)))
/* Macros check I2C monitor configuration type */
#define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup I2C_Public_Types I2C Public Types
* @{
*/
/**
* @brief I2C Own slave address setting structure
*/
typedef struct {
uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control,
should be in range from 0..3
*/
uint8_t SlaveAddr_7bit; /**< Value of 7-bit slave address */
uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality
when I2C control being in Slave mode, should be:
- ENABLE: Enable General Call function.
- DISABLE: Disable General Call function.
*/
uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1)
which is set to '1' will cause an automatic compare on
the corresponding bit of the received address when it
is compared to the SlaveAddr_7bit value associated with this
mask register. In other words, bits in SlaveAddr_7bit value
which are masked are not taken into account in determining
an address match
*/
} I2C_OWNSLAVEADDR_CFG_Type;
/**
* @brief Master transfer setup data structure definitions
*/
typedef struct
{
uint32_t sl_addr7bit; /**< Slave address in 7bit mode */
uint8_t* tx_data; /**< Pointer to Transmit data - NULL if data transmit
is not used */
uint32_t tx_length; /**< Transmit data length - 0 if data transmit
is not used*/
uint32_t tx_count; /**< Current Transmit data counter */
uint8_t* rx_data; /**< Pointer to Receive data - NULL if data receive
is not used */
uint32_t rx_length; /**< Receive data length - 0 if data receive is
not used */
uint32_t rx_count; /**< Current Receive data counter */
uint32_t retransmissions_max; /**< Max Re-Transmission value */
uint32_t retransmissions_count; /**< Current Re-Transmission counter */
uint32_t status; /**< Current status of I2C activity */
void (*callback)(void); /**< Pointer to Call back function when transmission complete
used in interrupt transfer mode */
} I2C_M_SETUP_Type;
/**
* @brief Slave transfer setup data structure definitions
*/
typedef struct
{
uint8_t* tx_data; /**< Pointer to transmit data - NULL if data transmit is not used */
uint32_t tx_length; /**< Transmit data length - 0 if data transmit is not used */
uint32_t tx_count; /**< Current transmit data counter */
uint8_t* rx_data; /**< Pointer to receive data - NULL if data received is not used */
uint32_t rx_length; /**< Receive data length - 0 if data receive is not used */
uint32_t rx_count; /**< Current receive data counter */
uint32_t status; /**< Current status of I2C activity */
void (*callback)(void); /**< Pointer to call-back function when transmission complete
used by interrupt transfer mode */
} I2C_S_SETUP_Type;
/**
* @brief Transfer option type definitions
*/
typedef enum {
I2C_TRANSFER_POLLING = 0, /**< Transfer in polling mode */
I2C_TRANSFER_INTERRUPT /**< Transfer in interrupt mode */
} I2C_TRANSFER_OPT_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup I2C_Public_Functions I2C Public Functions
* @{
*/
/* I2C Init/DeInit functions ---------- */
void I2C_Init(LPC_I2Cn_Type *I2Cx, uint32_t clockrate);
void I2C_DeInit(LPC_I2Cn_Type* I2Cx);
//void I2C_SetClock (LPC_I2Cn_Type *I2Cx, uint32_t target_clock);
void I2C_Cmd(LPC_I2Cn_Type* I2Cx, FunctionalState NewState);
/* I2C transfer data functions -------- */
Status I2C_MasterTransferData(LPC_I2Cn_Type *I2Cx, \
I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
Status I2C_SlaveTransferData(LPC_I2Cn_Type *I2Cx, \
I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
uint32_t I2C_MasterTransferComplete(LPC_I2Cn_Type *I2Cx);
uint32_t I2C_SlaveTransferComplete(LPC_I2Cn_Type *I2Cx);
void I2C_SetOwnSlaveAddr(LPC_I2Cn_Type *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);
uint8_t I2C_GetLastStatusCode(LPC_I2Cn_Type* I2Cx);
/* I2C Monitor functions ---------------*/
void I2C_MonitorModeConfig(LPC_I2Cn_Type *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState);
void I2C_MonitorModeCmd(LPC_I2Cn_Type *I2Cx, FunctionalState NewState);
uint8_t I2C_MonitorGetDatabuffer(LPC_I2Cn_Type *I2Cx);
BOOL_8 I2C_MonitorHandler(LPC_I2Cn_Type *I2Cx, uint8_t *buffer, uint32_t size);
/* I2C Interrupt handler functions ------*/
void I2C_IntCmd (LPC_I2Cn_Type *I2Cx, Bool NewState);
void I2C_MasterHandler (LPC_I2Cn_Type *I2Cx);
void I2C_SlaveHandler (LPC_I2Cn_Type *I2Cx);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_I2C_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_i2s.h
+374
View File
@@ -0,0 +1,374 @@
/**********************************************************************
* $Id$ lpc43xx_i2s.h 2011-06-02
*//**
* @file lpc43xx_i2s.h
* @brief Contains all macro definitions and function prototypes
* support for I2S firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup I2S I2S (Inter-IC Sound)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_I2S_H_
#define lpc43xx_I2S_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
*/
/*********************************************************************//**
* I2S configuration parameter defines
**********************************************************************/
/** I2S Wordwidth bit */
#define I2S_WORDWIDTH_8 ((uint32_t)(0))
#define I2S_WORDWIDTH_16 ((uint32_t)(1))
#define I2S_WORDWIDTH_32 ((uint32_t)(3))
/** I2S Channel bit */
#define I2S_STEREO ((uint32_t)(0))
#define I2S_MONO ((uint32_t)(1))
/** I2S Master/Slave mode bit */
#define I2S_MASTER_MODE ((uint8_t)(0))
#define I2S_SLAVE_MODE ((uint8_t)(1))
/** I2S Stop bit */
#define I2S_STOP_ENABLE ((uint8_t)(1))
#define I2S_STOP_DISABLE ((uint8_t)(0))
/** I2S Reset bit */
#define I2S_RESET_ENABLE ((uint8_t)(1))
#define I2S_RESET_DISABLE ((uint8_t)(0))
/** I2S Mute bit */
#define I2S_MUTE_ENABLE ((uint8_t)(1))
#define I2S_MUTE_DISABLE ((uint8_t)(0))
/** I2S Transmit/Receive bit */
#define I2S_TX_MODE ((uint8_t)(0))
#define I2S_RX_MODE ((uint8_t)(1))
/** I2S Clock Select bit */
#define I2S_CLKSEL_FRDCLK ((uint8_t)(0))
#define I2S_CLKSEL_MCLK ((uint8_t)(2))
/** I2S 4-pin Mode bit */
#define I2S_4PIN_ENABLE ((uint8_t)(1))
#define I2S_4PIN_DISABLE ((uint8_t)(0))
/** I2S MCLK Enable bit */
#define I2S_MCLK_ENABLE ((uint8_t)(1))
#define I2S_MCLK_DISABLE ((uint8_t)(0))
/** I2S select DMA bit */
#define I2S_DMA_1 ((uint8_t)(0))
#define I2S_DMA_2 ((uint8_t)(1))
/*********************************************************************//**
* Macro defines for DAO-Digital Audio Output register
**********************************************************************/
/** I2S wordwide - the number of bytes in data*/
#define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
#define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
#define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
/** I2S control mono or stereo format */
#define I2S_DAO_MONO ((uint32_t)(1<<2))
/** I2S control stop mode */
#define I2S_DAO_STOP ((uint32_t)(1<<3))
/** I2S control reset mode */
#define I2S_DAO_RESET ((uint32_t)(1<<4))
/** I2S control master/slave mode */
#define I2S_DAO_SLAVE ((uint32_t)(1<<5))
/** I2S word select half period minus one */
#define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6))
/** I2S control mute mode */
#define I2S_DAO_MUTE ((uint32_t)(1<<15))
/*********************************************************************//**
* Macro defines for DAI-Digital Audio Input register
**********************************************************************/
/** I2S wordwide - the number of bytes in data*/
#define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
#define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
#define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
/** I2S control mono or stereo format */
#define I2S_DAI_MONO ((uint32_t)(1<<2))
/** I2S control stop mode */
#define I2S_DAI_STOP ((uint32_t)(1<<3))
/** I2S control reset mode */
#define I2S_DAI_RESET ((uint32_t)(1<<4))
/** I2S control master/slave mode */
#define I2S_DAI_SLAVE ((uint32_t)(1<<5))
/** I2S word select half period minus one (9 bits)*/
#define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6))
/** I2S control mute mode */
#define I2S_DAI_MUTE ((uint32_t)(1<<15))
/*********************************************************************//**
* Macro defines for STAT register (Status Feedback register)
**********************************************************************/
/** I2S Status Receive or Transmit Interrupt */
#define I2S_STATE_IRQ ((uint32_t)(1))
/** I2S Status Receive or Transmit DMA1 */
#define I2S_STATE_DMA1 ((uint32_t)(1<<1))
/** I2S Status Receive or Transmit DMA2 */
#define I2S_STATE_DMA2 ((uint32_t)(1<<2))
/** I2S Status Current level of the Receive FIFO (5 bits)*/
#define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8))
/** I2S Status Current level of the Transmit FIFO (5 bits)*/
#define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16))
/*********************************************************************//**
* Macro defines for DMA1 register (DMA1 Configuration register)
**********************************************************************/
/** I2S control DMA1 for I2S receive */
#define I2S_DMA1_RX_ENABLE ((uint32_t)(1))
/** I2S control DMA1 for I2S transmit */
#define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1))
/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
#define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
#define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
/*********************************************************************//**
* Macro defines for DMA2 register (DMA2 Configuration register)
**********************************************************************/
/** I2S control DMA2 for I2S receive */
#define I2S_DMA2_RX_ENABLE ((uint32_t)(1))
/** I2S control DMA1 for I2S transmit */
#define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1))
/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
#define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
#define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
/*********************************************************************//**
* Macro defines for IRQ register (Interrupt Request Control register)
**********************************************************************/
/** I2S control I2S receive interrupt */
#define I2S_IRQ_RX_ENABLE ((uint32_t)(1))
/** I2S control I2S transmit interrupt */
#define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1))
/** I2S set the FIFO level on which to create an irq request */
#define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
/** I2S set the FIFO level on which to create an irq request */
#define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
/********************************************************************************//**
* Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
*********************************************************************************/
/** I2S Transmit MCLK rate denominator */
#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
/** I2S Transmit MCLK rate denominator */
#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
/** I2S Receive MCLK rate denominator */
#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
/** I2S Receive MCLK rate denominator */
#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
/*************************************************************************************//**
* Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
**************************************************************************************/
#define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F))
#define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F))
/**********************************************************************************//**
* Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
************************************************************************************/
/** I2S Transmit select clock source (2 bits)*/
#define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
/** I2S Transmit control 4-pin mode */
#define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
/** I2S Transmit control the TX_MCLK output */
#define I2S_TXMODE_MCENA ((uint32_t)(1<<3))
/** I2S Receive select clock source */
#define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
/** I2S Receive control 4-pin mode */
#define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
/** I2S Receive control the TX_MCLK output */
#define I2S_RXMODE_MCENA ((uint32_t)(1<<3))
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/** Macro to determine if it is valid I2S peripheral */
#define PARAM_I2Sx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2S0)) || (((uint32_t *)n)==((uint32_t *)LPC_I2S1)))
/** Macro to check Data to send valid */
#define PRAM_I2S_FREQ(freq) ((freq>=8000)&&(freq <= 96000))
/* Macro check I2S word width type */
#define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\
||(n==I2S_WORDWIDTH_32))
/* Macro check I2S channel type */
#define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)||(n==I2S_MONO))
/* Macro check I2S master/slave mode */
#define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE))
/* Macro check I2S stop mode */
#define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE))
/* Macro check I2S reset mode */
#define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE))
/* Macro check I2S reset mode */
#define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE))
/* Macro check I2S transmit/receive mode */
#define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)||(n==I2S_RX_MODE))
/* Macro check I2S clock select mode */
#define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK))
/* Macro check I2S 4-pin mode */
#define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE))
/* Macro check I2S MCLK mode */
#define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE))
/* Macro check I2S DMA mode */
#define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)||(n==I2S_DMA_2))
/* Macro check I2S DMA depth value */
#define PARAM_I2S_DMA_DEPTH(n) ((n<=31))
/* Macro check I2S irq level value */
#define PARAM_I2S_IRQ_LEVEL(n) ((n<=31))
/* Macro check I2S half-period value */
#define PARAM_I2S_HALFPERIOD(n) ((n>0)&&(n<512))
/* Macro check I2S bit-rate value */
#define PARAM_I2S_BITRATE(n) ((n<=63))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup I2S_Public_Types I2S Public Types
* @{
*/
/**
* @brief I2S configuration structure definition
*/
typedef struct {
uint8_t wordwidth; /** the number of bytes in data as follow:
-I2S_WORDWIDTH_8: 8 bit data
-I2S_WORDWIDTH_16: 16 bit data
-I2S_WORDWIDTH_32: 32 bit data */
uint8_t mono; /** Set mono/stereo mode, should be:
- I2S_STEREO: stereo mode
- I2S_MONO: mono mode */
uint8_t stop; /** Disables accesses on FIFOs, should be:
- I2S_STOP_ENABLE: enable stop mode
- I2S_STOP_DISABLE: disable stop mode */
uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be:
- I2S_RESET_ENABLE: enable reset mode
- I2S_RESET_DISABLE: disable reset mode */
uint8_t ws_sel; /** Set Master/Slave mode, should be:
- I2S_MASTER_MODE: I2S master mode
- I2S_SLAVE_MODE: I2S slave mode */
uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be:
- I2S_MUTE_ENABLE: enable mute mode
- I2S_MUTE_DISABLE: disable mute mode */
uint8_t Reserved0[2];
} I2S_CFG_Type;
/**
* @brief I2S DMA configuration structure definition
*/
typedef struct {
uint8_t DMAIndex; /** Select DMA1 or DMA2, should be:
- I2S_DMA_1: DMA1
- I2S_DMA_2: DMA2 */
uint8_t depth; /** FIFO level that triggers a DMA request */
uint8_t Reserved0[2];
}I2S_DMAConf_Type;
/**
* @brief I2S mode configuration structure definition
*/
typedef struct{
uint8_t clksel; /** Clock source selection, should be:
- I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output
- I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */
uint8_t fpin; /** Select four pin mode, should be:
- I2S_4PIN_ENABLE: 4-pin enable
- I2S_4PIN_DISABLE: 4-pin disable */
uint8_t mcena; /** Select MCLK mode, should be:
- I2S_MCLK_ENABLE: MCLK enable for output
- I2S_MCLK_DISABLE: MCLK disable for output */
uint8_t Reserved;
}I2S_MODEConf_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup I2S_Public_Functions I2S Public Functions
* @{
*/
/* I2S Init/DeInit functions ---------*/
void I2S_Init(LPC_I2Sn_Type *I2Sx);
void I2S_DeInit(LPC_I2Sn_Type *I2Sx);
/* I2S configuration functions --------*/
void I2S_Config(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct);
Status I2S_FreqConfig(LPC_I2Sn_Type *I2Sx, uint32_t Freq, uint8_t TRMode);
void I2S_SetBitRate(LPC_I2Sn_Type *I2Sx, uint8_t bitrate, uint8_t TRMode);
void I2S_ModeConfig(LPC_I2Sn_Type *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode);
uint8_t I2S_GetLevel(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
/* I2S operate functions -------------*/
void I2S_Send(LPC_I2Sn_Type *I2Sx, uint32_t BufferData);
uint32_t I2S_Receive(LPC_I2Sn_Type* I2Sx);
void I2S_Start(LPC_I2Sn_Type *I2Sx);
void I2S_Pause(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
void I2S_Mute(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
void I2S_Stop(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
/* I2S DMA functions ----------------*/
void I2S_DMAConfig(LPC_I2Sn_Type *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode);
void I2S_DMACmd(LPC_I2Sn_Type *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);
/* I2S IRQ functions ----------------*/
void I2S_IRQCmd(LPC_I2Sn_Type *I2Sx,uint8_t TRMode, FunctionalState NewState);
void I2S_IRQConfig(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, uint8_t level);
FunctionalState I2S_GetIRQStatus(LPC_I2Sn_Type *I2Sx,uint8_t TRMode);
uint8_t I2S_GetIRQDepth(LPC_I2Sn_Type *I2Sx,uint8_t TRMode);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_I2S_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_lcd.h
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/**********************************************************************
* $Id$ lpc43xx_lcd.h 2011-06-02
*//**
* @file lpc43xx_lcd.h
* @brief Contains all macro definitions and function prototypes
* support for LCD Driver
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup LCD LCD
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef __lpc43xx_LCD_H_
#define __lpc43xx_LCD_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup LCD_Private_Macros LCD Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/* LCD control enable bit */
#define CLCDC_LCDCTRL_ENABLE _BIT(0)
/* LCD control power enable bit */
#define CLCDC_LCDCTRL_PWR _BIT(11)
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup LCD_Public_Types LCD Public Types
* @{
*/
/*********************************************************************//**
* @brief LCD enumeration
**********************************************************************/
/** @brief LCD Interrupt Source */
typedef enum{
LCD_INT_FUF = _BIT(1), /* FIFO underflow bit */
LCD_INT_LNBU = _BIT(2), /* LCD next base address update bit */
LCD_INT_VCOMP = _BIT(3), /* vertical compare bit */
LCD_INT_BER = _BIT(4) /* AHB master error interrupt bit */
} LCD_INT_SRC;
/** @brief LCD signal polarity */
typedef enum {
LCD_SIGNAL_ACTIVE_HIGH = 0,
LCD_SIGNAL_ACTIVE_LOW = 1
} LCD_SIGNAL_POLARITY_OPT;
/** @brief LCD clock edge polarity */
typedef enum {
LCD_CLK_RISING = 0,
LCD_CLK_FALLING= 1
} LCD_CLK_EDGE_OPT;
/** @brief LCD bits per pixel and pixel format */
typedef enum {
LCD_BPP1 = 0,
LCD_BPP2,
LCD_BPP4,
LCD_BPP8,
LCD_BPP16,
LCD_BPP24,
LCD_BPP16_565,
LCD_BPP12_444
}LCD_PIXEL_FORMAT_OPT;
/** @brief LCD color format */
typedef enum {
LCD_COLOR_FORMAT_RGB = 0,
LCD_COLOR_FORMAT_BGR
}LCD_COLOR_FORMAT_OPT;
/*********************************************************************//**
* @brief LCD structure definitions
**********************************************************************/
/** @brief LCD Palette entry format */
typedef struct
{
uint32_t Rl:5;
uint32_t Gl:5;
uint32_t Bl:5;
uint32_t Il:1;
uint32_t Ru:5;
uint32_t Gu:5;
uint32_t Bu:5;
uint32_t Iu:1;
} LCD_PALETTE_ENTRY_Type;
/** @brief LCD cursor format in 1 byte LBBP */
typedef struct
{
uint8_t Pixel3:2;
uint8_t Pixel2:2;
uint8_t Pixel1:2;
uint8_t Pixel0:2;
} LCD_CURSOR_PIXEL_Type;
/** @brief LCD cursor size */
typedef enum
{
LCD_CURSOR_32x32 = 0,
LCD_CURSOR_64x64
} LCD_CURSOR_SIZE_OPT;
/** @brief LCD panel type */
typedef enum
{
LCD_TFT = 0x02, /* standard TFT */
LCD_MONO_4 = 0x01, /* 4-bit STN mono */
LCD_MONO_8 = 0x05, /* 8-bit STN mono */
LCD_CSTN = 0x00 /* color STN */
} LCD_PANEL_OPT;
/** @brief LCD porch configuration structure */
typedef struct {
uint16_t front; /* front porch setting in clocks */
uint16_t back; /* back porch setting in clocks */
}LCD_PORCHCFG_Type;
/** @brief LCD configuration structure */
typedef struct {
uint16_t screen_width; /* Pixels per line */
uint16_t screen_height; /* Lines per panel */
LCD_PORCHCFG_Type horizontal_porch; /* porch setting for horizontal */
LCD_PORCHCFG_Type vertical_porch; /* porch setting for vertical */
uint16_t HSync_pulse_width; /* HSYNC pulse width in clocks */
uint16_t VSync_pulse_width; /* VSYNC pulse width in clocks */
uint8_t ac_bias_frequency; /* AC bias frequency in clocks */
LCD_SIGNAL_POLARITY_OPT HSync_pol; /* HSYNC polarity */
LCD_SIGNAL_POLARITY_OPT VSync_pol; /* VSYNC polarity */
LCD_CLK_EDGE_OPT panel_clk_edge; /* Panel Clock Edge Polarity */
LCD_SIGNAL_POLARITY_OPT OE_pol; /* Output Enable polarity */
uint32_t line_end_delay; /* 0 if not use */
LCD_PIXEL_FORMAT_OPT bits_per_pixel; /* Maximum bits per pixel the display supports */
LCD_PANEL_OPT lcd_panel_type; /* LCD panel type */
LCD_COLOR_FORMAT_OPT corlor_format; /* BGR or RGB */
Bool dual_panel; /* Dual panel, TRUE = dual panel display */
} LCD_CFG_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup LCD_Public_Functions LCD Public Functions
* @{
*/
void LCD_Init(LPC_LCD_Type *LCDx, LCD_CFG_Type *LCD_ConfigStruct);
void LCD_DeInit(LPC_LCD_Type *LCDx);
void LCD_Power(LPC_LCD_Type *LCDx, FunctionalState OnOff);
void LCD_Enable(LPC_LCD_Type *LCDx, FunctionalState EnDis);
void LCD_SetFrameBuffer(LPC_LCD_Type *LCDx, void* buffer);
void LCD_SetLPFrameBuffer(LPC_LCD_Type *LCDx, void* buffer);
void LCD_LoadPalette(LPC_LCD_Type *LCDx, void* palette);
void LCD_SetInterrupt(LPC_LCD_Type *LCDx, LCD_INT_SRC Int);
void LCD_ClrInterrupt(LPC_LCD_Type *LCDx, LCD_INT_SRC Int);
LCD_INT_SRC LCD_GetInterrupt(LPC_LCD_Type *LCDx);
void LCD_Cursor_Config(LPC_LCD_Type *LCDx, LCD_CURSOR_SIZE_OPT cursor_size, Bool sync);
void LCD_Cursor_WriteImage(LPC_LCD_Type *LCDx, uint8_t cursor_num, void* Image);
void* LCD_Cursor_GetImageBufferAddress(LPC_LCD_Type *LCDx, uint8_t cursor_num);
void LCD_Cursor_Enable(LPC_LCD_Type *LCDx, uint8_t cursor_num, FunctionalState OnOff);
void LCD_Cursor_LoadPalette0(LPC_LCD_Type *LCDx, uint32_t palette_color);
void LCD_Cursor_LoadPalette1(LPC_LCD_Type *LCDx, uint32_t palette_color);
void LCD_Cursor_SetInterrupt(LPC_LCD_Type *LCDx);
void LCD_Cursor_ClrInterrupt(LPC_LCD_Type *LCDx);
void LCD_Cursor_SetPos(LPC_LCD_Type *LCDx, uint16_t x, uint16_t y);
void LCD_Cursor_SetClipPos(LPC_LCD_Type *LCDx, uint16_t x, uint16_t y);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __lpc43xx_LCD_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_libcfg_default.h
+195
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/**********************************************************************
* $Id$ lpc43xx_libcfg_default.h 2011-06-02
*//**
* @file lpc43xx_libcfg_default.h
* @brief Default Library configuration header file
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors’
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Library Configuration group ----------------------------------------------------------- */
/** @defgroup LIBCFG_DEFAULT LIBCFG_DEFAULT
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_LIBCFG_DEFAULT_H_
#define lpc43xx_LIBCFG_DEFAULT_H_
/* Includes ------------------------------------------------------------------- */
#include "lpc_types.h"
/* Public Macros -------------------------------------------------------------- */
/** @defgroup LIBCFG_DEFAULT_Public_Macros LIBCFG_DEFAULT Public Macros
* @{
*/
/************************** DEBUG MODE DEFINITIONS *********************************/
/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
the "CHECK_PARAM" macro in the FW library code */
//#define DEBUG
/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
/* Comment the line below to disable the specific peripheral inclusion */
/* GPIO ------------------------------- */
#define _GPIO
/* EXTI ------------------------------- */
#define _EXTI
/* UART ------------------------------- */
#define _UART
#define _UART0
#define _UART1
#define _UART2
#define _UART3
/* SPI ------------------------------- */
#define _SPI
/* SYSTICK --------------------------- */
#define _SYSTICK
/* SSP ------------------------------- */
#define _SSP
#define _SSP0
#define _SSP1
/* I2C ------------------------------- */
#define _I2C
#define _I2C0
#define _I2C1
#define _I2C2
/* TIMER ------------------------------- */
#define _TIM
/* WWDT ------------------------------- */
#define _WWDT
/* GPDMA ------------------------------- */
#define _GPDMA
/* DAC ------------------------------- */
#define _DAC
/* DAC ------------------------------- */
#define _ADC
/* PWM ------------------------------- */
#define _PWM
#define _PWM1
/* RTC ------------------------------- */
#define _RTC
/* I2S ------------------------------- */
#define _I2S
/* SDIO ------------------------------ */
#define _SDIF
#define _SDMMC
/* USB device ------------------------------- */
#define _USBDEV
#define _USB_DMA
/* QEI ------------------------------- */
#define _QEI
/* MCPWM ------------------------------- */
#define _MCPWM
/* CAN--------------------------------*/
#define _C_CAN
/* RIT ------------------------------- */
#define _RIT
/* EMAC ------------------------------ */
#define _EMAC
/* SCT ------------------------------ */
#define _SCT
/* LCD ------------------------------ */
#define _LCD
/* ATIMER ------------------------------ */
#define _ATIMER
/* RGU ------------------------------ */
#define _RGU
/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
#ifdef DEBUG
/*******************************************************************************
* @brief The CHECK_PARAM macro is used for function's parameters check.
* It is used only if the library is compiled in DEBUG mode.
* @param[in] expr - If expr is false, it calls check_failed() function
* which reports the name of the source file and the source
* line number of the call that failed.
* - If expr is true, it returns no value.
* @return None
*******************************************************************************/
#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
#else
#define CHECK_PARAM(expr)
#endif /* DEBUG */
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup LIBCFG_DEFAULT_Public_Functions LIBCFG_DEFAULT Public Functions
* @{
*/
#ifdef DEBUG
void check_failed(uint8_t *file, uint32_t line);
#endif
/**
* @}
*/
#endif /* lpc43xx_LIBCFG_DEFAULT_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_mcpwm.h
+343
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/**********************************************************************
* $Id$ lpc43xx_mcpwm.h 2011-06-02
*//**
* @file lpc43xx_mcpwm.h
* @brief Contains all macro definitions and function prototypes
* support for Motor Control PWM firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup MCPWM MCPWM (Motor Control PWM)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_MCPWM_H_
#define lpc43xx_MCPWM_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup MCPWM_Private_Macros MCPWM Private Macros
* @{
*/
/** Edge aligned mode for channel in MCPWM */
#define MCPWM_CHANNEL_EDGE_MODE ((uint32_t)(0))
/** Center aligned mode for channel in MCPWM */
#define MCPWM_CHANNEL_CENTER_MODE ((uint32_t)(1))
/** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */
#define MCPWM_CHANNEL_PASSIVE_LO ((uint32_t)(0))
/** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */
#define MCPWM_CHANNEL_PASSIVE_HI ((uint32_t)(1))
/* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of
* the six output pins under the control of the bits in this register */
#define MCPWM_PATENT_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */
#define MCPWM_PATENT_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */
#define MCPWM_PATENT_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */
#define MCPWM_PATENT_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */
#define MCPWM_PATENT_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */
#define MCPWM_PATENT_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */
/* Interrupt type in MCPWM */
/** Limit interrupt for channel (0) */
#define MCPWM_INTFLAG_LIM0 MCPWM_INT_ILIM(0)
/** Match interrupt for channel (0) */
#define MCPWM_INTFLAG_MAT0 MCPWM_INT_IMAT(0)
/** Capture interrupt for channel (0) */
#define MCPWM_INTFLAG_CAP0 MCPWM_INT_ICAP(0)
/** Limit interrupt for channel (1) */
#define MCPWM_INTFLAG_LIM1 MCPWM_INT_ILIM(1)
/** Match interrupt for channel (1) */
#define MCPWM_INTFLAG_MAT1 MCPWM_INT_IMAT(1)
/** Capture interrupt for channel (1) */
#define MCPWM_INTFLAG_CAP1 MCPWM_INT_ICAP(1)
/** Limit interrupt for channel (2) */
#define MCPWM_INTFLAG_LIM2 MCPWM_INT_ILIM(2)
/** Match interrupt for channel (2) */
#define MCPWM_INTFLAG_MAT2 MCPWM_INT_IMAT(2)
/** Capture interrupt for channel (2) */
#define MCPWM_INTFLAG_CAP2 MCPWM_INT_ICAP(2)
/** Fast abort interrupt */
#define MCPWM_INTFLAG_ABORT MCPWM_INT_ABORT
/*********************************************************************//**
* Macro defines for MCPWM Control register
**********************************************************************/
/* MCPWM Control register, these macro definitions below can be applied for these
* register type:
* - MCPWM Control read address
* - MCPWM Control set address
* - MCPWM Control clear address
*/
/**< Stops/starts timer channel n */
#define MCPWM_CON_RUN(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+0))) : (0))
/**< Edge/center aligned operation for channel n */
#define MCPWM_CON_CENTER(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+1))) : (0))
/**< Select polarity of the MCOAn and MCOBn pin */
#define MCPWM_CON_POLAR(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+2))) : (0))
/**< Control the dead-time feature for channel n */
#define MCPWM_CON_DTE(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+3))) : (0))
/**< Enable/Disable update of functional register for channel n */
#define MCPWM_CON_DISUP(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+4))) : (0))
/**< Control the polarity for all 3 channels */
#define MCPWM_CON_INVBDC ((uint32_t)(1<<29))
/**< 3-phase AC mode select */
#define MCPWM_CON_ACMODE ((uint32_t)(1<<30))
/**< 3-phase DC mode select */
#define MCPWM_CON_DCMODE (((uint32_t)1<<31))
/*********************************************************************//**
* Macro defines for MCPWM Capture Control register
**********************************************************************/
/* Capture Control register, these macro definitions below can be applied for these
* register type:
* - MCPWM Capture Control read address
* - MCPWM Capture Control set address
* - MCPWM Capture control clear address
*/
/** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */
#define MCPWM_CAPCON_CAPMCI_RE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0))
/** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */
#define MCPWM_CAPCON_CAPMCI_FE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0))
/** TC(n) is reset by channel (n) capture event */
#define MCPWM_CAPCON_RT(n) (((n<=2)) ? ((uint32_t)(1<<(18+(n)))) : (0))
/** Hardware noise filter: channel (n) capture events are delayed */
#define MCPWM_CAPCON_HNFCAP(n) (((n<=2)) ? ((uint32_t)(1<<(21+(n)))) : (0))
/*********************************************************************//**
* Macro defines for MCPWM Interrupt register
**********************************************************************/
/* Interrupt registers, these macro definitions below can be applied for these
* register type:
* - MCPWM Interrupt Enable read address
* - MCPWM Interrupt Enable set address
* - MCPWM Interrupt Enable clear address
* - MCPWM Interrupt Flags read address
* - MCPWM Interrupt Flags set address
* - MCPWM Interrupt Flags clear address
*/
/** Limit interrupt for channel (n) */
#define MCPWM_INT_ILIM(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+0))) : (0))
/** Match interrupt for channel (n) */
#define MCPWM_INT_IMAT(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+1))) : (0))
/** Capture interrupt for channel (n) */
#define MCPWM_INT_ICAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+2))) : (0))
/** Fast abort interrupt */
#define MCPWM_INT_ABORT ((uint32_t)(1<<15))
/*********************************************************************//**
* Macro defines for MCPWM Count Control register
**********************************************************************/
/* MCPWM Count Control register, these macro definitions below can be applied for these
* register type:
* - MCPWM Count Control read address
* - MCPWM Count Control set address
* - MCPWM Count Control clear address
*/
/** Counter(tc) advances on a rising edge on MCI(mci) pin */
#define MCPWM_CNTCON_TCMCI_RE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0))
/** Counter(cnt) advances on a falling edge on MCI(mci) pin */
#define MCPWM_CNTCON_TCMCI_FE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0))
/** Channel (n) is in counter mode */
#define MCPWM_CNTCON_CNTR(n) (((n<=2)) ? ((uint32_t)(1<<(29+n))) : (0))
/*********************************************************************//**
* Macro defines for MCPWM Dead-time register
**********************************************************************/
/** Dead time value x for channel n */
#define MCPWM_DT(n,x) (((n<=2)) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0))
/*********************************************************************//**
* Macro defines for MCPWM Communication Pattern register
**********************************************************************/
#define MCPWM_CP_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */
#define MCPWM_CP_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */
#define MCPWM_CP_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */
#define MCPWM_CP_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */
#define MCPWM_CP_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */
#define MCPWM_CP_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */
/*********************************************************************//**
* Macro defines for MCPWM Capture clear address register
**********************************************************************/
/** Clear the MCCAP (n) register */
#define MCPWM_CAPCLR_CAP(n) (((n<=2)) ? ((uint32_t)(1<<n)) : (0))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup MCPWM_Public_Types MCPWM Public Types
* @{
*/
/*********************************************************************//**
* @brief MCPWM enumeration
**********************************************************************/
/**
* @brief MCPWM channel identifier definition
*/
typedef enum
{
MCPWM_CHANNEL_0 = 0, /**< MCPWM channel 0 */
MCPWM_CHANNEL_1, /**< MCPWM channel 1 */
MCPWM_CHANNEL_2 /**< MCPWM channel 2 */
} en_MCPWM_Channel_Id;
/*********************************************************************//**
* @brief MCPWM structure definitions
**********************************************************************/
/**
* @brief Motor Control PWM Channel Configuration structure type definition
*/
typedef struct {
uint32_t channelType; /**< Edge/center aligned mode for this channel,
should be:
- MCPWM_CHANNEL_EDGE_MODE: Channel is in Edge mode
- MCPWM_CHANNEL_CENTER_MODE: Channel is in Center mode
*/
uint32_t channelPolarity; /**< Polarity of the MCOA and MCOB pins, should be:
- MCPWM_CHANNEL_PASSIVE_LO: Passive state is LOW, active state is HIGH
- MCPWM_CHANNEL_PASSIVE_HI: Passive state is HIGH, active state is LOW
*/
uint32_t channelDeadtimeEnable; /**< Enable/Disable DeadTime function for channel, should be:
- ENABLE.
- DISABLE.
*/
uint32_t channelDeadtimeValue; /**< DeadTime value, should be less than 0x3FF */
uint32_t channelUpdateEnable; /**< Enable/Disable updates of functional registers,
should be:
- ENABLE.
- DISABLE.
*/
uint32_t channelTimercounterValue; /**< MCPWM Timer Counter value */
uint32_t channelPeriodValue; /**< MCPWM Period value */
uint32_t channelPulsewidthValue; /**< MCPWM Pulse Width value */
} MCPWM_CHANNEL_CFG_Type;
/**
* @brief MCPWM Capture Configuration type definition
*/
typedef struct {
uint32_t captureChannel; /**< Capture Channel Number, should be in range from 0 to 2 */
uint32_t captureRising; /**< Enable/Disable Capture on Rising Edge event, should be:
- ENABLE.
- DISABLE.
*/
uint32_t captureFalling; /**< Enable/Disable Capture on Falling Edge event, should be:
- ENABLE.
- DISABLE.
*/
uint32_t timerReset; /**< Enable/Disable Timer reset function an capture, should be:
- ENABLE.
- DISABLE.
*/
uint32_t hnfEnable; /**< Enable/Disable Hardware noise filter function, should be:
- ENABLE.
- DISABLE.
*/
} MCPWM_CAPTURE_CFG_Type;
/**
* @brief MCPWM Count Control Configuration type definition
*/
typedef struct {
uint32_t counterChannel; /**< Counter Channel Number, should be in range from 0 to 2 */
uint32_t countRising; /**< Enable/Disable Capture on Rising Edge event, should be:
- ENABLE.
- DISABLE.
*/
uint32_t countFalling; /**< Enable/Disable Capture on Falling Edge event, should be:
- ENABLE.
- DISABLE.
*/
} MCPWM_COUNT_CFG_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup MCPWM_Public_Functions MCPWM Public Functions
* @{
*/
void MCPWM_Init(LPC_MCPWM_Type *MCPWMx);
void MCPWM_ConfigChannel(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
MCPWM_CHANNEL_CFG_Type * channelSetup);
void MCPWM_WriteToShadow(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
MCPWM_CHANNEL_CFG_Type *channelSetup);
void MCPWM_ConfigCapture(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
MCPWM_CAPTURE_CFG_Type *captureConfig);
void MCPWM_ClearCapture(LPC_MCPWM_Type *MCPWMx, uint32_t captureChannel);
uint32_t MCPWM_GetCapture(LPC_MCPWM_Type *MCPWMx, uint32_t captureChannel);
void MCPWM_CountConfig(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig);
void MCPWM_Start(LPC_MCPWM_Type *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
void MCPWM_Stop(LPC_MCPWM_Type *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
void MCPWM_ACMode(LPC_MCPWM_Type *MCPWMx,uint32_t acMode);
void MCPWM_DCMode(LPC_MCPWM_Type *MCPWMx, uint32_t dcMode,
uint32_t outputInvered, uint32_t outputPattern);
void MCPWM_IntConfig(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType, FunctionalState NewState);
void MCPWM_IntSet(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType);
void MCPWM_IntClear(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType);
FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_MCPWM_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_nvic.h
+73
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/**********************************************************************
* $Id$ lpc43xx_nvic.h 2011-06-02
*//**
* @file lpc43xx_nvic.h
* @brief Contains all macro definitions and function prototypes
* support for Nesting Vectored Interrupt firmware library
* on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup NVIC NVIC (Nested Vector Interrupt Controller)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_NVIC_H_
#define lpc43xx_NVIC_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Functions ----------------------------------------------------------- */
/** @defgroup NVIC_Public_Functions NVIC Public Functions
* @{
*/
void NVIC_SetVTOR(uint32_t offset);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_NVIC_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_pwr.h
+88
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@@ -0,0 +1,88 @@
/**********************************************************************
* $Id$ lpc43xx_pwr.h 2011-06-02
*//**
* @file lpc43xx_pwr.h
* @brief Contains all macro definitions and function prototypes
* support for Power Control firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup PWR PWR (Power Control)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_PWR_H_
#define lpc43xx_PWR_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup PWR_Private_Macros PWR Private Macros
* @{
*/
#define PWR_SLEEP_MODE_DEEP_SLEEP 0x3F00AA
#define PWR_SLEEP_MODE_POWER_DOWN 0x3FFCBA
#define PWR_SLEEP_MODE_DEEP_POWER_DOWN 0x3FFF7F
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup PWR_Public_Functions PWR Public Functions
* @{
*/
/* Clock Generator */
void PWR_Sleep(void);
void PWR_DeepSleep(void);
void PWR_PowerDown(void);
void PWR_DeepPowerDown(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_PWR_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_qei.h
+431
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@@ -0,0 +1,431 @@
/**********************************************************************
* $Id$ lpc43xx_qei.h 2011-06-02
*//**
* @file lpc43xx_qei.h
* @brief Contains all macro definitions and function prototypes
* support for QEI firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup QEI QEI (Quadrature Encoder Interface)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_QEI_H_
#define lpc43xx_QEI_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup QEI_Private_Macros QEI Private Macros
* @{
*/
/** QEI peripheral numver definition */
#define QEI_0 (0) /** Always 0 - because we just have only one QEI peripheral */
/** QEI Reset types */
#define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */
#define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */
#define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */
#define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */
/** QEI Direction Invert Type Option */
#define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */
#define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */
/** QEI Signal Mode Option */
#define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */
#define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */
/** QEI Capture Mode Option */
#define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */
#define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/
/** QEI Invert Index Signal Option */
#define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */
#define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */
/** QEI timer reload option */
#define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */
#define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */
/** QEI Flag Status type */
#define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */
/** QEI Compare Position channel option */
#define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */
#define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */
#define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */
/** QEI interrupt flag type */
#define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */
#define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */
#define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */
#define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */
#define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */
#define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */
#define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the
current position interrupt */
#define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the
current position interrupt */
#define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the
current position interrupt */
#define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current
index count interrupt */
#define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */
#define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */
#define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/* Quadrature Encoder Interface Control Register Definition --------------------- */
/*********************************************************************//**
* Macro defines for QEI Control register
**********************************************************************/
#define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */
#define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */
#define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */
#define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */
#define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */
/*********************************************************************//**
* Macro defines for QEI Configuration register
**********************************************************************/
#define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */
#define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */
#define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */
#define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */
#define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */
/*********************************************************************//**
* Macro defines for QEI Status register
**********************************************************************/
#define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */
#define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */
/* Quadrature Encoder Interface Interrupt registers definitions --------------------- */
/*********************************************************************//**
* Macro defines for QEI Interrupt Status register
**********************************************************************/
#define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */
#define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */
#define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */
#define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */
#define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */
#define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */
#define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the
current position */
#define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the
current position */
#define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the
current position */
#define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current
index count */
#define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when
both the POS0_Int bit is set and the REV_Int is set */
#define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when
both the POS1_Int bit is set and the REV_Int is set */
#define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when
both the POS2_Int bit is set and the REV_Int is set */
#define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
/*********************************************************************//**
* Macro defines for QEI Interrupt Set register
**********************************************************************/
#define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */
#define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */
#define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */
#define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */
#define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */
#define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */
#define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the
current position */
#define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the
current position */
#define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the
current position */
#define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current
index count */
#define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */
#define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */
#define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */
#define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */
/*********************************************************************//**
* Macro defines for QEI Interrupt Clear register
**********************************************************************/
#define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */
#define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */
#define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */
#define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */
#define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */
#define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */
#define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the
current position */
#define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the
current position */
#define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the
current position */
#define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current
index count */
#define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */
#define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */
#define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */
#define QEI_INTCLR_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Clear register bit-mask */
/*********************************************************************//**
* Macro defines for QEI Interrupt Enable register
**********************************************************************/
#define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */
#define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
#define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
#define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */
#define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */
#define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
#define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
current position */
#define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
current position */
#define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
current position */
#define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current
index count */
#define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
#define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
#define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
#define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */
/*********************************************************************//**
* Macro defines for QEI Interrupt Enable Set register
**********************************************************************/
#define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */
#define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */
#define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */
#define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */
#define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */
#define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */
#define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the
current position */
#define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the
current position */
#define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the
current position */
#define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current
index count */
#define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */
#define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */
#define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */
#define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */
/*********************************************************************//**
* Macro defines for QEI Interrupt Enable Clear register
**********************************************************************/
#define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */
#define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
#define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
#define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */
#define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */
#define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
#define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
current position */
#define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
current position */
#define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
current position */
#define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
index count */
#define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
#define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
#define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
#define QEI_IECLR_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Enable Clear register bit-mask */
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/* Macro check QEI peripheral */
#define PARAM_QEIx(n) ((n==LPC_QEI))
/* Macro check QEI reset type */
#define PARAM_QEI_RESET(n) ((n==QEI_CON_RESP) \
|| (n==QEI_RESET_POSOnIDX) \
|| (n==QEI_RESET_VEL) \
|| (n==QEI_RESET_IDX))
/* Macro check QEI Direction invert mode */
#define PARAM_QEI_DIRINV(n) ((n==QEI_DIRINV_NONE) || (n==QEI_DIRINV_CMPL))
/* Macro check QEI signal mode */
#define PARAM_QEI_SIGNALMODE(n) ((n==QEI_SIGNALMODE_QUAD) || (n==QEI_SIGNALMODE_CLKDIR))
/* Macro check QEI Capture mode */
#define PARAM_QEI_CAPMODE(n) ((n==QEI_CAPMODE_2X) || (n==QEI_CAPMODE_4X))
/* Macro check QEI Invert index mode */
#define PARAM_QEI_INVINX(n) ((n==QEI_INVINX_NONE) || (n==QEI_INVINX_EN))
/* Macro check QEI Direction invert mode */
#define PARAM_QEI_TIMERRELOAD(n) ((n==QEI_TIMERRELOAD_TICKVAL) || (n==QEI_TIMERRELOAD_USVAL))
/* Macro check QEI status type */
#define PARAM_QEI_STATUS(n) ((n==QEI_STATUS_DIR))
/* Macro check QEI combine position type */
#define PARAM_QEI_COMPPOS_CH(n) ((n==QEI_COMPPOS_CH_0) || (n==QEI_COMPPOS_CH_1) || (n==QEI_COMPPOS_CH_2))
/* Macro check QEI interrupt flag type */
#define PARAM_QEI_INTFLAG(n) ((n==QEI_INTFLAG_INX_Int) \
|| (n==QEI_INTFLAG_TIM_Int) \
|| (n==QEI_INTFLAG_VELC_Int) \
|| (n==QEI_INTFLAG_DIR_Int) \
|| (n==QEI_INTFLAG_ERR_Int) \
|| (n==QEI_INTFLAG_ENCLK_Int) \
|| (n==QEI_INTFLAG_POS0_Int) \
|| (n==QEI_INTFLAG_POS1_Int) \
|| (n==QEI_INTFLAG_POS2_Int) \
|| (n==QEI_INTFLAG_REV_Int) \
|| (n==QEI_INTFLAG_POS0REV_Int) \
|| (n==QEI_INTFLAG_POS1REV_Int) \
|| (n==QEI_INTFLAG_POS2REV_Int))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup QEI_Public_Types QEI Public Types
* @{
*/
/*********************************************************************//**
* @brief QEI structure definitions
**********************************************************************/
/**
* @brief QEI Configuration structure type definition
*/
typedef struct {
uint32_t DirectionInvert :1; /**< Direction invert option:
- QEI_DIRINV_NONE: QEI Direction is normal
- QEI_DIRINV_CMPL: QEI Direction is complemented
*/
uint32_t SignalMode :1; /**< Signal mode Option:
- QEI_SIGNALMODE_QUAD: Signal is in Quadrature phase mode
- QEI_SIGNALMODE_CLKDIR: Signal is in Clock/Direction mode
*/
uint32_t CaptureMode :1; /**< Capture Mode Option:
- QEI_CAPMODE_2X: Only Phase-A edges are counted (2X)
- QEI_CAPMODE_4X: BOTH Phase-A and Phase-B edges are counted (4X)
*/
uint32_t InvertIndex :1; /**< Invert Index Option:
- QEI_INVINX_NONE: the sense of the index input is normal
- QEI_INVINX_EN: inverts the sense of the index input
*/
} QEI_CFG_Type;
/**
* @brief Timer Reload Configuration structure type definition
*/
typedef struct {
uint8_t ReloadOption; /**< Velocity Timer Reload Option, should be:
- QEI_TIMERRELOAD_TICKVAL: Reload value in absolute value
- QEI_TIMERRELOAD_USVAL: Reload value in microsecond value
*/
uint8_t Reserved[3];
uint32_t ReloadValue; /**< Velocity Timer Reload Value, 32-bit long, should be matched
with Velocity Timer Reload Option
*/
} QEI_RELOADCFG_Type;
typedef struct
{
uint32_t PHA_FilterVal; /**< FILTERPHA register input */
uint32_t PHB_FilterVal; /**< FILTERPHB register input */
uint32_t INX_FilterVal; /**< FILTERINX register input */
} st_Qei_FilterCfg;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup QEI_Public_Functions QEI Public Functions
* @{
*/
void QEI_Init(uint8_t qeiId, QEI_CFG_Type *QEI_ConfigStruct);
void QEI_DeInit(uint8_t qeiId);
void QEI_Reset(uint8_t qeiId, uint32_t ulResetType);
void QEI_GetCfgDefault(QEI_CFG_Type *QIE_InitStruct);
FlagStatus QEI_GetStatus(uint8_t qeiId, uint32_t ulFlagType);
uint32_t QEI_GetPosition(uint8_t qeiId);
void QEI_SetMaxPosition(uint8_t qeiId, uint32_t ulMaxPos);
void QEI_SetPositionComp(uint8_t qeiId, uint8_t bPosCompCh, uint32_t ulPosComp);
uint32_t QEI_GetIndex(uint8_t qeiId);
void QEI_SetIndexComp(uint8_t qeiId, uint32_t ulIndexComp);
void QEI_SetTimerReload(uint8_t qeiId, QEI_RELOADCFG_Type *QEIReloadStruct);
uint32_t QEI_GetTimer(uint8_t qeiId);
uint32_t QEI_GetVelocity(uint8_t qeiId);
uint32_t QEI_GetVelocityCap(uint8_t qeiId);
void QEI_SetVelocityComp(uint8_t qeiId, uint32_t ulVelComp);
void QEI_SetDigiFilter(uint8_t qeiId, st_Qei_FilterCfg FilterVal);
uint32_t QEI_CalculateRPM(uint8_t qeiId, uint32_t ulVelCapValue, uint32_t ulPPR);
FlagStatus QEI_GetIntStatus(uint8_t qeiId, uint32_t ulIntType);
void QEI_IntCmd(uint8_t qeiId, uint32_t ulIntType, FunctionalState NewState);
void QEI_IntSet(uint8_t qeiId, uint32_t ulIntType);
void QEI_IntClear(uint8_t qeiId, uint32_t ulIntType);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_QEI_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_rgu.h
+144
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/**********************************************************************
* $Id$ lpc43xx_rgu.h 2011-06-02
*//**
* @file lpc43xx_rgu.h
* @brief Contains all macro definitions and function prototypes
* support for RGU firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup RGU RGU (Reset Generation Unit)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_RGU_H_
#define lpc43xx_RGU_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Types --------------------------------------------------------------- */
/** @defgroup RGU_Public_Types RGU Public Types
* @{
*/
/*********************************************************************//**
* @brief RGU enumeration
**********************************************************************/
/** @brief Out Reset Signal Generated by RGU */
typedef enum
{
RGU_SIG_CORE = 0, /**< Core reset signal */
RGU_SIG_PERIPH, /**< Peripheral reset signal */
RGU_SIG_MASTER, /**< Master reset signal */
RGU_SIG_WWDT = 4, /**< WWDT reset signal */
RGU_SIG_CREG, /**< CREG reset signal */
RGU_SIG_BUS = 8, /**< Bus reset signal */
RGU_SIG_SCU, /**< SCU reset signal */
RGU_SIG_PINMUX, /**< Pin mux reset signal */
RGU_SIG_M3 = 13, /**< Cortex-M3 reset signal */
RGU_SIG_LCD = 16, /**< LCD reset signal */
RGU_SIG_USB0, /**< USB0 reset signal */
RGU_SIG_USB1, /**< USB1 reset signal */
RGU_SIG_DMA, /**< DMA reset signal */
RGU_SIG_SDIO, /**< SDIO reset signal */
RGU_SIG_EMC, /**< EMC reset signal */
RGU_SIG_ETHERNET, /**< Ethernet reset signal */
RGU_SIG_AES, /**< AES reset signal */
RGU_SIG_GPIO = 28, /**< GPIO reset signal */
RGU_SIG_TIMER0 = 32, /**< TIMER 0 reset signal */
RGU_SIG_TIMER1, /**< TIMER 1 reset signal */
RGU_SIG_TIMER2, /**< TIMER 2 reset signal */
RGU_SIG_TIMER3, /**< TIMER 3 reset signal */
RGU_SIG_RITIMER, /**< RIT timer reset signal */
RGU_SIG_SCT, /**< SCT reset signal */
RGU_SIG_MOTOCONPWM, /**< Motor control reset signal */
RGU_SIG_QEI, /**< QEI reset signal */
RGU_SIG_ADC0, /**< ADC0 reset signal */
RGU_SIG_ADC1, /**< ADC1 reset signal */
RGU_SIG_DAC, /**< DAC reset signal */
RGU_SIG_UART0 = 44, /**< UART0 reset signal */
RGU_SIG_UART1, /**< UART1 reset signal */
RGU_SIG_UART2, /**< UART2 reset signal */
RGU_SIG_UART3, /**< UART3 reset signal */
RGU_SIG_I2C0, /**< I2C0 reset signal */
RGU_SIG_I2C1, /**< I2C1 reset signal */
RGU_SIG_SSP0, /**< SSP0 reset signal */
RGU_SIG_SSP1, /**< SSP1 reset signal */
RGU_SIG_I2S, /**< I2S reset signal */
RGU_SIG_SPIFI, /**< SPIFI reset signal */
RGU_SIG_CAN = 55 /**< CAN reset signal */
}RGU_SIG;
/** @brief Reset Cause Source */
typedef enum {
RGU_SRC_NONE, /**< No source */
RGU_SRC_SOFT, /**< Software reset source */
RGU_SRC_EXT, /**< External reset source */
RGU_SRC_CORE, /**< Core reset source */
RGU_SRC_PERIPH, /**< Peripheral reset source*/
RGU_SRC_MASTER, /**< Master reset source */
RGU_SRC_BOD, /**< BOD reset source */
RGU_SRC_WWDT /**< WWDT reset source */
}RGU_SRC;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup RGU_Public_Functions RGU Public Functions
* @{
*/
/* RGU peripheral control function ----------------*/
void RGU_SoftReset(RGU_SIG ResetSignal);
RGU_SRC RGU_GetSource(RGU_SIG ResetSignal);
Bool RGU_GetSignalStatus(RGU_SIG ResetSignal);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_RGU_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_rit.h
+111
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/**********************************************************************
* $Id$ lpc43xx_rit.h 2011-06-02
*//**
* @file lpc43xx_rit.h
* @brief Contains all macro definitions and function prototypes
* support for RIT firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup RIT RIT (Repetitive Interrupt Timer)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_RIT_H_
#define lpc43xx_RIT_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup RIT_Private_Macros RIT Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*********************************************************************//**
* Macro defines for RIT control register
**********************************************************************/
/** Set interrupt flag when the counter value equals the masked compare value */
#define RIT_CTRL_INTEN ((uint32_t) (1))
/** Set timer enable clear to 0 when the counter value equals the masked compare value */
#define RIT_CTRL_ENCLR ((uint32_t) _BIT(1))
/** Set timer enable on debug */
#define RIT_CTRL_ENBR ((uint32_t) _BIT(2))
/** Set timer enable */
#define RIT_CTRL_TEN ((uint32_t) _BIT(3))
/** Macro to determine if it is valid RIT peripheral */
#define PARAM_RITx(n) (((uint32_t *)n)==((uint32_t *)LPC_RITIMER))
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup RIT_Public_Functions RIT Public Functions
* @{
*/
/* RIT Init/DeInit functions */
void RIT_Init(LPC_RITIMER_Type *RITx);
void RIT_DeInit(LPC_RITIMER_Type *RITx);
/* RIT config timer functions */
void RIT_TimerConfig(LPC_RITIMER_Type *RITx, uint32_t time_interval);
/* Enable/Disable RIT functions */
void RIT_TimerClearCmd(LPC_RITIMER_Type *RITx, FunctionalState NewState);
void RIT_Cmd(LPC_RITIMER_Type *RITx, FunctionalState NewState);
void RIT_TimerDebugCmd(LPC_RITIMER_Type *RITx, FunctionalState NewState);
/* RIT Interrupt functions */
IntStatus RIT_GetIntStatus(LPC_RITIMER_Type *RITx);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_RIT_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_rtc.h
+327
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/**********************************************************************
* $Id$ lpc43xx_rtc.h 2011-06-02
*//**
* @file lpc43xx_rtc.h
* @brief Contains all macro definitions and function prototypes
* support for RTC firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup RTC RTC (Real-Time Clock)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_RTC_H_
#define lpc43xx_RTC_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup RTC_Private_Macros RTC Private Macros
* @{
*/
/* ----------------------- BIT DEFINITIONS ----------------------------------- */
/* Miscellaneous register group --------------------------------------------- */
/**********************************************************************
* ILR register definitions
**********************************************************************/
/** ILR register mask */
#define RTC_ILR_BITMASK ((0x00000003))
/** Bit inform the source interrupt is counter increment*/
#define RTC_IRL_RTCCIF ((1<<0))
/** Bit inform the source interrupt is alarm match*/
#define RTC_IRL_RTCALF ((1<<1))
/**********************************************************************
* CCR register definitions
**********************************************************************/
/** CCR register mask */
#define RTC_CCR_BITMASK ((0x00000013))
/** Clock enable */
#define RTC_CCR_CLKEN ((1<<0))
/** Clock reset */
#define RTC_CCR_CTCRST ((1<<1))
/** Calibration counter enable */
#define RTC_CCR_CCALEN ((1<<4))
/**********************************************************************
* CIIR register definitions
**********************************************************************/
/** Counter Increment Interrupt bit for second */
#define RTC_CIIR_IMSEC ((1<<0))
/** Counter Increment Interrupt bit for minute */
#define RTC_CIIR_IMMIN ((1<<1))
/** Counter Increment Interrupt bit for hour */
#define RTC_CIIR_IMHOUR ((1<<2))
/** Counter Increment Interrupt bit for day of month */
#define RTC_CIIR_IMDOM ((1<<3))
/** Counter Increment Interrupt bit for day of week */
#define RTC_CIIR_IMDOW ((1<<4))
/** Counter Increment Interrupt bit for day of year */
#define RTC_CIIR_IMDOY ((1<<5))
/** Counter Increment Interrupt bit for month */
#define RTC_CIIR_IMMON ((1<<6))
/** Counter Increment Interrupt bit for year */
#define RTC_CIIR_IMYEAR ((1<<7))
/** CIIR bit mask */
#define RTC_CIIR_BITMASK ((0xFF))
/**********************************************************************
* AMR register definitions
**********************************************************************/
/** Counter Increment Select Mask bit for second */
#define RTC_AMR_AMRSEC ((1<<0))
/** Counter Increment Select Mask bit for minute */
#define RTC_AMR_AMRMIN ((1<<1))
/** Counter Increment Select Mask bit for hour */
#define RTC_AMR_AMRHOUR ((1<<2))
/** Counter Increment Select Mask bit for day of month */
#define RTC_AMR_AMRDOM ((1<<3))
/** Counter Increment Select Mask bit for day of week */
#define RTC_AMR_AMRDOW ((1<<4))
/** Counter Increment Select Mask bit for day of year */
#define RTC_AMR_AMRDOY ((1<<5))
/** Counter Increment Select Mask bit for month */
#define RTC_AMR_AMRMON ((1<<6))
/** Counter Increment Select Mask bit for year */
#define RTC_AMR_AMRYEAR ((1<<7))
/** AMR bit mask */
#define RTC_AMR_BITMASK ((0xFF))
/**********************************************************************
* RTC_AUX register definitions
**********************************************************************/
/** RTC Oscillator Fail detect flag */
#define RTC_AUX_RTC_OSCF ((1<<4))
/**********************************************************************
* RTC_AUXEN register definitions
**********************************************************************/
/** Oscillator Fail Detect interrupt enable*/
#define RTC_AUXEN_RTC_OSCFEN ((1<<4))
/* Consolidated time register group ----------------------------------- */
/**********************************************************************
* Consolidated Time Register 0 definitions
**********************************************************************/
#define RTC_CTIME0_SECONDS_MASK ((0x3F))
#define RTC_CTIME0_MINUTES_MASK ((0x3F00))
#define RTC_CTIME0_HOURS_MASK ((0x1F0000))
#define RTC_CTIME0_DOW_MASK ((0x7000000))
/**********************************************************************
* Consolidated Time Register 1 definitions
**********************************************************************/
#define RTC_CTIME1_DOM_MASK ((0x1F))
#define RTC_CTIME1_MONTH_MASK ((0xF00))
#define RTC_CTIME1_YEAR_MASK ((0xFFF0000))
/**********************************************************************
* Consolidated Time Register 2 definitions
**********************************************************************/
#define RTC_CTIME2_DOY_MASK ((0xFFF))
/**********************************************************************
* Time Counter Group and Alarm register group
**********************************************************************/
/** SEC register mask */
#define RTC_SEC_MASK (0x0000003F)
/** MIN register mask */
#define RTC_MIN_MASK (0x0000003F)
/** HOUR register mask */
#define RTC_HOUR_MASK (0x0000001F)
/** DOM register mask */
#define RTC_DOM_MASK (0x0000001F)
/** DOW register mask */
#define RTC_DOW_MASK (0x00000007)
/** DOY register mask */
#define RTC_DOY_MASK (0x000001FF)
/** MONTH register mask */
#define RTC_MONTH_MASK (0x0000000F)
/** YEAR register mask */
#define RTC_YEAR_MASK (0x00000FFF)
#define RTC_SECOND_MAX 59 /*!< Maximum value of second */
#define RTC_MINUTE_MAX 59 /*!< Maximum value of minute*/
#define RTC_HOUR_MAX 23 /*!< Maximum value of hour*/
#define RTC_MONTH_MIN 1 /*!< Minimum value of month*/
#define RTC_MONTH_MAX 12 /*!< Maximum value of month*/
#define RTC_DAYOFMONTH_MIN 1 /*!< Minimum value of day of month*/
#define RTC_DAYOFMONTH_MAX 31 /*!< Maximum value of day of month*/
#define RTC_DAYOFWEEK_MAX 6 /*!< Maximum value of day of week*/
#define RTC_DAYOFYEAR_MIN 1 /*!< Minimum value of day of year*/
#define RTC_DAYOFYEAR_MAX 366 /*!< Maximum value of day of year*/
#define RTC_YEAR_MAX 4095 /*!< Maximum value of year*/
/**********************************************************************
* Calibration register
**********************************************************************/
/* Calibration register */
/** Calibration value */
#define RTC_CALIBRATION_CALVAL_MASK ((0x1FFFF))
/** Calibration direction */
#define RTC_CALIBRATION_LIBDIR ((1<<17))
/** Calibration max value */
#define RTC_CALIBRATION_MAX ((0x20000))
/** Calibration definitions */
#define RTC_CALIB_DIR_FORWARD ((uint8_t)(0))
#define RTC_CALIB_DIR_BACKWARD ((uint8_t)(1))
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/** Macro to determine if it is valid RTC peripheral */
#define PARAM_RTCx(x) (((uint32_t *)x)==((uint32_t *)LPC_RTC))
/* Macro check RTC interrupt type */
#define PARAM_RTC_INT(n) ((n==RTC_INT_COUNTER_INCREASE) || (n==RTC_INT_ALARM))
/* Macro check RTC time type */
#define PARAM_RTC_TIMETYPE(n) ((n==RTC_TIMETYPE_SECOND) || (n==RTC_TIMETYPE_MINUTE) \
|| (n==RTC_TIMETYPE_HOUR) || (n==RTC_TIMETYPE_DAYOFWEEK) \
|| (n==RTC_TIMETYPE_DAYOFMONTH) || (n==RTC_TIMETYPE_DAYOFYEAR) \
|| (n==RTC_TIMETYPE_MONTH) || (n==RTC_TIMETYPE_YEAR))
/* Macro check RTC calibration type */
#define PARAM_RTC_CALIB_DIR(n) ((n==RTC_CALIB_DIR_FORWARD) || (n==RTC_CALIB_DIR_BACKWARD))
/* Macro check RTC GPREG type */
#define PARAM_RTC_GPREG_CH(n) ((n<=63))
/* RTC GPREG base address*/
#define RTC_GPREG_BASE 0x40041000
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup RTC_Public_Types RTC Public Types
* @{
*/
/*********************************************************************//**
* @brief RTC enumeration
**********************************************************************/
/** @brief RTC interrupt source */
typedef enum {
RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF, /*!< Counter Increment Interrupt */
RTC_INT_ALARM = RTC_IRL_RTCALF /*!< The alarm interrupt */
} RTC_INT_OPT;
/** @brief RTC time type option */
typedef enum {
RTC_TIMETYPE_SECOND = 0, /*!< Second */
RTC_TIMETYPE_MINUTE = 1, /*!< Month */
RTC_TIMETYPE_HOUR = 2, /*!< Hour */
RTC_TIMETYPE_DAYOFWEEK = 3, /*!< Day of week */
RTC_TIMETYPE_DAYOFMONTH = 4, /*!< Day of month */
RTC_TIMETYPE_DAYOFYEAR = 5, /*!< Day of year */
RTC_TIMETYPE_MONTH = 6, /*!< Month */
RTC_TIMETYPE_YEAR = 7 /*!< Year */
} RTC_TIMETYPE_Num;
/*********************************************************************//**
* @brief RTC structure definitions
**********************************************************************/
/** @brief Time structure definitions for easy manipulate the data */
typedef struct {
uint32_t SEC; /*!< Seconds Register */
uint32_t MIN; /*!< Minutes Register */
uint32_t HOUR; /*!< Hours Register */
uint32_t DOM; /*!< Day of Month Register */
uint32_t DOW; /*!< Day of Week Register */
uint32_t DOY; /*!< Day of Year Register */
uint32_t MONTH; /*!< Months Register */
uint32_t YEAR; /*!< Years Register */
} RTC_TIME_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup RTC_Public_Functions RTC Public Functions
* @{
*/
void RTC_Init (LPC_RTC_Type *RTCx);
void RTC_DeInit(LPC_RTC_Type *RTCx);
void RTC_ResetClockTickCounter(LPC_RTC_Type *RTCx);
void RTC_Cmd (LPC_RTC_Type *RTCx, FunctionalState NewState);
void RTC_SetTime (LPC_RTC_Type *RTCx, uint32_t Timetype, uint32_t TimeValue);
uint32_t RTC_GetTime(LPC_RTC_Type *RTCx, uint32_t Timetype);
void RTC_SetFullTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime);
void RTC_GetFullTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime);
void RTC_AlarmIntConfig (LPC_RTC_Type *RTCx, uint32_t AlarmTimeType, FunctionalState NewState);
void RTC_SetAlarmTime (LPC_RTC_Type *RTCx, uint32_t Timetype, uint32_t ALValue);
uint32_t RTC_GetAlarmTime (LPC_RTC_Type *RTCx, uint32_t Timetype);
void RTC_SetFullAlarmTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime);
void RTC_GetFullAlarmTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime);
void RTC_CntIncrIntConfig (LPC_RTC_Type *RTCx, uint32_t CntIncrIntType, FunctionalState NewState);
IntStatus RTC_GetIntPending (LPC_RTC_Type *RTCx, uint32_t IntType);
void RTC_ClearIntPending (LPC_RTC_Type *RTCx, uint32_t IntType);
void RTC_CalibCounterCmd(LPC_RTC_Type *RTCx, FunctionalState NewState);
void RTC_CalibConfig(LPC_RTC_Type *RTCx, uint32_t CalibValue, uint8_t CalibDir);
void RTC_WriteGPREG (LPC_RTC_Type *RTCx, uint8_t Channel, uint32_t Value);
uint32_t RTC_ReadGPREG (LPC_RTC_Type *RTCx, uint8_t Channel);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_RTC_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_sct.h
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/**********************************************************************
* $Id$ lpc43xx_sct.h 2011-06-02
*//**
* @file lpc43xx_sct.h
* @brief Contains all macro definitions and function prototypes
* support for SCT firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup SCT SCT (State Configurable Timer)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_SCT_H_
#define lpc43xx_SCT_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private macros ------------------------------------------------------------- */
/** @defgroup SCT_Private_Macros SCT Private Macros
* @{
*/
/* -------------------------- BIT DEFINITIONS ----------------------------------- */
/*********************************************************************//**
* Macro defines for SCT configuration register
**********************************************************************/
/** Selects 16/32 bit counter */
#define SCT_CONFIG_16BIT_COUNTER 0x00000000
#define SCT_CONFIG_32BIT_COUNTER 0x00000001
/*********************************************************************//**
* Macro defines for SCT control register
**********************************************************************/
/** Stop low counter */
#define SCT_CTRL_STOP_L (1<<1)
/** Halt low counter */
#define SCT_CTRL_HALT_L (1<<2)
/** Clear low or unified counter */
#define SCT_CTRL_CLRCTR_L (1<<3)
/** Direction for low or unified counter */
#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0
#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
#define SCT_CTRL_BIDIR_L(x) (((x)&0x01)<<4)
/** Prescale clock for low or unified counter */
#define SCT_CTRL_PRE_L(x) (((x)&0xFF)<<5)
/** Stop high counter */
#define SCT_CTRL_STOP_H (1<<17)
/** Halt high counter */
#define SCT_CTRL_HALT_H (1<<18)
/** Clear high counter */
#define SCT_CTRL_CLRCTR_H (1<<19)
/** Direction for high counter */
#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0
#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
#define SCT_CTRL_BIDIR_H(x) (((x)&0x01)<<20)
/** Prescale clock for high counter */
#define SCT_CTRL_PRE_H(x) (((x)&0xFF)<<21)
/*********************************************************************//**
* Macro defines for SCT Conflict resolution register
**********************************************************************/
/** Define conflict solution */
#define SCT_RES_NOCHANGE (0)
#define SCT_RES_SET_OUTPUT (1)
#define SCT_RES_CLEAR_OUTPUT (2)
#define SCT_RES_TOGGLE_OUTPUT (3)
/* ------------------- CHECK PARAM DEFINITIONS ------------------------- */
/** Check SCT output number */
#define PARAM_SCT_OUTPUT_NUM(n) ((n)<= CONFIG_SCT_nOU )
/** Check SCT counter type */
#define PARAM_SCT_CONFIG_COUNTER_TYPE(n) ((n==SCT_CONFIG_16BIT_COUNTER)||(n==SCT_CONFIG_32BIT_COUNTER))
/** Check SCT conflict solution */
#define PARAM_SCT_RES(n) ((n==SCT_RES_NOCHANGE)||(n==SCT_RES_SET_OUTPUT)\
||(n==SCT_RES_CLEAR_OUTPUT)||(n==SCT_RES_TOGGLE_OUTPUT))
/** Check SCT event number */
#define PARAM_SCT_EVENT(n) ((n) <= 15)
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup SCT_Public_Functions SCT Public Functions
* @{
*/
void SCT_Config(uint32_t value);
void SCT_ControlSet(uint32_t value, FunctionalState ena);
void SCT_ConflictResolutionSet(uint8_t outnum, uint8_t value);
void SCT_EventFlagClear(uint8_t even_num);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_SCT_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_scu.h
+136
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/**********************************************************************
* $Id$ lpc43xx_scu.h 2011-06-02
*//**
* @file lpc43xx_scu.h
* @brief Contains all macro definitions and function prototypes
* support for SCU firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors’
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup SCU SCU (System Control Unit)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef __SCU_H
#define __SCU_H
#ifdef __cplusplus
extern "C"
{
#endif
/* Private macros ------------------------------------------------------------- */
/** @defgroup SCT_Private_Macros SCT Private Macros
* @{
*/
/** Port offset definition */
#define PORT_OFFSET 0x80
/** Pin offset definition */
#define PIN_OFFSET 0x04
/* Pin mode defines, following partly a definition from older chip architectures */
#define MD_PUP (0x0 << 3)
#define MD_BUK (0x1 << 3)
#define MD_PLN (0x2 << 3)
#define MD_PDN (0x3 << 3)
#define MD_EHS (0x1 << 5)
#define MD_EZI (0x1 << 6)
#define MD_ZI (0x1 << 7)
#define MD_EHD0 (0x1 << 8)
#define MD_EHD1 (0x1 << 9)
#define MD_EHD2 (0x3 << 8)
#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
/* Pin mode defines, more in line with the definitions in the LPC1800/4300 user manual */
/* Defines for SFSPx_y pin configuration registers */
#define PDN_ENABLE (1 << 3) // Pull-down enable
#define PDN_DISABLE (0 << 3) // Pull-down disable
#define PUP_ENABLE (0 << 4) // Pull-up enable
#define PUP_DISABLE (1 << 4) // Pull-up disable
#define SLEWRATE_SLOW (0 << 5) // Slew rate for low noise with medium speed
#define SLEWRATE_FAST (1 << 5) // Slew rate for medium noise with fast speed
#define INBUF_ENABLE (1 << 6) // Input buffer
#define INBUF_DISABLE (0 << 6) // Input buffer
#define FILTER_ENABLE (0 << 7) // Glitch filter (for signals below 30MHz)
#define FILTER_DISABLE (1 << 7) // No glitch filter (for signals above 30MHz)
#define DRIVE_8MA (1 << 8) // Drive strength of 8mA
#define DRIVE_14MA (1 << 9) // Drive strength of 14mA
#define DRIVE_20MA (3 << 8) // Drive strength of 20mA
/* Configuration examples for various I/O pins */
#define EMC_IO (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
#define LCD_PINCONFIG (PUP_DISABLE | PDN_DISABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
#define CLK_IN (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
#define CLK_OUT (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
#define GPIO_PUP (PUP_ENABLE | PDN_DISABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
#define GPIO_PDN (PUP_DISABLE | PDN_ENABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
#define GPIO_NOPULL (PUP_DISABLE | PDN_DISABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
#define UART_RX_TX (PUP_DISABLE | PDN_ENABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
#define SSP_IO (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
/* Pin function */
#define FUNC0 0x0 /** Function 0 */
#define FUNC1 0x1 /** Function 1 */
#define FUNC2 0x2 /** Function 2 */
#define FUNC3 0x3 /** Function 3 */
#define FUNC4 0x4
#define FUNC5 0x5
#define FUNC6 0x6
#define FUNC7 0x7
/**
* @}
*/
#define LPC_SCU_PIN(po, pi) (*(volatile int *) (LPC_SCU_BASE + ((po) * 0x80) + ((pi) * 0x4)) )
#define LPC_SCU_CLK(c) (*(volatile int *) (LPC_SCU_BASE + 0xC00 + ((c) * 0x4)) )
/* Public Functions ----------------------------------------------------------- */
/** @defgroup SCU_Public_Functions SCU Public Functions
* @{
*/
void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* end __SCU_H */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_sdif.h
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/**********************************************************************
* $Id$ lpc43xx_sdif.h 2012-Aug-15
*//**
* @file lpc43xx_sdif.h
* @brief Contains all macro definitions and function prototypes
* support for SDIO firmware library on LPC43xx
* @version 1.0
* @date 15. Aug. 2012
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup SDIF SDIF (SD Card Interface)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC43XX_SDIF_H
#define LPC43XX_SDIF_H
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup SDIF_Private_Macros SDIF Private Macros
* @{
*/
/** \brief SDIO chained DMA descriptor
*/
typedef struct {
volatile uint32_t des0; /*!< Control and status */
volatile uint32_t des1; /*!< Buffer size(s) */
volatile uint32_t des2; /*!< Buffer address pointer 1 */
volatile uint32_t des3; /*!< Buffer address pointer 2 */
} LPC_SDMMC_DMA_Type;
/** \brief SDIO DMA descriptor control (des0) register defines
*/
#define MCI_DMADES0_OWN (1UL << 31) /*!< DMA owns descriptor bit */
#define MCI_DMADES0_CES (1 << 30) /*!< Card Error Summary bit */
#define MCI_DMADES0_ER (1 << 5) /*!< End of descriptopr ring bit */
#define MCI_DMADES0_CH (1 << 4) /*!< Second address chained bit */
#define MCI_DMADES0_FS (1 << 3) /*!< First descriptor bit */
#define MCI_DMADES0_LD (1 << 2) /*!< Last descriptor bit */
#define MCI_DMADES0_DIC (1 << 1) /*!< Disable interrupt on completion bit */
/** \brief SDIO DMA descriptor size (des1) register defines
*/
#define MCI_DMADES1_BS1(x) (x) /*!< Size of buffer 1 */
#define MCI_DMADES1_BS2(x) ((x) << 13) /*!< Size of buffer 2 */
#define MCI_DMADES1_MAXTR 4096 /*!< Max transfer size per buffer */
/** \brief SDIO control register defines
*/
#define MCI_CTRL_USE_INT_DMAC (1 << 25) /*!< Use internal DMA */
#define MCI_CTRL_CARDV_MASK (0x7 << 16) /*!< SD_VOLT[2:0} pins output state mask */
#define MCI_CTRL_CEATA_INT_EN (1 << 11) /*!< Enable CE-ATA interrupts */
#define MCI_CTRL_SEND_AS_CCSD (1 << 10) /*!< Send auto-stop */
#define MCI_CTRL_SEND_CCSD (1 << 9) /*!< Send CCSD */
#define MCI_CTRL_ABRT_READ_DATA (1 << 8) /*!< Abort read data */
#define MCI_CTRL_SEND_IRQ_RESP (1 << 7) /*!< Send auto-IRQ response */
#define MCI_CTRL_READ_WAIT (1 << 6) /*!< Assert read-wait for SDIO */
#define MCI_CTRL_INT_ENABLE (1 << 4) /*!< Global interrupt enable */
#define MCI_CTRL_DMA_RESET (1 << 2) /*!< Reset internal DMA */
#define MCI_CTRL_FIFO_RESET (1 << 1) /*!< Reset data FIFO pointers */
#define MCI_CTRL_RESET (1 << 0) /*!< Reset controller */
/** \brief SDIO Power Enable register defines
*/
#define MCI_POWER_ENABLE 0x1 /*!< Enable slot power signal (SD_POW) */
/** \brief SDIO Clock divider register defines
*/
#define MCI_CLOCK_DIVIDER(dn, d2) ((d2) << ((dn) * 8)) /*!< Set cklock divider */
/** \brief SDIO Clock source register defines
*/
#define MCI_CLKSRC_CLKDIV0 0
#define MCI_CLKSRC_CLKDIV1 1
#define MCI_CLKSRC_CLKDIV2 2
#define MCI_CLKSRC_CLKDIV3 3
#define MCI_CLK_SOURCE(clksrc) (clksrc) /*!< Set cklock divider source */
/** \brief SDIO Clock Enable register defines
*/
#define MCI_CLKEN_LOW_PWR (1 << 16) /*!< Enable clock idle for slot */
#define MCI_CLKEN_ENABLE (1 << 0) /*!< Enable slot clock */
/** \brief SDIO time-out register defines
*/
#define MCI_TMOUT_DATA(clks) ((clks) << 8) /*!< Data timeout clocks */
#define MCI_TMOUT_DATA_MSK 0xFFFFFF00
#define MCI_TMOUT_RESP(clks) ((clks) & 0xFF) /*!< Response timeout clocks */
#define MCI_TMOUT_RESP_MSK 0xFF
/** \brief SDIO card-type register defines
*/
#define MCI_CTYPE_8BIT (1 << 16) /*!< Enable 4-bit mode */
#define MCI_CTYPE_4BIT (1 << 0) /*!< Enable 8-bit mode */
/** \brief SDIO Interrupt status & mask register defines
*/
#define MCI_INT_SDIO (1 << 16) /*!< SDIO interrupt */
#define MCI_INT_EBE (1 << 15) /*!< End-bit error */
#define MCI_INT_ACD (1 << 14) /*!< Auto command done */
#define MCI_INT_SBE (1 << 13) /*!< Start bit error */
#define MCI_INT_HLE (1 << 12) /*!< Hardware locked error */
#define MCI_INT_FRUN (1 << 11) /*!< FIFO overrun/underrun error */
#define MCI_INT_HTO (1 << 10) /*!< Host data starvation error */
#define MCI_INT_DTO (1 << 9) /*!< Data timeout error */
#define MCI_INT_RTO (1 << 8) /*!< Response timeout error */
#define MCI_INT_DCRC (1 << 7) /*!< Data CRC error */
#define MCI_INT_RCRC (1 << 6) /*!< Response CRC error */
#define MCI_INT_RXDR (1 << 5) /*!< RX data ready */
#define MCI_INT_TXDR (1 << 4) /*!< TX data needed */
#define MCI_INT_DATA_OVER (1 << 3) /*!< Data transfer over */
#define MCI_INT_CMD_DONE (1 << 2) /*!< Command done */
#define MCI_INT_RESP_ERR (1 << 1) /*!< Command response error */
#define MCI_INT_CD (1 << 0) /*!< Card detect */
/** \brief SDIO Command register defines
*/
#define MCI_CMD_START (1UL << 31) /*!< Start command */
#define MCI_CMD_VOLT_SWITCH (1 << 28) /*!< Voltage switch bit */
#define MCI_CMD_BOOT_MODE (1 << 27) /*!< Boot mode */
#define MCI_CMD_DISABLE_BOOT (1 << 26) /*!< Disable boot */
#define MCI_CMD_EXPECT_BOOT_ACK (1 << 25) /*!< Expect boot ack */
#define MCI_CMD_ENABLE_BOOT (1 << 24) /*!< Enable boot */
#define MCI_CMD_CCS_EXP (1 << 23) /*!< CCS expected */
#define MCI_CMD_CEATA_RD (1 << 22) /*!< CE-ATA read in progress */
#define MCI_CMD_UPD_CLK (1 << 21) /*!< Update clock register only */
#define MCI_CMD_INIT (1 << 15) /*!< Send init sequence */
#define MCI_CMD_STOP (1 << 14) /*!< Stop/abort command */
#define MCI_CMD_PRV_DAT_WAIT (1 << 13) /*!< Wait before send */
#define MCI_CMD_SEND_STOP (1 << 12) /*!< Send auto-stop */
#define MCI_CMD_STRM_MODE (1 << 11) /*!< Stream transfer mode */
#define MCI_CMD_DAT_WR (1 << 10) /*!< Read(0)/Write(1) selection */
#define MCI_CMD_DAT_EXP (1 << 9) /*!< Data expected */
#define MCI_CMD_RESP_CRC (1 << 8) /*!< Check response CRC */
#define MCI_CMD_RESP_LONG (1 << 7) /*!< Response length */
#define MCI_CMD_RESP_EXP (1 << 6) /*!< Response expected */
#define MCI_CMD_INDX(n) ((n) & 0x1F)
/** \brief SDIO status register definess
*/
#define MCI_STS_GET_FCNT(x) (((x) >> 17) & 0x1FF)
/** \brief SDIO FIFO threshold defines
*/
#define MCI_FIFOTH_TX_WM(x) ((x) & 0xFFF)
#define MCI_FIFOTH_RX_WM(x) (((x) & 0xFFF) << 16)
#define MCI_FIFOTH_DMA_MTS_1 (0UL << 28)
#define MCI_FIFOTH_DMA_MTS_4 (1UL << 28)
#define MCI_FIFOTH_DMA_MTS_8 (2UL << 28)
#define MCI_FIFOTH_DMA_MTS_16 (3UL << 28)
#define MCI_FIFOTH_DMA_MTS_32 (4UL << 28)
#define MCI_FIFOTH_DMA_MTS_64 (5UL << 28)
#define MCI_FIFOTH_DMA_MTS_128 (6UL << 28)
#define MCI_FIFOTH_DMA_MTS_256 (7UL << 28)
/** \brief Bus mode register defines
*/
#define MCI_BMOD_PBL1 (0 << 8) /*!< Burst length = 1 */
#define MCI_BMOD_PBL4 (1 << 8) /*!< Burst length = 4 */
#define MCI_BMOD_PBL8 (2 << 8) /*!< Burst length = 8 */
#define MCI_BMOD_PBL16 (3 << 8) /*!< Burst length = 16 */
#define MCI_BMOD_PBL32 (4 << 8) /*!< Burst length = 32 */
#define MCI_BMOD_PBL64 (5 << 8) /*!< Burst length = 64 */
#define MCI_BMOD_PBL128 (6 << 8) /*!< Burst length = 128 */
#define MCI_BMOD_PBL256 (7 << 8) /*!< Burst length = 256 */
#define MCI_BMOD_DE (1 << 7) /*!< Enable internal DMAC */
#define MCI_BMOD_DSL(len) ((len) << 2) /*!< Descriptor skip length */
#define MCI_BMOD_FB (1 << 1) /*!< Fixed bursts */
#define MCI_BMOD_SWR (1 << 0) /*!< Software reset of internal registers */
/** \brief Commonly used definitions
*/
#define SD_FIFO_SZ 32 /*!< Size of SDIO FIFOs (32-bit wide) */
/***********************************************************************
* MCI device structure and it defines
**********************************************************************/
/* Function prototype for SD interface IRQ callback */
typedef uint32_t (*MCI_IRQ_CB_FUNC_T)(uint32_t);
/* Function prototype for SD detect and write protect status check */
typedef int32_t (*PSCHECK_FUNC_T) (void);
/* Function prototype for SD slot power enable or slot reset */
typedef void (*PS_POWER_FUNC_T) (int32_t enable);
/* Card specific setup data */
struct _mci_card_struct
{
uint32_t response[4]; /*!< Most recent response */
uint32_t cid[4]; /*!< CID of acquired card */
uint32_t csd[4]; /*!< CSD of acquired card */
uint32_t ext_csd[512 / 4];
uint32_t card_type;
uint32_t rca; /*!< Relative address assigned to card */
uint32_t speed;
uint32_t block_len;
uint32_t device_size;
uint32_t blocknr;
PSCHECK_FUNC_T sdck_det;
PSCHECK_FUNC_T sdck_wp;
PS_POWER_FUNC_T sd_setpow;
PS_POWER_FUNC_T sd_setrst;
};
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup SDIO_Public_Functions SDIO Public Functions
* @{
*/
/* Setup DMA descriptors */
void sdif_dma_setup(uint32_t addr, uint32_t size);
/* Send a command on the SD bus */
int32_t sdif_send_cmd(uint32_t cmd, uint32_t arg);
/* Read the response from the last command */
void sdif_get_response(uint32_t *resp);
/* Sets the SD bus clock speed */
void sdif_set_clock(uint32_t speed);
/* Detect if an SD card is inserted
(uses SD_CD pin, returns 0 on card detect) */
int32_t sdif_card_ndetect(void);
/* Detect if write protect is enabled
(uses SD_WP pin, returns 1 if card is write protected) */
int32_t sdif_card_wp_on(void);
/* Enable or disable slot power, !0 = enable slot power
(Uses SD_POW pin, set to high or low based on enable parameter state) */
void sdif_power_onoff(int32_t enable);
/* Reset card in slot, must manually de-assert reset after assertion
(Uses SD_RST pin, set per reset parameter state) */
void sdif_reset(int32_t reset);
/* Set block size for transfer */
void sdif_set_blksize(uint32_t bytes);
/* Enter or exit low power mode. */
void sdif_set_lowpower_mode(int32_t lpmode);
/* Initialize the SD controller */
void sdif_init(uint32_t sdio_clock, MCI_IRQ_CB_FUNC_T irq_callback);
/* Close the SD controller */
void sdif_deinit(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* end LPC43XX_SDIF_H */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_sdmmc.h
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/**********************************************************************
* $Id$ lpc43xx_sdmmc.h 2012-Aug-15
*//**
* @file lpc43xx_sdmmc.h
* @brief SD/MMC card access and data driver
* @version 1.0
* @date 15. Aug. 2012
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup SDMMC SDMMC (SDMMC Card Interface)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC43XX_SDMMC_H
#define LPC43XX_SDMMC_H
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup SDMMC_Private_Macros SDMMC Private Macros
* @{
*/
/** \brief card type defines
*/
#define CARD_TYPE_SD (1 << 0)
#define CARD_TYPE_4BIT (1 << 1)
#define CARD_TYPE_8BIT (1 << 2)
#define CARD_TYPE_HC (OCR_HC_CCS) /*!< high capacity card > 2GB */
#define MMC_SECTOR_SIZE 512
/** \brief Setup options for the SDIO driver
*/
#define US_TIMEOUT 1000000 /*!< give 1 atleast 1 sec for the card to respond */
#define MS_ACQUIRE_DELAY (10) /*!< inter-command acquire oper condition delay in msec*/
#define INIT_OP_RETRIES 50 /*!< initial OP_COND retries */
#define SET_OP_RETRIES 1000 /*!< set OP_COND retries */
#define SDIO_BUS_WIDTH 4 /*!< Max bus width supported */
#define SD_MMC_ENUM_CLOCK 400000 /*!< Typical enumeration clock rate */
#define MMC_MAX_CLOCK 20000000 /*!< Max MMC clock rate */
#define MMC_LOW_BUS_MAX_CLOCK 26000000 /*!< Type 0 MMC card max clock rate */
#define MMC_HIGH_BUS_MAX_CLOCK 52000000 /*!< Type 1 MMC card max clock rate */
#define SD_MAX_CLOCK 25000000 /*!< Max SD clock rate */
/* Function prototype for event setup function */
typedef void (*MCI_EVSETUP_FUNC_T)(uint32_t);
/* Function prototype for wait (for IRQ) function */
typedef uint32_t (*MCI_WAIT_CB_FUNC_T)(uint32_t);
/* Function prototype for milliSecond delay function */
typedef void (*MCI_MSDELAY_FUNC_T)(uint32_t);
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup SDMMC_Public_Functions SDMMC Public Functions
* @{
*/
/* Attempt to enumerate an SDMMC card */
int32_t sdmmc_acquire(MCI_EVSETUP_FUNC_T evsetup_cb,
MCI_WAIT_CB_FUNC_T waitfunc_cb, MCI_MSDELAY_FUNC_T msdelay_func,
struct _mci_card_struct *pcardinfo);
/* Get card's current state (idle, transfer, program, etc.) */
int32_t sdmmc_get_state(void);
/* Get card's size */
int32_t sdmmc_get_device_size(void);
/* SDMMC read function - reads data from a card */
int32_t sdmmc_read_blocks(void *buffer, int32_t start_block,
int32_t end_block);
/* SDMMC write function - writes data to a card. After calling this
function, do not use read or write until the card state has
left the program state. */
int32_t sdmmc_write_blocks(void *buffer, int32_t start_block,
int32_t end_block);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* end LPC43XX_SDMMC_H */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_ssp.h
+451
View File
@@ -0,0 +1,451 @@
/**********************************************************************
* $Id$ lpc43xx_ssp.h 2011-06-02
*//**
* @file lpc43xx_ssp.h
* @brief Contains all macro definitions and function prototypes
* support for SSP firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup SSP SSP (Synchronous Serial Port)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_SSP_H_
#define lpc43xx_SSP_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup SSP_Private_Macros SSP Private Macros
* @{
*/
/*********************************************************************//**
* SSP configuration parameter defines
**********************************************************************/
/** Clock phase control bit */
#define SSP_CPHA_FIRST ((uint32_t)(0))
#define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
/** Clock polarity control bit */
/* There's no bug here!!!
* - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
* That means the active clock is in HI state.
* - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
* high between frames. That means the active clock is in LO state.
*/
#define SSP_CPOL_HI ((uint32_t)(0))
#define SSP_CPOL_LO SSP_CR0_CPOL_HI
/** SSP master mode enable */
#define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
#define SSP_MASTER_MODE ((uint32_t)(0))
/** SSP data bit number defines */
#define SSP_DATABIT_4 SSP_CR0_DSS(4) /*!< Databit number = 4 */
#define SSP_DATABIT_5 SSP_CR0_DSS(5) /*!< Databit number = 5 */
#define SSP_DATABIT_6 SSP_CR0_DSS(6) /*!< Databit number = 6 */
#define SSP_DATABIT_7 SSP_CR0_DSS(7) /*!< Databit number = 7 */
#define SSP_DATABIT_8 SSP_CR0_DSS(8) /*!< Databit number = 8 */
#define SSP_DATABIT_9 SSP_CR0_DSS(9) /*!< Databit number = 9 */
#define SSP_DATABIT_10 SSP_CR0_DSS(10) /*!< Databit number = 10 */
#define SSP_DATABIT_11 SSP_CR0_DSS(11) /*!< Databit number = 11 */
#define SSP_DATABIT_12 SSP_CR0_DSS(12) /*!< Databit number = 12 */
#define SSP_DATABIT_13 SSP_CR0_DSS(13) /*!< Databit number = 13 */
#define SSP_DATABIT_14 SSP_CR0_DSS(14) /*!< Databit number = 14 */
#define SSP_DATABIT_15 SSP_CR0_DSS(15) /*!< Databit number = 15 */
#define SSP_DATABIT_16 SSP_CR0_DSS(16) /*!< Databit number = 16 */
/** SSP Frame Format definition */
/** Motorola SPI mode */
#define SSP_FRAME_SPI SSP_CR0_FRF_SPI
/** TI synchronous serial mode */
#define SSP_FRAME_TI SSP_CR0_FRF_TI
/** National Micro-wire mode */
#define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE
/*********************************************************************//**
* SSP Status defines
**********************************************************************/
/** SSP status TX FIFO Empty bit */
#define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE
/** SSP status TX FIFO not full bit */
#define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF
/** SSP status RX FIFO not empty bit */
#define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE
/** SSP status RX FIFO full bit */
#define SSP_STAT_RXFIFO_FULL SSP_SR_RFF
/** SSP status SSP Busy bit */
#define SSP_STAT_BUSY SSP_SR_BSY
/*********************************************************************//**
* SSP Interrupt Configuration defines
**********************************************************************/
/** Receive Overrun */
#define SSP_INTCFG_ROR SSP_IMSC_ROR
/** Receive TimeOut */
#define SSP_INTCFG_RT SSP_IMSC_RT
/** Rx FIFO is at least half full */
#define SSP_INTCFG_RX SSP_IMSC_RX
/** Tx FIFO is at least half empty */
#define SSP_INTCFG_TX SSP_IMSC_TX
/*********************************************************************//**
* SSP Configured Interrupt Status defines
**********************************************************************/
/** Receive Overrun */
#define SSP_INTSTAT_ROR SSP_MIS_ROR
/** Receive TimeOut */
#define SSP_INTSTAT_RT SSP_MIS_RT
/** Rx FIFO is at least half full */
#define SSP_INTSTAT_RX SSP_MIS_RX
/** Tx FIFO is at least half empty */
#define SSP_INTSTAT_TX SSP_MIS_TX
/*********************************************************************//**
* SSP Raw Interrupt Status defines
**********************************************************************/
/** Receive Overrun */
#define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR
/** Receive TimeOut */
#define SSP_INTSTAT_RAW_RT SSP_RIS_RT
/** Rx FIFO is at least half full */
#define SSP_INTSTAT_RAW_RX SSP_RIS_RX
/** Tx FIFO is at least half empty */
#define SSP_INTSTAT_RAW_TX SSP_RIS_TX
/*********************************************************************//**
* SSP Interrupt Clear defines
**********************************************************************/
/** Writing a 1 to this bit clears the "frame was received when
* RxFIFO was full" interrupt */
#define SSP_INTCLR_ROR SSP_ICR_ROR
/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
* has not been read for a timeout period" interrupt */
#define SSP_INTCLR_RT SSP_ICR_RT
/*********************************************************************//**
* SSP DMA defines
**********************************************************************/
/** SSP bit for enabling RX DMA */
#define SSP_DMA_RX SSP_DMA_RXDMA_EN
/** SSP bit for enabling TX DMA */
#define SSP_DMA_TX SSP_DMA_TXDMA_EN
/* SSP Status Implementation definitions */
#define SSP_STAT_DONE (1UL<<8) /**< Done */
#define SSP_STAT_ERROR (1UL<<9) /**< Error */
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*********************************************************************//**
* Macro defines for CR0 register
**********************************************************************/
/** SSP data size select, must be 4 bits to 16 bits */
#define SSP_CR0_DSS(n) ((uint32_t)((n-1)&0xF))
/** SSP control 0 Motorola SPI mode */
#define SSP_CR0_FRF_SPI ((uint32_t)(0<<4))
/** SSP control 0 TI synchronous serial mode */
#define SSP_CR0_FRF_TI ((uint32_t)(1<<4))
/** SSP control 0 National Micro-wire mode */
#define SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4))
/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
bus clock high between frames, (0) = low */
#define SSP_CR0_CPOL_HI ((uint32_t)(1<<6))
/** SPI clock out phase bit (used in SPI mode only), (1) = captures data
on the second clock transition of the frame, (0) = first */
#define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7))
/** SSP serial clock rate value load macro, divider rate is
PERIPH_CLK / (cpsr * (SCR + 1)) */
#define SSP_CR0_SCR(n) ((uint32_t)((n&0xFF)<<8))
/** SSP CR0 bit mask */
#define SSP_CR0_BITMASK ((uint32_t)(0xFFFF))
/*********************************************************************//**
* Macro defines for CR1 register
**********************************************************************/
/** SSP control 1 loopback mode enable bit */
#define SSP_CR1_LBM_EN ((uint32_t)(1<<0))
/** SSP control 1 enable bit */
#define SSP_CR1_SSP_EN ((uint32_t)(1<<1))
/** SSP control 1 slave enable */
#define SSP_CR1_SLAVE_EN ((uint32_t)(1<<2))
/** SSP control 1 slave out disable bit, disables transmit line in slave
mode */
#define SSP_CR1_SO_DISABLE ((uint32_t)(1<<3))
/** SSP CR1 bit mask */
#define SSP_CR1_BITMASK ((uint32_t)(0x0F))
/*********************************************************************//**
* Macro defines for DR register
**********************************************************************/
/** SSP data bit mask */
#define SSP_DR_BITMASK(n) ((n)&0xFFFF)
/*********************************************************************//**
* Macro defines for SR register
**********************************************************************/
/** SSP status TX FIFO Empty bit */
#define SSP_SR_TFE ((uint32_t)(1<<0))
/** SSP status TX FIFO not full bit */
#define SSP_SR_TNF ((uint32_t)(1<<1))
/** SSP status RX FIFO not empty bit */
#define SSP_SR_RNE ((uint32_t)(1<<2))
/** SSP status RX FIFO full bit */
#define SSP_SR_RFF ((uint32_t)(1<<3))
/** SSP status SSP Busy bit */
#define SSP_SR_BSY ((uint32_t)(1<<4))
/** SSP SR bit mask */
#define SSP_SR_BITMASK ((uint32_t)(0x1F))
/*********************************************************************//**
* Macro defines for CPSR register
**********************************************************************/
/** SSP clock prescaler */
#define SSP_CPSR_CPDVSR(n) ((uint32_t)(n&0xFF))
/** SSP CPSR bit mask */
#define SSP_CPSR_BITMASK ((uint32_t)(0xFF))
/*********************************************************************//**
* Macro define for (IMSC) Interrupt Mask Set/Clear registers
**********************************************************************/
/** Receive Overrun */
#define SSP_IMSC_ROR ((uint32_t)(1<<0))
/** Receive TimeOut */
#define SSP_IMSC_RT ((uint32_t)(1<<1))
/** Rx FIFO is at least half full */
#define SSP_IMSC_RX ((uint32_t)(1<<2))
/** Tx FIFO is at least half empty */
#define SSP_IMSC_TX ((uint32_t)(1<<3))
/** IMSC bit mask */
#define SSP_IMSC_BITMASK ((uint32_t)(0x0F))
/*********************************************************************//**
* Macro define for (RIS) Raw Interrupt Status registers
**********************************************************************/
/** Receive Overrun */
#define SSP_RIS_ROR ((uint32_t)(1<<0))
/** Receive TimeOut */
#define SSP_RIS_RT ((uint32_t)(1<<1))
/** Rx FIFO is at least half full */
#define SSP_RIS_RX ((uint32_t)(1<<2))
/** Tx FIFO is at least half empty */
#define SSP_RIS_TX ((uint32_t)(1<<3))
/** RIS bit mask */
#define SSP_RIS_BITMASK ((uint32_t)(0x0F))
/*********************************************************************//**
* Macro define for (MIS) Masked Interrupt Status registers
**********************************************************************/
/** Receive Overrun */
#define SSP_MIS_ROR ((uint32_t)(1<<0))
/** Receive TimeOut */
#define SSP_MIS_RT ((uint32_t)(1<<1))
/** Rx FIFO is at least half full */
#define SSP_MIS_RX ((uint32_t)(1<<2))
/** Tx FIFO is at least half empty */
#define SSP_MIS_TX ((uint32_t)(1<<3))
/** MIS bit mask */
#define SSP_MIS_BITMASK ((uint32_t)(0x0F))
/*********************************************************************//**
* Macro define for (ICR) Interrupt Clear registers
**********************************************************************/
/** Writing a 1 to this bit clears the "frame was received when
* RxFIFO was full" interrupt */
#define SSP_ICR_ROR ((uint32_t)(1<<0))
/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
* has not been read for a timeout period" interrupt */
#define SSP_ICR_RT ((uint32_t)(1<<1))
/** ICR bit mask */
#define SSP_ICR_BITMASK ((uint32_t)(0x03))
/*********************************************************************//**
* Macro defines for DMACR register
**********************************************************************/
/** SSP bit for enabling RX DMA */
#define SSP_DMA_RXDMA_EN ((uint32_t)(1<<0))
/** SSP bit for enabling TX DMA */
#define SSP_DMA_TXDMA_EN ((uint32_t)(1<<1))
/** DMACR bit mask */
#define SSP_DMA_BITMASK ((uint32_t)(0x03))
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/** Macro to determine if it is valid SSP port number */
#define PARAM_SSPx(n) ((((uint32_t *)n)==((uint32_t *)LPC_SSP0)) \
|| (((uint32_t *)n)==((uint32_t *)LPC_SSP1)))
/** Macro check clock phase control mode */
#define PARAM_SSP_CPHA(n) ((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND))
/** Macro check clock polarity mode */
#define PARAM_SSP_CPOL(n) ((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO))
/* Macro check master/slave mode */
#define PARAM_SSP_MODE(n) ((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE))
/* Macro check databit value */
#define PARAM_SSP_DATABIT(n) ((n==SSP_DATABIT_4) || (n==SSP_DATABIT_5) \
|| (n==SSP_DATABIT_6) || (n==SSP_DATABIT_16) \
|| (n==SSP_DATABIT_7) || (n==SSP_DATABIT_8) \
|| (n==SSP_DATABIT_9) || (n==SSP_DATABIT_10) \
|| (n==SSP_DATABIT_11) || (n==SSP_DATABIT_12) \
|| (n==SSP_DATABIT_13) || (n==SSP_DATABIT_14) \
|| (n==SSP_DATABIT_15))
/* Macro check frame type */
#define PARAM_SSP_FRAME(n) ((n==SSP_FRAME_SPI) || (n==SSP_FRAME_TI)\
|| (n==SSP_FRAME_MICROWIRE))
/* Macro check SSP status */
#define PARAM_SSP_STAT(n) ((n==SSP_STAT_TXFIFO_EMPTY) || (n==SSP_STAT_TXFIFO_NOTFULL) \
|| (n==SSP_STAT_RXFIFO_NOTEMPTY) || (n==SSP_STAT_RXFIFO_FULL) \
|| (n==SSP_STAT_BUSY))
/* Macro check interrupt configuration */
#define PARAM_SSP_INTCFG(n) ((n==SSP_INTCFG_ROR) || (n==SSP_INTCFG_RT) \
|| (n==SSP_INTCFG_RX) || (n==SSP_INTCFG_TX))
/* Macro check interrupt status value */
#define PARAM_SSP_INTSTAT(n) ((n==SSP_INTSTAT_ROR) || (n==SSP_INTSTAT_RT) \
|| (n==SSP_INTSTAT_RX) || (n==SSP_INTSTAT_TX))
/* Macro check interrupt status raw value */
#define PARAM_SSP_INTSTAT_RAW(n) ((n==SSP_INTSTAT_RAW_ROR) || (n==SSP_INTSTAT_RAW_RT) \
|| (n==SSP_INTSTAT_RAW_RX) || (n==SSP_INTSTAT_RAW_TX))
/* Macro check interrupt clear mode */
#define PARAM_SSP_INTCLR(n) ((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT))
/* Macro check DMA mode */
#define PARAM_SSP_DMA(n) ((n==SSP_DMA_TX) || (n==SSP_DMA_RX))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup SSP_Public_Types SSP Public Types
* @{
*/
/** @brief SSP configuration structure */
typedef struct {
uint32_t Databit; /** Databit number, should be SSP_DATABIT_x,
where x is in range from 4 - 16 */
uint32_t CPHA; /** Clock phase, should be:
- SSP_CPHA_FIRST: first clock edge
- SSP_CPHA_SECOND: second clock edge */
uint32_t CPOL; /** Clock polarity, should be:
- SSP_CPOL_HI: high level
- SSP_CPOL_LO: low level */
uint32_t Mode; /** SSP mode, should be:
- SSP_MASTER_MODE: Master mode
- SSP_SLAVE_MODE: Slave mode */
uint32_t FrameFormat; /** Frame Format:
- SSP_FRAME_SPI: Motorola SPI frame format
- SSP_FRAME_TI: TI frame format
- SSP_FRAME_MICROWIRE: National Microwire frame format */
uint32_t ClockRate; /** Clock rate,in Hz */
} SSP_CFG_Type;
/**
* @brief SSP Transfer Type definitions
*/
typedef enum {
SSP_TRANSFER_POLLING = 0, /**< Polling transfer */
SSP_TRANSFER_INTERRUPT /**< Interrupt transfer */
} SSP_TRANSFER_Type;
/**
* @brief SPI Data configuration structure definitions
*/
typedef struct {
void *tx_data; /**< Pointer to transmit data */
uint32_t tx_cnt; /**< Transmit counter */
void *rx_data; /**< Pointer to transmit data */
uint32_t rx_cnt; /**< Receive counter */
uint32_t length; /**< Length of transfer data */
uint32_t status; /**< Current status of SSP activity */
} SSP_DATA_SETUP_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup SSP_Public_Functions SSP Public Functions
* @{
*/
void SSP_Init(LPC_SSPn_Type *SSPx, SSP_CFG_Type *SSP_ConfigStruct);
void SSP_DeInit(LPC_SSPn_Type* SSPx);
void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct);
void SSP_Cmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);
void SSP_LoopBackCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);
void SSP_SlaveOutputCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);
void SSP_SendData(LPC_SSPn_Type* SSPx, uint16_t Data);
uint16_t SSP_ReceiveData(LPC_SSPn_Type* SSPx);
int32_t SSP_ReadWrite (LPC_SSPn_Type *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
SSP_TRANSFER_Type xfType);
FlagStatus SSP_GetStatus(LPC_SSPn_Type* SSPx, uint32_t FlagType);
uint8_t SSP_GetDataSize(LPC_SSPn_Type* SSPx);
void SSP_IntConfig(LPC_SSPn_Type *SSPx, uint32_t IntType, FunctionalState NewState);
IntStatus SSP_GetRawIntStatus(LPC_SSPn_Type *SSPx, uint32_t RawIntType);
IntStatus SSP_GetIntStatus (LPC_SSPn_Type *SSPx, uint32_t IntType);
void SSP_ClearIntPending(LPC_SSPn_Type *SSPx, uint32_t IntType);
void SSP_DMACmd(LPC_SSPn_Type *SSPx, uint32_t DMAMode, FunctionalState NewState);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_SSP_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_timer.h
+357
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@@ -0,0 +1,357 @@
/**********************************************************************
* $Id$ lpc43xx_timer.h 2011-06-02
*//**
* @file lpc43xx_timer.h
* @brief Contains all functions support for Timer firmware library
* on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup TIMER TIMER
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef __lpc43xx_TIMER_H_
#define __lpc43xx_TIMER_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup TIMER_Private_Macros TIMER Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/**********************************************************************
** Interrupt information
**********************************************************************/
/** Macro to clean interrupt pending */
#define TIM_IR_CLR(n) _BIT(n)
/**********************************************************************
** Timer interrupt register definitions
**********************************************************************/
/** Macro for getting a timer match interrupt bit */
#define TIM_MATCH_INT(n) (_BIT(n & 0x0F))
/** Macro for getting a capture event interrupt bit */
#define TIM_CAP_INT(n) (_BIT(((n & 0x0F) + 4)))
/**********************************************************************
* Timer control register definitions
**********************************************************************/
/** Timer/counter enable bit */
#define TIM_ENABLE ((uint32_t)(1<<0))
/** Timer/counter reset bit */
#define TIM_RESET ((uint32_t)(1<<1))
/** Timer control bit mask */
#define TIM_TCR_MASKBIT ((uint32_t)(3))
/**********************************************************************
* Timer match control register definitions
**********************************************************************/
/** Bit location for interrupt on MRx match, n = 0 to 3 */
#define TIM_INT_ON_MATCH(n) (_BIT((n * 3)))
/** Bit location for reset on MRx match, n = 0 to 3 */
#define TIM_RESET_ON_MATCH(n) (_BIT(((n * 3) + 1)))
/** Bit location for stop on MRx match, n = 0 to 3 */
#define TIM_STOP_ON_MATCH(n) (_BIT(((n * 3) + 2)))
/** Timer Match control bit mask */
#define TIM_MCR_MASKBIT ((uint32_t)(0x0FFF))
/** Timer Match control bit mask for specific channel*/
#define TIM_MCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<(n*3)))
/**********************************************************************
* Timer capture control register definitions
**********************************************************************/
/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */
#define TIM_CAP_RISING(n) (_BIT((n * 3)))
/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */
#define TIM_CAP_FALLING(n) (_BIT(((n * 3) + 1)))
/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */
#define TIM_INT_ON_CAP(n) (_BIT(((n * 3) + 2)))
/** Mask bit for rising and falling edge bit */
#define TIM_EDGE_MASK(n) (_SBF((n * 3), 0x03))
/** Timer capture control bit mask */
#define TIM_CCR_MASKBIT ((uint32_t)(0x3F))
/** Timer Capture control bit mask for specific channel*/
#define TIM_CCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<(n*3)))
/**********************************************************************
* Timer external match register definitions
**********************************************************************/
/** Bit location for output state change of MAT.n when external match
happens, n = 0 to 3 */
#define TIM_EM(n) _BIT(n)
/** Output state change of MAT.n when external match happens: no change */
#define TIM_EM_NOTHING ((uint8_t)(0x0))
/** Output state change of MAT.n when external match happens: low */
#define TIM_EM_LOW ((uint8_t)(0x1))
/** Output state change of MAT.n when external match happens: high */
#define TIM_EM_HIGH ((uint8_t)(0x2))
/** Output state change of MAT.n when external match happens: toggle */
#define TIM_EM_TOGGLE ((uint8_t)(0x3))
/** Macro for setting for the MAT.n change state bits */
#define TIM_EM_SET(n,s) (_SBF(((n << 1) + 4), (s & 0x03)))
/** Mask for the MAT.n change state bits */
#define TIM_EM_MASK(n) (_SBF(((n << 1) + 4), 0x03))
/** Timer external match bit mask */
#define TIM_EMR_MASKBIT 0x0FFF
/**********************************************************************
* Timer Count Control Register definitions
**********************************************************************/
/** Mask to get the Counter/timer mode bits */
#define TIM_CTCR_MODE_MASK 0x3
/** Mask to get the count input select bits */
#define TIM_CTCR_INPUT_MASK 0xC
/** Timer Count control bit mask */
#define TIM_CTCR_MASKBIT 0xF
#define TIM_COUNTER_MODE ((uint8_t)(1))
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/** Macro to determine if it is valid TIMER peripheral */
#define PARAM_TIMx(n) ((((uint32_t *)n)==((uint32_t *)LPC_TIMER0)) || (((uint32_t *)n)==((uint32_t *)LPC_TIMER1)) \
|| (((uint32_t *)n)==((uint32_t *)LPC_TIMER2)) || (((uint32_t *)n)==((uint32_t *)LPC_TIMER3)))
/* Macro check interrupt type */
#define PARAM_TIM_INT_TYPE(TYPE) ((TYPE ==TIM_MR0_INT)||(TYPE ==TIM_MR1_INT)\
||(TYPE ==TIM_MR2_INT)||(TYPE ==TIM_MR3_INT)\
||(TYPE ==TIM_CR0_INT)||(TYPE ==TIM_CR1_INT)\
||(TYPE ==TIM_CR2_INT)||(TYPE ==TIM_CR3_INT))
/* Macro check TIMER mode */
#define PARAM_TIM_MODE_OPT(MODE) ((MODE == TIM_TIMER_MODE)||(MODE == TIM_COUNTER_RISING_MODE)\
|| (MODE == TIM_COUNTER_RISING_MODE)||(MODE == TIM_COUNTER_RISING_MODE))
/* Macro check TIMER prescale value */
#define PARAM_TIM_PRESCALE_OPT(OPT) ((OPT == TIM_PRESCALE_TICKVAL)||(OPT == TIM_PRESCALE_USVAL))
/* Macro check TIMER counter intput mode */
#define PARAM_TIM_COUNTER_INPUT_OPT(OPT) ((OPT == TIM_COUNTER_INCAP0)||(OPT == TIM_COUNTER_INCAP1)\
||(OPT == TIM_COUNTER_INCAP2)||(OPT == TIM_COUNTER_INCAP3))
/* Macro check TIMER external match mode */
#define PARAM_TIM_EXTMATCH_OPT(OPT) ((OPT == TIM_EXTMATCH_NOTHING)||(OPT == TIM_EXTMATCH_LOW)\
||(OPT == TIM_EXTMATCH_HIGH)||(OPT == TIM_EXTMATCH_TOGGLE))
/* Macro check TIMER external match mode */
#define PARAM_TIM_CAP_MODE_OPT(OPT) ((OPT == TIM_CAPTURE_NONE)||(OPT == TIM_CAPTURE_RISING) \
||(OPT == TIM_CAPTURE_FALLING)||(OPT == TIM_CAPTURE_ANY))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup TIMER_Public_Types TIMER Public Types
* @{
*/
/***********************************************************************
* @brief Timer device enumeration
**********************************************************************/
/** @brief interrupt type */
typedef enum
{
TIM_MR0_INT =0, /*!< interrupt for Match channel 0*/
TIM_MR1_INT =1, /*!< interrupt for Match channel 1*/
TIM_MR2_INT =2, /*!< interrupt for Match channel 2*/
TIM_MR3_INT =3, /*!< interrupt for Match channel 3*/
TIM_CR0_INT =4, /*!< interrupt for Capture channel 0*/
TIM_CR1_INT =5, /*!< interrupt for Capture channel 1*/
TIM_CR2_INT =6, /*!< interrupt for Capture channel 1*/
TIM_CR3_INT =7 /*!< interrupt for Capture channel 1*/
}TIM_INT_TYPE;
/** @brief Timer/counter operating mode */
typedef enum
{
TIM_TIMER_MODE = 0, /*!< Timer mode */
TIM_COUNTER_RISING_MODE, /*!< Counter rising mode */
TIM_COUNTER_FALLING_MODE, /*!< Counter falling mode */
TIM_COUNTER_ANY_MODE /*!< Counter on both edges */
} TIM_MODE_OPT;
/** @brief Timer/Counter prescale option */
typedef enum
{
TIM_PRESCALE_TICKVAL = 0, /*!< Prescale in absolute value */
TIM_PRESCALE_USVAL /*!< Prescale in microsecond value */
} TIM_PRESCALE_OPT;
/** @brief Counter input option */
typedef enum
{
TIM_COUNTER_INCAP0 = 0, /*!< CAPn.0 input pin for TIMERn */
TIM_COUNTER_INCAP1, /*!< CAPn.1 input pin for TIMERn */
TIM_COUNTER_INCAP2, /*!< CAPn.2 input pin for TIMERn */
TIM_COUNTER_INCAP3 /*!< CAPn.3 input pin for TIMERn */
} TIM_COUNTER_INPUT_OPT;
/** @brief Timer/Counter external match option */
typedef enum
{
TIM_EXTMATCH_NOTHING = 0, /*!< Do nothing for external output pin if match */
TIM_EXTMATCH_LOW, /*!< Force external output pin to low if match */
TIM_EXTMATCH_HIGH, /*!< Force external output pin to high if match */
TIM_EXTMATCH_TOGGLE /*!< Toggle external output pin if match */
}TIM_EXTMATCH_OPT;
/** @brief Timer/counter capture mode options */
typedef enum {
TIM_CAPTURE_NONE = 0, /*!< No Capture */
TIM_CAPTURE_RISING, /*!< Rising capture mode */
TIM_CAPTURE_FALLING, /*!< Falling capture mode */
TIM_CAPTURE_ANY /*!< On both edges */
} TIM_CAP_MODE_OPT;
/***********************************************************************
* @brief Timer structure definitions
**********************************************************************/
/** @brief Configuration structure in TIMER mode */
typedef struct
{
uint8_t PrescaleOption; /**< Timer Prescale option, should be:
- TIM_PRESCALE_TICKVAL: Prescale in absolute value
- TIM_PRESCALE_USVAL: Prescale in microsecond value
*/
uint8_t Reserved[3]; /**< Reserved */
uint32_t PrescaleValue; /**< Prescale value */
} TIM_TIMERCFG_Type;
/** @brief Configuration structure in COUNTER mode */
typedef struct {
uint8_t CounterOption; /**< Counter Option, should be:
- TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn
- TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn
*/
uint8_t CountInputSelect;
uint8_t Reserved[2];
} TIM_COUNTERCFG_Type;
/** @brief Match channel configuration structure */
typedef struct {
uint8_t MatchChannel; /**< Match channel, should be in range
from 0..3 */
uint8_t IntOnMatch; /**< Interrupt On match, should be:
- ENABLE: Enable this function.
- DISABLE: Disable this function.
*/
uint8_t StopOnMatch; /**< Stop On match, should be:
- ENABLE: Enable this function.
- DISABLE: Disable this function.
*/
uint8_t ResetOnMatch; /**< Reset On match, should be:
- ENABLE: Enable this function.
- DISABLE: Disable this function.
*/
uint8_t ExtMatchOutputType; /**< External Match Output type, should be:
- TIM_EXTMATCH_NOTHING: Do nothing for external output pin if match
- TIM_EXTMATCH_LOW: Force external output pin to low if match
- TIM_EXTMATCH_HIGH: Force external output pin to high if match
- TIM_EXTMATCH_TOGGLE: Toggle external output pin if match.
*/
uint8_t Reserved[3]; /** Reserved */
uint32_t MatchValue; /** Match value */
} TIM_MATCHCFG_Type;
/** @brief Capture Input configuration structure */
typedef struct {
uint8_t CaptureChannel; /**< Capture channel, should be in range
from 0..1 */
uint8_t RisingEdge; /**< caption rising edge, should be:
- ENABLE: Enable rising edge.
- DISABLE: Disable this function.
*/
uint8_t FallingEdge; /**< caption falling edge, should be:
- ENABLE: Enable falling edge.
- DISABLE: Disable this function.
*/
uint8_t IntOnCaption; /**< Interrupt On caption, should be:
- ENABLE: Enable interrupt function.
- DISABLE: Disable this function.
*/
} TIM_CAPTURECFG_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup TIMER_Public_Functions TIMER Public Functions
* @{
*/
/* Init/DeInit TIM functions -----------*/
void TIM_Init(LPC_TIMERn_Type *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct);
void TIM_DeInit(LPC_TIMERn_Type *TIMx);
/* TIM interrupt functions -------------*/
void TIM_ClearIntPending(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag);
void TIM_ClearIntCapturePending(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag);
FlagStatus TIM_GetIntStatus(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag);
FlagStatus TIM_GetIntCaptureStatus(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag);
/* TIM configuration functions --------*/
void TIM_ConfigStructInit(TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct);
void TIM_ConfigMatch(LPC_TIMERn_Type *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct);
void TIM_UpdateMatchValue(LPC_TIMERn_Type *TIMx,uint8_t MatchChannel, uint32_t MatchValue);
void TIM_SetMatchExt(LPC_TIMERn_Type *TIMx,TIM_EXTMATCH_OPT ext_match );
void TIM_ConfigCapture(LPC_TIMERn_Type *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct);
void TIM_Cmd(LPC_TIMERn_Type *TIMx, FunctionalState NewState);
uint32_t TIM_GetCaptureValue(LPC_TIMERn_Type *TIMx, TIM_COUNTER_INPUT_OPT CaptureChannel);
void TIM_ResetCounter(LPC_TIMERn_Type *TIMx);
void TIM_Waitus(uint32_t time);
void TIM_Waitms(uint32_t time);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __lpc43xx_TIMER_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_uart.h
+683
View File
@@ -0,0 +1,683 @@
/**********************************************************************
* $Id$ lpc43xx_uart.h 2011-06-02
*//**
* @file lpc43xx_uart.h
* @brief Contains all macro definitions and function prototypes
* support for UART firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup UART UART
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef __lpc43xx_UART_H
#define __lpc43xx_UART_H
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup UART_Public_Macros UART Public Macros
* @{
*/
/** UART time-out definitions in case of using Read() and Write function
* with Blocking Flag mode
*/
#define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL)
/**
* @}
*/
/* Private Macros ------------------------------------------------------------- */
/** @defgroup UART_Private_Macros UART Private Macros
* @{
*/
/* Accepted Error baud rate value (in percent unit) */
#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Receiver Buffer Register
**********************************************************************/
#define UART_RBR_MASKBIT ((uint8_t)0xFF) /*!< UART Received Buffer mask bit (8 bits) */
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Transmit Holding Register
**********************************************************************/
#define UART_THR_MASKBIT ((uint8_t)0xFF) /*!< UART Transmit Holding mask bit (8 bits) */
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Divisor Latch LSB register
**********************************************************************/
#define UART_LOAD_DLL(div) ((div) & 0xFF) /**< Macro for loading least significant halfs of divisors */
#define UART_DLL_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch LSB bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Divisor Latch MSB register
**********************************************************************/
#define UART_DLM_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch MSB bit mask */
#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /**< Macro for loading most significant halfs of divisors */
/*********************************************************************//**
* Macro defines for Macro defines for UART interrupt enable register
**********************************************************************/
#define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) /*!< RBR Interrupt enable*/
#define UART_IER_THREINT_EN ((uint32_t)(1<<1)) /*!< THR Interrupt enable*/
#define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) /*!< RX line status interrupt enable*/
#define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) /*!< Modem status interrupt enable */
#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) /*!< CTS1 signal transition interrupt enable */
#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) /*!< Enables the end of auto-baud interrupt */
#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) /*!< Enables the auto-baud time-out interrupt */
#define UART_IER_BITMASK ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */
#define UART1_IER_BITMASK ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART interrupt identification register
**********************************************************************/
#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) /*!<Interrupt Status - Active low */
#define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /*!<Interrupt identification: Receive line status*/
#define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /*!<Interrupt identification: Receive data available*/
#define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /*!<Interrupt identification: Character time-out indicator*/
#define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) /*!<Interrupt identification: THRE interrupt*/
#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /*!<Interrupt identification: Modem interrupt*/
#define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /*!<Interrupt identification: Interrupt ID mask */
#define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /*!<These bits are equivalent to UnFCR[0] */
#define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) /*!< End of auto-baud interrupt */
#define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) /*!< Auto-baud time-out interrupt */
#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /*!< UART interrupt identification register bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART FIFO control register
**********************************************************************/
#define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) /*!< UART FIFO enable */
#define UART_FCR_RX_RS ((uint8_t)(1<<1)) /*!< UART FIFO RX reset */
#define UART_FCR_TX_RS ((uint8_t)(1<<2)) /*!< UART FIFO TX reset */
#define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) /*!< UART DMA mode selection */
#define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /*!< UART FIFO trigger level 0: 1 character */
#define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) /*!< UART FIFO trigger level 1: 4 character */
#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /*!< UART FIFO trigger level 2: 8 character */
#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /*!< UART FIFO trigger level 3: 14 character */
#define UART_FCR_BITMASK ((uint8_t)(0xCF)) /*!< UART FIFO control bit mask */
#define UART_TX_FIFO_SIZE (16)
/*********************************************************************//**
* Macro defines for Macro defines for UART line control register
**********************************************************************/
#define UART_LCR_WLEN5 ((uint8_t)(0)) /*!< UART 5 bit data mode */
#define UART_LCR_WLEN6 ((uint8_t)(1<<0)) /*!< UART 6 bit data mode */
#define UART_LCR_WLEN7 ((uint8_t)(2<<0)) /*!< UART 7 bit data mode */
#define UART_LCR_WLEN8 ((uint8_t)(3<<0)) /*!< UART 8 bit data mode */
#define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) /*!< UART Two Stop Bits Select */
#define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) /*!< UART Parity Enable */
#define UART_LCR_PARITY_ODD ((uint8_t)(0)) /*!< UART Odd Parity Select */
#define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) /*!< UART Even Parity Select */
#define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) /*!< UART force 1 stick parity */
#define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) /*!< UART force 0 stick parity */
#define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) /*!< UART Transmission Break enable */
#define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) /*!< UART Divisor Latches Access bit enable */
#define UART_LCR_BITMASK ((uint8_t)(0xFF)) /*!< UART line control bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART1 Modem Control Register
**********************************************************************/
#define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) /*!< Source for modem output pin DTR */
#define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) /*!< Source for modem output pin RTS */
#define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) /*!< Loop back mode select */
#define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) /*!< Enable Auto RTS flow-control */
#define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) /*!< Enable Auto CTS flow-control */
#define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) /*!< UART1 bit mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART line status register
**********************************************************************/
#define UART_LSR_RDR ((uint8_t)(1<<0)) /*!<Line status register: Receive data ready*/
#define UART_LSR_OE ((uint8_t)(1<<1)) /*!<Line status register: Overrun error*/
#define UART_LSR_PE ((uint8_t)(1<<2)) /*!<Line status register: Parity error*/
#define UART_LSR_FE ((uint8_t)(1<<3)) /*!<Line status register: Framing error*/
#define UART_LSR_BI ((uint8_t)(1<<4)) /*!<Line status register: Break interrupt*/
#define UART_LSR_THRE ((uint8_t)(1<<5)) /*!<Line status register: Transmit holding register empty*/
#define UART_LSR_TEMT ((uint8_t)(1<<6)) /*!<Line status register: Transmitter empty*/
#define UART_LSR_RXFE ((uint8_t)(1<<7)) /*!<Error in RX FIFO*/
#define UART_LSR_BITMASK ((uint8_t)(0xFF)) /*!<UART Line status bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART Modem (UART1 only) status register
**********************************************************************/
#define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) /*!< Set upon state change of input CTS */
#define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) /*!< Set upon state change of input DSR */
#define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) /*!< Set upon low to high transition of input RI */
#define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) /*!< Set upon state change of input DCD */
#define UART1_MSR_CTS ((uint8_t)(1<<4)) /*!< Clear To Send State */
#define UART1_MSR_DSR ((uint8_t)(1<<5)) /*!< Data Set Ready State */
#define UART1_MSR_RI ((uint8_t)(1<<6)) /*!< Ring Indicator State */
#define UART1_MSR_DCD ((uint8_t)(1<<7)) /*!< Data Carrier Detect State */
#define UART1_MSR_BITMASK ((uint8_t)(0xFF)) /*!< MSR register bit-mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART Scratch Pad Register
**********************************************************************/
#define UART_SCR_BIMASK ((uint8_t)(0xFF)) /*!< UART Scratch Pad bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART Auto baudrate control register
**********************************************************************/
#define UART_ACR_START ((uint32_t)(1<<0)) /**< UART Auto-baud start */
#define UART_ACR_MODE ((uint32_t)(1<<1)) /**< UART Auto baudrate Mode 1 */
#define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) /**< UART Auto baudrate restart */
#define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) /**< UART End of auto-baud interrupt clear */
#define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) /**< UART Auto-baud time-out interrupt clear */
#define UART_ACR_BITMASK ((uint32_t)(0x307)) /**< UART Auto Baudrate register bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART IrDA control register
**********************************************************************/
#define UART_ICR_IRDAEN ((uint32_t)(1<<0)) /**< IrDA mode enable */
#define UART_ICR_IRDAINV ((uint32_t)(1<<1)) /**< IrDA serial input inverted */
#define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) /**< IrDA fixed pulse width mode */
#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */
#define UART_ICR_BITMASK ((uint32_t)(0x3F)) /*!< UART IRDA bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART half duplex register
**********************************************************************/
#define UART_HDEN_HDEN ((uint32_t)(1<<0)) /**< enable half-duplex mode*/
/*********************************************************************//**
* Macro defines for Macro defines for UART smart card interface control register
**********************************************************************/
#define UART_SCICTRL_SCIEN ((uint32_t)(1<<0)) /**< enable asynchronous half-duplex smart card interface*/
#define UART_SCICTRL_NACKDIS ((uint32_t)(1<<1)) /**< NACK response is inhibited*/
#define UART_SCICTRL_PROTSEL_T1 ((uint32_t)(1<<2)) /**< ISO7816-3 protocol T1 is selected*/
#define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5)) /**< number of retransmission*/
#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)((n&0xFF)<<8)) /**< Extra guard time*/
/*********************************************************************//**
* Macro defines for Macro defines for UART synchronous control register
**********************************************************************/
#define UART_SYNCCTRL_SYNC ((uint32_t)(1<<0)) /**< enable synchronous mode*/
#define UART_SYNCCTRL_CSRC_MASTER ((uint32_t)(1<<1)) /**< synchronous master mode*/
#define UART_SYNCCTRL_FES ((uint32_t)(1<<2)) /**< sample on falling edge*/
#define UART_SYNCCTRL_TSBYPASS ((uint32_t)(1<<3)) /**< to be defined*/
#define UART_SYNCCTRL_CSCEN ((uint32_t)(1<<4)) /**< continuous running clock enable (master mode only)*/
#define UART_SYNCCTRL_STARTSTOPDISABLE ((uint32_t)(1<<5)) /**< do not send start/stop bit*/
#define UART_SYNCCTRL_CCCLR ((uint32_t)(1<<6)) /**< stop continuous clock*/
/*********************************************************************//**
* Macro defines for Macro defines for UART Fractional divider register
**********************************************************************/
#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /**< Baud-rate generation pre-scaler divisor */
#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /**< Baud-rate pre-scaler multiplier value */
#define UART_FDR_BITMASK ((uint32_t)(0xFF)) /**< UART Fractional Divider register bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART Tx Enable register
**********************************************************************/
#define UART1_TER_TXEN ((uint8_t)(1<<7)) /*!< Transmit enable bit */
#define UART1_TER_BITMASK ((uint8_t)(0x80)) /**< UART Transmit Enable Register bit mask */
#define UART0_2_3_TER_TXEN ((uint8_t)(1<<0)) /*!< Transmit enable bit */
#define UART0_2_3_TER_BITMASK ((uint8_t)(0x01)) /**< UART Transmit Enable Register bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART1 RS485 Control register
**********************************************************************/
#define UART_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM)
is disabled */
#define UART_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) /*!< The receiver is disabled */
#define UART_RS485CTRL_AADEN ((uint32_t)(1<<2)) /*!< Auto Address Detect (AAD) is enabled */
#define UART_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) /*!< If direction control is enabled
(bit DCTRL = 1), pin DTR is used for direction control */
#define UART_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) /*!< Enable Auto Direction Control */
#define UART_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) /*!< This bit reverses the polarity of the direction
control signal on the RTS (or DTR) pin. The direction control pin
will be driven to logic "1" when the transmitter has data to be sent */
#define UART_RS485CTRL_BITMASK ((uint32_t)(0x3F)) /**< RS485 control bit-mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART1 RS-485 Address Match register
**********************************************************************/
#define UART_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART1 RS-485 Delay value register
**********************************************************************/
/* Macro defines for UART1 RS-485 Delay value register */
#define UART_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART FIFO Level register
**********************************************************************/
#define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) /**< Reflects the current level of the UART receiver FIFO */
#define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) /**< Reflects the current level of the UART transmitter FIFO */
#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /**< UART FIFO Level Register bit mask */
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/** Macro to check the input UART_DATABIT parameters */
#define PARAM_UART_DATABIT(databit) ((databit==UART_DATABIT_5) || (databit==UART_DATABIT_6)\
|| (databit==UART_DATABIT_7) || (databit==UART_DATABIT_8))
/** Macro to check the input UART_STOPBIT parameters */
#define PARAM_UART_STOPBIT(stopbit) ((stopbit==UART_STOPBIT_1) || (stopbit==UART_STOPBIT_2))
/** Macro to check the input UART_PARITY parameters */
#define PARAM_UART_PARITY(parity) ((parity==UART_PARITY_NONE) || (parity==UART_PARITY_ODD) \
|| (parity==UART_PARITY_EVEN) || (parity==UART_PARITY_SP_1) \
|| (parity==UART_PARITY_SP_0))
/** Macro to check the input UART_FIFO parameters */
#define PARAM_UART_FIFO_LEVEL(fifo) ((fifo==UART_FIFO_TRGLEV0) \
|| (fifo==UART_FIFO_TRGLEV1) || (fifo==UART_FIFO_TRGLEV2) \
|| (fifo==UART_FIFO_TRGLEV3))
/** Macro to check the input UART_INTCFG parameters */
#define PARAM_UART_INTCFG(IntCfg) ((IntCfg==UART_INTCFG_RBR) || (IntCfg==UART_INTCFG_THRE) \
|| (IntCfg==UART_INTCFG_RLS) || (IntCfg==UART_INTCFG_ABEO) \
|| (IntCfg==UART_INTCFG_ABTO))
/** Macro to check the input UART1_INTCFG parameters - expansion input parameter for UART1 */
#define PARAM_UART1_INTCFG(IntCfg) ((IntCfg==UART1_INTCFG_MS) || (IntCfg==UART1_INTCFG_CTS))
/** Macro to check the input UART_AUTOBAUD_MODE parameters */
#define PARAM_UART_AUTOBAUD_MODE(ABmode) ((ABmode==UART_AUTOBAUD_MODE0) || (ABmode==UART_AUTOBAUD_MODE1))
/** Macro to check the input UART_AUTOBAUD_INTSTAT parameters */
#define PARAM_UART_AUTOBAUD_INTSTAT(ABIntStat) ((ABIntStat==UART_AUTOBAUD_INTSTAT_ABEO) || \
(ABIntStat==UART_AUTOBAUD_INTSTAT_ABTO))
/** Macro to check the input UART_IrDA_PULSEDIV parameters */
#define PARAM_UART_IrDA_PULSEDIV(PulseDiv) ((PulseDiv==UART_IrDA_PULSEDIV2) || (PulseDiv==UART_IrDA_PULSEDIV4) \
|| (PulseDiv==UART_IrDA_PULSEDIV8) || (PulseDiv==UART_IrDA_PULSEDIV16) \
|| (PulseDiv==UART_IrDA_PULSEDIV32) || (PulseDiv==UART_IrDA_PULSEDIV64) \
|| (PulseDiv==UART_IrDA_PULSEDIV128) || (PulseDiv==UART_IrDA_PULSEDIV256))
/* Macro to check the input UART1_SignalState parameters */
#define PARAM_UART1_SIGNALSTATE(x) ((x==INACTIVE) || (x==ACTIVE))
/** Macro to check the input PARAM_UART1_MODEM_PIN parameters */
#define PARAM_UART1_MODEM_PIN(x) ((x==UART1_MODEM_PIN_DTR) || (x==UART1_MODEM_PIN_RTS))
/** Macro to check the input PARAM_UART1_MODEM_MODE parameters */
#define PARAM_UART1_MODEM_MODE(x) ((x==UART1_MODEM_MODE_LOOPBACK) || (x==UART1_MODEM_MODE_AUTO_RTS) \
|| (x==UART1_MODEM_MODE_AUTO_CTS))
/** Macro to check the direction control pin type */
#define PARAM_UART_RS485_DIRCTRL_PIN(x) ((x==UART_RS485_DIRCTRL_RTS) || (x==UART_RS485_DIRCTRL_DTR)|| (x==UART_RS485_DIRCTRL_DIR))
/* Macro to determine if it is valid UART port number */
#define PARAM_UARTx(x) ((((uint32_t *)x)==((uint32_t *)LPC_USART0)) \
|| (((uint32_t *)x)==((uint32_t *)LPC_UART1)) \
|| (((uint32_t *)x)==((uint32_t *)LPC_USART2)) \
|| (((uint32_t *)x)==((uint32_t *)LPC_USART3)))
#define PARAM_UART_IrDA(x) (((uint32_t *)x)==((uint32_t *)LPC_USART3))
#define PARAM_UART1_MODEM(x) (((uint32_t *)x)==((uint32_t *)LPC_UART1))
/** Macro to check the input value for UART_RS485_CFG_MATCHADDRVALUE parameter */
#define PARAM_UART_RS485_CFG_MATCHADDRVALUE(x) ((x<0xFF))
/** Macro to check the input value for UART_RS485_CFG_DELAYVALUE parameter */
#define PARAM_UART_RS485_CFG_DELAYVALUE(x) ((x<0xFF))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup UART_Public_Types UART Public Types
* @{
*/
/***********************************************************************
* @brief UART enumeration
**********************************************************************/
/**
* @brief UART Databit type definitions
*/
typedef enum {
UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */
UART_DATABIT_6, /*!< UART 6 bit data mode */
UART_DATABIT_7, /*!< UART 7 bit data mode */
UART_DATABIT_8 /*!< UART 8 bit data mode */
} UART_DATABIT_Type;
/**
* @brief UART Stop bit type definitions
*/
typedef enum {
UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */
UART_STOPBIT_2 /*!< UART Two Stop Bits Select */
} UART_STOPBIT_Type;
/**
* @brief UART Parity type definitions
*/
typedef enum {
UART_PARITY_NONE = 0, /*!< No parity */
UART_PARITY_ODD, /*!< Odd parity */
UART_PARITY_EVEN, /*!< Even parity */
UART_PARITY_SP_1, /*!< Forced "1" stick parity */
UART_PARITY_SP_0 /*!< Forced "0" stick parity */
} UART_PARITY_Type;
/**
* @brief FIFO Level type definitions
*/
typedef enum {
UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */
UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */
UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */
UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */
} UART_FITO_LEVEL_Type;
/********************************************************************//**
* @brief UART Interrupt Type definitions
**********************************************************************/
typedef enum {
UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/
UART_INTCFG_THRE, /*!< THR Interrupt enable*/
UART_INTCFG_RLS, /*!< RX line status interrupt enable*/
UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */
UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */
UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */
UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */
} UART_INT_Type;
/**
* @brief UART Line Status Type definition
*/
typedef enum {
UART_LINESTAT_RDR = UART_LSR_RDR, /*!<Line status register: Receive data ready*/
UART_LINESTAT_OE = UART_LSR_OE, /*!<Line status register: Overrun error*/
UART_LINESTAT_PE = UART_LSR_PE, /*!<Line status register: Parity error*/
UART_LINESTAT_FE = UART_LSR_FE, /*!<Line status register: Framing error*/
UART_LINESTAT_BI = UART_LSR_BI, /*!<Line status register: Break interrupt*/
UART_LINESTAT_THRE = UART_LSR_THRE, /*!<Line status register: Transmit holding register empty*/
UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!<Line status register: Transmitter empty*/
UART_LINESTAT_RXFE = UART_LSR_RXFE /*!<Error in RX FIFO*/
} UART_LS_Type;
/**
* @brief UART Auto-baudrate mode type definition
*/
typedef enum {
UART_AUTOBAUD_MODE0 = 0, /**< UART Auto baudrate Mode 0 */
UART_AUTOBAUD_MODE1 /**< UART Auto baudrate Mode 1 */
} UART_AB_MODE_Type;
/**
* @brief Auto Baudrate mode configuration type definition
*/
typedef struct {
UART_AB_MODE_Type ABMode; /**< Autobaudrate mode */
FunctionalState AutoRestart; /**< Auto Restart state */
} UART_AB_CFG_Type;
/**
* @brief UART End of Auto-baudrate type definition
*/
typedef enum {
UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /**< UART End of auto-baud interrupt */
UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /**< UART Auto-baud time-out interrupt */
}UART_ABEO_Type;
/**
* UART IrDA Control type Definition
*/
typedef enum {
UART_IrDA_PULSEDIV2 = 0, /**< Pulse width = 2 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV4, /**< Pulse width = 4 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV8, /**< Pulse width = 8 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV16, /**< Pulse width = 16 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV32, /**< Pulse width = 32 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV64, /**< Pulse width = 64 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV128, /**< Pulse width = 128 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV256 /**< Pulse width = 256 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
} UART_IrDA_PULSE_Type;
/********************************************************************//**
* @brief UART1 Full modem - Signal states definition
**********************************************************************/
typedef enum {
INACTIVE = 0, /* In-active state */
ACTIVE = !INACTIVE /* Active state */
}UART1_SignalState;
/**
* @brief UART modem status type definition
*/
typedef enum {
UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */
UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */
UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */
UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */
UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /*!< Clear To Send State */
UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /*!< Data Set Ready State */
UART1_MODEM_STAT_RI = UART1_MSR_RI, /*!< Ring Indicator State */
UART1_MODEM_STAT_DCD = UART1_MSR_DCD /*!< Data Carrier Detect State */
} UART_MODEM_STAT_type;
/**
* @brief Modem output pin type definition
*/
typedef enum {
UART1_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */
UART1_MODEM_PIN_RTS /*!< Source for modem output pin RTS */
} UART_MODEM_PIN_Type;
/**
* @brief UART Modem mode type definition
*/
typedef enum {
UART1_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */
UART1_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */
UART1_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */
} UART_MODEM_MODE_Type;
/**
* @brief UART Direction Control Pin type definition
*/
typedef enum {
UART_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */
UART_RS485_DIRCTRL_DTR, /**< Pin DTR is used for direction control */
UART_RS485_DIRCTRL_DIR /**< Pin DIR is used for direction control */
} UART_RS485_DIRCTRL_PIN_Type;
/********************************************************************//**
* @brief UART Configuration Structure definition
**********************************************************************/
typedef struct {
uint32_t Baud_rate; /**< UART baud rate */
UART_PARITY_Type Parity; /**< Parity selection, should be:
- UART_PARITY_NONE: No parity
- UART_PARITY_ODD: Odd parity
- UART_PARITY_EVEN: Even parity
- UART_PARITY_SP_1: Forced "1" stick parity
- UART_PARITY_SP_0: Forced "0" stick parity
*/
UART_DATABIT_Type Databits; /**< Number of data bits, should be:
- UART_DATABIT_5: UART 5 bit data mode
- UART_DATABIT_6: UART 6 bit data mode
- UART_DATABIT_7: UART 7 bit data mode
- UART_DATABIT_8: UART 8 bit data mode
*/
UART_STOPBIT_Type Stopbits; /**< Number of stop bits, should be:
- UART_STOPBIT_1: UART 1 Stop Bits Select
- UART_STOPBIT_2: UART 2 Stop Bits Select
*/
uint32_t Clock_Speed; // Set to 0 to try to get it from clock routines
} UART_CFG_Type;
/********************************************************************//**
* @brief UART FIFO Configuration Structure definition
**********************************************************************/
typedef struct {
FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be:
- ENABLE: Reset Rx FIFO in UART
- DISABLE: Do not reset Rx FIFO in UART
*/
FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be:
- ENABLE: Reset Tx FIFO in UART
- DISABLE: Do not reset Tx FIFO in UART
*/
FunctionalState FIFO_DMAMode; /**< DMA mode, should be:
- ENABLE: Enable DMA mode in UART
- DISABLE: Disable DMA mode in UART
*/
UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be:
- UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
- UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
- UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
- UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
*/
} UART_FIFO_CFG_Type;
/********************************************************************//**
* @brief UART1 Full modem - RS485 Control configuration type
**********************************************************************/
typedef struct {
FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:
- ENABLE: Enable this function.
- DISABLE: Disable this function. */
FunctionalState Rx_State; /*!< Receiver State:
- ENABLE: Enable Receiver.
- DISABLE: Disable Receiver. */
FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state:
- ENABLE: ENABLE this function.
- DISABLE: Disable this function. */
FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State:
- ENABLE: Enable this function.
- DISABLE: Disable this function. */
UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state:
- UART1_RS485_DIRCTRL_RTS:
pin RTS is used for direction control.
- UART1_RS485_DIRCTRL_DTR:
pin DTR is used for direction control. */
SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on
the RTS (or DTR) pin:
- RESET: The direction control pin will be driven
to logic "0" when the transmitter has data to be sent.
- SET: The direction control pin will be driven
to logic "1" when the transmitter has data to be sent. */
uint8_t MatchAddrValue; /*!< address match value for RS-485/EIA-485 mode, 8-bit long */
uint8_t DelayValue; /*!< delay time is in periods of the baud clock, 8-bit long */
} UART_RS485_CTRLCFG_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup UART_Public_Functions UART Public Functions
* @{
*/
/* UART Init/DeInit functions --------------------------------------------------*/
void UART_Init(LPC_USARTn_Type *UARTx, UART_CFG_Type *UART_ConfigStruct);
void UART_DeInit(LPC_USARTn_Type* UARTx);
void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct);
/* UART Send/Receive functions -------------------------------------------------*/
void UART_SendByte(LPC_USARTn_Type* UARTx, uint8_t Data);
uint8_t UART_ReceiveByte(LPC_USARTn_Type* UARTx);
uint32_t UART_Send(LPC_USARTn_Type *UARTx, uint8_t *txbuf,
uint32_t buflen, TRANSFER_BLOCK_Type flag);
uint32_t UART_Receive(LPC_USARTn_Type *UARTx, uint8_t *rxbuf, \
uint32_t buflen, TRANSFER_BLOCK_Type flag);
/* UART FIFO functions ----------------------------------------------------------*/
void UART_FIFOConfig(LPC_USARTn_Type *UARTx, UART_FIFO_CFG_Type *FIFOCfg);
void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct);
/* UART operate functions -------------------------------------------------------*/
void UART_IntConfig(LPC_USARTn_Type *UARTx, UART_INT_Type UARTIntCfg, \
FunctionalState NewState);
void UART_ABCmd(LPC_USARTn_Type *UARTx, UART_AB_CFG_Type *ABConfigStruct, \
FunctionalState NewState);
void UART_TxCmd(LPC_USARTn_Type *UARTx, FunctionalState NewState);
uint8_t UART_GetLineStatus(LPC_USARTn_Type* UARTx);
FlagStatus UART_CheckBusy(LPC_USARTn_Type *UARTx);
void UART_ForceBreak(LPC_USARTn_Type* UARTx);
/* UART1 FullModem functions ----------------------------------------------------*/
void UART_FullModemForcePinState(LPC_UART1_Type *UARTx, UART_MODEM_PIN_Type Pin, \
UART1_SignalState NewState);
void UART_FullModemConfigMode(LPC_UART1_Type *UARTx, UART_MODEM_MODE_Type Mode, \
FunctionalState NewState);
uint8_t UART_FullModemGetStatus(LPC_UART1_Type *UARTx);
/* UART RS485 functions ----------------------------------------------------------*/
void UART_RS485Config(LPC_USARTn_Type *UARTx, \
UART_RS485_CTRLCFG_Type *RS485ConfigStruct);
void UART_RS485ReceiverCmd(LPC_USARTn_Type *UARTx, FunctionalState NewState);
void UART_RS485SendSlvAddr(LPC_USARTn_Type *UARTx, uint8_t SlvAddr);
uint32_t UART_RS485SendData(LPC_USARTn_Type *UARTx, uint8_t *pData, uint32_t size);
/* UART IrDA functions-------------------------------------------------------------*/
void UART_IrDAInvtInputCmd(LPC_USARTn_Type* UARTx, FunctionalState NewState);
void UART_IrDACmd(LPC_USARTn_Type* UARTx, FunctionalState NewState);
void UART_IrDAPulseDivConfig(LPC_USARTn_Type *UARTx, UART_IrDA_PULSE_Type PulseDiv);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __lpc43xx_UART_H */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_wwdt.h
+182
View File
@@ -0,0 +1,182 @@
/**********************************************************************
* $Id$ lpc43xx_wwdt.h 2011-06-02
*//**
* @file lpc43xx_wwdt.h
* @brief Contains all macro definitions and function prototypes
* support for WWDT firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors�
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup WWDT WWDT (Windowed WatchDog Timer)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_WWDT_H_
#define lpc43xx_WWDT_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup WWDT_Public_Macros WWDT Public Macros
* @{
*/
/** WDT oscillator frequency value */
#define WDT_OSC (12000000UL) /* WWDT uses IRC clock */
/**
* @}
*/
/* Private Macros ------------------------------------------------------------- */
/** @defgroup WWDT_Private_Macros WWDT Private Macros
* @{
*/
// time is calculated by usec
#define WDT_GET_FROM_USEC(time) ((time*10)/((WWDT_US_INDEX *10 * 4)/WDT_OSC))
#define WDT_GET_USEC(counter) ((counter * ((WWDT_US_INDEX *10 * 4)/WDT_OSC))/10)
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/** WWDT interrupt enable bit */
#define WWDT_WDMOD_WDEN ((uint32_t)(1<<0))
/** WWDT interrupt enable bit */
#define WWDT_WDMOD_WDRESET ((uint32_t)(1<<1))
/** WWDT time out flag bit */
#define WWDT_WDMOD_WDTOF ((uint32_t)(1<<2))
/** WDT Time Out flag bit */
#define WWDT_WDMOD_WDINT ((uint32_t)(1<<3))
/** WWDT Protect flag bit */
#define WWDT_WDMOD_WDPROTECT ((uint32_t)(1<<4))
/** Define divider index for microsecond ( us ) */
#define WWDT_US_INDEX ((uint32_t)(1000000))
/** WWDT Time out minimum value */
#define WWDT_TIMEOUT_MIN ((uint32_t)(0xFF))
/** WWDT Time out maximum value */
#define WWDT_TIMEOUT_MAX ((uint32_t)(0x00FFFFFF))
/** WWDT Warning minimum value */
#define WWDT_WARNINT_MIN ((uint32_t)(0xFF))
/** WWDT Warning maximum value */
#define WWDT_WARNINT_MAX ((uint32_t)(0x000003FF))
/** WWDT Windowed minimum value */
#define WWDT_WINDOW_MIN ((uint32_t)(0xFF))
/** WWDT Windowed minimum value */
#define WWDT_WINDOW_MAX ((uint32_t)(0x00FFFFFF))
/** WWDT timer constant register mask */
#define WWDT_WDTC_MASK ((uint32_t)(0x00FFFFFF))
/** WWDT warning value register mask */
#define WWDT_WDWARNINT_MASK ((uint32_t)(0x000003FF))
/** WWDT feed sequence register mask */
#define WWDT_WDFEED_MASK ((uint32_t)(0x000000FF))
/** WWDT flag */
#define WWDT_WARNINT_FLAG ((uint8_t)(0))
#define WWDT_TIMEOUT_FLAG ((uint8_t)(1))
/** WWDT mode definitions */
#define WWDT_PROTECT_MODE ((uint8_t)(0))
#define WWDT_RESET_MODE ((uint8_t)(1))
/* WWDT Timer value definition (us) */
#define WWDT_TIMEOUT_USEC_MIN ((uint32_t)(WDT_GET_USEC(WWDT_TIMEOUT_MIN)))//microseconds
#define WWDT_TIMEOUT_USEC_MAX ((uint32_t)(WDT_GET_USEC(WWDT_TIMEOUT_MAX)))
#define WWDT_TIMEWARN_USEC_MIN ((uint32_t)(WDT_GET_USEC(WWDT_WARNINT_MIN)))
#define WWDT_TIMEWARN_USEC_MAX ((uint32_t)(WDT_GET_USEC(WWDT_WARNINT_MAX)))
#define WWDT_TIMEWINDOWED_USEC_MIN ((uint32_t)(WDT_GET_USEC(WWDT_WINDOW_MIN)))
#define WWDT_TIMEWINDOWED_USEC_MAX ((uint32_t)(WDT_GET_USEC(WWDT_WINDOW_MAX)))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup WWDT_Public_Types WWDT Public Types
* @{
*/
/********************************************************************//**
* @brief WWDT structure definitions
**********************************************************************/
typedef struct Wdt_Config
{
uint8_t wdtReset; /**< if ENABLE -> the Reset bit is enabled */
uint8_t wdtProtect; /**< if ENABLE -> the Protect bit is enabled */
uint32_t wdtTmrConst; /**< Set the constant value to timeout the WDT (us) */
uint32_t wdtWarningVal; /**< Set the value to warn the WDT with interrupt (us) */
uint32_t wdtWindowVal; /**< Set a window vaule for WDT (us) */
}st_Wdt_Config;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup WWDT_Public_Functions WWDT Public Functions
* @{
*/
void WWDT_Init(void);
void WWDT_UpdateTimeOut(uint32_t TimeOut);
void WWDT_Feed (void);
void WWDT_SetWarning(uint32_t WarnTime);
void WWDT_SetWindow(uint32_t WindowedTime);
void WWDT_Configure(st_Wdt_Config wdtCfg);
void WWDT_Start(void);
FlagStatus WWDT_GetStatus (uint8_t Status);
void WWDT_ClearStatusFlag (uint8_t flag);
uint32_t WWDT_GetCurrentCount(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_WWDT_H_ */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc_sdmmc.h
+333
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/**************************************************************************//**
* @file lpc_sdmmc.h (SD/MMC common defines)
* @brief Common definitions used with SD/MMC controllers and cards
* @version V1.00
* @date 02. November 2011
*
* @note
* Copyright (C) 2012 NXP Semiconductors. All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors’
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
******************************************************************************/
#ifndef __LPC_SDMMC_H
#define __LPC_SDMMC_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup LPCSDMMC_Definitions Common SDMMC Definitions
*/
/* SD/MMC commands - this matrix shows the command, response types, and
supported card type for that command.
Command Number Resp SD MMC
----------------------- ------ ----- --- ---
Reset (go idle) CMD0 NA x x
Send op condition CMD1 R3 x
All send CID CMD2 R2 x x
Send relative address CMD3 R1 x
Send relative address CMD3 R6 x
Program DSR CMD4 NA x
Select/deselect card CMD7 R1b x
Select/deselect card CMD7 R1 x
Send CSD CMD9 R2 x x
Send CID CMD10 R2 x x
Read data until stop CMD11 R1 x x
Stop transmission CMD12 R1/b x x
Send status CMD13 R1 x x
Go inactive state CMD15 NA x x
Set block length CMD16 R1 x x
Read single block CMD17 R1 x x
Read multiple blocks CMD18 R1 x x
Write data until stop CMD20 R1 x
Setblock count CMD23 R1 x
Write single block CMD24 R1 x x
Write multiple blocks CMD25 R1 x x
Program CID CMD26 R1 x
Program CSD CMD27 R1 x x
Set write protection CMD28 R1b x x
Clear write protection CMD29 R1b x x
Send write protection CMD30 R1 x x
Erase block start CMD32 R1 x
Erase block end CMD33 R1 x
Erase block start CMD35 R1 x
Erase block end CMD36 R1 x
Erase blocks CMD38 R1b x
Fast IO CMD39 R4 x
Go IRQ state CMD40 R5 x
Lock/unlock CMD42 R1b x
Application command CMD55 R1 x
General command CMD56 R1b x
*** SD card application commands - these must be preceded with ***
*** MMC CMD55 application specific command first ***
Set bus width ACMD6 R1 x
Send SD status ACMD13 R1 x
Send number WR blocks ACMD22 R1 x
Set WR block erase cnt ACMD23 R1 x
Send op condition ACMD41 R3 x
Set clear card detect ACMD42 R1 x
Send CSR ACMD51 R1 x */
/** \brief SD/MMC command enumeration value.
*/
typedef enum
{
SDMMC_IDLE, /*!< Put card in idle mode */
MMC_SENDOP_COND, /*!< Send operating condition */
SDMMC_ALL_SEND_CID, /*!< All cards send CID */
SDMMC_SRA, /*!< Set relative address */
MMC_PROGRAM_DSR, /*!< Program DSR */
SDMMC_SELECT_CARD, /*!< Select card */
SDMMC_SEND_CSD, /*!< Send CSD data */
SDMMC_SEND_CID, /*!< Send CID register data (with rel. addr) */
SDMMC_READ_UNTIL_STOP, /*!< Read data until stop */
SDMMC_STOP_XFER, /*!< Stop current transmission */
SDMMC_SSTAT, /*!< Send status */
SDMMC_INACTIVE, /*!< Put card in inactive state */
SDMMC_SET_BLEN, /*!< Set block transfer length */
SDMMC_READ_SINGLE, /*!< Read single block */
SDMMC_READ_MULTIPLE, /*!< Read multiple blocks */
SDMMC_WRITE_UNTIL_STOP, /*!< Write data until stop */
SDMMC_SET_BLOCK_COUNT, /*!< Set block count */
SDMMC_WRITE_SINGLE, /*!< Write single block */
SDMMC_WRITE_MULTIPLE, /*!< Write multiple blocks */
MMC_PROGRAM_CID, /*!< Program CID */
SDMMC_PROGRAM_CSD, /*!< Program CSD */
SDMMC_SET_WR_PROT, /*!< Set write protection */
SDMMC_CLEAR_WR_PROT, /*!< Clear write protection */
SDMMC_SEND_WR_PROT, /*!< Send write protection */
SD_ERASE_BLOCK_START, /*!< Set starting erase block */
SD_ERASE_BLOCK_END, /*!< Set ending erase block */
MMC_ERASE_BLOCK_START, /*!< Set starting erase block */
MMC_ERASE_BLOCK_END, /*!< Set ending erase block */
MMC_ERASE_BLOCKS, /*!< Erase blocks */
MMC_FAST_IO, /*!< Fast IO */
MMC_GO_IRQ_STATE, /*!< Go into IRQ state */
MMC_LOCK_UNLOCK, /*!< Lock/unlock */
SDMMC_APP_CMD, /*!< Application specific command */
SDMMC_GEN_CMD, /*!< General purpose command */
SDMMC_INVALID_CMD /*!< Invalid SDMMC command */
} SDMMC_COMMAND_T;
/** \brief SDMMC application specific commands for SD cards only - these
must be preceded by the SDMMC CMD55 to work correctly.
*/
typedef enum
{
SD_SET_BUS_WIDTH, /*!< Set the SD bus width */
SD_SEND_STATUS, /*!< Send the SD card status */
SD_SEND_WR_BLOCKS, /*!< Send the number of written clocks */
SD_SET_ERASE_COUNT, /*!< Set the number of blocks to pre-erase */
SD_SENDOP_COND, /*!< Send the OCR register (init) */
SD_CLEAR_CARD_DET, /*!< Set or clear the 50K detect pullup */
SD_SEND_SCR, /*!< Send the SD configuration register */
SD_INVALID_APP_CMD /*!< Invalid SD application command */
} SD_APP_CMD_T;
/** \brief Possible SDMMC response types
*/
typedef enum
{
SDMMC_RESPONSE_R1, /*!< Typical status */
SDMMC_RESPONSE_R1B, /*!< Typical status with busy */
SDMMC_RESPONSE_R2, /*!< CID/CSD registers (CMD2 and CMD10) */
SDMMC_RESPONSE_R3, /*!< OCR register (CMD1, ACMD41) */
SDMMC_RESPONSE_R4, /*!< Fast IO response word */
SDMMC_RESPONSE_R5, /*!< Go IRQ state response word */
SDMMC_RESPONSE_R6, /*!< Published RCA response */
SDMMC_RESPONSE_NONE /*!< No response expected */
} SDMMC_RESPONSE_T;
/** \brief Possible SDMMC card state types
*/
typedef enum
{
SDMMC_IDLE_ST = 0, /*!< Idle state */
SDMMC_READY_ST, /*!< Ready state */
SDMMC_IDENT_ST, /*!< Identification State */
SDMMC_STBY_ST, /*!< standby state */
SDMMC_TRAN_ST, /*!< transfer state */
SDMMC_DATA_ST, /*!< Sending-data State */
SDMMC_RCV_ST, /*!< Receive-data State */
SDMMC_PRG_ST, /*!< Programming State */
SDMMC_DIS_ST /*!< Disconnect State */
} SDMMC_STATE_T;
#ifdef __cplusplus
}
#endif
/* Standard MMC commands (3.1) type argument response */
/* class 1 */
#define MMC_GO_IDLE_STATE 0 /* bc */
#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
#define MMC_ALL_SEND_CID 2 /* bcr R2 */
#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
#define MMC_SET_DSR 4 /* bc [31:16] RCA */
#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
#define MMC_SEND_EXT_CSD 8 /* bc R1 */
#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
/* class 2 */
#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
/* class 3 */
#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
/* class 4 */
#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
#define MMC_PROGRAM_CID 26 /* adtc R1 */
#define MMC_PROGRAM_CSD 27 /* adtc R1 */
/* class 6 */
#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
/* class 5 */
#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
#define MMC_ERASE 37 /* ac R1b */
/* class 9 */
#define MMC_FAST_IO 39 /* ac <Complex> R4 */
#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
/* class 7 */
#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
/* class 8 */
#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1b */
/* SD commands type argument response */
/* class 8 */
/* This is basically the same command as for MMC with some quirks. */
#define SD_SEND_RELATIVE_ADDR 3 /* ac R6 */
#define SD_CMD8 8 /* bcr [31:0] OCR R3 */
/* Application commands */
#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R1 (R4) */
#define SD_APP_SEND_SCR 51 /* adtc R1 */
/*
MMC status in R1
Type
e : error bit
s : status bit
r : detected and set for the actual command response
x : detected and set during command execution. the host must poll
the card by sending status command in order to read these bits.
Clear condition
a : according to the card state
b : always related to the previous command. Reception of
a valid command will clear it (with a delay of one command)
c : clear by read
*/
#define R1_OUT_OF_RANGE (1UL<<31) /* er, c */
#define R1_ADDRESS_ERROR (1<<30) /* erx, c */
#define R1_BLOCK_LEN_ERROR (1<<29) /* er, c */
#define R1_ERASE_SEQ_ERROR (1<<28) /* er, c */
#define R1_ERASE_PARAM (1<<27) /* ex, c */
#define R1_WP_VIOLATION (1<<26) /* erx, c */
#define R1_CARD_IS_LOCKED (1<<25) /* sx, a */
#define R1_LOCK_UNLOCK_FAILED (1<<24) /* erx, c */
#define R1_COM_CRC_ERROR (1<<23) /* er, b */
#define R1_ILLEGAL_COMMAND (1<<22) /* er, b */
#define R1_CARD_ECC_FAILED (1<<21) /* ex, c */
#define R1_CC_ERROR (1<<20) /* erx, c */
#define R1_ERROR (1<<19) /* erx, c */
#define R1_UNDERRUN (1<<18) /* ex, c */
#define R1_OVERRUN (1<<17) /* ex, c */
#define R1_CID_CSD_OVERWRITE (1<<16) /* erx, c, CID/CSD overwrite */
#define R1_WP_ERASE_SKIP (1<<15) /* sx, c */
#define R1_CARD_ECC_DISABLED (1<<14) /* sx, a */
#define R1_ERASE_RESET (1<<13) /* sr, c */
#define R1_STATUS(x) (x & 0xFFFFE000)
#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
#define R1_READY_FOR_DATA (1<<8) /* sx, a */
#define R1_APP_CMD (1<<5) /* sr, c */
#define OCR_ALL_READY (1UL<<31) /* Card Power up status bit */
#define OCR_HC_CCS (1<<30) /* High capacity card */
#define OCR_VOLTAGE_RANGE_MSK 0x00ff8000
#define SD_SEND_IF_ARG 0x000001AA
#define SD_SEND_IF_ECHO_MSK 0x000000FF
#define SD_SEND_IF_RESP 0x000000AA
#define CMD_MASK_RESP (0x3UL<<28)
#define CMD_RESP(r) (((r) & 0x3)<<28)
#define CMD_RESP_R0 (0<<28)
#define CMD_RESP_R1 (1<<28)
#define CMD_RESP_R2 (2<<28)
#define CMD_RESP_R3 (3<<28)
#define CMD_BIT_AUTO_STOP (1<<24)
#define CMD_BIT_APP (1<<23)
#define CMD_BIT_INIT (1<<22)
#define CMD_BIT_BUSY (1<<21)
#define CMD_BIT_LS (1<<20) /* Low speed, used during acquire */
#define CMD_BIT_DATA (1<<19)
#define CMD_BIT_WRITE (1<<18)
#define CMD_BIT_STREAM (1<<17)
#define CMD_MASK_CMD (0xff)
#define CMD_SHIFT_CMD (0)
#define CMD(c,r) ( ((c) & CMD_MASK_CMD) | CMD_RESP((r)) )
#define CMD_IDLE CMD(MMC_GO_IDLE_STATE,0) | CMD_BIT_LS | CMD_BIT_INIT
#define CMD_SD_OP_COND CMD(SD_APP_OP_COND,1) | CMD_BIT_LS | CMD_BIT_APP
#define CMD_SD_SEND_IF_COND CMD(SD_CMD8,1) | CMD_BIT_LS
#define CMD_MMC_OP_COND CMD(MMC_SEND_OP_COND,3) | CMD_BIT_LS | CMD_BIT_INIT
#define CMD_ALL_SEND_CID CMD(MMC_ALL_SEND_CID,2) | CMD_BIT_LS
#define CMD_MMC_SET_RCA CMD(MMC_SET_RELATIVE_ADDR,1) | CMD_BIT_LS
#define CMD_SD_SEND_RCA CMD(SD_SEND_RELATIVE_ADDR,1) | CMD_BIT_LS
#define CMD_SEND_CSD CMD(MMC_SEND_CSD,2) | CMD_BIT_LS
#define CMD_SEND_EXT_CSD CMD(MMC_SEND_EXT_CSD,1) | CMD_BIT_LS | CMD_BIT_DATA
#define CMD_DESELECT_CARD CMD(MMC_SELECT_CARD,0)
#define CMD_SELECT_CARD CMD(MMC_SELECT_CARD,1)
#define CMD_SET_BLOCKLEN CMD(MMC_SET_BLOCKLEN,1)
#define CMD_SEND_STATUS CMD(MMC_SEND_STATUS,1)
#define CMD_READ_SINGLE CMD(MMC_READ_SINGLE_BLOCK,1) | CMD_BIT_DATA
#define CMD_READ_MULTIPLE CMD(MMC_READ_MULTIPLE_BLOCK,1) | CMD_BIT_DATA | CMD_BIT_AUTO_STOP
#define CMD_SD_SET_WIDTH CMD(SD_APP_SET_BUS_WIDTH,1)| CMD_BIT_APP
#define CMD_STOP CMD(MMC_STOP_TRANSMISSION,1) | CMD_BIT_BUSY
#define CMD_WRITE_SINGLE CMD(MMC_WRITE_BLOCK,1) | CMD_BIT_DATA | CMD_BIT_WRITE
#define CMD_WRITE_MULTIPLE CMD(MMC_WRITE_MULTIPLE_BLOCK,1) | CMD_BIT_DATA | CMD_BIT_WRITE | CMD_BIT_AUTO_STOP
#define MMC_SECTOR_SIZE 512
#endif /* end __LPC_SDMMC_H */
/*****************************************************************************
** End Of File
******************************************************************************/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc_types.h
+216
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/**********************************************************************
* $Id$ lpc_types.h 2011-06-02
*//**
* @file lpc_types.h
* @brief Contains the NXP ABL typedefs for C standard types.
* It is intended to be used in ISO C conforming development
* environments and checks for this insofar as it is possible
* to do so.
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors’
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Type group ----------------------------------------------------------- */
/** @defgroup LPC_Types LPC_Types
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC_TYPES_H
#define LPC_TYPES_H
/* Includes ------------------------------------------------------------------- */
#include <stdint.h>
/* Public Types --------------------------------------------------------------- */
/** @defgroup LPC_Types_Public_Types LPC_Types Public Types
* @{
*/
/**
* @brief Boolean Type definition
*/
typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
/**
* @brief Flag Status and Interrupt Flag Status type definition
*/
typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
/**
* @brief Functional State Definition
*/
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
/**
* @ Status type definition
*/
typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
/**
* Read/Write transfer type mode (Block or non-block)
*/
typedef enum
{
NONE_BLOCKING = 0, /**< None Blocking type */
BLOCKING, /**< Blocking type */
} TRANSFER_BLOCK_Type;
/** Pointer to Function returning Void (any number of parameters) */
typedef void (*PFV)();
/** Pointer to Function returning int32_t (any number of parameters) */
typedef int32_t(*PFI)();
/**
* @}
*/
/* Public Macros -------------------------------------------------------------- */
/** @defgroup LPC_Types_Public_Macros LPC_Types Public Macros
* @{
*/
/* _BIT(n) sets the bit at position "n"
* _BIT(n) is intended to be used in "OR" and "AND" expressions:
* e.g., "(_BIT(3) | _BIT(7))".
*/
#undef _BIT
/* Set bit macro */
#define _BIT(n) (1<<(n))
/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
* _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
* e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
*/
#undef _SBF
/* Set bit field macro */
#define _SBF(f,v) ((v)<<(f))
/* _BITMASK constructs a symbol with 'field_width' least significant
* bits set.
* e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
* The symbol is intended to be used to limit the bit field width
* thusly:
* <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
* If "any_expression" results in a value that is larger than can be
* contained in 'x' bits, the bits above 'x - 1' are masked off. When
* used with the _SBF example above, the example would be written:
* a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
* This ensures that the value written to a_reg is no wider than
* 16 bits, and makes the code easier to read and understand.
*/
#undef _BITMASK
/* Bitmask creation macro */
#define _BITMASK(field_width) ( _BIT(field_width) - 1)
/* NULL pointer */
#ifndef NULL
#define NULL ((void*) 0)
#endif
/* Number of elements in an array */
#define NELEMENTS(array) (sizeof (array) / sizeof (array[0]))
/* Static data/function define */
#define STATIC static
/* External data/function define */
#define EXTERN extern
#if !defined(MAX)
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
#if !defined(MIN)
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
/**
* @}
*/
/* Old Type Definition compatibility ------------------------------------------ */
/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types
* @{
*/
/** SMA type for character type */
typedef char CHAR;
/** SMA type for 8 bit unsigned value */
typedef uint8_t UNS_8;
/** SMA type for 8 bit signed value */
typedef int8_t INT_8;
/** SMA type for 16 bit unsigned value */
typedef uint16_t UNS_16;
/** SMA type for 16 bit signed value */
typedef int16_t INT_16;
/** SMA type for 32 bit unsigned value */
typedef uint32_t UNS_32;
/** SMA type for 32 bit signed value */
typedef int32_t INT_32;
/** SMA type for 64 bit signed value */
typedef int64_t INT_64;
/** SMA type for 64 bit unsigned value */
typedef uint64_t UNS_64;
/** 32 bit boolean type */
typedef Bool BOOL_32;
/** 16 bit boolean type */
typedef Bool BOOL_16;
/** 8 bit boolean type */
typedef Bool BOOL_8;
#ifdef __CC_ARM
#define INLINE __inline
#else
#define INLINE inline
#endif
/**
* @}
*/
#endif /* LPC_TYPES_H */
/**
* @}
*/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/sdio.h
+291
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/****************************************************************************************************//**
* @file sdio.h
*
* @status EXPERIMENTAL
*
* @brief Header file for NXP LPC18xx/43xx SDIO driver
*
* @version V1.0
* @date 02. November 2011
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors’
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*
*******************************************************************************************************/
#ifndef __SDIO_H
#define __SDIO_H
/** \defgroup LPCSDMMC_Definitions LPC18xx_43xx SDIO definitions
This file defines common definitions and values used for SDMMC:
- Registers, bitfields, and structures
- Commands and statuses
- States
@{
*/
/** \brief SDIO chained DMA descriptor
*/
typedef struct {
volatile uint32_t des0; /*!< Control and status */
volatile uint32_t des1; /*!< Buffer size(s) */
volatile uint32_t des2; /*!< Buffer address pointer 1 */
volatile uint32_t des3; /*!< Buffer address pointer 2 */
} LPC_SDMMC_DMA_Type;
/** \brief SDIO DMA descriptor control (des0) register defines
*/
#define MCI_DMADES0_OWN (1UL<<31) /*!< DMA owns descriptor bit */
#define MCI_DMADES0_CES (1<<30) /*!< Card Error Summary bit */
#define MCI_DMADES0_ER (1<<5) /*!< End of descriptopr ring bit */
#define MCI_DMADES0_CH (1<<4) /*!< Second address chained bit */
#define MCI_DMADES0_FS (1<<3) /*!< First descriptor bit */
#define MCI_DMADES0_LD (1<<2) /*!< Last descriptor bit */
#define MCI_DMADES0_DIC (1<<1) /*!< Disable interrupt on completion bit */
/** \brief SDIO DMA descriptor size (des1) register defines
*/
#define MCI_DMADES1_BS1(x) (x) /*!< Size of buffer 1 */
#define MCI_DMADES1_BS2(x) ((x) << 13) /*!< Size of buffer 2 */
#define MCI_DMADES1_MAXTR 4096 /*!< Max transfer size per buffer */
/** \brief SD/SDIO/MMC control register defines
*/
#define MCI_CTRL_USE_INT_DMAC (1<<25) /*!< Use internal DMA */
#define MCI_CTRL_ENABLE_OD_PUP (1<<24) /*!< Enable external open-drain pullup */
#define MCI_CTRL_CARDV_B_MASK 0xF00000 /*!< Card regulator-B voltage setting; */
#define MCI_CTRL_CARDV_A_MASK 0xF0000 /*!< Card regulator-A voltage setting; */
#define MCI_CTRL_CEATA_INT_EN (1<<11) /*!< Enable CE-ATA interrupts */
#define MCI_CTRL_SEND_AS_CCSD (1<<10) /*!< Send auto-stop */
#define MCI_CTRL_SEND_CCSD (1<<9) /*!< Send CCSD */
#define MCI_CTRL_ABRT_READ_DATA (1<<8) /*!< Abort read data */
#define MCI_CTRL_SEND_IRQ_RESP (1<<7) /*!< Send auto-IRQ response */
#define MCI_CTRL_READ_WAIT (1<<6) /*!< Assert read-wait for SDIO */
#define MCI_CTRL_DMA_ENABLE (1<<5) /*!< Enable DMA transfer mode */
#define MCI_CTRL_INT_ENABLE (1<<4) /*!< Global interrupt enable */
#define MCI_CTRL_DMA_RESET (1<<2) /*!< Reset internal DMA */
#define MCI_CTRL_FIFO_RESET (1<<1) /*!< Reset data FIFO pointers */
#define MCI_CTRL_RESET (1<<0) /*!< Reset controller */
/** \brief Power Enable register defines
*/
#define MCI_POWER_ENABLE(slot) (1<<(slot)) /*!< Enable slot power signal */
/** \brief Clock divider register defines
*/
#define MCI_CLOCK_DIVIDER(divnum, divby2) ((divby2)<<((divnum) * 8)) /*!< Set slot cklock divider */
/** \brief Clock source register defines
*/
#define MCI_CLKSRC_CLKDIV0 0
#define MCI_CLKSRC_CLKDIV1 1
#define MCI_CLKSRC_CLKDIV2 2
#define MCI_CLKSRC_CLKDIV3 3
#define MCI_CLK_SOURCE(slot, clksrc) ((clksrc)<<((slot) * 2)) /*!< Set slot cklock divider source */
/** \brief Clock Enable register defines
*/
#define MCI_CLKEN_LOW_PWR(slot) (1<<((slot) + 16)) /*!< Enable clock idle for slot */
#define MCI_CLKEN_ENABLE(slot) (1<<(slot)) /*!< Enable slot clock */
/** \brief time-out register defines
*/
#define MCI_TMOUT_DATA(clks) ((clks)<<8) /*!< Data timeout clocks */
#define MCI_TMOUT_DATA_MSK 0xFFFFFF00
#define MCI_TMOUT_RESP(clks) ((clks) & 0xFF) /*!< Response timeout clocks */
#define MCI_TMOUT_RESP_MSK 0xFF
/** \brief card-type register defines
*/
#define MCI_CTYPE_8BIT(slot) (1<<((slot) + 16)) /*!< Enable 4-bit mode */
#define MCI_CTYPE_4BIT(slot) (1<<(slot)) /*!< Enable 8-bit mode */
/** \brief Bus mode register defines
*/
#define MCI_BMOD_PBL1 (0<<8) /*!< Burst length = 1 */
#define MCI_BMOD_PBL4 (1<<8) /*!< Burst length = 4 */
#define MCI_BMOD_PBL8 (2<<8) /*!< Burst length = 8 */
#define MCI_BMOD_PBL16 (3<<8) /*!< Burst length = 16 */
#define MCI_BMOD_PBL32 (4<<8) /*!< Burst length = 32 */
#define MCI_BMOD_PBL64 (5<<8) /*!< Burst length = 64 */
#define MCI_BMOD_PBL128 (6<<8) /*!< Burst length = 128 */
#define MCI_BMOD_PBL256 (7<<8) /*!< Burst length = 256 */
#define MCI_BMOD_DE (1<<7) /*!< Enable internal DMAC */
#define MCI_BMOD_DSL(len) ((len)<<2) /*!< Descriptor skip length */
#define MCI_BMOD_FB (1<<1) /*!< Fixed bursts */
#define MCI_BMOD_SWR (1<<0) /*!< Software reset of internal registers */
/** \brief Interrupt status & mask register defines
*/
#define MCI_INT_SDIO(slot) (1<<(slot)) /*!< Slot specific interrupt enable */
#define MCI_INT_EBE (1<<15) /*!< End-bit error */
#define MCI_INT_ACD (1<<14) /*!< Auto command done */
#define MCI_INT_SBE (1<<13) /*!< Start bit error */
#define MCI_INT_HLE (1<<12) /*!< Hardware locked error */
#define MCI_INT_FRUN (1<<11) /*!< FIFO overrun/underrun error */
#define MCI_INT_HTO (1<<10) /*!< Host data starvation error */
#define MCI_INT_DTO (1<<9) /*!< Data timeout error */
#define MCI_INT_RTO (1<<8) /*!< Response timeout error */
#define MCI_INT_DCRC (1<<7) /*!< Data CRC error */
#define MCI_INT_RCRC (1<<6) /*!< Response CRC error */
#define MCI_INT_RXDR (1<<5) /*!< RX data ready */
#define MCI_INT_TXDR (1<<4) /*!< TX data needed */
#define MCI_INT_DATA_OVER (1<<3) /*!< Data transfer over */
#define MCI_INT_CMD_DONE (1<<2) /*!< Command done */
#define MCI_INT_RESP_ERR (1<<1) /*!< Command response error */
#define MCI_INT_CD (1<<0) /*!< Card detect */
#define MCI_INT_ERROR 0xbfc2
/** \brief Command register defines
*/
#define MCI_CMD_START (1UL<<31) /*!< Start command */
#define MCI_CMD_VOLT_SWITCH (1<<28) /*!< Voltage switch bit */
#define MCI_CMD_BOOT_MODE (1<<27) /*!< Boot mode */
#define MCI_CMD_DISABLE_BOOT (1<<26) /*!< Disable boot */
#define MCI_CMD_EXPECT_BOOT_ACK (1<<25) /*!< Expect boot ack */
#define MCI_CMD_ENABLE_BOOT (1<<24) /*!< Enable boot */
#define MCI_CMD_CCS_EXP (1<<23) /*!< CCS expected */
#define MCI_CMD_CEATA_RD (1<<22) /*!< CE-ATA read in progress */
#define MCI_CMD_UPD_CLK (1<<21) /*!< Update clock register only */
#define MCI_CMD_CARDNUM 0x1F0000
#define MCI_CMD_INIT (1<<15) /*!< Send init sequence */
#define MCI_CMD_STOP (1<<14) /*!< Stop/abort command */
#define MCI_CMD_PRV_DAT_WAIT (1<<13) /*!< Wait before send */
#define MCI_CMD_SEND_STOP (1<<12) /*!< Send auto-stop */
#define MCI_CMD_STRM_MODE (1<<11) /*!< Stream transfer mode */
#define MCI_CMD_DAT_WR (1<<10) /*!< Read(0)/Write(1) selection */
#define MCI_CMD_DAT_EXP (1<<9) /*!< Data expected */
#define MCI_CMD_RESP_CRC (1<<8) /*!< Check response CRC */
#define MCI_CMD_RESP_LONG (1<<7) /*!< Response length */
#define MCI_CMD_RESP_EXP (1<<6) /*!< Response expected */
#define MCI_CMD_INDX(n) ((n) & 0x1F)
/** \brief status register definess
*/
#define MCI_STS_GET_FCNT(x) (((x)>>17) & 0x1FF)
/** \brief card type defines
*/
#define CARD_TYPE_SD (1 << 0)
#define CARD_TYPE_4BIT (1 << 1)
#define CARD_TYPE_8BIT (1 << 2)
#define CARD_TYPE_HC (OCR_HC_CCS) /*!< high capacity card > 2GB */
/** \brief Commonly used definitions
*/
#define MMC_SECTOR_SIZE 512
#define MCI_FIFO_SZ 32 /*!< Size of SDIO FIFO (32-bit wide) */
/** \brief Setup options for the SDIO driver
*/
#define US_TIMEOUT 1000000 /*!< give 1 atleast 1 sec for the card to respond */
#define MS_ACQUIRE_DELAY (10) /*!< inter-command acquire oper condition delay in msec*/
#define INIT_OP_RETRIES 10 /*!< initial OP_COND retries */
#define SET_OP_RETRIES 200 /*!< set OP_COND retries */
#define SDIO_BUS_WIDTH 4 /*!< Max bus width supported */
#define SD_MMC_ENUM_CLOCK 400000 /*!< Typical enumeration clock rate */
#define MMC_MAX_CLOCK 20000000 /*!< Max MMC clock rate */
#define MMC_LOW_BUS_MAX_CLOCK 26000000 /*!< Type 0 MMC card max clock rate */
#define MMC_HIGH_BUS_MAX_CLOCK 52000000 /*!< Type 1 MMC card max clock rate */
#define SD_MAX_CLOCK 25000000 /*!< Max SD clock rate */
#define SYS_REG_SD_CARD_DELAY 0x1B /*!< SD card delay (register) */
#define SYS_REG_MMC_CARD_DELAY 0x16 /*!< MMC card delay (register) */
/* The SDIO driver can be used in polled or IRQ based modes. In polling
mode, the driver functions block until complete. In IRQ mode, the
functions won't block and the status must be checked elsewhere. */
#define SDIO_USE_POLLING /* non-polling mode does not work yet */
/* If the following define is enabled, 'double buffer' type DMA descriptors
will be used instead of chained descriptors. */
/* Note: Avoid using double buffer mode - is isn't working yet. */
//#define USE_DMADESC_DBUFF
/***********************************************************************
* MCI device structure and it defines
**********************************************************************/
typedef struct _mci_card_struct MCI_CARD_INFO_T;
typedef uint32_t (*MCI_CMD_WAIT_FUNC_T)(MCI_CARD_INFO_T* , uint32_t);
typedef void (*MCI_IRQ_CB_FUNC_T)(MCI_CARD_INFO_T* , uint32_t);
struct _mci_card_struct
{
uint32_t response[4]; /*!< Most recent response */
uint32_t cid[4]; /*!< CID of acquired card */
uint32_t csd[4]; /*!< CSD of acquired card */
uint32_t ext_csd[MMC_SECTOR_SIZE/4];
uint32_t card_type;
uint32_t rca; /*!< Relative address assigned to card */
uint32_t speed;
uint32_t block_len;
uint32_t device_size;
uint32_t blocknr;
MCI_CMD_WAIT_FUNC_T wait_func;
MCI_IRQ_CB_FUNC_T irq_callback;
};
/** \brief MCI driver API functions
*/
/* Initialize the SDIO controller */
void sdio_init(MCI_CMD_WAIT_FUNC_T waitfunc,
MCI_IRQ_CB_FUNC_T irqfunc);
/* Detect if an SD card is inserted */
int sdio_card_detect(void);
/* Detect if write protect is enabled */
int sdio_card_wp_on(void);
/* Enable or disable slot power */
void sdio_power_onoff(int enable);
void sdio_power_on(void);
void sdio_power_off(void);
/* Function to enumerate the SD/MMC/SDHC/MMC+ cards */
int sdio_acquire(void);
/* Close the SDIO controller */
void sdio_deinit(void);
/* SDIO read function - reads data from a card */
int sdio_read_blocks(void *buffer,
int start_block,
int end_block);
/* SDIO write function - writes data to a card. After calling this
function, do not use read or write until the card state has
left the program state. */
int sdio_write_blocks(void *buffer,
int start_block,
int end_block);
/* Get card's current state (idle, transfer, program, etc.) */
int sdio_get_state(void);
int sdio_get_device_size(void);
extern uint32_t sdio_clk_rate;
#ifdef __cplusplus
}
#endif
#endif /* end __SDIO_H */
/*****************************************************************************
** End Of File
******************************************************************************/
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/spifi_rom_api.h
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/***********************************************************************
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors’
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
#ifndef SPIFI_ROM_API_H
#define SPIFI_ROM_API_H
#include <stdint.h>
/* define the symbol TESTING in the environment if test output desired */
/* maintain LONGEST_PROT >= the length (in bytes) of the largest
protection block of any serial flash that this driver handles */
#define LONGEST_PROT 68
typedef uint8_t uc;
#ifndef NULL
#define NULL ((void *)0)
#endif
/* protection/sector descriptors */
typedef struct {
uint32_t base;
uc flags;
int8_t log2;
uint16_t rept;
} protEnt;
/* bits in the flags byte */
enum {RWPROT=1};
/* overall data structure includes # sectors, length of protection reg,
array of descriptors
typedef struct {
uint16_t sectors;
uint16_t protBytes;
protEnt *entries;
} protDesc; */
typedef union {
uint16_t hw;
uc byte[2];
}stat_t;
/* the object that init returns, and other routines use as an operand */
typedef struct {
uint32_t base, regbase, devSize, memSize;
uc mfger, devType, devID, busy;
stat_t stat;
uint16_t reserved;
uint16_t set_prot, write_prot;
uint32_t mem_cmd, prog_cmd;
uint16_t sectors, protBytes;
uint32_t opts, errCheck;
uc erase_shifts[4], erase_ops[4];
protEnt *protEnts;
char prot[LONGEST_PROT];
} SPIFIobj;
/* operands of program and erase */
typedef struct {
char *dest;
uint32_t length;
char *scratch;
int32_t protect;
uint32_t options;
} SPIFIopers;
/* instruction classes for wait_busy */
typedef enum {stat_inst, block_erase, prog_inst, chip_erase} inst_type;
/* bits in options operands (MODE3, RCVCLK, and FULLCLK
have the same relationship as in the Control register) */
#define S_MODE3 1
#define S_MODE0 0
#define S_MINIMAL 2
#define S_MAXIMAL 0
#define S_FORCE_ERASE 4
#define S_ERASE_NOT_REQD 8
#define S_CALLER_ERASE 8
#define S_ERASE_AS_REQD 0
#define S_VERIFY_PROG 0x10
#define S_VERIFY_ERASE 0x20
#define S_NO_VERIFY 0
#define S_RCVCLK 0x80
#define S_INTCLK 0
#define S_FULLCLK 0x40
#define S_HALFCLK 0
#define S_DUAL 0x100
#define S_CALLER_PROT 0x200
#define S_DRIVER_PROT 0
/* the following values in the first post-address memory command byte work
for all known quad devices that support "no opcode" operation */
#define NO_OPCODE_FOLLOWS 0xA5
#define OPCODE_FOLLOWS 0xFF
/* basic SPI commands for serial flash */
#define BASE_READ_CMD (CMD_RD<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|UNL_DATA)
#define FAST_READ_CMD (CMD_READ_FAST<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|1<<INTLEN_SHIFT|UNL_DATA)
#define BASE_PROG_CMD (CMD_PROG<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|DOUT)
/* the length of a standard program command is 256 on all devices */
#define PROG_SIZE 256
/* options in obj->opts (mostly for setMulti) */
/* used by Winbond: send 0xA3 command so hardware can read faster */
#define OPT_SEND_A3 1
/* used by SST: send 0x38 command to enable quad and allow full command set */
#define OPT_SEND_38 2
/* used by Winbond and others: read status reg 2, check it,
if necessary write it back with Quad Enable set */
#define OPT_35_OR02_01 4
/* used by Atmel: read Configuration register, if necessary set Quad Enable */
#define OPT_3F_OR80_3E 8
/* used by Numonyx to set all-quad mode: only for parts that include RSTQIO */
#define OPT_65_CLR_C0_61 0x10
/* used by Numonyx: send 0x81 command to write Volatile Configuration Register
to set # dummy bytes and allow XIP mode */
#define OPT_81 0x20
/* set for devices without full device erase command (Numonyx type 0x40) */
#define OPT_NO_DEV_ERASE 0x40
/* used by Macronix: status reg 2 includes selection between write-protect
in status reg and command-based */
#define OPT_WPSEL 0x80
/* set when protection data has been read into the SPIFI object */
#define OPT_PROT_READ 0x100
/* set if device needs 4-byte address (and maybe 0x4B command = use 4-byte address) */
#define OPT_4BAD 0x200
/* set if setMulti should set the Dual bit in Control reg */
#define OPT_DUAL 0x400
/* send "# dummy bits" in C0 command to Winbond */
#define OPT_C0 0x800
/* set QE for Chingis */
#define OPT_05_OR40_01 0x1000
/* write status does not go busy */
#define OPT_01_NO_BUSY 0x2000
/* protection mode bits moved from protMode byte to opts Fri May 13 2011 */
#define OPT_PROT_STAT 0x4000
#define OPT_PROT_REG 0x8000
#define OPT_PROT_CMD3 0x10000
#define OPT_PROT_CMDE 0x20000
#define OPT_PROT_MASK 0x3C000
#define OPT_ALL_QUAD 0x40000
#ifndef OMIT_ROM_TABLE
/* interface to ROM API */
typedef struct {
int32_t (*spifi_init) (SPIFIobj *obj, uint32_t csHigh, uint32_t options,
uint32_t mhz);
int32_t (*spifi_program) (SPIFIobj *obj, char *source, SPIFIopers *opers);
int32_t (*spifi_erase) (SPIFIobj *obj, SPIFIopers *opers);
/* mode switching */
void (*cancel_mem_mode)(SPIFIobj *obj);
void (*set_mem_mode) (SPIFIobj *obj);
/* mid level functions */
int32_t (*checkAd) (SPIFIobj *obj, SPIFIopers *opers);
int32_t (*setProt) (SPIFIobj *obj, SPIFIopers *opers, char *change,
char *saveProt);
int32_t (*check_block) (SPIFIobj *obj, char *source, SPIFIopers *opers,
uint32_t check_program);
int32_t (*send_erase_cmd) (SPIFIobj *obj, uint8_t op, uint32_t addr);
uint32_t (*ck_erase) (SPIFIobj *obj, uint32_t *addr, uint32_t length);
int32_t (*prog_block) (SPIFIobj *obj, char *source, SPIFIopers *opers,
uint32_t *left_in_page);
uint32_t (*ck_prog) (SPIFIobj *obj, char *source, char *dest, uint32_t length);
/* low level functions */
void(*setSize) (SPIFIobj *obj, int32_t value);
int32_t (*setDev) (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd,
uint32_t prog_cmd);
uint32_t (*cmd) (uc op, uc addrLen, uc intLen, uint16_t len);
uint32_t (*readAd) (SPIFIobj *obj, uint32_t cmd, uint32_t addr);
void (*send04) (SPIFIobj *obj, uc op, uc len, uint32_t value);
void (*wren_sendAd) (SPIFIobj *obj, uint32_t cmd, uint32_t addr, uint32_t value);
int32_t (*write_stat) (SPIFIobj *obj, uc len, uint16_t value);
int32_t (*wait_busy) (SPIFIobj *obj, uc prog_or_erase);
} SPIFI_RTNS;
#define define_spifi_romPtr(name) const SPIFI_RTNS *name=*((SPIFI_RTNS **)SPIFI_ROM_PTR)
#endif /* OMIT_ROM_TABLE */
#ifdef USE_SPIFI_LIB
extern SPIFI_RTNS spifi_table;
#endif /* USE_SPIFI_LIB */
/* example of using this interface:
#include "spifi_rom_api.h"
#define CSHIGH 4
#define SPIFI_MHZ 80
#define source_data_ad (char *)1234
int32_t rc;
SPIFIopers opers;
define_spifi_romPtr(spifi);
SPIFIobj *obj = malloc(sizeof(SPIFIobj));
if (!obj) { can't allocate memory }
rc = spifi->spifi_init (obj, CSHIGH, S_FULLCLK+S_RCVCLK, SPIFI_MHZ);
if (rc) { investigate init error rc }
printf ("the serial flash contains %d bytes\n", obj->devSize);
opers.dest = where_to_program;
opers.length = how_many_bytes;
opers.scratch = NULL; // unprogrammed data is not saved/restored
opers.protect = -1; // save & restore protection
opers.options = S_VERIFY_PROG;
rc = spifi->spifi_program (obj, source_data_ad, &opers);
if (rc) { investigate program error rc }
*/
/* these are for normal users, including boot code */
int32_t spifi_init (SPIFIobj *obj, uint32_t csHigh, uint32_t options, uint32_t mhz);
int32_t spifi_program (SPIFIobj *obj, char *source, SPIFIopers *opers);
int32_t spifi_erase (SPIFIobj *obj, SPIFIopers *opers);
/* these are used by the manufacturer-specific init functions */
void setSize (SPIFIobj *obj, int32_t value);
int32_t setDev (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, uint32_t prog_cmd);
uint32_t read04(SPIFIobj *obj, uc op, uc len);
int32_t write_stat (SPIFIobj *obj, uc len, uint16_t value);
void setProtEnts(SPIFIobj *obj, const protEnt *p, uint32_t protTabLen);
/* needs to be defined for each platform */
void pullMISO(int high);
#ifdef TESTING
/* used by testing code */
unsigned short getProtBytes (SPIFIobj *obj, unsigned short *sectors);
/* predeclare a debug routine */
void wait_sample (volatile unsigned *addr, unsigned mask, unsigned value);
#endif
#endif /* SPIFI_ROM_API_H */
hw/mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/system_LPC43xx.h
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/**********************************************************************
* $Id$ system_lpc43xx.h 2011-06-02
*//**
* @file system_lpc43xx.h
* @brief Cortex-M3 Device System Header File for NXP lpc43xx Series.
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __SYSTEM_lpc43xx_H
#define __SYSTEM_lpc43xx_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_lpc43xx_H */