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move board and mcu into hw folder

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This commit is contained in:
hathach
2018-03-02 13:41:35 +07:00
parent 2580b4c6a7
commit 349fa2aed8
250 changed files with 47186 additions and 47134 deletions
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hw/mcu/lpc43xx/iar/FlashLPC18xx_43xx_SPIFI.board
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<?xml version="1.0" encoding="iso-8859-1"?>
<flash_board>
<pass>
<loader>$PROJ_DIR$\..\..\..\mcu\lpc43xx\iar\FlashLPC18xx_43xx_SPIFI.flash</loader>
</pass>
</flash_board>
hw/mcu/lpc43xx/iar/FlashLPC18xx_43xx_SPIFI.flash
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<?xml version="1.0" encoding="iso-8859-1"?>
<flash_device>
<exe>$PROJ_DIR$\..\..\..\mcu\lpc43xx\iar\FlashLPC18xx_43xx_SPIFI.out</exe>
<page>256</page>
<block>1 0x4000000</block>
<flash_base>0x14000000</flash_base>
<macro>$PROJ_DIR$\..\..\..\mcu\lpc43xx\iar\FlashLPC18xx_43xx_SPIFI.mac</macro>
<aggregate>1</aggregate>
</flash_device>
hw/mcu/lpc43xx/iar/FlashLPC18xx_43xx_SPIFI.mac
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__Setup()
{
/* set SPIFI clock */
//LPC_CGU->BASE_SPIFI0_CLK = 1<<24 | 1<<11; /* IRC 12 MHz is good enough for us */
__writeMemory32( 1<<24 | 1<<11, 0x40051304, "Memory");
//LPC_SCU->SFSP3_3 = 0xF3; /* high drive for SCLK */
__writeMemory32( 0xF3, 0x4008618C, "Memory");
/* IO pins */
//LPC_SCU->SFSP3_4=LPC_SCU->SFSP3_5=LPC_SCU->SFSP3_6=LPC_SCU->SFSP3_7 = 0xD3;
__writeMemory32( 0xD3, 0x40086190, "Memory");
__writeMemory32( 0xD3, 0x40086194, "Memory");
__writeMemory32( 0xD3, 0x40086198, "Memory");
__writeMemory32( 0xD3, 0x4008619C, "Memory");
//LPC_SCU->SFSP3_8 = 0x13; /* CS doesn't need feedback */
__writeMemory32( 0x13, 0x400861A0, "Memory");
__writeMemory32(0x14000000, 0x40043100, "Memory"); // map SPIFI to shadow area at address 0
}
execUserReset()
{
__message "----- execUserReset\n";
__Setup();
}
execUserFlashInit(){
__message "----- execUserFlashInit\n";
__Setup();
}
hw/mcu/lpc43xx/iar/FlashLPC18xx_43xx_SPIFI.out
BIN
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hw/mcu/lpc43xx/iar/lpc18xx_43xx_debug.mac
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__Setup(){
__writeMemory32((int)&__vector_table, 0x40043100, "Memory"); // map BootArea to shadow area at address 0
__writeMemory32((int)&__vector_table, 0xE000ED08, "Memory"); // map BootArea to shadow area at address 0
__message "Memory at: ", &__vector_table, " mapped to 0x00000000\n";
}
execUserReset()
{
__message "execUserReset\n";
__Setup();
__message "execUserReset Finish\n";
}
execUserFlashInit(){
__message "execUserFlashInit\n";
__Setup();
__message "execUserFlashInit Finish\n";
}
hw/mcu/lpc43xx/iar/lpc4330_m4_spifi.icf
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x14000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x14000140;
define symbol __ICFEDIT_region_ROM_end__ = 0x1407FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x1001FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x2000;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/**** End of ICF editor section. ###ICF###*/
/********** Local SRAM Region **********/
define symbol LOCAL_SRAM_start__ = 0x10080000;
define symbol LOCAL_SRAM_end__ = 0x1008FFFF;
/** Power-Down preserved Local SRAM Region **/
define symbol PD_LOCAL_SRAM_start__ = 0x10090000;
define symbol PD_LOCAL_SRAM_end__ = 0x10091FFF;
/********** AHB SRAM Region 1 **********/
define symbol AHB_SRAM1_start__ = 0x20000000;
define symbol AHB_SRAM1_end__ = 0x20007FFF;
/********** AHB SRAM Region 2 **********/
define symbol AHB_SRAM2_start__ = 0x20008000;
define symbol AHB_SRAM2_end__ = 0x2000BFFF;
/********* ETB/AHB SRAM Region *********/
define symbol ETB_SRAM_start__ = 0x2000C000;
define symbol ETB_SRAM_end__ = 0x2000FFFF;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region LOCAL_SRAM_region = mem:[from LOCAL_SRAM_start__ to LOCAL_SRAM_end__];
define region PD_LOCAL_SRAM_region = mem:[from PD_LOCAL_SRAM_start__ to PD_LOCAL_SRAM_end__];
define region AHB_SRAM1_region = mem:[from AHB_SRAM1_start__ to AHB_SRAM1_end__];
define region AHB_SRAM2_region = mem:[from AHB_SRAM2_start__ to AHB_SRAM2_end__];
define region ETB_SRAM_region = mem:[from ETB_SRAM_start__ to ETB_SRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
place in LOCAL_SRAM_region { section .local_sram };
place in PD_LOCAL_SRAM_region { section .pd_local_sram };
place in AHB_SRAM2_region { section .ahb_sram2 };
place in ETB_SRAM_region { section .etb_sram };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
hw/mcu/lpc43xx/iar/startup_LPC43xx.s
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/**************************************************
*
* Part one of the system initialization code, contains low-level
* initialization, plain thumb variant.
*
* Copyright 2011 IAR Systems. All rights reserved.
*
* $Revision: 50291 $
*
**************************************************/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD DAC_IRQHandler ; 16 D/A Converter
DCD M0CORE_IRQHandler ; 17 CortexM0
DCD DMA_IRQHandler ; 18 General Purpose DMA
DCD 0 ; 19 Reserved
DCD 0 ; 20 Reserved
DCD ETH_IRQHandler ; 21 Ethernet
DCD SDIO_IRQHandler ; 22 SD/MMC
DCD LCD_IRQHandler ; 23 LCD
DCD USB0_IRQHandler ; 24 USB0
DCD USB1_IRQHandler ; 25 USB1
DCD SCT_IRQHandler ; 26 State Configurable Timer
DCD RITIMER_IRQHandler ; 27 Repetitive Interrupt Timer
DCD TIMER0_IRQHandler ; 28 Timer0
DCD TIMER1_IRQHandler ; 29 Timer1
DCD TIMER2_IRQHandler ; 30 Timer2
DCD TIMER3_IRQHandler ; 31 Timer3
DCD MCPWM_IRQHandler ; 32 Motor Control PWM
DCD ADC0_IRQHandler ; 33 A/D Converter 0
DCD I2C0_IRQHandler ; 34 I2C0
DCD I2C1_IRQHandler ; 35 I2C1
DCD SPI_IRQHandler ; 36 Reserved
DCD ADC1_IRQHandler ; 37 A/D Converter 1
DCD SSP0_IRQHandler ; 38 SSP0
DCD SSP1_IRQHandler ; 39 SSP1
DCD USART0_IRQHandler ; 40 UART0
DCD UART1_IRQHandler ; 41 UART1
DCD UART2_IRQHandler ; 42 UART2
DCD UART3_IRQHandler ; 43 UART3
DCD I2S0_IRQHandler ; 44 I2S0
DCD I2S1_IRQHandler ; 45 I2S1
DCD SPIFI_IRQHandler ; 46 SPIFI
DCD SGPIO_IRQHandler ; 47 SGPIO
DCD GPIO0_IRQHandler ; 48 GPIO0
DCD GPIO1_IRQHandler ; 49 GPIO1
DCD GPIO2_IRQHandler ; 50 GPIO2
DCD GPIO3_IRQHandler ; 51 GPIO3
DCD GPIO4_IRQHandler ; 52 GPIO4
DCD GPIO5_IRQHandler ; 53 GPIO5
DCD GPIO6_IRQHandler ; 54 GPIO6
DCD GPIO7_IRQHandler ; 55 GPIO7
DCD GINT0_IRQHandler ; 56 GINT0
DCD GINT1_IRQHandler ; 57 GINT1
DCD EVENTROUTER_IRQHandler ; 58 Event Router
DCD C_CAN1_IRQHandler ; 59 CCAN1
DCD 0
DCD 0
DCD ATIMER_IRQHandler ; 62 Alarm Timer
DCD RTC_IRQHandler ; 63 RTC
DCD 0
DCD WWDT_IRQHandler ; 65 WWDT
DCD 0
DCD C_CAN0_IRQHandler ; 67 CCAN0
DCD QEI_IRQHandler ; 68 QEI
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
PUBWEAK HardFault_Handler
PUBWEAK MemManage_Handler
PUBWEAK BusFault_Handler
PUBWEAK UsageFault_Handler
PUBWEAK SVC_Handler
PUBWEAK DebugMon_Handler
PUBWEAK PendSV_Handler
PUBWEAK SysTick_Handler
PUBWEAK DAC_IRQHandler
PUBWEAK M0CORE_IRQHandler
PUBWEAK DMA_IRQHandler
PUBWEAK ETH_IRQHandler
PUBWEAK SDIO_IRQHandler
PUBWEAK LCD_IRQHandler
PUBWEAK USB0_IRQHandler
PUBWEAK USB1_IRQHandler
PUBWEAK SCT_IRQHandler
PUBWEAK RITIMER_IRQHandler
PUBWEAK TIMER0_IRQHandler
PUBWEAK TIMER1_IRQHandler
PUBWEAK TIMER2_IRQHandler
PUBWEAK TIMER3_IRQHandler
PUBWEAK MCPWM_IRQHandler
PUBWEAK ADC0_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
PUBWEAK SPI_IRQHandler
PUBWEAK ADC1_IRQHandler
PUBWEAK SSP0_IRQHandler
PUBWEAK SSP1_IRQHandler
PUBWEAK USART0_IRQHandler
PUBWEAK UART1_IRQHandler
PUBWEAK UART2_IRQHandler
PUBWEAK UART3_IRQHandler
PUBWEAK I2S0_IRQHandler
PUBWEAK I2S1_IRQHandler
PUBWEAK SPIFI_IRQHandler
PUBWEAK SGPIO_IRQHandler
PUBWEAK GPIO0_IRQHandler
PUBWEAK GPIO1_IRQHandler
PUBWEAK GPIO2_IRQHandler
PUBWEAK GPIO3_IRQHandler
PUBWEAK GPIO4_IRQHandler
PUBWEAK GPIO5_IRQHandler
PUBWEAK GPIO6_IRQHandler
PUBWEAK GPIO7_IRQHandler
PUBWEAK GINT0_IRQHandler
PUBWEAK GINT1_IRQHandler
PUBWEAK EVENTROUTER_IRQHandler
PUBWEAK C_CAN1_IRQHandler
PUBWEAK ATIMER_IRQHandler
PUBWEAK RTC_IRQHandler
PUBWEAK WWDT_IRQHandler
PUBWEAK C_CAN0_IRQHandler
PUBWEAK QEI_IRQHandler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
SVC_Handler
B SVC_Handler
DebugMon_Handler
B DebugMon_Handler
PendSV_Handler
B PendSV_Handler
SysTick_Handler
B SysTick_Handler
HardFault_Handler
B HardFault_Handler
MemManage_Handler
B MemManage_Handler
BusFault_Handler
B BusFault_Handler
UsageFault_Handler
DAC_IRQHandler
M0CORE_IRQHandler
DMA_IRQHandler
ETH_IRQHandler
SDIO_IRQHandler
LCD_IRQHandler
USB0_IRQHandler
USB1_IRQHandler
SCT_IRQHandler
RITIMER_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
MCPWM_IRQHandler
ADC0_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI_IRQHandler
ADC1_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
USART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SPIFI_IRQHandler
SGPIO_IRQHandler
GPIO0_IRQHandler
GPIO1_IRQHandler
GPIO2_IRQHandler
GPIO3_IRQHandler
GPIO4_IRQHandler
GPIO5_IRQHandler
GPIO6_IRQHandler
GPIO7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
EVENTROUTER_IRQHandler
C_CAN1_IRQHandler
ATIMER_IRQHandler
RTC_IRQHandler
WWDT_IRQHandler
C_CAN0_IRQHandler
QEI_IRQHandler
Default_IRQHandler
B Default_IRQHandler
THUMB
PUBLIC getPC
SECTION .text:CODE:REORDER(2)
getPC
MOV R0,LR
BX LR
/* CRP Section - not needed for flashless devices */
;;; SECTION .crp:CODE:ROOT(2)
;;; DATA
/* Code Read Protection
NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
- Copy RAM to flash command can not write to Sector 0.
- Erase command can erase Sector 0 only when all sectors
are selected for erase.
- Compare command is disabled.
- Read Memory command is disabled.
CRP2 0x87654321 - Read Memory is disabled.
- Write to RAM is disabled.
- "Go" command is disabled.
- Copy RAM to flash is disabled.
- Compare is disabled.
CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
by pulling PIO0_1 LOW is disabled if a valid user code is
present in flash sector 0.
Caution: If CRP3 is selected, no future factory testing can be
performed on the device.
*/
;;; DCD 0xFFFFFFFF
;;;
END