rename nxp_sof_received to nxp_int_sof

implementing freeRTOS integration
change get_period_frame_list from using lst_idx to hostid (fix bug)
adding polling interval supported for interrupt: 1ms, 2ms, 4ms, 8ms
- add interval_ms to get_period_head function
- add bInterval to qhd_init
- add support for sub-frame (less than 8 micro frames) interval
- add bunch of test for interrupt different intervals

tests/test/host/ehci/test_ehci_init.c

@@ -87,11 +87,12 @@ void test_hcd_init_usbint(void)
     TEST_ASSERT_FALSE(regs->usb_int_enable_bit.framelist_rollover);
     TEST_ASSERT_FALSE(regs->usb_int_enable_bit.pci_host_system_error);
 
+    TEST_ASSERT_FALSE(regs->usb_int_enable_bit.nxp_int_sof);
     TEST_ASSERT_FALSE(regs->usb_int_enable_bit.usb);
     TEST_ASSERT_TRUE(regs->usb_int_enable_bit.nxp_int_async);
     TEST_ASSERT_TRUE(regs->usb_int_enable_bit.nxp_int_period);
 
-    TEST_IGNORE_MESSAGE("not use nxp int async/period, use usbint instead");
+    // TODO to be portable use usbint instead of nxp int async/period
   }
 }
 
@@ -115,27 +116,46 @@ void test_hcd_init_async_list(void)
   }
 }
 
+void check_qhd_endpoint_link(ehci_link_t *p_prev, ehci_qhd_t *p_qhd)
+{
+  //------------- period list check -------------//
+  TEST_ASSERT_EQUAL_HEX((uint32_t) p_qhd, align32(p_prev->address));
+  TEST_ASSERT_FALSE(p_prev->terminate);
+  TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, p_prev->type);
+}
+
 void test_hcd_init_period_list(void)
 {
 #if EHCI_PERIODIC_LIST
   for(uint32_t i=0; i<CONTROLLER_HOST_NUMBER; i++)
   {
-    uint8_t           const hostid      = i+TEST_CONTROLLER_HOST_START_INDEX;
-    ehci_registers_t* const regs        = get_operational_register(hostid);
-    ehci_qhd_t *      const period_head = get_period_head(hostid);
-    ehci_link_t *     const framelist   = get_period_frame_list(hostid);
+    uint8_t           const hostid          = i+TEST_CONTROLLER_HOST_START_INDEX;
+    ehci_registers_t* const regs            = get_operational_register(hostid);
+    ehci_qhd_t *      const period_head_arr = get_period_head(hostid, 1);
+    ehci_link_t *     const framelist       = get_period_frame_list(hostid);
 
     TEST_ASSERT_EQUAL_HEX( (uint32_t) framelist, regs->periodic_list_base);
-    for(uint32_t list_idx=0; list_idx < EHCI_FRAMELIST_SIZE; list_idx++)
+
+    check_qhd_endpoint_link( framelist+1,  period_head_arr+1);
+    check_qhd_endpoint_link( framelist+3,  period_head_arr+1);
+    check_qhd_endpoint_link( framelist+5,  period_head_arr+1);
+    check_qhd_endpoint_link( framelist+7,  period_head_arr+1);
+
+    check_qhd_endpoint_link( framelist+2,  period_head_arr+2);
+    check_qhd_endpoint_link( framelist+6,  period_head_arr+2);
+
+    check_qhd_endpoint_link( framelist,  period_head_arr);
+    check_qhd_endpoint_link( framelist+4,  period_head_arr);
+    check_qhd_endpoint_link( (ehci_link_t*) (period_head_arr+1),  period_head_arr);
+    check_qhd_endpoint_link( (ehci_link_t*) (period_head_arr+2),  period_head_arr);
+
+    for(uint32_t i=0; i<3; i++)
     {
-      TEST_ASSERT_EQUAL_HEX( (uint32_t) period_head, align32((uint32_t)framelist[list_idx].address) );
-      TEST_ASSERT_FALSE(framelist[list_idx].terminate);
-      TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, framelist[list_idx].type);
+      TEST_ASSERT(period_head_arr[i].interrupt_smask);
+      TEST_ASSERT(period_head_arr[i].qtd_overlay.halted);
     }
 
-    TEST_ASSERT(period_head->interrupt_smask)
-    TEST_ASSERT_TRUE(period_head->next.terminate);
-    TEST_ASSERT(period_head->qtd_overlay.halted);
+    TEST_ASSERT_TRUE(period_head_arr[0].next.terminate);
   }
 #endif
 }

tests/test/host/ehci/test_ehci_structure.c

@@ -252,7 +252,7 @@ void test_register_usbsts(void)
   TEST_ASSERT_EQUAL( 3  , BITFIELD_OFFSET_OF_MEMBER(ehci_registers_t, usb_sts_bit, framelist_rollover));
   TEST_ASSERT_EQUAL( 4  , BITFIELD_OFFSET_OF_MEMBER(ehci_registers_t, usb_sts_bit, pci_host_system_error));
   TEST_ASSERT_EQUAL( 5  , BITFIELD_OFFSET_OF_MEMBER(ehci_registers_t, usb_sts_bit, async_advance));
-  TEST_ASSERT_EQUAL( 7  , BITFIELD_OFFSET_OF_MEMBER(ehci_registers_t, usb_sts_bit, nxp_sof_received));
+  TEST_ASSERT_EQUAL( 7  , BITFIELD_OFFSET_OF_MEMBER(ehci_registers_t, usb_sts_bit, nxp_int_sof));
   TEST_ASSERT_EQUAL( 12 , BITFIELD_OFFSET_OF_MEMBER(ehci_registers_t, usb_sts_bit, hc_halted));
   TEST_ASSERT_EQUAL( 13 , BITFIELD_OFFSET_OF_MEMBER(ehci_registers_t, usb_sts_bit, reclamation));
   TEST_ASSERT_EQUAL( 14 , BITFIELD_OFFSET_OF_MEMBER(ehci_registers_t, usb_sts_bit, period_schedule_status));
@@ -269,7 +269,7 @@ void test_register_usbint(void)
   TEST_ASSERT_EQUAL( 3  , BITFIELD_OFFSET_OF_MEMBER(ehci_registers_t, usb_int_enable_bit, framelist_rollover));
   TEST_ASSERT_EQUAL( 4  , BITFIELD_OFFSET_OF_MEMBER(ehci_registers_t, usb_int_enable_bit, pci_host_system_error));
   TEST_ASSERT_EQUAL( 5  , BITFIELD_OFFSET_OF_MEMBER(ehci_registers_t, usb_int_enable_bit, async_advance));
-  TEST_ASSERT_EQUAL( 7  , BITFIELD_OFFSET_OF_MEMBER(ehci_registers_t, usb_int_enable_bit, nxp_sof_received));
+  TEST_ASSERT_EQUAL( 7  , BITFIELD_OFFSET_OF_MEMBER(ehci_registers_t, usb_int_enable_bit, nxp_int_sof));
   TEST_ASSERT_EQUAL( 18 , BITFIELD_OFFSET_OF_MEMBER(ehci_registers_t, usb_int_enable_bit, nxp_int_async));
   TEST_ASSERT_EQUAL( 19 , BITFIELD_OFFSET_OF_MEMBER(ehci_registers_t, usb_int_enable_bit, nxp_int_period));
 

tests/test/host/ehci/test_ehci_usbh_hcd_integration.c

@@ -59,7 +59,7 @@ uint8_t dev_addr;
 uint8_t hostid;
 ehci_registers_t * regs;
 ehci_qhd_t *async_head;
-ehci_qhd_t *period_head;
+ehci_qhd_t *period_head_arr;
 
 void setUp(void)
 {
@@ -84,7 +84,7 @@ void setUp(void)
 
   regs = get_operational_register(hostid);
   async_head =  get_async_head( hostid );
-  period_head = get_period_head( hostid );
+  period_head_arr = get_period_head( hostid, 1 );
   regs->usb_sts = 0; // hcd_init clear usb_sts by writing 1s
 }
 

tests/test/host/ehci/test_pipe_interrupt_open.c

@@ -54,7 +54,12 @@ uint8_t const hub_port = 2;
 uint8_t dev_addr;
 uint8_t hostid;
 
-ehci_qhd_t *period_head;
+ehci_qhd_t *period_head_arr;
+
+ehci_qhd_t *p_int_qhd;
+pipe_handle_t pipe_hdl;
+
+uint8_t count_set_bits(uint8_t x);
 
 //--------------------------------------------------------------------+
 // Setup/Teardown + helper declare
@@ -76,7 +81,9 @@ void setUp(void)
     usbh_devices[i].speed    = TUSB_SPEED_HIGH;
   }
 
-  period_head = get_period_head( hostid );
+  period_head_arr = get_period_head( hostid, 1 );
+  p_int_qhd = NULL;
+  memclr_(&pipe_hdl, sizeof(pipe_handle_t));
 }
 
 void tearDown(void)
@@ -107,6 +114,7 @@ void verify_open_qhd(ehci_qhd_t *p_qhd, uint8_t endpoint_addr, uint16_t max_pack
   TEST_ASSERT_NULL(p_qhd->p_qtd_list_tail);
 }
 
+
 //--------------------------------------------------------------------+
 // PIPE OPEN
 //--------------------------------------------------------------------+
@@ -117,7 +125,7 @@ tusb_descriptor_endpoint_t const desc_ept_interrupt_out =
     .bEndpointAddress = 0x02,
     .bmAttributes     = { .xfer = TUSB_XFER_INTERRUPT },
     .wMaxPacketSize   = 16,
-    .bInterval        = 1
+    .bInterval        = 4
 };
 void verify_int_qhd(ehci_qhd_t *p_qhd, tusb_descriptor_endpoint_t const * desc_endpoint, uint8_t class_code)
 {
@@ -127,40 +135,148 @@ void verify_int_qhd(ehci_qhd_t *p_qhd, tusb_descriptor_endpoint_t const * desc_e
   TEST_ASSERT_FALSE(p_qhd->data_toggle_control);
   TEST_ASSERT_FALSE(p_qhd->non_hs_control_endpoint);
 
-  //  TEST_ASSERT_EQUAL(desc_endpoint->bInterval); TDD highspeed bulk/control OUT
-
   TEST_ASSERT_EQUAL(desc_endpoint->bEndpointAddress & 0x80 ? EHCI_PID_IN : EHCI_PID_OUT, p_qhd->pid_non_control);
+}
 
+void check_int_endpoint_link(ehci_qhd_t *p_prev, ehci_qhd_t *p_qhd)
+{
   //------------- period list check -------------//
-  TEST_ASSERT_EQUAL_HEX((uint32_t) p_qhd, align32(period_head->next.address));
-  TEST_ASSERT_FALSE(period_head->next.terminate);
-  TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, period_head->next.type);
+  TEST_ASSERT_EQUAL_HEX((uint32_t) p_qhd, align32(p_prev->next.address));
+  TEST_ASSERT_FALSE(p_prev->next.terminate);
+  TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, p_prev->next.type);
 }
 
 void test_open_interrupt_qhd_hs(void)
 {
-  ehci_qhd_t *p_qhd;
-  pipe_handle_t pipe_hdl;
-
   //------------- Code Under TEST -------------//
   pipe_hdl = hcd_pipe_open(dev_addr, &desc_ept_interrupt_out, TUSB_CLASS_HID);
 
   TEST_ASSERT_EQUAL(dev_addr, pipe_hdl.dev_addr);
   TEST_ASSERT_EQUAL(TUSB_XFER_INTERRUPT, pipe_hdl.xfer_type);
 
-  p_qhd = &ehci_data.device[ pipe_hdl.dev_addr-1].qhd[ pipe_hdl.index ];
+  p_int_qhd = &ehci_data.device[ pipe_hdl.dev_addr-1].qhd[ pipe_hdl.index ];
 
-  verify_int_qhd(p_qhd, &desc_ept_interrupt_out, TUSB_CLASS_HID);
+  verify_int_qhd(p_int_qhd, &desc_ept_interrupt_out, TUSB_CLASS_HID);
 
-  TEST_ASSERT_EQUAL(0xFF, p_qhd->interrupt_smask);
-//  TEST_ASSERT_EQUAL(0, p_qhd->non_hs_interrupt_cmask);
+  TEST_ASSERT_EQUAL(0, p_int_qhd->non_hs_interrupt_cmask);
+}
+
+void test_open_interrupt_hs_interval_1(void)
+{
+  tusb_descriptor_endpoint_t int_edp_interval = desc_ept_interrupt_out;
+  int_edp_interval.bInterval = 1;
+
+  //------------- Code Under TEST -------------//
+  pipe_hdl = hcd_pipe_open(dev_addr, &int_edp_interval, TUSB_CLASS_HID);
+  p_int_qhd = &ehci_data.device[ pipe_hdl.dev_addr-1].qhd[ pipe_hdl.index ];
+
+  TEST_ASSERT_EQUAL(0              , p_int_qhd->interval_ms);
+  TEST_ASSERT_EQUAL(BIN8(11111111) , p_int_qhd->interrupt_smask);
+
+  check_int_endpoint_link(period_head_arr, p_int_qhd);
+}
+
+void test_open_interrupt_hs_interval_2(void)
+{
+  tusb_descriptor_endpoint_t int_edp_interval = desc_ept_interrupt_out;
+  int_edp_interval.bInterval = 2;
+
+  //------------- Code Under TEST -------------//
+  pipe_hdl = hcd_pipe_open(dev_addr, &int_edp_interval, TUSB_CLASS_HID);
+  p_int_qhd = &ehci_data.device[ pipe_hdl.dev_addr-1].qhd[ pipe_hdl.index ];
+
+  TEST_ASSERT_EQUAL(0 , p_int_qhd->interval_ms);
+  TEST_ASSERT_EQUAL(4 , count_set_bits(p_int_qhd->interrupt_smask)); // either 10101010 or 01010101
+  check_int_endpoint_link(period_head_arr, p_int_qhd);
+}
+
+void test_open_interrupt_hs_interval_3(void)
+{
+  tusb_descriptor_endpoint_t int_edp_interval = desc_ept_interrupt_out;
+  int_edp_interval.bInterval = 3;
+
+  //------------- Code Under TEST -------------//
+  pipe_hdl = hcd_pipe_open(dev_addr, &int_edp_interval, TUSB_CLASS_HID);
+  p_int_qhd = &ehci_data.device[ pipe_hdl.dev_addr-1].qhd[ pipe_hdl.index ];
+
+  TEST_ASSERT_EQUAL(0, p_int_qhd->interval_ms);
+  TEST_ASSERT_EQUAL(2, count_set_bits(p_int_qhd->interrupt_smask) );
+  check_int_endpoint_link(period_head_arr, p_int_qhd);
+}
+
+void test_open_interrupt_hs_interval_4(void)
+{
+  tusb_descriptor_endpoint_t int_edp_interval = desc_ept_interrupt_out;
+  int_edp_interval.bInterval = 4;
+
+  //------------- Code Under TEST -------------//
+  pipe_hdl = hcd_pipe_open(dev_addr, &int_edp_interval, TUSB_CLASS_HID);
+  p_int_qhd = &ehci_data.device[ pipe_hdl.dev_addr-1].qhd[ pipe_hdl.index ];
+
+  TEST_ASSERT_EQUAL(1, p_int_qhd->interval_ms);
+  TEST_ASSERT_EQUAL(1, count_set_bits(p_int_qhd->interrupt_smask) );
+  check_int_endpoint_link(period_head_arr, p_int_qhd);
+}
+
+void test_open_interrupt_hs_interval_5(void)
+{
+  tusb_descriptor_endpoint_t int_edp_interval = desc_ept_interrupt_out;
+  int_edp_interval.bInterval = 5;
+
+  //------------- Code Under TEST -------------//
+  pipe_hdl = hcd_pipe_open(dev_addr, &int_edp_interval, TUSB_CLASS_HID);
+  p_int_qhd = &ehci_data.device[ pipe_hdl.dev_addr-1].qhd[ pipe_hdl.index ];
+
+  TEST_ASSERT_EQUAL(2, p_int_qhd->interval_ms);
+  TEST_ASSERT_EQUAL(1, count_set_bits(p_int_qhd->interrupt_smask) );
+  check_int_endpoint_link( get_period_head(hostid, 2), p_int_qhd );
+}
+
+void test_open_interrupt_hs_interval_6(void)
+{
+  tusb_descriptor_endpoint_t int_edp_interval = desc_ept_interrupt_out;
+  int_edp_interval.bInterval = 6;
+
+  //------------- Code Under TEST -------------//
+  pipe_hdl = hcd_pipe_open(dev_addr, &int_edp_interval, TUSB_CLASS_HID);
+  p_int_qhd = &ehci_data.device[ pipe_hdl.dev_addr-1].qhd[ pipe_hdl.index ];
+
+  TEST_ASSERT_EQUAL(4, p_int_qhd->interval_ms);
+  TEST_ASSERT_EQUAL(1, count_set_bits(p_int_qhd->interrupt_smask) );
+  check_int_endpoint_link( get_period_head(hostid, 4), p_int_qhd);
+}
+
+void test_open_interrupt_hs_interval_7(void)
+{
+  tusb_descriptor_endpoint_t int_edp_interval = desc_ept_interrupt_out;
+  int_edp_interval.bInterval = 7;
+
+  //------------- Code Under TEST -------------//
+  pipe_hdl = hcd_pipe_open(dev_addr, &int_edp_interval, TUSB_CLASS_HID);
+  p_int_qhd = &ehci_data.device[ pipe_hdl.dev_addr-1].qhd[ pipe_hdl.index ];
+
+  TEST_ASSERT_EQUAL(8, p_int_qhd->interval_ms);
+  TEST_ASSERT_EQUAL(1, count_set_bits(p_int_qhd->interrupt_smask) );
+  check_int_endpoint_link( get_period_head(hostid, 8), p_int_qhd);
+}
+
+void test_open_interrupt_hs_interval_8(void)
+{
+  tusb_descriptor_endpoint_t int_edp_interval = desc_ept_interrupt_out;
+  int_edp_interval.bInterval = 8;
+
+  //------------- Code Under TEST -------------//
+  pipe_hdl = hcd_pipe_open(dev_addr, &int_edp_interval, TUSB_CLASS_HID);
+  p_int_qhd = &ehci_data.device[ pipe_hdl.dev_addr-1].qhd[ pipe_hdl.index ];
+
+  TEST_ASSERT_EQUAL(16, p_int_qhd->interval_ms);
+  TEST_ASSERT_EQUAL(1, count_set_bits(p_int_qhd->interrupt_smask) );
+  check_int_endpoint_link( get_period_head(hostid, 16), p_int_qhd);
+  check_int_endpoint_link( get_period_head(hostid, 8) , p_int_qhd);
 }
 
 void test_open_interrupt_qhd_non_hs(void)
 {
-  ehci_qhd_t *p_qhd;
-  pipe_handle_t pipe_hdl;
-
   usbh_devices[dev_addr].speed = TUSB_SPEED_FULL;
 
   //------------- Code Under TEST -------------//
@@ -169,12 +285,29 @@ void test_open_interrupt_qhd_non_hs(void)
   TEST_ASSERT_EQUAL(dev_addr, pipe_hdl.dev_addr);
   TEST_ASSERT_EQUAL(TUSB_XFER_INTERRUPT, pipe_hdl.xfer_type);
 
-  p_qhd = &ehci_data.device[ pipe_hdl.dev_addr-1].qhd[ pipe_hdl.index ];
+  p_int_qhd = &ehci_data.device[ pipe_hdl.dev_addr-1].qhd[ pipe_hdl.index ];
 
-  verify_int_qhd(p_qhd, &desc_ept_interrupt_out, TUSB_CLASS_HID);
+  verify_int_qhd(p_int_qhd, &desc_ept_interrupt_out, TUSB_CLASS_HID);
 
-  TEST_ASSERT_EQUAL(1, p_qhd->interrupt_smask);
-  TEST_ASSERT_EQUAL(0x1c, p_qhd->non_hs_interrupt_cmask);
+  TEST_ASSERT_EQUAL(desc_ept_interrupt_out.bInterval, p_int_qhd->interval_ms);
+  TEST_ASSERT_EQUAL(1, p_int_qhd->interrupt_smask);
+  TEST_ASSERT_EQUAL(0x1c, p_int_qhd->non_hs_interrupt_cmask);
+}
+
+void test_open_interrupt_qhd_non_hs_9(void)
+{
+  tusb_descriptor_endpoint_t int_edp_interval = desc_ept_interrupt_out;
+  int_edp_interval.bInterval = 32;
+
+  usbh_devices[dev_addr].speed = TUSB_SPEED_FULL;
+
+  //------------- Code Under TEST -------------//
+  pipe_hdl = hcd_pipe_open(dev_addr, &int_edp_interval, TUSB_CLASS_HID);
+  p_int_qhd = &ehci_data.device[ pipe_hdl.dev_addr-1].qhd[ pipe_hdl.index ];
+
+  TEST_ASSERT_EQUAL(int_edp_interval.bInterval, p_int_qhd->interval_ms);
+  check_int_endpoint_link( get_period_head(hostid, 32), p_int_qhd);
+  check_int_endpoint_link( get_period_head(hostid, 8) , p_int_qhd);
 }
 
 //--------------------------------------------------------------------+
@@ -182,17 +315,28 @@ void test_open_interrupt_qhd_non_hs(void)
 //--------------------------------------------------------------------+
 void test_interrupt_close(void)
 {
-  ehci_qhd_t *p_qhd;
-  pipe_handle_t pipe_hdl;
-
   pipe_hdl = hcd_pipe_open(dev_addr, &desc_ept_interrupt_out, TUSB_CLASS_HID);
-  p_qhd = qhd_get_from_pipe_handle(pipe_hdl);
+  p_int_qhd = qhd_get_from_pipe_handle(pipe_hdl);
 
   //------------- Code Under TEST -------------//
   hcd_pipe_close(pipe_hdl);
 
-  TEST_ASSERT(p_qhd->is_removing);
-  TEST_ASSERT( align32(period_head->next.address) != (uint32_t) p_qhd );
-  TEST_ASSERT_EQUAL_HEX( (uint32_t) period_head, align32(p_qhd->next.address ) );
-  TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, p_qhd->next.type);
+  TEST_ASSERT(p_int_qhd->is_removing);
+  TEST_ASSERT( align32(period_head_arr->next.address) != (uint32_t) p_int_qhd );
+  TEST_ASSERT_EQUAL_HEX( (uint32_t) period_head_arr, align32(p_int_qhd->next.address ) );
+  TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, p_int_qhd->next.type);
+}
+
+uint8_t count_set_bits(uint8_t x)
+{
+  uint8_t result = 0;
+  for (uint8_t i=0; i<8; i++)
+  {
+    if ( x & BIT_(i) )
+    {
+      ++result;
+    }
+  }
+
+  return result;
 }

tests/test/host/ehci/test_pipe_interrupt_xfer.c

@@ -56,7 +56,7 @@ uint8_t hostid;
 uint8_t xfer_data [100];
 uint8_t data2[100];
 
-ehci_qhd_t *period_head;
+ehci_qhd_t *period_head_arr;
 ehci_qhd_t *p_qhd_interrupt;
 pipe_handle_t pipe_hdl_interrupt;
 
@@ -67,7 +67,7 @@ tusb_descriptor_endpoint_t const desc_ept_interrupt_in =
     .bEndpointAddress = 0x81,
     .bmAttributes     = { .xfer = TUSB_XFER_INTERRUPT },
     .wMaxPacketSize   = 8,
-    .bInterval        = 0
+    .bInterval        = 2
 };
 
 tusb_descriptor_endpoint_t const desc_ept_interupt_out =
@@ -77,7 +77,7 @@ tusb_descriptor_endpoint_t const desc_ept_interupt_out =
     .bEndpointAddress = 0x01,
     .bmAttributes     = { .xfer = TUSB_XFER_INTERRUPT },
     .wMaxPacketSize   = 64,
-    .bInterval        = 0
+    .bInterval        = 3
 };
 
 //--------------------------------------------------------------------+
@@ -103,7 +103,7 @@ void setUp(void)
     usbh_devices[i].speed    = TUSB_SPEED_HIGH;
   }
 
-  period_head =  get_period_head( hostid );
+  period_head_arr =  get_period_head( hostid, 1 );
   pipe_hdl_interrupt = hcd_pipe_open(dev_addr, &desc_ept_interrupt_in, TUSB_CLASS_HID);
 
   TEST_ASSERT_EQUAL(dev_addr, pipe_hdl_interrupt.dev_addr);
@@ -186,22 +186,49 @@ void test_interrupt_xfer_double(void)
   TEST_ASSERT_TRUE(p_tail->int_on_complete);
 }
 
-void test_interrupt_xfer_complete_isr(void)
+void check_qhd_after_complete(ehci_qhd_t *p_qhd)
+{
+  TEST_ASSERT_TRUE(p_qhd->qtd_overlay.next.terminate);
+  TEST_ASSERT_NULL(p_qhd->p_qtd_list_head);
+  TEST_ASSERT_NULL(p_qhd->p_qtd_list_tail);
+}
+
+void test_interrupt_xfer_complete_isr_interval_less_than_1ms(void)
 {
   hcd_pipe_xfer(pipe_hdl_interrupt, xfer_data, sizeof(xfer_data), false);
   hcd_pipe_xfer(pipe_hdl_interrupt, data2, sizeof(data2), true);
 
+  usbh_isr_Expect(pipe_hdl_interrupt, TUSB_CLASS_HID, TUSB_EVENT_XFER_COMPLETE);
+
   ehci_qtd_t* p_head = p_qhd_interrupt->p_qtd_list_head;
   ehci_qtd_t* p_tail = p_qhd_interrupt->p_qtd_list_tail;
 
-  usbh_isr_Expect(pipe_hdl_interrupt, TUSB_CLASS_HID, TUSB_EVENT_XFER_COMPLETE);
-
   //------------- Code Under Test -------------//
   ehci_controller_run(hostid);
 
-  TEST_ASSERT_TRUE(p_qhd_interrupt->qtd_overlay.next.terminate);
+  check_qhd_after_complete(p_qhd_interrupt);
   TEST_ASSERT_FALSE(p_head->used);
   TEST_ASSERT_FALSE(p_tail->used);
-  TEST_ASSERT_NULL(p_qhd_interrupt->p_qtd_list_head);
-  TEST_ASSERT_NULL(p_qhd_interrupt->p_qtd_list_tail);
+}
+
+void test_interrupt_xfer_complete_isr_interval_2ms(void)
+{
+  tusb_descriptor_endpoint_t desc_endpoint_2ms = desc_ept_interrupt_in;
+  desc_endpoint_2ms.bInterval = 5;
+
+  pipe_handle_t pipe_hdl_2ms = hcd_pipe_open(dev_addr, &desc_endpoint_2ms, TUSB_CLASS_HID);
+  ehci_qhd_t * p_qhd_2ms = &ehci_data.device[ dev_addr -1].qhd[ pipe_hdl_2ms.index ];
+
+  hcd_pipe_xfer(pipe_hdl_2ms, xfer_data, sizeof(xfer_data), false);
+
+  ehci_qtd_t* p_head = p_qhd_2ms->p_qtd_list_head;
+  ehci_qtd_t* p_tail = p_qhd_2ms->p_qtd_list_tail;
+
+  //------------- Code Under Test -------------//
+  ehci_controller_run(hostid);
+
+  check_qhd_after_complete(p_qhd_2ms);
+  TEST_ASSERT_FALSE(p_head->used);
+  TEST_ASSERT_FALSE(p_tail->used);
+
 }

tests/test/host/ehci/test_pipe_isochronous_open.c

@@ -54,7 +54,7 @@ uint8_t const hub_port = 2;
 uint8_t dev_addr;
 uint8_t hostid;
 
-ehci_qhd_t *period_head;
+ehci_qhd_t *period_head_arr;
 //--------------------------------------------------------------------+
 // Setup/Teardown + helper declare
 //--------------------------------------------------------------------+
@@ -75,7 +75,7 @@ void setUp(void)
     usbh_devices[i].speed    = TUSB_SPEED_HIGH;
   }
 
-  period_head = get_period_head( hostid );
+  period_head_arr = get_period_head( hostid, 1 );
 }
 
 void tearDown(void)

tests/test/support/ehci_controller.c

@@ -123,7 +123,7 @@ void ehci_controller_run(uint8_t hostid)
   complete_all_qtd_in_list((ehci_qhd_t*) regs->async_list_base);
 
   //------------- Period List -------------//
-  complete_all_qtd_in_list( get_period_head(hostid) );
+  complete_all_qtd_in_list( get_period_head(hostid, 1) );
   regs->usb_sts = EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_NXP_PERIODIC;
 
   hcd_isr(hostid);

tests/test/support/ehci_controller.h

@@ -64,9 +64,9 @@ void ehci_controller_device_plug(uint8_t hostid, tusb_speed_t speed);
 void ehci_controller_device_unplug(uint8_t hostid);
 
 ehci_registers_t* get_operational_register(uint8_t hostid);
-ehci_link_t* get_period_frame_list(uint8_t list_idx);
+ehci_link_t* get_period_frame_list(uint8_t hostid);
 ehci_qhd_t* get_async_head(uint8_t hostid);
-ehci_qhd_t* get_period_head(uint8_t hostid);
+ehci_qhd_t* get_period_head(uint8_t hostid, uint8_t interval_ms);
 ehci_qhd_t* get_control_qhd(uint8_t dev_addr);
 ehci_qtd_t* get_control_qtds(uint8_t dev_addr);
 ehci_qhd_t* qhd_get_from_pipe_handle(pipe_handle_t pipe_hdl);

tests/test/test_osal_freeRTOS.c

@@ -37,8 +37,8 @@
 
 #include "unity.h"
 #include "errors.h"
-#include "freeRTOS.h"
-#include "osal_freeRTOS.h"
+//#include "freeRTOS.h"
+//#include "osal_freeRTOS.h"
 //#include "mock_task.h"
 //#include "queue.h"
 //#include "mock_portmacro.h"