Add MM32 SDK and USB driver
Signed-off-by: zhangslice <1304224508@qq.com>
This commit is contained in:
zhangslice
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////////////////////////////////////////////////////////////////////////////////
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/// @file: dtype.h
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/// @author AE TEAM
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/// @brief Define the data types to be used in the project, including the function
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/// library and application code. Use the data types defined in this file.
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////////////////////////////////////////////////////////////////////////////////
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#ifndef __DTYPE_H
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#define __DTYPE_H //This is done to avoid including the header file repeatedly in the same file
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//Defines the read and write characteristics of data, which is often used for storage limits of peripheral registers
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#ifndef __I
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#define __I volatile const //only read
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#endif
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#ifndef __O
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#define __O volatile //only write
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#endif
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#ifndef __IO
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#define __IO volatile //read write
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#endif
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//Common data type definitions
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typedef unsigned char int8u; //haven't symbol8 bit integer variable
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typedef signed char int8s; //have symbol8 bit integer variable
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typedef unsigned short int16u; //haven't symbol16 bit integer variable
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typedef signed short int16s; //have symbol16 bit integer variable
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typedef unsigned int int32u; //haven't symbol32 bit integer variable
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typedef signed int int32s; //have symbol32 bit integer variable
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typedef float fp32; //Single-precision floating-point number (32-bit length)
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typedef double fp64; //Double-precision floating-point number (64-bit length)
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#endif //__DTYPE_H
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@@ -0,0 +1,341 @@
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////////////////////////////////////////////////////////////////////////////////
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/// @file hal_adc.h
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/// @author AE TEAM
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/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE ADC
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/// FIRMWARE LIBRARY.
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////////////////////////////////////////////////////////////////////////////////
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/// @attention
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///
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/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
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/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
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/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
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/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
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/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
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/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
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///
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/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
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////////////////////////////////////////////////////////////////////////////////
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// Define to prevent recursive inclusion
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#ifndef __HAL_ADC_H
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#define __HAL_ADC_H
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// Files includes
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#include "types.h"
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#include "reg_adc.h"
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////////////////////////////////////////////////////////////////////////////////
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/// @addtogroup MM32_Hardware_Abstract_Layer
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup ADC_HAL
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/// @brief ADC HAL modules
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup ADC_Exported_Types
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Channels
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_Channel_0 = 0x00, ///< ADC Channel 0
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ADC_Channel_1 = 0x01, ///< ADC Channel 1
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ADC_Channel_2 = 0x02, ///< ADC Channel 2
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ADC_Channel_3 = 0x03, ///< ADC Channel 3
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ADC_Channel_4 = 0x04, ///< ADC Channel 4
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ADC_Channel_5 = 0x05, ///< ADC Channel 5
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ADC_Channel_6 = 0x06, ///< ADC Channel 6
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ADC_Channel_7 = 0x07, ///< ADC Channel 7
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ADC_Channel_8 = 0x08, ///< ADC Channel 8
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ADC_Channel_9 = 0x09, ///< ADC Channel 9
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ADC_Channel_10 = 0x0A, ///< ADC Channel 10
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ADC_Channel_11 = 0x0B, ///< ADC Channel 11
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ADC_Channel_12 = 0x0C, ///< ADC Channel 12
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ADC_Channel_13 = 0x0D, ///< ADC Channel 13
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ADC_Channel_14 = 0x0E, ///< ADC Channel 14
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ADC_Channel_15 = 0x0F, ///< ADC Channel 15
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ADC_Channel_TempSensor = 0x0E, ///< Temperature sensor channel(ADC1)
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ADC_Channel_VoltReference = 0x0F, ///< Internal reference voltage channel(ADC1)
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ADC_Channel_Vrefint = 0x0F, ///< Internal reference voltage channel(ADC1)
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} ADCCHANNEL_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Sampling_Times
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_Samctl_1_5 = ADC_SMPR1_SAMCTL0_2_5, ///< ADC sample time select 1.5t
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ADC_Samctl_2_5 = ADC_SMPR1_SAMCTL0_2_5, ///< ADC sample time select 2.5t
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ADC_Samctl_3_5 = ADC_SMPR1_SAMCTL0_3_5, ///< ADC sample time select 3.5t
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ADC_Samctl_4_5 = ADC_SMPR1_SAMCTL0_4_5, ///< ADC sample time select 4.5t
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ADC_Samctl_5_5 = ADC_SMPR1_SAMCTL0_5_5, ///< ADC sample time select 5.5t
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ADC_Samctl_6_5 = ADC_SMPR1_SAMCTL0_6_5, ///< ADC sample time select 6.5t
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ADC_Samctl_7_5 = ADC_SMPR1_SAMCTL0_7_5, ///< ADC sample time select 7.5t
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ADC_Samctl_8_5 = ADC_SMPR1_SAMCTL0_8_5, ///< ADC sample time select 7.5t
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ADC_Samctl_13_5 = ADC_SMPR1_SAMCTL0_14_5, ///< ADC sample time select 13.5t
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ADC_Samctl_14_5 = ADC_SMPR1_SAMCTL0_14_5, ///< ADC sample time select 14.5t
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ADC_Samctl_28_5 = ADC_SMPR1_SAMCTL0_29_5, ///< ADC sample time select 28.5t
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ADC_Samctl_29_5 = ADC_SMPR1_SAMCTL0_29_5, ///< ADC sample time select 29.5t
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ADC_Samctl_41_5 = ADC_SMPR1_SAMCTL0_42_5, ///< ADC sample time select 41.5t
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ADC_Samctl_42_5 = ADC_SMPR1_SAMCTL0_42_5, ///< ADC sample time select 42.5t
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ADC_Samctl_55_5 = ADC_SMPR1_SAMCTL0_56_5, ///< ADC sample time select 55.5t
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ADC_Samctl_56_5 = ADC_SMPR1_SAMCTL0_56_5, ///< ADC sample time select 56.5t
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ADC_Samctl_71_5 = ADC_SMPR1_SAMCTL0_72_5, ///< ADC sample time select 71.5t
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ADC_Samctl_72_5 = ADC_SMPR1_SAMCTL0_72_5, ///< ADC sample time select 72.5t
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ADC_Samctl_239_5 = ADC_SMPR1_SAMCTL0_240_5, ///< ADC sample time select 239.5t
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ADC_Samctl_240_5 = ADC_SMPR1_SAMCTL0_240_5 ///< ADC sample time select 240.5t
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} ADCSAM_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Resolution
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_Resolution_12b = ADC_CFGR_RSLTCTL_12, ///< ADC resolution select 12bit
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ADC_Resolution_11b = ADC_CFGR_RSLTCTL_11, ///< ADC resolution select 11bit
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ADC_Resolution_10b = ADC_CFGR_RSLTCTL_10, ///< ADC resolution select 10bit
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ADC_Resolution_9b = ADC_CFGR_RSLTCTL_9, ///< ADC resolution select 9bit
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ADC_Resolution_8b = ADC_CFGR_RSLTCTL_8 ///< ADC resolution select 8bit
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} ADCRSL_TypeDef;
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/// @brief ADC_Prescare
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_PCLK2_PRESCARE_3 = ADC_CFGR_PRE_3, ///< ADC preclk 3
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ADC_PCLK2_PRESCARE_5 = ADC_CFGR_PRE_5, ///< ADC preclk 5
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ADC_PCLK2_PRESCARE_7 = ADC_CFGR_PRE_7, ///< ADC preclk 7
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ADC_PCLK2_PRESCARE_9 = ADC_CFGR_PRE_9, ///< ADC preclk 9
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ADC_PCLK2_PRESCARE_11 = ADC_CFGR_PRE_11, ///< ADC preclk 11
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ADC_PCLK2_PRESCARE_13 = ADC_CFGR_PRE_13, ///< ADC preclk 13
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ADC_PCLK2_PRESCARE_15 = ADC_CFGR_PRE_15, ///< ADC preclk 15
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ADC_PCLK2_PRESCARE_17 = ADC_CFGR_PRE_17, ///< ADC preclk 17
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ADC_PCLK2_PRESCARE_2 = ADC_CFGR_PRE_2, ///< ADC preclk 2
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ADC_PCLK2_PRESCARE_4 = ADC_CFGR_PRE_4, ///< ADC preclk 4
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ADC_PCLK2_PRESCARE_6 = ADC_CFGR_PRE_6, ///< ADC preclk 6
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ADC_PCLK2_PRESCARE_8 = ADC_CFGR_PRE_8, ///< ADC preclk 8
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ADC_PCLK2_PRESCARE_10 = ADC_CFGR_PRE_10, ///< ADC preclk 10
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ADC_PCLK2_PRESCARE_12 = ADC_CFGR_PRE_12, ///< ADC preclk 12
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ADC_PCLK2_PRESCARE_14 = ADC_CFGR_PRE_14, ///< ADC preclk 14
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ADC_PCLK2_PRESCARE_16 = ADC_CFGR_PRE_16 ///< ADC preclk 16
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} ADCPRE_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Conversion_Mode
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_Mode_Imm = ADC_CR_IMM, ///< ADC single convert mode
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ADC_Mode_Scan = ADC_CR_SCAN, ///< ADC single period convert mode
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ADC_Mode_Continue = ADC_CR_CONTINUE ///< ADC continue scan convert mode
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} ADCMODE_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Extrenal_Trigger_Sources_For_Regular_Channels_Conversion
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC1_ExternalTrigConv_T1_CC1 = ADC_CR_T1_CC1,
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ADC1_ExternalTrigConv_T1_CC2 = ADC_CR_T1_CC2,
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ADC1_ExternalTrigConv_T1_CC3 = ADC_CR_T1_CC3,
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ADC1_ExternalTrigConv_T2_CC2 = ADC_CR_T2_CC2,
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ADC1_ExternalTrigConv_T3_TRIG = ADC_CR_T3_TRIG,
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ADC1_ExternalTrigConv_T3_CC1 = ADC_CR_T3_CC1,
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ADC1_ExternalTrigConv_EXTI_11 = ADC_CR_EXTI_11,
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ADC1_ExternalTrigConv_T1_CC4_CC5 = ADC_CR_T1_CC4_CC5,
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ADC1_ExternalTrigConv_T1_TRIG = ADC_CR_T1_TRIG,
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ADC1_ExternalTrigConv_T8_CC4 = ADC_CR_T8_CC4,
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ADC1_ExternalTrigConv_T8_CC4_CC5 = ADC_CR_T8_CC4_CC5,
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ADC1_ExternalTrigConv_T2_CC1 = ADC_CR_T2_CC1,
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ADC1_ExternalTrigConv_T3_CC4 = ADC_CR_T3_CC4,
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ADC1_ExternalTrigConv_T2_TRIG = ADC_CR_T2_TRIG,
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ADC1_ExternalTrigConv_T8_CC5 = ADC_CR_T8_CC5,
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ADC1_ExternalTrigConv_EXTI_15 = ADC_CR_EXTI_15,
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ADC1_ExternalTrigConv_T1_CC4 = ADC_CR_TIM1_CC4,
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ADC1_ExternalTrigConv_T1_CC5 = ADC_CR_TIM1_CC5
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} EXTERTRIG_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Data_Align
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_DataAlign_Right = ADC_CR_RIGHT, ///< ADC data left align
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ADC_DataAlign_Left = ADC_CR_LEFT ///< ADC data right align
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} ADCDATAALI_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Flags_Definition
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_IT_EOC = 1, ///< ADC conversion flag
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ADC_FLAG_EOC = 1,
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ADC_IT_AWD = 2, ///< ADC window comparator flag
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ADC_FLAG_AWD = 2
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} ADCFLAG_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Trig_Edge
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_ADC_Trig_Edge_Dual = ADC_CR_TRG_EDGE_DUAL, ///< ADC trig edge dual mode down and up
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ADC_ADC_Trig_Edge_Down = ADC_CR_TRG_EDGE_DOWN, ///< ADC trig edge single mode down
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ADC_ADC_Trig_Edge_Up = ADC_CR_TRG_EDGE_UP, ///< ADC trig edge single mode up
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ADC_ADC_Trig_Edge_Mask = ADC_CR_TRG_EDGE_MASK ///< ADC trig edge is mask, not allowed
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} ADCTRIGEDGE_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Scan_Direct
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_Scan_Direct_Up = ADC_CR_SCANDIR, ///< ADC scan from low channel to high channel
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ADC_Scan_Direct_Down = 0 ///< ADC scan from High channel to low channel
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} ADCSCANDIRECT_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Trig_Shift
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_ADC_Trig_Shift_0 = ADC_CR_TRGSHIFT_0, ///< ADC trig shift bit is 0
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ADC_ADC_Trig_Shift_4 = ADC_CR_TRGSHIFT_4, ///< ADC trig shift bit is 4
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ADC_ADC_Trig_Shift_16 = ADC_CR_TRGSHIFT_16, ///< ADC trig shift bit is 16
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ADC_ADC_Trig_Shift_32 = ADC_CR_TRGSHIFT_32, ///< ADC trig shift bit is 32
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ADC_ADC_Trig_Shift_64 = ADC_CR_TRGSHIFT_64, ///< ADC trig shift bit is 64
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ADC_ADC_Trig_Shift_128 = ADC_CR_TRGSHIFT_128, ///< ADC trig shift bit is 128
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ADC_ADC_Trig_Shift_256 = ADC_CR_TRGSHIFT_256, ///< ADC trig shift bit is 256
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ADC_ADC_Trig_Shift_512 = ADC_CR_TRGSHIFT_512, ///< ADC trig shift bit is 512
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} ADCTRIGSHIFT_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Inject_Sequence_Length the sequencer length for injected channels
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_Inject_Seqen_Len1 = 0, ///< ADC Injected Seqence length is 1
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ADC_Inject_Seqen_Len2 = 1, ///< ADC Injected Seqence length is 2
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ADC_Inject_Seqen_Len3 = 2, ///< ADC Injected Seqence length is 3
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ADC_Inject_Seqen_Len4 = 3, ///< ADC Injected Seqence length is 4
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} ADC_INJ_SEQ_LEN_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Inject_Sequence_Length the sequencer length for injected channels
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_InjectedChannel_1 = 0x00,
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ADC_InjectedChannel_2 = 0x04,
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ADC_InjectedChannel_3 = 0x08,
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ADC_InjectedChannel_4 = 0x0c,
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} ADC_INJ_SEQ_Channel_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Extrenal_Trigger_Sources_For_Regular_Channels_Conversion
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC1_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO
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ADC1_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4
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ADC1_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5
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ADC1_InjectExtTrigSrc_T2_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM2 CC1
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ADC1_InjectExtTrigSrc_T3_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM3 CC4
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ADC1_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4
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ADC1_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5
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ADC1_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12
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ADC2_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO
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ADC2_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4
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ADC2_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5
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ADC2_InjectExtTrigSrc_T2_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM2 CC1
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ADC2_InjectExtTrigSrc_T3_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM3 CC4
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ADC2_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4
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ADC2_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5
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ADC2_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12
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ADC3_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO
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ADC3_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4
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ADC3_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5
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ADC3_InjectExtTrigSrc_T4_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM4 CC1
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ADC3_InjectExtTrigSrc_T5_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM5 CC4
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ADC3_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4
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ADC3_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5
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ADC3_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12
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} EXTER_INJ_TRIG_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC Init Structure definition
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////////////////////////////////////////////////////////////////////////////////
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typedef struct {
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u32 ADC_Resolution; ///< Convert data resolution
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u32 ADC_PRESCARE; ///< Clock prescaler
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u32 ADC_Mode; ///< ADC conversion mode
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FunctionalState ADC_ContinuousConvMode; ///< Useless just for compatibility
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u32 ADC_ExternalTrigConv; ///< External trigger source selection
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u32 ADC_DataAlign; ///< Data alignmentn
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} ADC_InitTypeDef;
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup ADC_Exported_Variables
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/// @{
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#ifdef _HAL_ADC_C_
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#define GLOBAL
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#else
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#define GLOBAL extern
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#endif
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#undef GLOBAL
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup ADC_Exported_Functions
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/// @{
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void ADC_DeInit(ADC_TypeDef* adc);
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void ADC_Init(ADC_TypeDef* adc, ADC_InitTypeDef* init_struct);
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void ADC_StructInit(ADC_InitTypeDef* init_struct);
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void ADC_Cmd(ADC_TypeDef* adc, FunctionalState state);
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void ADC_DMACmd(ADC_TypeDef* adc, FunctionalState state);
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void ADC_ITConfig(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt, FunctionalState state);
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void ADC_SoftwareStartConvCmd(ADC_TypeDef* adc, FunctionalState state);
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void ADC_RegularChannelConfig(ADC_TypeDef* adc, u32 channel, u8 rank, u32 sample_time);//ADCSAM_TypeDef
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void ADC_ExternalTrigConvCmd(ADC_TypeDef* adc, FunctionalState state);
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void ADC_ExternalTrigConvConfig(ADC_TypeDef* adc, EXTERTRIG_TypeDef adc_external_trig_source);
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#define ADC_ExternalTrigInjectedConvConfig ADC_ExternalTrigConvConfig
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void ADC_AnalogWatchdogCmd(ADC_TypeDef* adc, FunctionalState state);
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void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* adc, u16 high_threshold, u16 low_threshold);
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void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel);
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void ADC_TempSensorVrefintCmd(FunctionalState state);
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void ADC_ClearITPendingBit(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt);
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void ADC_ClearFlag(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag);
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u16 ADC_GetConversionValue(ADC_TypeDef* adc);
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FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* adc);
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag);
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt);
|
||||
void ADC_TempSensorCmd(FunctionalState state);
|
||||
void ADC_VrefintCmd(FunctionalState state);
|
||||
void exADC_TempSensorVrefintCmd(u32 chs, FunctionalState state);
|
||||
void ADC_ANY_CH_Config(ADC_TypeDef* adc, u8 rank, ADCCHANNEL_TypeDef adc_channel);
|
||||
void ADC_ANY_NUM_Config(ADC_TypeDef* adc, u8 num);
|
||||
void ADC_ANY_Cmd(ADC_TypeDef* adc, FunctionalState state);
|
||||
void ADC_AutoInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state);
|
||||
void ADC_ExternalTrigInjectedConvertConfig(ADC_TypeDef* adc, EXTER_INJ_TRIG_TypeDef ADC_ExtInjTrigSource);
|
||||
void ADC_InjectedConvCmd(ADC_TypeDef* adc, FunctionalState state);
|
||||
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state);
|
||||
void ADC_InjectedSequencerConfig(ADC_TypeDef* adc, u32 event, u32 sample_time);
|
||||
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_LEN_TypeDef Length);
|
||||
void ADC_InjectedSequencerChannelConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, ADCCHANNEL_TypeDef channel);
|
||||
u16 ADC_GetInjectedConversionValue(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr);
|
||||
u16 ADC_GetInjectedCurrentConvertedValue(ADC_TypeDef* adc);
|
||||
void ADC_SetInjectedOffset(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, u16 value);
|
||||
u16 ADC_GetChannelConvertedValue(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel);
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
@@ -0,0 +1,130 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_bkp.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE BKP
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_BKP_H
|
||||
#define __HAL_BKP_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_bkp.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup BKP_HAL
|
||||
/// @brief BKP HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup BKP_Exported_Types
|
||||
/// @{
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Data_Backup_Register
|
||||
/// @anchor Data_Backup_Register
|
||||
|
||||
typedef enum {
|
||||
BKP_DR1 = 0x0010,
|
||||
BKP_DR2 = 0x0014,
|
||||
BKP_DR3 = 0x0018,
|
||||
BKP_DR4 = 0x001C,
|
||||
BKP_DR5 = 0x0020,
|
||||
BKP_DR6 = 0x0024,
|
||||
BKP_DR7 = 0x0028,
|
||||
BKP_DR8 = 0x002C,
|
||||
BKP_DR9 = 0x0030,
|
||||
BKP_DR10 = 0x0034,
|
||||
BKP_DR11 = 0x0038,
|
||||
BKP_DR12 = 0x003C,
|
||||
BKP_DR13 = 0x0040,
|
||||
BKP_DR14 = 0x0044,
|
||||
BKP_DR15 = 0x0048,
|
||||
BKP_DR16 = 0x004C,
|
||||
BKP_DR17 = 0x0050,
|
||||
BKP_DR18 = 0x0054,
|
||||
BKP_DR19 = 0x0058,
|
||||
BKP_DR20 = 0x005C
|
||||
} BKPDR_Typedef;
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Tamper_Pin_active_level
|
||||
/// @anchor Tamper_Pin_active_level
|
||||
typedef enum {
|
||||
BKP_TamperPinLevel_High, ///< Tamper pin active on high level
|
||||
BKP_TamperPinLevel_Low = BKP_CR_TPAL, ///< Tamper pin active on low level
|
||||
} BKPTPAL_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief RTC_output_source_to_output_on_the_Tamper_pin
|
||||
/// @anchor RTC_output_source_to_output_on_the_Tamper_pin
|
||||
typedef enum {
|
||||
BKP_RTCOutputSource_None = 0x0000, ///< No RTC output on the Tamper pin
|
||||
BKP_RTCOutputSource_CalibClock = 0x0080, ///< Output the RTC clock with frequency divided by 64 on the Tamper pin
|
||||
BKP_RTCOutputSource_Alarm = 0x0100, ///< Output the RTC Alarm pulse signal on the Tamper pin
|
||||
BKP_RTCOutputSource_Second = 0x0300 ///< Output the RTC Second pulse signal on the Tamper pin
|
||||
} BKPRTCOUTPUTSRC_Typedef;
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup BKP_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_BKP_C_
|
||||
#define GLOBAL
|
||||
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup BKP_Exported_Functions
|
||||
/// @{
|
||||
|
||||
void BKP_WriteBackupRegister(BKPDR_Typedef bkp_dr, u16 data);
|
||||
u16 BKP_ReadBackupRegister(BKPDR_Typedef bkp_dr);
|
||||
|
||||
void BKP_DeInit(void);
|
||||
void BKP_ClearFlag(void);
|
||||
void BKP_ClearITPendingBit(void);
|
||||
void BKP_TamperPinLevelConfig(BKPTPAL_Typedef tamper_pin_level);
|
||||
void BKP_TamperPinCmd(FunctionalState state);
|
||||
void BKP_ITConfig(FunctionalState state);
|
||||
void BKP_RTCOutputConfig(BKPRTCOUTPUTSRC_Typedef rtc_output_source);
|
||||
void BKP_SetRTCCalibrationValue(u8 calibration_value);
|
||||
|
||||
ITStatus BKP_GetITStatus(void);
|
||||
FlagStatus BKP_GetFlagStatus(void);
|
||||
void exBKP_Init(void);
|
||||
void exBKP_ImmWrite(BKPDR_Typedef bkp_dr, u16 data);
|
||||
u16 exBKP_ImmRead(BKPDR_Typedef bkp_dr);
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_BKP_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,340 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_can.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CAN
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_CAN_H
|
||||
#define __HAL_CAN_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_can.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CAN_HAL
|
||||
/// @brief CAN HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CAN_Exported_Types
|
||||
/// @{
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Initialization
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CANINITFAILED = 0x00000000, ///< CAN initialization failed
|
||||
CANINITOK = 0x00000001 ///< CAN initialization ok
|
||||
} emCAN_INIT_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_sleep_constants
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CANSLEEPFAILED = 0x00000000, ///< CAN did not enter the sleep mode
|
||||
CANSLEEPOK = 0x00000001 ///< CAN entered the sleep mode
|
||||
} emCAN_SLEEP_conts_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_wake_up_constants
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CANWAKEUPFAILED = 0x00000000, ///< CAN did not leave the sleep mode
|
||||
CANWAKEUPOK = 0x00000001 ///< CAN leaved the sleep mode
|
||||
} emCAN_WAKE_conts_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Mode
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CAN_BASICMode = 0x00000000,
|
||||
CAN_PELIMode = 0x00000080,
|
||||
CAN_WorkMode = 0x00000080,
|
||||
CAN_ResetMode = 0x00000001,
|
||||
CAN_ListenOnlyMode = 0x00000002,
|
||||
CAN_SeftTestMode = 0x00000004,
|
||||
CAN_FilterMode_Singal = 0x00000008,
|
||||
CAN_FilterMode_Double = 0x000000f7,
|
||||
CAN_SleepMode = 0x00000010
|
||||
} emCAN_CAN_Mode_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief BASIC_CAN_interrupt
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CAN_IT_RIE = CAN_CR_RIE, ///< Overflow interrupt enable
|
||||
CAN_IT_TIE = CAN_CR_TIE, ///< Transmit interrupt enable
|
||||
CAN_IT_EIE = CAN_CR_EIE, ///< Error interrupt enable
|
||||
CAN_IT_OIE = CAN_CR_OIE ///< Receive interrupt enable
|
||||
} emCAN_BASIC_IntEn_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief PELI_CAN_interrupt
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CAN_IT_RI = CAN_IR_RI, ///< Overflow interrupt enable
|
||||
CAN_IT_TI = CAN_IR_TI, ///< Transmit interrupt enable
|
||||
CAN_IT_EI = CAN_IR_EI, ///< Error interrupt enable
|
||||
CAN_IT_DOI = CAN_IR_DOI, ///< Receive interrupt enable
|
||||
CAN_IT_WUI = 0x00001010, ///< Receive interrupt enable
|
||||
CAN_IT_EPI = CAN_IR_EPI, ///< Receive interrupt enable
|
||||
CAN_IT_ALI = CAN_IR_ALI, ///< Receive interrupt enable
|
||||
CAN_IT_BEI = CAN_IR_BEI, ///< Receive interrupt enable
|
||||
CAN_IT_ALL = 0xFFFF ///< Receive interrupt enable
|
||||
|
||||
} emCAN_PELI_IntEn_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Status
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CAN_STATUS_RBS = CAN_SR_RBS,
|
||||
CAN_STATUS_DOS = CAN_SR_DOS,
|
||||
CAN_STATUS_TBS = CAN_SR_TBS,
|
||||
CAN_STATUS_TCS = CAN_SR_TCS,
|
||||
CAN_STATUS_RS = CAN_SR_RS,
|
||||
CAN_STATUS_TS = CAN_SR_TS,
|
||||
CAN_STATUS_ES = CAN_SR_ES,
|
||||
CAN_STATUS_BS = CAN_SR_BS
|
||||
} emCAN_Status_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Command_register
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CAN_TR = CAN_CMR_TR, ///< Transmission request
|
||||
CAN_AT = CAN_CMR_AT,
|
||||
CAN_RRB = CAN_CMR_RRB,
|
||||
CAN_CDO = CAN_CMR_CDO
|
||||
} emCAN_Command_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Peli transmit frame definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DataFrame = 0, ///< Data Frame
|
||||
RemoteFrame = !DataFrame
|
||||
} TransFrame;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Basic init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u8 SJW;
|
||||
u8 BRP;
|
||||
FlagStatus SAM;
|
||||
u8 TESG2;
|
||||
u8 TESG1;
|
||||
FunctionalState GTS;
|
||||
u8 CDCLK;
|
||||
u8 CLOSE_OPEN_CLK;
|
||||
u8 RXINTEN;
|
||||
u8 CBP;
|
||||
} CAN_Basic_InitTypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Peli init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u8 SJW;
|
||||
u8 BRP;
|
||||
FlagStatus SAM;
|
||||
u8 TESG2;
|
||||
u8 TESG1;
|
||||
FunctionalState LOM;
|
||||
FunctionalState STM;
|
||||
FunctionalState SM;
|
||||
FunctionalState SRR;
|
||||
u32 EWLR;
|
||||
} CAN_Peli_InitTypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Basic filter init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef struct {
|
||||
u8 CAN_FilterId; ///< Specifies the filter identification number. This parameter can be a value between 0x00 and 0xFF.
|
||||
u8 CAN_FilterMaskId; ///< Specifies the filter mask number or identification number, This parameter can be a value between
|
||||
///< 0x00 and 0xFF.
|
||||
} CAN_Basic_FilterInitTypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Peli filter init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef struct {
|
||||
u8 AFM;
|
||||
u8 CAN_FilterId0; ///< Specifies the filter identification number, This parameter can be a value between 0x00 and 0xFF
|
||||
u8 CAN_FilterId1;
|
||||
u8 CAN_FilterId2;
|
||||
u8 CAN_FilterId3;
|
||||
u8 CAN_FilterMaskId0; ///< Specifies the filter mask number or identification number, This parameter can be a value between
|
||||
///< 0x00 and 0xFF
|
||||
u8 CAN_FilterMaskId1;
|
||||
u8 CAN_FilterMaskId2;
|
||||
u8 CAN_FilterMaskId3;
|
||||
} CAN_Peli_FilterInitTypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Basic Tx message structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef struct {
|
||||
u8 IDH; ///< Specifies the standard high identifier. This parameter can be a value between 0 to 0xFF.
|
||||
u8 IDL; ///< Specifies the standard low identifier. This parameter can be a value between 0 to 0x7.
|
||||
u8 RTR; ///< Specifies the type of frame for the message that will be transmitted. This parameter can be @TransFrame.
|
||||
u8 DLC; ///< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8.
|
||||
u8 Data[8]; ///< Contains the data to be transmitted. It ranges from 0 to 0xFF.
|
||||
} CanBasicTxMsg;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Basic Rx message structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef struct {
|
||||
u16 ID; ///< Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF.
|
||||
u8 RTR; ///< Specifies the type of frame for the received message. This parameter can be a value of @ref TransFrame
|
||||
u8 DLC; ///< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8
|
||||
u8 Data[8]; ///< Contains the data to be received. It ranges from 0 to 0xFF.
|
||||
} CanBasicRxMsg;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Peli_Tx message structure definition
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef struct {
|
||||
u8 IDLL; ///< Specifies the extended identifier.
|
||||
///< This parameter can be a value between 0 to 0xFF.
|
||||
u8 IDLH;
|
||||
u8 IDHL;
|
||||
u8 IDHH;
|
||||
u8 FF; ///< Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of @ref
|
||||
///< CAN_identifier_type
|
||||
u8 RTR; ///< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref
|
||||
///< TransFrame.
|
||||
u8 DLC; ///< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8.
|
||||
u8 Data[8]; ///< Contains the data to be transmitted. It ranges from 0 to 0xFF.
|
||||
} CanPeliTxMsg;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN Rx message structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u32 ID; ///< Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF.
|
||||
u8 FF; ///< Specifies the type of identifier for the message that will be received. This parameter can be a value of @ref
|
||||
///< CAN_identifier_type.
|
||||
u8 RTR; ///< Specifies the type of frame for the received message. This parameter can be a value of @ref TransFrame.
|
||||
u8 DLC; ///< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8.
|
||||
u8 Data[8]; ///< Contains the data to be received. It ranges from 0 to0xFF.
|
||||
} CanPeliRxMsg;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CAN_Exported_Constants
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup parasmeter_of_CAN_transmission_register
|
||||
/// @{
|
||||
#define CANTXFAILED (0x00U) ///< CAN transmission failed
|
||||
#define CANTXOK (0x01U) ///< CAN transmission succeeded
|
||||
#define CANTXPENDING (0x02U) ///< CAN transmission pending
|
||||
#define CAN_NO_MB (0x04U) ///< CAN cell did not provide an empty mailbox
|
||||
/// @}
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CAN_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_CAN_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CAN_Exported_Functions
|
||||
/// @{
|
||||
|
||||
// Basic and Peli Work all need function ---------------------------------------
|
||||
|
||||
void CAN_Mode_Cmd(CAN_TypeDef* can, u32 mode);
|
||||
void CAN_ResetMode_Cmd(CAN_TypeDef* can, FunctionalState state);
|
||||
void CAN_ClearDataOverflow(CAN_TypeDef* can);
|
||||
void CAN_ClearITPendingBit(CAN_TypeDef* can);
|
||||
|
||||
// Basic Work function ---------------------------------------------------------
|
||||
void CAN_DeInit(CAN_TypeDef* can);
|
||||
void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* basic_filter_init_struct);
|
||||
void CAN_StructInit(CAN_Basic_InitTypeDef* basic_init_struct);
|
||||
void CAN_ITConfig(CAN_TypeDef* can, u32 it, FunctionalState state);
|
||||
void CAN_CancelTransmit(CAN_TypeDef* can);
|
||||
void CAN_FIFORelease(CAN_TypeDef* can);
|
||||
void CAN_Receive(CAN_TypeDef* can, CanBasicRxMsg* basic_receive_message);
|
||||
|
||||
u8 CAN_Transmit(CAN_TypeDef* can, CanBasicTxMsg* basic_transmit_message);
|
||||
u8 CAN_Init(CAN_TypeDef* can, CAN_Basic_InitTypeDef* basic_init_struct);
|
||||
u8 CAN_Sleep(CAN_TypeDef* can);
|
||||
u8 CAN_WakeUp(CAN_TypeDef* can);
|
||||
|
||||
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* can, u32 flag);
|
||||
ITStatus CAN_GetITStatus(CAN_TypeDef* can, u32 it);
|
||||
|
||||
// Peli Work function ----------------------------------------------------------
|
||||
void CAN_Peli_SleepMode_Cmd(FunctionalState state);
|
||||
void CAN_Peli_Init(CAN_Peli_InitTypeDef* init_struct);
|
||||
void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* peli_init_struct);
|
||||
void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct);
|
||||
void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct);
|
||||
void CAN_Peli_Transmit(CanPeliTxMsg* peli_transmit_message);
|
||||
void CAN_Peli_TransmitRepeat(CanPeliTxMsg* peli_transmit_message);
|
||||
void CAN_Peli_Receive(CanPeliRxMsg* peli_receive_message);
|
||||
void CAN_Peli_ITConfig(u32 it, FunctionalState state);
|
||||
void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef* init_struct, u32 src_clk, u32 baud);
|
||||
|
||||
u32 CAN_Peli_GetRxFIFOInfo(void);
|
||||
u8 CAN_Peli_GetLastErrorCode(void);
|
||||
u8 CAN_Peli_GetReceiveErrorCounter(void);
|
||||
u8 CAN_Peli_GetLSBTransmitErrorCounter(void);
|
||||
|
||||
ITStatus CAN_Peli_GetITStatus(u32 it);
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
@@ -0,0 +1,228 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_comp.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE COMP
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_COMP_H
|
||||
#define __HAL_COMP_H
|
||||
|
||||
|
||||
// Files includes
|
||||
#include "reg_common.h"
|
||||
#include "reg_comp.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup COMP_HAL
|
||||
/// @brief COMP HAL modules
|
||||
/// @{
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup COMP_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP_InvertingInput
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
COMP_InvertingInput_IO0 = COMP_CSR_INM_0, ///< INM0 as COMP inverting input
|
||||
COMP_InvertingInput_IO1 = COMP_CSR_INM_1, ///< INM1 as COMP inverting input
|
||||
COMP_InvertingInput_IO2 = COMP_CSR_INM_2, ///< INM2 as COMP inverting input
|
||||
COMP_InvertingInput_CRV = COMP_CSR_INM_3, ///< INM3 as COMP inverting input
|
||||
COMP_InvertingInput_IO3 = COMP_CSR_INM_3, ///< INM3 as COMP inverting input
|
||||
} EM_COMP_InvertingInput;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP_NonInvertingInput
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
COMP_NonInvertingInput_IO0 = COMP_CSR_INP_INP0, ///< INP0 as COMP non-inverting input
|
||||
COMP_NonInvertingInput_IO1 = COMP_CSR_INP_INP1, ///< INP1 as COMP non-inverting input
|
||||
COMP_NonInvertingInput_IO2 = COMP_CSR_INP_INP2, ///< INP2 as COMP non-inverting input
|
||||
COMP_NonInvertingInput_IO3 = COMP_CSR_INP_INP3, ///< INP3 as COMP non-inverting input
|
||||
} EM_COMP_NonInvertingInput;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP_Output
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
COMP_Output_None = 0x00000000, ///< No output
|
||||
COMP_Output_TIM1BKIN = COMP_CSR_OUT_TIM1_BRAKE, ///< Timer1 brake input
|
||||
COMP_Output_TIM1OCREFCLR = COMP_CSR_OUT_TIM1_OCREFCLR, ///< Timer1 ocrefclear input
|
||||
COMP_Output_TIM1IC1 = COMP_CSR_OUT_TIM1_CAPTURE1, ///< Timer1 input capture 1
|
||||
COMP_Output_TIM2IC4 = COMP_CSR_OUT_TIM2_CAPTURE4, ///< Timer2 input capture 4
|
||||
COMP_Output_TIM2OCREFCLR = COMP_CSR_OUT_TIM2_OCREFCLR, ///< Timer2 ocrefclear input
|
||||
COMP_Output_TIM3IC1 = COMP_CSR_OUT_TIM3_CAPTURE1, ///< Timer3 input capture 1
|
||||
COMP_Output_TIM3OCREFCLR = COMP_CSR_OUT_TIM3_OCREFCLR ///< Timer3 ocrefclear input
|
||||
} EM_COMP_Output;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP_OutputPoloarity
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
COMP_NonInverted = 0x00000000, ///< COMP non-inverting output
|
||||
COMP_OutputPol_NonInverted = 0x00000000,
|
||||
COMP_Inverted = 0x00008000, ///< COMP inverting output
|
||||
COMP_OutputPol_Inverted = 0x00008000
|
||||
} EM_COMP_OutputPol;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP_Hysteresis
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
COMP_Hysteresis_No = COMP_CSR_HYST_0, ///< Hysteresis Voltage: 0mV
|
||||
COMP_Hysteresis_Low = COMP_CSR_HYST_15, ///< Hysteresis Voltage: 15mV
|
||||
COMP_Hysteresis_Medium = COMP_CSR_HYST_30, ///< Hysteresis Voltage: 30mV
|
||||
COMP_Hysteresis_High = COMP_CSR_HYST_90 ///< Hysteresis Voltage: 90mV
|
||||
} EM_COMP_Hysteresis;
|
||||
typedef enum {
|
||||
COMP_Filter_0_Period = COMP_CSR_OFLT_0, ///< filter is ((u32)0x00000000)
|
||||
COMP_Filter_2_Period = COMP_CSR_OFLT_1, ///< filter is ((u32)0x00040000)
|
||||
COMP_Filter_4_Period = COMP_CSR_OFLT_2, ///< filter is ((u32)0x00080000)
|
||||
COMP_Filter_8_Period = COMP_CSR_OFLT_3, ///< filter is ((u32)0x000C0000)
|
||||
COMP_Filter_16_Period = COMP_CSR_OFLT_4, ///< filter is ((u32)0x00100000)
|
||||
COMP_Filter_32_Period = COMP_CSR_OFLT_5, ///< filter is ((u32)0x00140000)
|
||||
COMP_Filter_64_Period = COMP_CSR_OFLT_6, ///< filter is ((u32)0x00180000)
|
||||
COMP_Filter_128_Period = COMP_CSR_OFLT_7, ///< filter is ((u32)0x001C0000)
|
||||
} EM_COMP_FILT;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP_Mode
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
COMP_Mode_HighSpeed = COMP_CSR_MODE_HIGHRATE, ///< Comparator high rate mode
|
||||
COMP_Mode_MediumSpeed = COMP_CSR_MODE_MEDIUMRATE, ///< Comparator medium rate mode
|
||||
COMP_Mode_LowPower = COMP_CSR_MODE_LOWPOWER, ///< Comparator low power mode
|
||||
COMP_Mode_UltraLowPower = COMP_CSR_MODE_LOWESTPOWER ///< Comparator lowest power mode
|
||||
} EM_COMP_Mode;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP_OutputLevel
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
COMP_OutputLevel_High = COMP_CSR_OUT, ///< High output
|
||||
COMP_OutputLevel_Low = 0x00000000 ///< Low output
|
||||
} EM_COMP_OutputLevel;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
union {
|
||||
u32 COMP_InvertingInput;
|
||||
u32 Invert; ///< Selects the inverting input of the comparator.
|
||||
};
|
||||
union {
|
||||
u32 COMP_NonInvertingInput;
|
||||
u32 NonInvert; ///< Selects the non inverting input of the comparator.
|
||||
};
|
||||
union {
|
||||
u32 COMP_Output;
|
||||
u32 Output; ///< Selects the output redirection of the comparator.
|
||||
u32 BlankingSrce; ///< Selects the output blanking source of the comparator.
|
||||
};
|
||||
union {
|
||||
u32 COMP_OutputPol;
|
||||
u32 OutputPol; ///< Selects the output polarity of the comparator.
|
||||
};
|
||||
union {
|
||||
u32 COMP_Hysteresis;
|
||||
u32 Hysteresis; ///< Selects the hysteresis voltage of the comparator.
|
||||
};
|
||||
union {
|
||||
u32 COMP_Mode;
|
||||
u32 Mode; ///< Selects the operating mode of the comparator and allows
|
||||
};
|
||||
union {
|
||||
u32 COMP_Filter;
|
||||
u32 OFLT; ///< to adjust the speed/consumption.
|
||||
};
|
||||
} COMP_InitTypeDef;
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
|
||||
FunctionalState COMP_Poll_En; ///< Selects the inverting input of the comparator.
|
||||
|
||||
u32 COMP_Poll_Ch; ///< Selects the non inverting input of the comparator.
|
||||
u32 COMP_Poll_Fixn; ///< Selects the output redirection of the comparator.
|
||||
u32 COMP_Poll_Period; ///< Selects the output polarity of the comparator.
|
||||
u32 COMP_Poll_Pout; ///< Selects the hysteresis voltage of the comparator.
|
||||
|
||||
} COMP_POLL_InitTypeDef;
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup COMP_Exported_Constants
|
||||
/// @{
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
COMP1 = (0x00000C), ///< Select comparator 1
|
||||
COMP2 = (0x000010), ///< Select comparator 2
|
||||
} COMP_Selection_TypeDef;
|
||||
|
||||
#define COMP_BlankingSrce_None ((u32)0x00000000)
|
||||
#define COMP_CSR_CLEAR_MASK ((u32)0x00000003)
|
||||
|
||||
#define COMP_CSR_COMPSW1 ((u32)0x00000002)
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///@defgroup COMP_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_COMP_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup COMP_Exported_Functions
|
||||
/// @{
|
||||
|
||||
|
||||
void COMP_DeInit(COMP_Selection_TypeDef selection);
|
||||
void COMP_Init(COMP_Selection_TypeDef selection, COMP_InitTypeDef* init_struct);
|
||||
void COMP_StructInit(COMP_InitTypeDef* init_struct);
|
||||
void COMP_Cmd(COMP_Selection_TypeDef selection, FunctionalState state);
|
||||
void COMP_SwitchCmd(COMP_Selection_TypeDef selection, FunctionalState state);
|
||||
void COMP_LockConfig(COMP_Selection_TypeDef selection);
|
||||
|
||||
u32 COMP_GetOutputLevel(COMP_Selection_TypeDef selection);
|
||||
|
||||
void COMP_SetCrv(u8 crv_select, u8 crv_level);
|
||||
#define SET_COMP_CRV COMP_SetCrv
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_COMP_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,62 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_conf.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GENERIC MICROCONTROLLER
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_CONF_H
|
||||
#define __HAL_CONF_H
|
||||
// Files includes
|
||||
#include "mm32_device.h"
|
||||
|
||||
#include "hal_adc.h"
|
||||
#include "hal_bkp.h"
|
||||
#include "hal_can.h"
|
||||
#include "hal_comp.h"
|
||||
#include "hal_crc.h"
|
||||
#include "hal_crs.h"
|
||||
#include "hal_dac.h"
|
||||
#include "hal_dbg.h"
|
||||
#include "hal_dma.h"
|
||||
#include "hal_exti.h"
|
||||
#include "hal_flash.h"
|
||||
#include "hal_gpio.h"
|
||||
#include "hal_i2c.h"
|
||||
#include "hal_iwdg.h"
|
||||
#include "hal_misc.h"
|
||||
#include "hal_pwr.h"
|
||||
#include "hal_rcc.h"
|
||||
#include "hal_rtc.h"
|
||||
#include "hal_spi.h"
|
||||
#include "hal_syscfg.h"
|
||||
#include "hal_tim.h"
|
||||
#include "hal_uart.h"
|
||||
#include "hal_uid.h"
|
||||
#include "hal_wwdg.h"
|
||||
#include "hal_redefine.h"
|
||||
#include "hal_eth.h"
|
||||
#include "hal_eth_conf.h"
|
||||
#include "hal_fsmc.h"
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_CONF_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,84 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_crc.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CRC
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_CRC_H
|
||||
#define __HAL_CRC_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
#include "reg_crc.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CRC_HAL
|
||||
/// @brief CRC HAL modules
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CRC_Exported_Types
|
||||
/// @{
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CRC_Exported_Constants
|
||||
/// @{
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CRC_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_CRC_C_
|
||||
#define GLOBAL
|
||||
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CRC_Exported_Functions
|
||||
/// @{
|
||||
void CRC_ResetDR(void);
|
||||
void CRC_SetIDRegister(u8 id_value);
|
||||
|
||||
u32 CRC_CalcCRC(u32 data);
|
||||
u32 CRC_CalcBlockCRC(u32* buffer, u32 length);
|
||||
u32 CRC_GetCRC(void);
|
||||
|
||||
u8 CRC_GetIDRegister(void);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_CRC_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,46 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_crs.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CRS
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_CRS_H
|
||||
#define __HAL_CRS_H
|
||||
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_crs.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CRS_HAL
|
||||
/// @brief CRS HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup GPIO_Exported_Types
|
||||
/// @{
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
@@ -0,0 +1,166 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_dac.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DAC
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_DAC_H
|
||||
#define __HAL_DAC_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_dac.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DAC_HAL
|
||||
/// @brief DAC HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DAC_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DAC_Trigger_Selection
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DAC_Trigger_None = 0x00000000,
|
||||
DAC_Trigger_T1_TRIG = (DAC_CR_TSEL1_TIM1_TRIG | DAC_CR_TEN1),
|
||||
DAC_Trigger_T3_TRIG = (DAC_CR_TSEL1_TIM3_TRIG | DAC_CR_TEN1),
|
||||
DAC_Trigger_T2_TRIG = (DAC_CR_TSEL1_TIM2_TRIG | DAC_CR_TEN1),
|
||||
DAC_Trigger_T4_TRIG = (DAC_CR_TSEL1_TIM4_TRIG | DAC_CR_TEN1),
|
||||
DAC_Trigger_Ext_IT9 = (DAC_CR_TSEL1_EXTI9 | DAC_CR_TEN1),
|
||||
DAC_Trigger_Software = (DAC_CR_TSEL1_SOFTWARE)
|
||||
} emDACTRIG_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DAC_Wave_Generation
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DAC_WaveGeneration_None = DAC_CR_WAVE1_NONE,
|
||||
DAC_WaveGeneration_Noise = DAC_CR_WAVE1_NOISE,
|
||||
DAC_WaveGeneration_Triangle = DAC_CR_WAVE1_TRIANGLE
|
||||
} emDACWAVE_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DAC_Mask_Amplitude
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DAC_TriangleAmplitude_1 = DAC_CR_MAMP1_1,
|
||||
DAC_TriangleAmplitude_3 = DAC_CR_MAMP1_3,
|
||||
DAC_TriangleAmplitude_7 = DAC_CR_MAMP1_7,
|
||||
DAC_TriangleAmplitude_15 = DAC_CR_MAMP1_15,
|
||||
DAC_TriangleAmplitude_31 = DAC_CR_MAMP1_31,
|
||||
DAC_TriangleAmplitude_63 = DAC_CR_MAMP1_63,
|
||||
DAC_TriangleAmplitude_127 = DAC_CR_MAMP1_127,
|
||||
DAC_TriangleAmplitude_255 = DAC_CR_MAMP1_255,
|
||||
DAC_TriangleAmplitude_511 = DAC_CR_MAMP1_511,
|
||||
DAC_TriangleAmplitude_1023 = DAC_CR_MAMP1_1023,
|
||||
DAC_TriangleAmplitude_2047 = DAC_CR_MAMP1_2047,
|
||||
DAC_TriangleAmplitude_4095 = DAC_CR_MAMP1_4095
|
||||
} emDACAMP_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief channel
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DAC_Channel_1, ///< DAC channel 1
|
||||
DAC_Channel_2 = (u32)0x00000010 ///< DAC Channel 2
|
||||
} emDACCH_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DAC_Data_Alignement
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DAC_Align_12b_R = ((u32)0x00000000),
|
||||
DAC_Align_12b_L = ((u32)0x00000004),
|
||||
DAC_Align_8b_R = ((u32)0x00000008)
|
||||
} emDACALIGN_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DAC_Output_Buffer
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DAC_OutputBuffer_Enable = 0x00000000, ///< DAC output buffer enable
|
||||
DAC_OutputBuffer_Disable = DAC_CR_BOFF1 ///< DAC output buffer disable
|
||||
} emDACBOFF_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DAC Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
emDACTRIG_TypeDef DAC_Trigger;
|
||||
emDACWAVE_TypeDef DAC_WaveGeneration;
|
||||
emDACAMP_TypeDef DAC_LFSRUnmask_TriangleAmplitude;
|
||||
emDACBOFF_TypeDef DAC_OutputBuffer;
|
||||
} DAC_InitTypeDef;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DAC_Exported_Constants
|
||||
/// @{
|
||||
#define DHR12R1_Offset ((u32)0x00000008)
|
||||
#define DHR12R2_Offset ((u32)0x00000014)
|
||||
#define DHR12RD_Offset ((u32)0x00000020)
|
||||
#define DOR_Offset ((u32)0x0000002C)
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DAC_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_DAC_C_
|
||||
#define GLOBAL
|
||||
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DAC_Exported_Functions
|
||||
/// @{
|
||||
void DAC_DeInit(void);
|
||||
void DAC_Init(emDACCH_TypeDef channel, DAC_InitTypeDef* init_struct);
|
||||
void DAC_StructInit(DAC_InitTypeDef* init_struct);
|
||||
void DAC_Cmd(emDACCH_TypeDef channel, FunctionalState state);
|
||||
void DAC_DMACmd(emDACCH_TypeDef channel, FunctionalState state);
|
||||
void DAC_SoftwareTriggerCmd(emDACCH_TypeDef channel, FunctionalState state);
|
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState state);
|
||||
void DAC_WaveGenerationCmd(emDACCH_TypeDef channel, emDACWAVE_TypeDef wave, FunctionalState state);
|
||||
void DAC_SetChannel1Data(emDACALIGN_TypeDef alignement, u16 data);
|
||||
void DAC_SetChannel2Data(emDACALIGN_TypeDef alignement, u16 data);
|
||||
void DAC_SetDualChannelData(emDACALIGN_TypeDef alignement, u16 data2, u16 data1);
|
||||
|
||||
u16 DAC_GetDataOutputValue(emDACCH_TypeDef channel);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_DAC_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
@@ -0,0 +1,72 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_dbg.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DBG
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_DBG_H
|
||||
#define __HAL_DBG_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
#include "reg_dbg.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DBG_HAL
|
||||
/// @brief DBG HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DBG_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DIV_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_DBG_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DBG_Exported_Functions
|
||||
/// @{
|
||||
void DBGMCU_Configure(u32 periph, FunctionalState state);
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_DBG_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,41 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_device.h
|
||||
/// @author AE team
|
||||
/// @brief CMSIS Cortex-M Peripheral Access Layer for MindMotion
|
||||
/// microcontroller devices
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_DEVICE_H
|
||||
#define __HAL_DEVICE_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#include "mm32_device.h"
|
||||
|
||||
|
||||
#endif // __HAL_device_H
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,306 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_dma.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DMA
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_DMA_H
|
||||
#define __HAL_DMA_H
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
#include "reg_dma.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DMA_HAL
|
||||
/// @brief DMA HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DMA_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA data transfer direction Enumerate definition
|
||||
/// @anchor DMA_data_transfer_direction
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_DIR_PeripheralSRC = 0U,
|
||||
DMA_DIR_PeripheralDST = DMA_CCR_DIR // 0x00000010U
|
||||
} DMA_data_transfer_direction_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA peripheral incremented mode Enumerate definition
|
||||
/// @anchor DMA_peripheral_incremented_mode
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_PeripheralInc_Disable = 0U,
|
||||
DMA_PeripheralInc_Enable = DMA_CCR_PINC // 0x00000040U
|
||||
} DMA_peripheral_incremented_mode_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA memory incremented mode Enumerate definition
|
||||
/// @anchor DMA_memory_incremented_mode
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_MemoryInc_Disable = 0U,
|
||||
DMA_MemoryInc_Enable = DMA_CCR_MINC // 0x00000080U
|
||||
} DMA_memory_incremented_mode_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA peripheral data size Enumerate definition
|
||||
/// @anchor DMA_peripheral_data_size
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_PeripheralDataSize_Byte = 0U,
|
||||
DMA_PeripheralDataSize_HalfWord = DMA_CCR_PSIZE_HALFWORD,
|
||||
DMA_PeripheralDataSize_Word = DMA_CCR_PSIZE_WORD
|
||||
} DMA_peripheral_data_size_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA memory data size Enumerate definition
|
||||
/// @anchor DMA_memory_data_size
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_MemoryDataSize_Byte = 0U,
|
||||
DMA_MemoryDataSize_HalfWord = DMA_CCR_MSIZE_HALFWORD, // 0x00000400U
|
||||
DMA_MemoryDataSize_Word = DMA_CCR_MSIZE_WORD // 0x00000800U
|
||||
} DMA_memory_data_size_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA circular normal mode Enumerate definition
|
||||
/// @anchor DMA_circular_normal_mode
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_Mode_Normal = 0U,
|
||||
DMA_Mode_Circular = DMA_CCR_CIRC // 0x00000020U
|
||||
} DMA_circular_normal_mode_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA priority level Enumerate definition
|
||||
/// @anchor DMA_priority_level
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_Priority_Low = 0U,
|
||||
DMA_Priority_Medium = DMA_CCR_PL_Medium, // 0x00001000U
|
||||
DMA_Priority_High = DMA_CCR_PL_High, // 0x00002000U
|
||||
DMA_Priority_VeryHigh = DMA_CCR_PL_VeryHigh // 0x00003000U
|
||||
} DMA_priority_level_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA memory to memory Enumerate definition
|
||||
/// @anchor DMA_memory_to_memory
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_M2M_Disable = 0U,
|
||||
DMA_M2M_Enable = DMA_CCR_M2M // 0x00004000U
|
||||
} DMA_memory_to_memory_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA auto reload Enumerate definition
|
||||
/// @anchor DMA_auto_reload
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_Auto_Reload_Disable = 0U, //
|
||||
DMA_Auto_Reload_Enable = DMA_CCR_ARE
|
||||
} DMA_auto_reload_TypeDef;
|
||||
/// @brief DMA Interrupt Setting Enumerate definition
|
||||
/// @anchor DMA_auto_reload
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_IT_TC = DMA_CCR_TCIE, //(0x00000002UL),
|
||||
DMA_IT_HT = DMA_CCR_HTIE, //(0x00000004UL),
|
||||
DMA_IT_TE = DMA_CCR_TEIE, //(0x00000008UL),
|
||||
} DMA_Interrupt_EN_TypeDef;
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA interrupts Enumerate definition
|
||||
/// @anchor DMA_Flags
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMAx_IT_GLy = (0x00000001UL),
|
||||
DMAx_IT_TCy = (0x00000002UL),
|
||||
DMAx_IT_HTy = (0x00000004UL),
|
||||
DMAx_IT_TEy = (0x00000008UL),
|
||||
DMA1_IT_GL1 = (0x00000001UL),
|
||||
DMA1_IT_TC1 = (0x00000002UL),
|
||||
DMA1_IT_HT1 = (0x00000004UL),
|
||||
DMA1_IT_TE1 = (0x00000008UL),
|
||||
DMA1_IT_GL2 = (0x00000010UL),
|
||||
DMA1_IT_TC2 = (0x00000020UL),
|
||||
DMA1_IT_HT2 = (0x00000040UL),
|
||||
DMA1_IT_TE2 = (0x00000080UL),
|
||||
DMA1_IT_GL3 = (0x00000100UL),
|
||||
DMA1_IT_TC3 = (0x00000200UL),
|
||||
DMA1_IT_HT3 = (0x00000400UL),
|
||||
DMA1_IT_TE3 = (0x00000800UL),
|
||||
DMA1_IT_GL4 = (0x00001000UL),
|
||||
DMA1_IT_TC4 = (0x00002000UL),
|
||||
DMA1_IT_HT4 = (0x00004000UL),
|
||||
DMA1_IT_TE4 = (0x00008000UL),
|
||||
DMA1_IT_GL5 = (0x00010000UL),
|
||||
DMA1_IT_TC5 = (0x00020000UL),
|
||||
DMA1_IT_HT5 = (0x00040000UL),
|
||||
DMA1_IT_TE5 = (0x00080000UL),
|
||||
DMA1_IT_GL6 = (0x00100000UL),
|
||||
DMA1_IT_TC6 = (0x00200000UL),
|
||||
DMA1_IT_HT6 = (0x00400000UL),
|
||||
DMA1_IT_TE6 = (0x00800000UL),
|
||||
DMA1_IT_GL7 = (0x01000000UL),
|
||||
DMA1_IT_TC7 = (0x02000000UL),
|
||||
DMA1_IT_HT7 = (0x04000000UL),
|
||||
DMA1_IT_TE7 = (0x08000000UL),
|
||||
DMA2_IT_GL1 = (0x10000001UL),
|
||||
DMA2_IT_TC1 = (0x10000002UL),
|
||||
DMA2_IT_HT1 = (0x10000004UL),
|
||||
DMA2_IT_TE1 = (0x10000008UL),
|
||||
DMA2_IT_GL2 = (0x10000010UL),
|
||||
DMA2_IT_TC2 = (0x10000020UL),
|
||||
DMA2_IT_HT2 = (0x10000040UL),
|
||||
DMA2_IT_TE2 = (0x10000080UL),
|
||||
DMA2_IT_GL3 = (0x10000100UL),
|
||||
DMA2_IT_TC3 = (0x10000200UL),
|
||||
DMA2_IT_HT3 = (0x10000400UL),
|
||||
DMA2_IT_TE3 = (0x10000800UL),
|
||||
DMA2_IT_GL4 = (0x10001000UL),
|
||||
DMA2_IT_TC4 = (0x10002000UL),
|
||||
DMA2_IT_HT4 = (0x10004000UL),
|
||||
DMA2_IT_TE4 = (0x10008000UL),
|
||||
DMA2_IT_GL5 = (0x10010000UL),
|
||||
DMA2_IT_TC5 = (0x10020000UL),
|
||||
DMA2_IT_HT5 = (0x10040000UL),
|
||||
DMA2_IT_TE5 = (0x10080000UL),
|
||||
} DMA_Interrupts_TypeDef;
|
||||
typedef enum {
|
||||
DMAx_FLAG_GLy = (0x00000001UL),
|
||||
DMAx_FLAG_TCy = (0x00000002UL),
|
||||
DMAx_FLAG_HTy = (0x00000004UL),
|
||||
DMAx_FLAG_TEy = (0x00000008UL),
|
||||
DMA1_FLAG_GL1 = (0x00000001UL),
|
||||
DMA1_FLAG_TC1 = (0x00000002UL),
|
||||
DMA1_FLAG_HT1 = (0x00000004UL),
|
||||
DMA1_FLAG_TE1 = (0x00000008UL),
|
||||
DMA1_FLAG_GL2 = (0x00000010UL),
|
||||
DMA1_FLAG_TC2 = (0x00000020UL),
|
||||
DMA1_FLAG_HT2 = (0x00000040UL),
|
||||
DMA1_FLAG_TE2 = (0x00000080UL),
|
||||
DMA1_FLAG_GL3 = (0x00000100UL),
|
||||
DMA1_FLAG_TC3 = (0x00000200UL),
|
||||
DMA1_FLAG_HT3 = (0x00000400UL),
|
||||
DMA1_FLAG_TE3 = (0x00000800UL),
|
||||
DMA1_FLAG_GL4 = (0x00001000UL),
|
||||
DMA1_FLAG_TC4 = (0x00002000UL),
|
||||
DMA1_FLAG_HT4 = (0x00004000UL),
|
||||
DMA1_FLAG_TE4 = (0x00008000UL),
|
||||
DMA1_FLAG_GL5 = (0x00010000UL),
|
||||
DMA1_FLAG_TC5 = (0x00020000UL),
|
||||
DMA1_FLAG_HT5 = (0x00040000UL),
|
||||
DMA1_FLAG_TE5 = (0x00080000UL),
|
||||
DMA1_FLAG_GL6 = (0x00100000UL),
|
||||
DMA1_FLAG_TC6 = (0x00200000UL),
|
||||
DMA1_FLAG_HT6 = (0x00400000UL),
|
||||
DMA1_FLAG_TE6 = (0x00800000UL),
|
||||
DMA1_FLAG_GL7 = (0x01000000UL),
|
||||
DMA1_FLAG_TC7 = (0x02000000UL),
|
||||
DMA1_FLAG_HT7 = (0x04000000UL),
|
||||
DMA1_FLAG_TE7 = (0x08000000UL),
|
||||
DMA2_FLAG_GL1 = (0x10000001UL),
|
||||
DMA2_FLAG_TC1 = (0x10000002UL),
|
||||
DMA2_FLAG_HT1 = (0x10000004UL),
|
||||
DMA2_FLAG_TE1 = (0x10000008UL),
|
||||
DMA2_FLAG_GL2 = (0x10000010UL),
|
||||
DMA2_FLAG_TC2 = (0x10000020UL),
|
||||
DMA2_FLAG_HT2 = (0x10000040UL),
|
||||
DMA2_FLAG_TE2 = (0x10000080UL),
|
||||
DMA2_FLAG_GL3 = (0x10000100UL),
|
||||
DMA2_FLAG_TC3 = (0x10000200UL),
|
||||
DMA2_FLAG_HT3 = (0x10000400UL),
|
||||
DMA2_FLAG_TE3 = (0x10000800UL),
|
||||
DMA2_FLAG_GL4 = (0x10001000UL),
|
||||
DMA2_FLAG_TC4 = (0x10002000UL),
|
||||
DMA2_FLAG_HT4 = (0x10004000UL),
|
||||
DMA2_FLAG_TE4 = (0x10008000UL),
|
||||
DMA2_FLAG_GL5 = (0x10010000UL),
|
||||
DMA2_FLAG_TC5 = (0x10020000UL),
|
||||
DMA2_FLAG_HT5 = (0x10040000UL),
|
||||
DMA2_FLAG_TE5 = (0x10080000UL),
|
||||
} DMA_Flags_TypeDef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u32 DMA_PeripheralBaseAddr; ///< the peripheral base address for DMA Channeln.
|
||||
u32 DMA_MemoryBaseAddr; ///< the memory base address for DMA Channeln.
|
||||
DMA_data_transfer_direction_TypeDef DMA_DIR; ///< the peripheral is the source or destination.
|
||||
u32 DMA_BufferSize; ///< Specifies the buffer size, in data unit, of the Buffer size
|
||||
DMA_peripheral_incremented_mode_TypeDef DMA_PeripheralInc; ///< Specifies whether the Peripheral address increment or not
|
||||
DMA_memory_incremented_mode_TypeDef DMA_MemoryInc; ///< Specifies whether the memory address register is increment or not
|
||||
DMA_peripheral_data_size_TypeDef DMA_PeripheralDataSize; ///< Specifies the Peripheral data width.
|
||||
DMA_memory_data_size_TypeDef DMA_MemoryDataSize; ///< Specifies the Memory data width.
|
||||
DMA_circular_normal_mode_TypeDef DMA_Mode; ///< Specifies the operation mode of the DMA Channeln circular or normal mode.
|
||||
DMA_priority_level_TypeDef DMA_Priority; ///< Specifies the software priority for the DMA priority level
|
||||
DMA_memory_to_memory_TypeDef DMA_M2M; ///< Specifies if the DMA Channeln will be used in memory-to-memory transfer.
|
||||
DMA_auto_reload_TypeDef DMA_Auto_reload; ///< Specifies if the DMA Channeln will auto reload the CNDTR register
|
||||
} DMA_InitTypeDef;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DMA_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_DMA_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DMA_Exported_Functions
|
||||
/// @{
|
||||
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* channel);
|
||||
void DMA_Init(DMA_Channel_TypeDef* channel, DMA_InitTypeDef* init_struct);
|
||||
void DMA_StructInit(DMA_InitTypeDef* init_struct);
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* channel, FunctionalState state);
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* channel, DMA_Interrupt_EN_TypeDef it, FunctionalState state);
|
||||
void DMA_ClearFlag(DMA_Flags_TypeDef flag);
|
||||
void DMA_ClearITPendingBit(DMA_Interrupts_TypeDef it);
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* channel, u16 length);
|
||||
u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* channel);
|
||||
FlagStatus DMA_GetFlagStatus(DMA_Flags_TypeDef flag);
|
||||
ITStatus DMA_GetITStatus(DMA_Interrupts_TypeDef it);
|
||||
|
||||
void exDMA_SetPeripheralAddress(DMA_Channel_TypeDef* channel, u32 addr);
|
||||
void exDMA_SetTransmitLen(DMA_Channel_TypeDef* channel, u16 len);
|
||||
void exDMA_SetMemoryAddress(DMA_Channel_TypeDef* channel, u32 addr);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_DMA_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,729 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file HAL_eth.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE HAL_eth.h EXAMPLES.
|
||||
/// ////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef __HAL_ETH_H
|
||||
#define __HAL_ETH_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "mm32_device.h"
|
||||
#include "HAL_eth_conf.h"
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup ETH_HAL
|
||||
/// @brief ETH HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup ETH_Exported_Types
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ETH | Header | Extra | VLAN tag | Payload | CRC |
|
||||
// Size | 14 | 2 | 4 | 46 ~ 1500 | 4 |
|
||||
#define ETH_MAX_PACKET_SIZE 1524
|
||||
#define ETH_HEADER 14 ///< MAC Dest Addr 6 byte + MAC Src Addr 6 byte + Lenth/Type 2 byte
|
||||
#define ETH_EXTRA 2
|
||||
#define VLAN_TAG 4
|
||||
#define ETH_PAYLOAD_MIN 46
|
||||
#define ETH_PAYLOAD_MAX 1500
|
||||
#define JUMBO_FRAME_PAYLOAD 9000
|
||||
|
||||
#ifndef ETH_RX_BUF_SIZE
|
||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
|
||||
#endif
|
||||
|
||||
#ifndef ETH_RX_BUF_NUM
|
||||
#define ETH_RX_BUF_NUM 4
|
||||
#endif
|
||||
|
||||
#ifndef ETH_TX_BUF_SIZE
|
||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
|
||||
#endif
|
||||
|
||||
#ifndef ETH_TX_BUF_NUM
|
||||
#define ETH_TX_BUF_NUM 4
|
||||
#endif
|
||||
|
||||
#define ETH_DMA_RDES_FL_Pos 16 ///< Ethernet DMA Received Frame Length Position
|
||||
|
||||
#define ETH_WAKEUP_REGISTER_LENGTH 8 ///< ETHERNET Remote Wake-up frame register length
|
||||
|
||||
#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 ///< ETHERNET Missed frames counter Shift
|
||||
|
||||
#define ETH_DMA_TDES_COLLISION_COUNTSHIFT 3 ///< ETHERNET DMA Tx descriptors Collision Count Shift
|
||||
#define ETH_DMA_TDES_BUFFER2_SIZESHIFT 11 ///< ETHERNET DMA Tx descriptors Buffer2 Size Shift
|
||||
|
||||
#define ETH_DMA_RDES_FRAME_LENGTHSHIFT 16 ///< ETHERNET DMA Rx descriptors Frame Length Shift
|
||||
#define ETH_DMA_RDES_BUFFER2_SIZESHIFT 11 ///< ETHERNET DMA Rx descriptors Buffer2 Size Shift
|
||||
|
||||
///< ETHERNET errors
|
||||
#define ETH_ERROR ((u32)0)
|
||||
#define ETH_SUCCESS ((u32)1)
|
||||
|
||||
|
||||
#ifdef _HAL_ETH_C_
|
||||
#define GLOBAL
|
||||
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief ETH Init Structure Definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
__IO u32 ETH_AutoNegotiation;
|
||||
__IO u32 ETH_Watchdog;
|
||||
__IO u32 ETH_Jabber;
|
||||
__IO u32 ETH_InterFrameGap;
|
||||
__IO u32 ETH_CarrierSense;
|
||||
__IO u32 ETH_Speed;
|
||||
__IO u32 ETH_ReceiveOwn;
|
||||
__IO u32 ETH_LoopbackMode;
|
||||
__IO u32 ETH_Mode;
|
||||
__IO u32 ETH_ChecksumOffload;
|
||||
__IO u32 ETH_RetryTransmission;
|
||||
__IO u32 ETH_AutomaticPadCRCStrip;
|
||||
__IO u32 ETH_BackOffLimit;
|
||||
__IO u32 ETH_DeferralCheck;
|
||||
__IO u32 ETH_ReceiveAll;
|
||||
__IO u32 ETH_SourceAddrFilter;
|
||||
__IO u32 ETH_PassControlFrames;
|
||||
__IO u32 ETH_BroadcastFramesReception;
|
||||
__IO u32 ETH_DestinationAddrFilter;
|
||||
__IO u32 ETH_PromiscuousMode;
|
||||
__IO u32 ETH_MulticastFramesFilter;
|
||||
__IO u32 ETH_UnicastFramesFilter;
|
||||
__IO u32 ETH_HashTableHigh;
|
||||
__IO u32 ETH_HashTableLow;
|
||||
__IO u32 ETH_PauseTime;
|
||||
__IO u32 ETH_ZeroQuantaPause;
|
||||
__IO u32 ETH_PauseLowThreshold;
|
||||
__IO u32 ETH_UnicastPauseFrameDetect;
|
||||
__IO u32 ETH_ReceiveFlowControl;
|
||||
__IO u32 ETH_TransmitFlowControl;
|
||||
__IO u32 ETH_VLANTagComparison;
|
||||
__IO u32 ETH_VLANTagIdentifier;
|
||||
__IO u32 ETH_DropTCPIPChecksumErrorFrame;
|
||||
__IO u32 ETH_ReceiveStoreForward;
|
||||
__IO u32 ETH_FlushReceivedFrame;
|
||||
__IO u32 ETH_TransmitStoreForward;
|
||||
__IO u32 ETH_TransmitThresholdControl;
|
||||
__IO u32 ETH_ForwardErrorFrames;
|
||||
__IO u32 ETH_ForwardUndersizedGoodFrames;
|
||||
__IO u32 ETH_ReceiveThresholdControl;
|
||||
__IO u32 ETH_SecondFrameOperate;
|
||||
__IO u32 ETH_AddressAlignedBeats;
|
||||
__IO u32 ETH_FixedBurst;
|
||||
__IO u32 ETH_RxDMABurstLength;
|
||||
__IO u32 ETH_TxDMABurstLength;
|
||||
__IO u32 ETH_DescriptorSkipLength;
|
||||
__IO u32 ETH_DMAArbitration;
|
||||
} ETH_InitTypeDef;
|
||||
|
||||
typedef struct {
|
||||
__IO u32 CS; ///< Control and Status
|
||||
__IO u32 BL; ///< Buffer1, Buffer2 lengths
|
||||
__IO u32 BUF1ADDR; ///< Buffer1 address pointer
|
||||
__IO u32 BUF2NDADDR; ///< Buffer2 or next descriptor address pointer
|
||||
|
||||
#ifdef USE_ENHANCED_DMA_DESCRIPTORS ///< Enhanced ETHERNET DMA PTP Descriptors
|
||||
__IO u32 ExtendedStatus; ///< Extended status for PTP receive descriptor
|
||||
__IO u32 Reserved1; ///< Reserved
|
||||
__IO u32 TimeStampLow; ///< Time Stamp Low value for transmit and receive
|
||||
__IO u32 TimeStampHigh; ///< Time Stamp High value for transmit and receive
|
||||
#endif
|
||||
} ETH_DMADESCTypeDef;
|
||||
|
||||
typedef struct {
|
||||
__IO u32 len;
|
||||
__IO u32 buf;
|
||||
__IO ETH_DMADESCTypeDef* ptrDesc;
|
||||
} FrameTypeDef;
|
||||
|
||||
typedef struct {
|
||||
__IO ETH_DMADESCTypeDef* ptrFS_Rx_Desc; ///< First Segment Rx Desc
|
||||
__IO ETH_DMADESCTypeDef* ptrLS_Rx_Desc; ///< Last Segment Rx Desc
|
||||
__IO u32 cnt; ///< Segment count
|
||||
} ETH_DMA_Rx_Frame_infos;
|
||||
|
||||
|
||||
|
||||
#define ETH_DMA_TDES_OWN ((u32)0x80000000) ///< OWN bit: descriptor is owned by DMA engine
|
||||
#define ETH_DMA_TDES_ES ((u32)0x00008000) ///< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT
|
||||
#define ETH_DMA_TDES_JT ((u32)0x00004000) ///< Jabber Timeout
|
||||
#define ETH_DMA_TDES_FF ((u32)0x00002000) ///< Frame Flushed: DMA/MTL flushed the frame due to SW flush
|
||||
#define ETH_DMA_TDES_LCA ((u32)0x00000800) ///< Loss of Carrier: carrier lost during transmission
|
||||
#define ETH_DMA_TDES_NC ((u32)0x00000400) ///< No Carrier: no carrier signal from the transceiver
|
||||
#define ETH_DMA_TDES_LCO ((u32)0x00000200) ///< Late Collision: transmission aborted due to collision
|
||||
#define ETH_DMA_TDES_EC ((u32)0x00000100) ///< Excessive Collision: transmission aborted after 16 collisions
|
||||
#define ETH_DMA_TDES_VF ((u32)0x00000080) ///< VLAN Frame
|
||||
#define ETH_DMA_TDES_CC ((u32)0x00000078) ///< Collision Count
|
||||
#define ETH_DMA_TDES_ED ((u32)0x00000004) ///< Excessive Deferral
|
||||
#define ETH_DMA_TDES_UF ((u32)0x00000002) ///< Underflow Error: late data arrival from the memory
|
||||
#define ETH_DMA_TDES_DB ((u32)0x00000001) ///< Deferred Bit
|
||||
|
||||
#define ETH_DMA_TDES_IC ((u32)0x80000000) ///< Interrupt on Completion
|
||||
#define ETH_DMA_TDES_LS ((u32)0x40000000) ///< Last Segment
|
||||
#define ETH_DMA_TDES_FS ((u32)0x20000000) ///< First Segment
|
||||
#define ETH_DMA_TDES_DC ((u32)0x04000000) ///< Disable CRC
|
||||
#define ETH_DMA_TDES_TER ((u32)0x02000000) ///< Transmit end of ring
|
||||
#define ETH_DMA_TDES_TCH ((u32)0x01000000) ///< Second Address Chained
|
||||
#define ETH_DMA_TDES_DP ((u32)0x00800000) ///< Disable Padding
|
||||
#define ETH_DMA_TDES_TBS2 ((u32)0x003FF800) ///< Transmit Buffer 2 Size
|
||||
#define ETH_DMA_TDES_TBS1 ((u32)0x000007FF) ///< Transmit Buffer 1 Size
|
||||
|
||||
#define ETH_DMA_TDES_B1AP ((u32)0xFFFFFFFF) ///< Buffer 1 Address Pointer
|
||||
|
||||
#define ETH_DMA_TDES_B2AP ((u32)0xFFFFFFFF) ///< Buffer 2 Address Pointer
|
||||
|
||||
#if defined(USE_ENHANCED_DMA_DESCRIPTORS)
|
||||
#define ETH_DMA_PTP_TDES_TTSL ((u32)0xFFFFFFFF) ///< Transmit Time Stamp Low
|
||||
#define ETH_DMA_PTP_TDES_TTSH ((u32)0xFFFFFFFF) ///< Transmit Time Stamp High
|
||||
#endif
|
||||
|
||||
#define ETH_DMA_RDES_OWN ((u32)0x80000000) ///< OWN bit: descriptor is owned by DMA engine
|
||||
#define ETH_DMA_RDES_AFM ((u32)0x40000000) ///< DA Filter Fail for the rx frame
|
||||
#define ETH_DMA_RDES_FL ((u32)0x3FFF0000) ///< Receive descriptor frame length
|
||||
#define ETH_DMA_RDES_ES ((u32)0x00008000) ///< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE
|
||||
#define ETH_DMA_RDES_DE ((u32)0x00004000) ///< Descriptor error: no more descriptors for receive frame
|
||||
#define ETH_DMA_RDES_SAF ((u32)0x00002000) ///< SA Filter Fail for the received frame
|
||||
#define ETH_DMA_RDES_LE ((u32)0x00001000) ///< Frame size not matching with length field
|
||||
#define ETH_DMA_RDES_OE ((u32)0x00000800) ///< Overflow Error: Frame was damaged due to buffer overflow
|
||||
#define ETH_DMA_RDES_VLAN ((u32)0x00000400) ///< VLAN Tag: received frame is a VLAN frame
|
||||
#define ETH_DMA_RDES_FS ((u32)0x00000200) ///< First descriptor of the frame
|
||||
#define ETH_DMA_RDES_LS ((u32)0x00000100) ///< Last descriptor of the frame
|
||||
#define ETH_DMA_RDES_IPV4HCE ((u32)0x00000080) ///< IPC Checksum Error: Rx Ipv4 header checksum error
|
||||
#define ETH_DMA_RDES_LC ((u32)0x00000040) ///< Late collision occurred during reception
|
||||
#define ETH_DMA_RDES_FT ((u32)0x00000020) ///< Frame type - Ethernet, otherwise 802.3
|
||||
#define ETH_DMA_RDES_RWT ((u32)0x00000010) ///< Receive Watchdog Timeout: watchdog timer expired during reception
|
||||
#define ETH_DMA_RDES_RE ((u32)0x00000008) ///< Receive error: error reported by MII interface
|
||||
#define ETH_DMA_RDES_DBE ((u32)0x00000004) ///< Dribble bit error: frame contains non int multiple of 8 bits
|
||||
#define ETH_DMA_RDES_CE ((u32)0x00000002) ///< CRC error
|
||||
#define ETH_DMA_RDES_MAMPCE ((u32)0x00000001) ///< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
|
||||
|
||||
#define ETH_DMA_RDES_DIC ((u32)0x80000000) ///< Disable Interrupt on Completion
|
||||
#define ETH_DMA_RDES_RER ((u32)0x02000000) ///< Receive End of Ring
|
||||
#define ETH_DMA_RDES_RCH ((u32)0x01000000) ///< Second Address Chained
|
||||
#define ETH_DMA_RDES_RBS2 ((u32)0x003FF800) ///< Receive Buffer2 Size
|
||||
#define ETH_DMA_RDES_RBS1 ((u32)0x000007FF) ///< Receive Buffer1 Size
|
||||
|
||||
#define ETH_DMA_RDES_B1AP ((u32)0xFFFFFFFF) ///< Buffer 1 Address Pointer
|
||||
|
||||
#define ETH_DMA_RDES_B2AP ((u32)0xFFFFFFFF) ///< Buffer 2 Address Pointer
|
||||
|
||||
|
||||
#if defined(USE_ENHANCED_DMA_DESCRIPTORS)
|
||||
#define ETH_DMA_PTP_RDES_PTPV ((u32)0x00002000) ///< PTP Version
|
||||
#define ETH_DMA_PTP_RDES_PTPFT ((u32)0x00001000) ///< PTP Frame Type
|
||||
#define ETH_DMA_PTP_RDES_PTPMT ((u32)0x00000F00) ///< PTP Message Type
|
||||
#define ETH_DMA_PTP_RDES_PTPMT_Sync ((u32)0x00000100) ///< SYNC message (all clock types)
|
||||
#define ETH_DMA_PTP_RDES_PTPMT_FollowUp ((u32)0x00000200) ///< FollowUp message (all clock types)
|
||||
#define ETH_DMA_PTP_RDES_PTPMT_DelayReq ((u32)0x00000300) ///< DelayReq message (all clock types)
|
||||
#define ETH_DMA_PTP_RDES_PTPMT_DelayResp ((u32)0x00000400) ///< DelayResp message (all clock types)
|
||||
#define ETH_DMA_PTP_RDES_PTPMT_PdelayReq_Announce ((u32)0x00000500) ///< PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock)
|
||||
#define ETH_DMA_PTP_RDES_PTPMT_PdelayResp_Manag ((u32)0x00000600) ///< PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock)
|
||||
#define ETH_DMA_PTP_RDES_PTPMT_PdelayRespFollowUp_Signal ((u32)0x00000700) ///< PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock)
|
||||
#define ETH_DMA_PTP_RDES_IPV6PR ((u32)0x00000080) ///< IPv6 Packet Received
|
||||
#define ETH_DMA_PTP_RDES_IPV4PR ((u32)0x00000040) ///< IPv4 Packet Received
|
||||
#define ETH_DMA_PTP_RDES_IPCB ((u32)0x00000020) ///< IP Checksum Bypassed
|
||||
#define ETH_DMA_PTP_RDES_IPPE ((u32)0x00000010) ///< IP Payload Error
|
||||
#define ETH_DMA_PTP_RDES_IPHE ((u32)0x00000008) ///< IP Header Error
|
||||
#define ETH_DMA_PTP_RDES_IPPT ((u32)0x00000007) ///< IP Payload Type
|
||||
#define ETH_DMA_PTP_RDES_IPPT_UDP ((u32)0x00000001) ///< UDP payload encapsulated in the IP datagram
|
||||
#define ETH_DMA_PTP_RDES_IPPT_TCP ((u32)0x00000002) ///< TCP payload encapsulated in the IP datagram
|
||||
#define ETH_DMA_PTP_RDES_IPPT_ICMP ((u32)0x00000003) ///< ICMP payload encapsulated in the IP datagram
|
||||
|
||||
|
||||
|
||||
#define ETH_DMA_PTP_RDES_TTSL ((u32)0xFFFFFFFF) ///< Receive Time Stamp Low
|
||||
#define ETH_DMA_PTP_RDES_TTSH ((u32)0xFFFFFFFF) ///< Receive Time Stamp High
|
||||
#endif
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#define PHY_READ_TIMEOUT ((u32)0x0004FFFF)
|
||||
#define PHY_WRITE_TIMEOUT ((u32)0x0004FFFF)
|
||||
|
||||
#define PHY_BCR 0 ///< Transceiver Basic Control Register
|
||||
#define PHY_BSR 1 ///< Transceiver Basic Status Register
|
||||
|
||||
#define PHY_Reset ((u16)0x8000) ///< PHY Reset
|
||||
#define PHY_Loopback ((u16)0x4000) ///< Select loop-back mode
|
||||
#define PHY_FULLDUPLEX_100M ((u16)0x2100) ///< Set the full-duplex mode at 100 Mb/s
|
||||
#define PHY_HALFDUPLEX_100M ((u16)0x2000) ///< Set the half-duplex mode at 100 Mb/s
|
||||
#define PHY_FULLDUPLEX_10M ((u16)0x0100) ///< Set the full-duplex mode at 10 Mb/s
|
||||
#define PHY_HALFDUPLEX_10M ((u16)0x0000) ///< Set the half-duplex mode at 10 Mb/s
|
||||
#define PHY_AutoNegotiation ((u16)0x1000) ///< Enable auto-negotiation function
|
||||
#define PHY_Restart_AutoNegotiation ((u16)0x0200) ///< Restart auto-negotiation function
|
||||
#define PHY_Powerdown ((u16)0x0800) ///< Select the power down mode
|
||||
#define PHY_Isolate ((u16)0x0400) ///< Isolate PHY from MII
|
||||
|
||||
#define PHY_AutoNego_Complete ((u16)0x0020) ///< Auto-Negotiation process completed
|
||||
#define PHY_Linked_Status ((u16)0x0004) ///< Valid link established
|
||||
#define PHY_Jabber_detection ((u16)0x0002) ///< Jabber condition detected
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#define ETH_AutoNegotiation_Enable ((u32)0x00000001)
|
||||
#define ETH_AutoNegotiation_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_Watchdog_Enable ((u32)0x00000000)
|
||||
#define ETH_Watchdog_Disable ((u32)0x00800000)
|
||||
|
||||
#define ETH_Jabber_Enable ((u32)0x00000000)
|
||||
#define ETH_Jabber_Disable ((u32)0x00400000)
|
||||
|
||||
#define ETH_InterFrameGap_96Bit ((u32)0x00000000) ///< minimum IFG between frames during transmission is 96Bit
|
||||
#define ETH_InterFrameGap_88Bit ((u32)0x00020000) ///< minimum IFG between frames during transmission is 88Bit
|
||||
#define ETH_InterFrameGap_80Bit ((u32)0x00040000) ///< minimum IFG between frames during transmission is 80Bit
|
||||
#define ETH_InterFrameGap_72Bit ((u32)0x00060000) ///< minimum IFG between frames during transmission is 72Bit
|
||||
#define ETH_InterFrameGap_64Bit ((u32)0x00080000) ///< minimum IFG between frames during transmission is 64Bit
|
||||
#define ETH_InterFrameGap_56Bit ((u32)0x000A0000) ///< minimum IFG between frames during transmission is 56Bit
|
||||
#define ETH_InterFrameGap_48Bit ((u32)0x000C0000) ///< minimum IFG between frames during transmission is 48Bit
|
||||
#define ETH_InterFrameGap_40Bit ((u32)0x000E0000) ///< minimum IFG between frames during transmission is 40Bit
|
||||
|
||||
#define ETH_CarrierSense_Enable ((u32)0x00000000)
|
||||
#define ETH_CarrierSense_Disable ((u32)0x00010000)
|
||||
|
||||
#define ETH_Speed_10M ((u32)0x00000000)
|
||||
#define ETH_Speed_100M ((u32)0x00004000)
|
||||
|
||||
#define ETH_ReceiveOwn_Enable ((u32)0x00000000)
|
||||
#define ETH_ReceiveOwn_Disable ((u32)0x00002000)
|
||||
|
||||
#define ETH_LoopbackMode_Enable ((u32)0x00001000)
|
||||
#define ETH_LoopbackMode_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_Mode_FullDuplex ((u32)0x00000800)
|
||||
#define ETH_Mode_HalfDuplex ((u32)0x00000000)
|
||||
|
||||
#define ETH_ChecksumOffload_Enable ((u32)0x00000400)
|
||||
#define ETH_ChecksumOffload_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_RetryTransmission_Enable ((u32)0x00000000)
|
||||
#define ETH_RetryTransmission_Disable ((u32)0x00000200)
|
||||
|
||||
#define ETH_AutomaticPadCRCStrip_Enable ((u32)0x00000080)
|
||||
#define ETH_AutomaticPadCRCStrip_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_BackOffLimit_10 ((u32)0x00000000)
|
||||
#define ETH_BackOffLimit_8 ((u32)0x00000020)
|
||||
#define ETH_BackOffLimit_4 ((u32)0x00000040)
|
||||
#define ETH_BackOffLimit_1 ((u32)0x00000060)
|
||||
|
||||
#define ETH_DeferralCheck_Enable ((u32)0x00000010)
|
||||
#define ETH_DeferralCheck_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_ReceiveAll_Enable ((u32)0x80000000)
|
||||
#define ETH_ReceiveAll_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_SourceAddrFilter_Normal_Enable ((u32)0x00000200)
|
||||
#define ETH_SourceAddrFilter_Inverse_Enable ((u32)0x00000300)
|
||||
#define ETH_SourceAddrFilter_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_PassControlFrames_BlockAll ((u32)0x00000040) ///< MAC filters all control frames from reaching the application
|
||||
#define ETH_PassControlFrames_ForwardAll ((u32)0x00000080) ///< MAC forwards all control frames to application even if they fail the Address Filter
|
||||
#define ETH_PassControlFrames_ForwardPassedAddrFilter ((u32)0x000000C0) ///< MAC forwards control frames that pass the Address Filter.
|
||||
|
||||
#define ETH_BroadcastFramesReception_Enable ((u32)0x00000000)
|
||||
#define ETH_BroadcastFramesReception_Disable ((u32)0x00000020)
|
||||
|
||||
#define ETH_DestinationAddrFilter_Normal ((u32)0x00000000)
|
||||
#define ETH_DestinationAddrFilter_Inverse ((u32)0x00000008)
|
||||
|
||||
#define ETH_PromiscuousMode_Enable ((u32)0x00000001)
|
||||
#define ETH_PromiscuousMode_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_MulticastFramesFilter_PerfectHashTable ((u32)0x00000404)
|
||||
#define ETH_MulticastFramesFilter_HashTable ((u32)0x00000004)
|
||||
#define ETH_MulticastFramesFilter_Perfect ((u32)0x00000000)
|
||||
#define ETH_MulticastFramesFilter_None ((u32)0x00000010)
|
||||
|
||||
#define ETH_UnicastFramesFilter_PerfectHashTable ((u32)0x00000402)
|
||||
#define ETH_UnicastFramesFilter_HashTable ((u32)0x00000002)
|
||||
#define ETH_UnicastFramesFilter_Perfect ((u32)0x00000000)
|
||||
|
||||
#define ETH_ZeroQuantaPause_Enable ((u32)0x00000000)
|
||||
#define ETH_ZeroQuantaPause_Disable ((u32)0x00000080)
|
||||
|
||||
#define ETH_PauseLowThreshold_Minus4 ((u32)0x00000000) ///< Pause time minus 4 slot times
|
||||
#define ETH_PauseLowThreshold_Minus28 ((u32)0x00000010) ///< Pause time minus 28 slot times
|
||||
#define ETH_PauseLowThreshold_Minus144 ((u32)0x00000020) ///< Pause time minus 144 slot times
|
||||
#define ETH_PauseLowThreshold_Minus256 ((u32)0x00000030) ///< Pause time minus 256 slot times
|
||||
|
||||
#define ETH_UnicastPauseFrameDetect_Enable ((u32)0x00000008)
|
||||
#define ETH_UnicastPauseFrameDetect_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_ReceiveFlowControl_Enable ((u32)0x00000004)
|
||||
#define ETH_ReceiveFlowControl_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_TransmitFlowControl_Enable ((u32)0x00000002)
|
||||
#define ETH_TransmitFlowControl_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_VLANTagComparison_12Bit ((u32)0x00010000)
|
||||
#define ETH_VLANTagComparison_16Bit ((u32)0x00000000)
|
||||
|
||||
#define ETH_MAC_FLAG_TST ((u32)0x00000200) ///< Time stamp trigger flag (on MAC)
|
||||
#define ETH_MAC_FLAG_MMCT ((u32)0x00000040) ///< MMC transmit flag
|
||||
#define ETH_MAC_FLAG_MMCR ((u32)0x00000020) ///< MMC receive flag
|
||||
#define ETH_MAC_FLAG_MMC ((u32)0x00000010) ///< MMC flag (on MAC)
|
||||
#define ETH_MAC_FLAG_PMT ((u32)0x00000008) ///< PMT flag (on MAC)
|
||||
|
||||
#define ETH_MAC_IT_TST ((u32)0x00000200) ///< Time stamp trigger interrupt (on MAC)
|
||||
#define ETH_MAC_IT_MMCT ((u32)0x00000040) ///< MMC transmit interrupt
|
||||
#define ETH_MAC_IT_MMCR ((u32)0x00000020) ///< MMC receive interrupt
|
||||
#define ETH_MAC_IT_MMC ((u32)0x00000010) ///< MMC interrupt (on MAC)
|
||||
#define ETH_MAC_IT_PMT ((u32)0x00000008) ///< PMT interrupt (on MAC)
|
||||
|
||||
#define ETH_MAC_Address0 ((u32)0x00000000)
|
||||
#define ETH_MAC_Address1 ((u32)0x00000008)
|
||||
#define ETH_MAC_Address2 ((u32)0x00000010)
|
||||
#define ETH_MAC_Address3 ((u32)0x00000018)
|
||||
|
||||
#define ETH_MAC_AddressFilter_SA ((u32)0x00000000)
|
||||
#define ETH_MAC_AddressFilter_DA ((u32)0x00000008)
|
||||
|
||||
#define ETH_MAC_AddressMask_Byte6 ((u32)0x20000000) ///< Mask MAC Address high reg bits [15:8]
|
||||
#define ETH_MAC_AddressMask_Byte5 ((u32)0x10000000) ///< Mask MAC Address high reg bits [7:0]
|
||||
#define ETH_MAC_AddressMask_Byte4 ((u32)0x08000000) ///< Mask MAC Address low reg bits [31:24]
|
||||
#define ETH_MAC_AddressMask_Byte3 ((u32)0x04000000) ///< Mask MAC Address low reg bits [23:16]
|
||||
#define ETH_MAC_AddressMask_Byte2 ((u32)0x02000000) ///< Mask MAC Address low reg bits [15:8]
|
||||
#define ETH_MAC_AddressMask_Byte1 ((u32)0x01000000) ///< Mask MAC Address low reg bits [70]
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#define ETH_DMA_TDES_LastSegment ((u32)0x40000000) ///< Last Segment
|
||||
#define ETH_DMA_TDES_FirstSegment ((u32)0x20000000) ///< First Segment
|
||||
|
||||
#define ETH_DMA_TDES_ChecksumByPass ((u32)0x00000000) ///< Checksum engine bypass
|
||||
#define ETH_DMA_TDES_ChecksumIPV4Header ((u32)0x00400000) ///< IPv4 header checksum insertion
|
||||
#define ETH_DMA_TDES_ChecksumTCPUDPICMPSegment ((u32)0x00800000) ///< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present
|
||||
#define ETH_DMA_TDES_ChecksumTCPUDPICMPFull ((u32)0x00C00000) ///< TCP/UDP/ICMP checksum fully in hardware including pseudo header
|
||||
|
||||
#define ETH_DMA_RDES_Buffer1 ((u32)0x00000000) ///< DMA Rx Desc Buffer1
|
||||
#define ETH_DMA_RDES_Buffer2 ((u32)0x00000001) ///< DMA Rx Desc Buffer2
|
||||
|
||||
#define ETH_DropTCPIPChecksumErrorFrame_Enable ((u32)0x00000000)
|
||||
#define ETH_DropTCPIPChecksumErrorFrame_Disable ((u32)0x04000000)
|
||||
|
||||
#define ETH_ReceiveStoreForward_Enable ((u32)0x02000000)
|
||||
#define ETH_ReceiveStoreForward_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_FlushReceivedFrame_Enable ((u32)0x00000000)
|
||||
#define ETH_FlushReceivedFrame_Disable ((u32)0x01000000)
|
||||
|
||||
#define ETH_TransmitStoreForward_Enable ((u32)0x00200000)
|
||||
#define ETH_TransmitStoreForward_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_TransmitThresholdControl_64Bytes ((u32)0x00000000) ///< threshold level of the MTL Transmit FIFO is 64 Bytes
|
||||
#define ETH_TransmitThresholdControl_128Bytes ((u32)0x00004000) ///< threshold level of the MTL Transmit FIFO is 128 Bytes
|
||||
#define ETH_TransmitThresholdControl_192Bytes ((u32)0x00008000) ///< threshold level of the MTL Transmit FIFO is 192 Bytes
|
||||
#define ETH_TransmitThresholdControl_256Bytes ((u32)0x0000C000) ///< threshold level of the MTL Transmit FIFO is 256 Bytes
|
||||
#define ETH_TransmitThresholdControl_40Bytes ((u32)0x00010000) ///< threshold level of the MTL Transmit FIFO is 40 Bytes
|
||||
#define ETH_TransmitThresholdControl_32Bytes ((u32)0x00014000) ///< threshold level of the MTL Transmit FIFO is 32 Bytes
|
||||
#define ETH_TransmitThresholdControl_24Bytes ((u32)0x00018000) ///< threshold level of the MTL Transmit FIFO is 24 Bytes
|
||||
#define ETH_TransmitThresholdControl_16Bytes ((u32)0x0001C000) ///< threshold level of the MTL Transmit FIFO is 16 Bytes
|
||||
|
||||
#define ETH_ForwardErrorFrames_Enable ((u32)0x00000080)
|
||||
#define ETH_ForwardErrorFrames_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_ForwardUndersizedGoodFrames_Enable ((u32)0x00000040)
|
||||
#define ETH_ForwardUndersizedGoodFrames_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_ReceiveThresholdControl_64Bytes ((u32)0x00000000) ///< threshold level of the MTL Receive FIFO is 64 Bytes
|
||||
#define ETH_ReceiveThresholdControl_32Bytes ((u32)0x00000008) ///< threshold level of the MTL Receive FIFO is 32 Bytes
|
||||
#define ETH_ReceiveThresholdControl_96Bytes ((u32)0x00000010) ///< threshold level of the MTL Receive FIFO is 96 Bytes
|
||||
#define ETH_ReceiveThresholdControl_128Bytes ((u32)0x00000018) ///< threshold level of the MTL Receive FIFO is 128 Bytes
|
||||
|
||||
#define ETH_SecondFrameOperate_Enable ((u32)0x00000004)
|
||||
#define ETH_SecondFrameOperate_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_AddressAlignedBeats_Enable ((u32)0x02000000)
|
||||
#define ETH_AddressAlignedBeats_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_FixedBurst_Enable ((u32)0x00010000)
|
||||
#define ETH_FixedBurst_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_RxDMABurstLength_1Beat ((u32)0x00020000) ///< maximum number of beats to be transferred in one RxDMA transaction is 1
|
||||
#define ETH_RxDMABurstLength_2Beat ((u32)0x00040000) ///< maximum number of beats to be transferred in one RxDMA transaction is 2
|
||||
#define ETH_RxDMABurstLength_4Beat ((u32)0x00080000) ///< maximum number of beats to be transferred in one RxDMA transaction is 4
|
||||
#define ETH_RxDMABurstLength_8Beat ((u32)0x00100000) ///< maximum number of beats to be transferred in one RxDMA transaction is 8
|
||||
#define ETH_RxDMABurstLength_16Beat ((u32)0x00200000) ///< maximum number of beats to be transferred in one RxDMA transaction is 16
|
||||
#define ETH_RxDMABurstLength_32Beat ((u32)0x00400000) ///< maximum number of beats to be transferred in one RxDMA transaction is 32
|
||||
#define ETH_RxDMABurstLength_4xPBL_4Beat ((u32)0x01020000) ///< maximum number of beats to be transferred in one RxDMA transaction is 4
|
||||
#define ETH_RxDMABurstLength_4xPBL_8Beat ((u32)0x01040000) ///< maximum number of beats to be transferred in one RxDMA transaction is 8
|
||||
#define ETH_RxDMABurstLength_4xPBL_16Beat ((u32)0x01080000) ///< maximum number of beats to be transferred in one RxDMA transaction is 16
|
||||
#define ETH_RxDMABurstLength_4xPBL_32Beat ((u32)0x01100000) ///< maximum number of beats to be transferred in one RxDMA transaction is 32
|
||||
#define ETH_RxDMABurstLength_4xPBL_64Beat ((u32)0x01200000) ///< maximum number of beats to be transferred in one RxDMA transaction is 64
|
||||
#define ETH_RxDMABurstLength_4xPBL_128Beat ((u32)0x01400000) ///< maximum number of beats to be transferred in one RxDMA transaction is 128
|
||||
|
||||
#define ETH_TxDMABurstLength_1Beat ((u32)0x00000100) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1
|
||||
#define ETH_TxDMABurstLength_2Beat ((u32)0x00000200) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2
|
||||
#define ETH_TxDMABurstLength_4Beat ((u32)0x00000400) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4
|
||||
#define ETH_TxDMABurstLength_8Beat ((u32)0x00000800) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8
|
||||
#define ETH_TxDMABurstLength_16Beat ((u32)0x00001000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16
|
||||
#define ETH_TxDMABurstLength_32Beat ((u32)0x00002000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32
|
||||
#define ETH_TxDMABurstLength_4xPBL_4Beat ((u32)0x01000100) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4
|
||||
#define ETH_TxDMABurstLength_4xPBL_8Beat ((u32)0x01000200) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8
|
||||
#define ETH_TxDMABurstLength_4xPBL_16Beat ((u32)0x01000400) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16
|
||||
#define ETH_TxDMABurstLength_4xPBL_32Beat ((u32)0x01000800) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32
|
||||
#define ETH_TxDMABurstLength_4xPBL_64Beat ((u32)0x01001000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64
|
||||
#define ETH_TxDMABurstLength_4xPBL_128Beat ((u32)0x01002000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128
|
||||
|
||||
#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((u32)0x00000000)
|
||||
#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((u32)0x00004000)
|
||||
#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((u32)0x00008000)
|
||||
#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((u32)0x0000C000)
|
||||
#define ETH_DMAArbitration_RxPriorTx ((u32)0x00000002)
|
||||
|
||||
#define ETH_DMA_FLAG_TST ((u32)0x20000000) ///< Time-stamp trigger interrupt (on DMA)
|
||||
#define ETH_DMA_FLAG_PMT ((u32)0x10000000) ///< PMT interrupt (on DMA)
|
||||
#define ETH_DMA_FLAG_MMC ((u32)0x08000000) ///< MMC interrupt (on DMA)
|
||||
#define ETH_DMA_FLAG_DataTransferError ((u32)0x00800000) ///< Error bits 0-Rx DMA, 1-Tx DMA
|
||||
#define ETH_DMA_FLAG_ReadWriteError ((u32)0x01000000) ///< Error bits 0-write trnsf, 1-read transfr
|
||||
#define ETH_DMA_FLAG_AccessError ((u32)0x02000000) ///< Error bits 0-data buffer, 1-desc. access
|
||||
#define ETH_DMA_FLAG_NIS ((u32)0x00010000) ///< Normal interrupt summary flag
|
||||
#define ETH_DMA_FLAG_AIS ((u32)0x00008000) ///< Abnormal interrupt summary flag
|
||||
#define ETH_DMA_FLAG_ER ((u32)0x00004000) ///< Early receive flag
|
||||
#define ETH_DMA_FLAG_FBE ((u32)0x00002000) ///< Fatal bus error flag
|
||||
#define ETH_DMA_FLAG_ET ((u32)0x00000400) ///< Early transmit flag
|
||||
#define ETH_DMA_FLAG_RWT ((u32)0x00000200) ///< Receive watchdog timeout flag
|
||||
#define ETH_DMA_FLAG_RPS ((u32)0x00000100) ///< Receive process stopped flag
|
||||
#define ETH_DMA_FLAG_RBU ((u32)0x00000080) ///< Receive buffer unavailable flag
|
||||
#define ETH_DMA_FLAG_R ((u32)0x00000040) ///< Receive flag
|
||||
#define ETH_DMA_FLAG_TU ((u32)0x00000020) ///< Underflow flag
|
||||
#define ETH_DMA_FLAG_RO ((u32)0x00000010) ///< Overflow flag
|
||||
#define ETH_DMA_FLAG_TJT ((u32)0x00000008) ///< Transmit jabber timeout flag
|
||||
#define ETH_DMA_FLAG_TBU ((u32)0x00000004) ///< Transmit buffer unavailable flag
|
||||
#define ETH_DMA_FLAG_TPS ((u32)0x00000002) ///< Transmit process stopped flag
|
||||
#define ETH_DMA_FLAG_T ((u32)0x00000001) ///< Transmit flag
|
||||
|
||||
#define ETH_DMA_IT_TST ((u32)0x20000000) ///< Time-stamp trigger interrupt (on DMA)
|
||||
#define ETH_DMA_IT_PMT ((u32)0x10000000) ///< PMT interrupt (on DMA)
|
||||
#define ETH_DMA_IT_MMC ((u32)0x08000000) ///< MMC interrupt (on DMA)
|
||||
#define ETH_DMA_IT_NIS ((u32)0x00010000) ///< Normal interrupt summary
|
||||
#define ETH_DMA_IT_AIS ((u32)0x00008000) ///< Abnormal interrupt summary
|
||||
#define ETH_DMA_IT_ER ((u32)0x00004000) ///< Early receive interrupt
|
||||
#define ETH_DMA_IT_FBE ((u32)0x00002000) ///< Fatal bus error interrupt
|
||||
#define ETH_DMA_IT_ET ((u32)0x00000400) ///< Early transmit interrupt
|
||||
#define ETH_DMA_IT_RWT ((u32)0x00000200) ///< Receive watchdog timeout interrupt
|
||||
#define ETH_DMA_IT_RPS ((u32)0x00000100) ///< Receive process stopped interrupt
|
||||
#define ETH_DMA_IT_RBU ((u32)0x00000080) ///< Receive buffer unavailable interrupt
|
||||
#define ETH_DMA_IT_R ((u32)0x00000040) ///< Receive interrupt
|
||||
#define ETH_DMA_IT_TU ((u32)0x00000020) ///< Underflow interrupt
|
||||
#define ETH_DMA_IT_RO ((u32)0x00000010) ///< Overflow interrupt
|
||||
#define ETH_DMA_IT_TJT ((u32)0x00000008) ///< Transmit jabber timeout interrupt
|
||||
#define ETH_DMA_IT_TBU ((u32)0x00000004) ///< Transmit buffer unavailable interrupt
|
||||
#define ETH_DMA_IT_TPS ((u32)0x00000002) ///< Transmit process stopped interrupt
|
||||
#define ETH_DMA_IT_T ((u32)0x00000001) ///< Transmit interrupt
|
||||
|
||||
#define ETH_DMA_TransmitProcess_Stopped ((u32)0x00000000) ///< Stopped - Reset or Stop Tx Command issued
|
||||
#define ETH_DMA_TransmitProcess_Fetching ((u32)0x00100000) ///< Running - fetching the Tx descriptor
|
||||
#define ETH_DMA_TransmitProcess_Waiting ((u32)0x00200000) ///< Running - waiting for status
|
||||
#define ETH_DMA_TransmitProcess_Reading ((u32)0x00300000) ///< Running - reading the data from host memory
|
||||
#define ETH_DMA_TransmitProcess_Suspended ((u32)0x00600000) ///< Suspended - Tx Descriptor unavailable
|
||||
#define ETH_DMA_TransmitProcess_Closing ((u32)0x00700000) ///< Running - closing Rx descriptor
|
||||
|
||||
#define ETH_DMA_ReceiveProcess_Stopped ((u32)0x00000000) ///< Stopped - Reset or Stop Rx Command issued
|
||||
#define ETH_DMA_ReceiveProcess_Fetching ((u32)0x00020000) ///< Running - fetching the Rx descriptor
|
||||
#define ETH_DMA_ReceiveProcess_Waiting ((u32)0x00060000) ///< Running - waiting for packet
|
||||
#define ETH_DMA_ReceiveProcess_Suspended ((u32)0x00080000) ///< Suspended - Rx Descriptor unavailable
|
||||
#define ETH_DMA_ReceiveProcess_Closing ((u32)0x000A0000) ///< Running - closing descriptor
|
||||
#define ETH_DMA_ReceiveProcess_Queuing ((u32)0x000E0000) ///< Running - queuing the receive frame into host memory
|
||||
|
||||
#define ETH_DMA_Overflow_RxFIFOCounter ((u32)0x10000000) ///< Overflow bit for FIFO overflow counter
|
||||
#define ETH_DMA_Overflow_MissedFrameCounter ((u32)0x00010000) ///< Overflow bit for missed frame counter
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#define ETH_PMT_FLAG_WUFFRPR ((u32)0x80000000) ///< Wake-Up Frame Filter Register Pointer Reset
|
||||
#define ETH_PMT_FLAG_WUFR ((u32)0x00000040) ///< Wake-Up Frame Received
|
||||
#define ETH_PMT_FLAG_MPR ((u32)0x00000020) ///< Magic Packet Received
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#define ETH_MMC_IT_TGF ((u32)0x00200000) ///< When Tx good frame counter reaches half the maximum value
|
||||
#define ETH_MMC_IT_TGFMSC ((u32)0x00008000) ///< When Tx good multi col counter reaches half the maximum value
|
||||
#define ETH_MMC_IT_TGFSC ((u32)0x00004000) ///< When Tx good single col counter reaches half the maximum value
|
||||
|
||||
#define ETH_MMC_IT_RGUF ((u32)0x10020000) ///< When Rx good unicast frames counter reaches half the maximum value
|
||||
#define ETH_MMC_IT_RFAE ((u32)0x10000040) ///< When Rx alignment error counter reaches half the maximum value
|
||||
#define ETH_MMC_IT_RFCE ((u32)0x10000020) ///< When Rx crc error counter reaches half the maximum value
|
||||
|
||||
#define ETH_MMCCR ((u32)0x00000100) ///< MMC CR register
|
||||
#define ETH_MMCRIR ((u32)0x00000104) ///< MMC RIR register
|
||||
#define ETH_MMCTIR ((u32)0x00000108) ///< MMC TIR register
|
||||
#define ETH_MMCRIMR ((u32)0x0000010C) ///< MMC RIMR register
|
||||
#define ETH_MMCTIMR ((u32)0x00000110) ///< MMC TIMR register
|
||||
#define ETH_MMCTGFSCCR ((u32)0x0000014C) ///< MMC TGFSCCR register
|
||||
#define ETH_MMCTGFMSCCR ((u32)0x00000150) ///< MMC TGFMSCCR register
|
||||
#define ETH_MMCTGFCR ((u32)0x00000168) ///< MMC TGFCR register
|
||||
#define ETH_MMCRFCECR ((u32)0x00000194) ///< MMC RFCECR register
|
||||
#define ETH_MMCRFAECR ((u32)0x00000198) ///< MMC RFAECR register
|
||||
#define ETH_MMCRGUFCR ((u32)0x000001C4) ///< MMC RGUFCR register
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#define ETH_PTP_FineUpdate ((u32)0x00000001) ///< Fine Update method
|
||||
#define ETH_PTP_CoarseUpdate ((u32)0x00000000) ///< Coarse Update method
|
||||
|
||||
#define ETH_PTP_FLAG_TSARU ((u32)0x00000020) ///< Addend Register Update
|
||||
#define ETH_PTP_FLAG_TSITE ((u32)0x00000010) ///< Time Stamp Interrupt Trigger
|
||||
#define ETH_PTP_FLAG_TSSTU ((u32)0x00000008) ///< Time Stamp Update
|
||||
#define ETH_PTP_FLAG_TSSTI ((u32)0x00000004) ///< Time Stamp Initialize
|
||||
|
||||
#define ETH_PTP_FLAG_TSTTR ((u32)0x10000002) ///< Time stamp target time reached
|
||||
#define ETH_PTP_FLAG_TSSO ((u32)0x10000001) ///< Time stamp seconds overflow
|
||||
|
||||
#define ETH_PTP_PositiveTime ((u32)0x00000000) ///< Positive time value
|
||||
#define ETH_PTP_NegativeTime ((u32)0x80000000) ///< Negative time value
|
||||
|
||||
#define ETH_PTPTSCR ((u32)0x00000700) ///< PTP TSCR register
|
||||
#define ETH_PTPSSIR ((u32)0x00000704) ///< PTP SSIR register
|
||||
#define ETH_PTPTSHR ((u32)0x00000708) ///< PTP TSHR register
|
||||
#define ETH_PTPTSLR ((u32)0x0000070C) ///< PTP TSLR register
|
||||
#define ETH_PTPTSHUR ((u32)0x00000710) ///< PTP TSHUR register
|
||||
#define ETH_PTPTSLUR ((u32)0x00000714) ///< PTP TSLUR register
|
||||
#define ETH_PTPTSAR ((u32)0x00000718) ///< PTP TSAR register
|
||||
#define ETH_PTPTTHR ((u32)0x0000071C) ///< PTP TTHR register
|
||||
#define ETH_PTPTTLR ((u32)0x00000720) ///< PTP TTLR register
|
||||
|
||||
#define ETH_PTPTSSR ((u32)0x00000728) ///< PTP TSSR register
|
||||
|
||||
#define ETH_PTP_OrdinaryClock ((u32)0x00000000) ///< Ordinary Clock
|
||||
#define ETH_PTP_BoundaryClock ((u32)0x00010000) ///< Boundary Clock
|
||||
#define ETH_PTP_EndToEndTransparentClock ((u32)0x00020000) ///< End To End Transparent Clock
|
||||
#define ETH_PTP_PeerToPeerTransparentClock ((u32)0x00030000) ///< Peer To Peer Transparent Clock
|
||||
|
||||
#define ETH_PTP_SnapshotMasterMessage ((u32)0x00008000) ///< Time stamp snapshot for message relevant to master enable
|
||||
#define ETH_PTP_SnapshotEventMessage ((u32)0x00004000) ///< Time stamp snapshot for event message enable
|
||||
#define ETH_PTP_SnapshotIPV4Frames ((u32)0x00002000) ///< Time stamp snapshot for IPv4 frames enable
|
||||
#define ETH_PTP_SnapshotIPV6Frames ((u32)0x00001000) ///< Time stamp snapshot for IPv6 frames enable
|
||||
#define ETH_PTP_SnapshotPTPOverEthernetFrames ((u32)0x00000800) ///< Time stamp snapshot for PTP over ethernet frames enable
|
||||
#define ETH_PTP_SnapshotAllReceivedFrames ((u32)0x00000100) ///< Time stamp snapshot for all received frames enable
|
||||
|
||||
#define ETH_MAC_ADDR_HBASE (ETH_BASE + 0x40) ///< ETHERNET MAC address high offset
|
||||
#define ETH_MAC_ADDR_LBASE (ETH_BASE + 0x44) ///< ETHERNET MAC address low offset
|
||||
|
||||
#define MACMIIAR_CR_MASK ((u32)0xFFFFFFE3)
|
||||
|
||||
#define MACCR_CLEAR_MASK ((u32)0xFF20810F)
|
||||
#define MACFCR_CLEAR_MASK ((u32)0x0000FF41)
|
||||
#define DMAOMR_CLEAR_MASK ((u32)0xF8DE3F23)
|
||||
|
||||
|
||||
|
||||
GLOBAL __IO ETH_DMADESCTypeDef* DMATxDescToSet;
|
||||
GLOBAL __IO ETH_DMADESCTypeDef* DMARxDescToGet;
|
||||
|
||||
GLOBAL ETH_DMA_Rx_Frame_infos RX_Frame_Descriptor;
|
||||
GLOBAL __IO ETH_DMA_Rx_Frame_infos* DMA_RX_FRAME_infos;
|
||||
GLOBAL __IO u32 Frame_Rx_index;
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
void ETH_DeInit(void);
|
||||
void ETH_StructInit(ETH_InitTypeDef* ptr);
|
||||
u32 ETH_Init(ETH_InitTypeDef* ptr, u16 phy_addr);
|
||||
void ETH_Start(void);
|
||||
void ETH_Stop(void);
|
||||
void ETH_MACTransmissionCmd(FunctionalState sta);
|
||||
void ETH_MACReceptionCmd(FunctionalState sta);
|
||||
FlagStatus ETH_GetFlowControlBusyStatus(void);
|
||||
void ETH_InitiatePauseControlFrame(void);
|
||||
void ETH_BackPressureActivationCmd(FunctionalState sta);
|
||||
void ETH_MACAddressConfig(u32 reg_addr, u8* mac_addr);
|
||||
void ETH_GetMACAddress(u32 reg_addr, u8* mac_addr);
|
||||
void ETH_MACAddressPerfectFilterCmd(u32 reg_addr, FunctionalState sta);
|
||||
void ETH_MACAddressFilterConfig(u32 reg_addr, u32 sta);
|
||||
void ETH_MACAddressMaskBytesFilterConfig(u32 reg_addr, u32 mask_byte);
|
||||
FrameTypeDef ETH_Get_Received_Frame(void);
|
||||
FrameTypeDef ETH_Get_Received_Frame_interrupt(void);
|
||||
u32 ETH_Prepare_Transmit_Descriptors(u16 len);
|
||||
void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt);
|
||||
u32 ETH_CheckFrameReceived(void);
|
||||
void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt);
|
||||
FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag);
|
||||
u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef* ptr_desc);
|
||||
void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc);
|
||||
void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
|
||||
void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val);
|
||||
void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val);
|
||||
void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
|
||||
void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
|
||||
void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
|
||||
void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef* ptr_desc, u32 buf1_size, u32 buf2_size);
|
||||
FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag);
|
||||
void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc);
|
||||
u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef* ptr_desc);
|
||||
void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
|
||||
u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef* ptr_desc, u32 buf);
|
||||
u32 ETH_GetRxPktSize(ETH_DMADESCTypeDef* ptr_desc);
|
||||
void ETH_SoftwareReset(void);
|
||||
FlagStatus ETH_GetSoftwareResetStatus(void);
|
||||
FlagStatus ETH_GetDMAFlagStatus(u32 flag);
|
||||
void ETH_DMAClearFlag(u32 flag);
|
||||
void ETH_DMAITConfig(u32 it, FunctionalState sta);
|
||||
ITStatus ETH_GetDMAITStatus(u32 it);
|
||||
void ETH_DMAClearITPendingBit(u32 it);
|
||||
u32 ETH_GetTransmitProcessState(void);
|
||||
u32 ETH_GetReceiveProcessState(void);
|
||||
void ETH_FlushTransmitFIFO(void);
|
||||
FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
|
||||
void ETH_DMATransmissionCmd(FunctionalState sta);
|
||||
void ETH_DMAReceptionCmd(FunctionalState sta);
|
||||
FlagStatus ETH_GetDMAOverflowStatus(u32 val);
|
||||
u32 ETH_GetRxOverflowMissedFrameCounter(void);
|
||||
u32 ETH_GetBufferUnavailableMissedFrameCounter(void);
|
||||
u32 ETH_GetCurrentTxDescStartAddress(void);
|
||||
u32 ETH_GetCurrentRxDescStartAddress(void);
|
||||
u32 ETH_GetCurrentTxBufferAddress(void);
|
||||
u32 ETH_GetCurrentRxBufferAddress(void);
|
||||
void ETH_ResumeDMATransmission(void);
|
||||
void ETH_ResumeDMAReception(void);
|
||||
void ETH_SetReceiveWatchdogTimer(u8 val);
|
||||
u16 ETH_ReadPHYRegister(u16 addr, u16 reg);
|
||||
u16 ETH_WritePHYRegister(u16 addr, u16 reg, u16 val);
|
||||
u32 ETH_PHYLoopBackCmd(u16 addr, FunctionalState sta);
|
||||
void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
|
||||
void ETH_SetWakeUpFrameFilterRegister(u32* buf);
|
||||
void ETH_GlobalUnicastWakeUpCmd(FunctionalState sta);
|
||||
FlagStatus ETH_GetPMTFlagStatus(u32 flag);
|
||||
void ETH_WakeUpFrameDetectionCmd(FunctionalState sta);
|
||||
void ETH_MagicPacketDetectionCmd(FunctionalState sta);
|
||||
void ETH_PowerDownCmd(FunctionalState sta);
|
||||
void ETH_MMCCounterFullPreset(void);
|
||||
void ETH_MMCCounterHalfPreset(void);
|
||||
void ETH_MMCCounterFreezeCmd(FunctionalState sta);
|
||||
void ETH_MMCResetOnReadCmd(FunctionalState sta);
|
||||
void ETH_MMCCounterRolloverCmd(FunctionalState sta);
|
||||
void ETH_MMCCountersReset(void);
|
||||
void ETH_MMCITConfig(u32 it, FunctionalState sta);
|
||||
ITStatus ETH_GetMMCITStatus(u32 it);
|
||||
u32 ETH_GetMMCRegister(u32 reg);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_ETH_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,68 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_eth_conf.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE hal_eth_conf.h EXAMPLES.
|
||||
/// ////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef __HAL_ETH_CONF_H
|
||||
#define __HAL_ETH_CONF_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup ETH_HAL
|
||||
/// @brief ETH HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup ETH_Exported_Types
|
||||
/// @{
|
||||
|
||||
|
||||
// #define USE_ENHANCED_DMA_DESCRIPTORS
|
||||
// #define CUSTOM_DRIVER_BUFFERS_CONFIG
|
||||
#define DP83848
|
||||
|
||||
#ifdef CUSTOM_DRIVER_BUFFERS_CONFIG
|
||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
|
||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
|
||||
#define ETH_RX_BUF_NUM 4
|
||||
#define ETH_TX_BUF_NUM 4
|
||||
#endif
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#if defined(DP83848)
|
||||
#define PHY_SR ((u16)0x10)
|
||||
#define PHY_SR_LINKSTATUS ((u16)0x0001)
|
||||
#define PHY_SPEED_STATUS ((u16)0x0002)
|
||||
#define PHY_DUPLEX_STATUS ((u16)0x0004)
|
||||
|
||||
#define PHY_MICR ((u16)0x11)
|
||||
#define PHY_MICR_INT_EN ((u16)0x0002)
|
||||
#define PHY_MICR_INT_OE ((u16)0x0001)
|
||||
|
||||
#define PHY_MISR ((u16)0x12)
|
||||
#define PHY_MISR_LINK_INT_EN ((u16)0x0020)
|
||||
#define PHY_LINK_STATUS ((u16)0x2000)
|
||||
#endif
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_ETH_CONF_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,181 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_exti.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE EXTI
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_EXTI_H
|
||||
#define __HAL_EXTI_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
#include "reg_exti.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup EXTI_HAL
|
||||
/// @brief EXTI HAL modules
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup EXTI_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief EXTI mode enumeration
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
EXTI_Mode_Interrupt = 0x00, ///< EXTI interrupt mode
|
||||
EXTI_Mode_Event = 0x04 ///< EXTI event mode
|
||||
} EXTIMode_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief EXTI Trigger enumeration
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
EXTI_Trigger_Rising = 0x08, ///< EXTI rising edge triggering
|
||||
EXTI_Trigger_Falling = 0x0C, ///< EXTI falling edge triggering
|
||||
EXTI_Trigger_Rising_Falling = 0x10 ///< EXTI rising and falling edge triggers
|
||||
} EXTITrigger_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief EXTI Init Structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u32 EXTI_Line; ///< Specifies the EXTI lines to be enabled or disabled.
|
||||
///< This parameter can be any combination of @ref EXTI_Lines
|
||||
EXTIMode_TypeDef EXTI_Mode; ///< Specifies the mode for the EXTI lines.
|
||||
///< This parameter can be a value of @ref EXTIMode_TypeDef
|
||||
EXTITrigger_TypeDef EXTI_Trigger; ///< Specifies the trigger signal active edge for the EXTI lines.
|
||||
///< This parameter can be a value of @ref EXTIMode_TypeDef
|
||||
FunctionalState EXTI_LineCmd; ///< Specifies the new state of the selected EXTI lines.
|
||||
///< This parameter can be set either to ENABLE or DISABLE
|
||||
} EXTI_InitTypeDef;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup EXTI_Exported_Constants
|
||||
/// @{
|
||||
|
||||
|
||||
|
||||
#define EXTI_LineNone ((u32)0x0000000) ///< No interrupt selected
|
||||
#define EXTI_Line0 ((u32)0x0000001) ///< External interrupt line 0
|
||||
#define EXTI_Line1 ((u32)0x0000002) ///< External interrupt line 1
|
||||
#define EXTI_Line2 ((u32)0x0000004) ///< External interrupt line 2
|
||||
#define EXTI_Line3 ((u32)0x0000008) ///< External interrupt line 3
|
||||
#define EXTI_Line4 ((u32)0x0000010) ///< External interrupt line 4
|
||||
#define EXTI_Line5 ((u32)0x0000020) ///< External interrupt line 5
|
||||
#define EXTI_Line6 ((u32)0x0000040) ///< External interrupt line 6
|
||||
#define EXTI_Line7 ((u32)0x0000080) ///< External interrupt line 7
|
||||
#define EXTI_Line8 ((u32)0x0000100) ///< External interrupt line 8
|
||||
#define EXTI_Line9 ((u32)0x0000200) ///< External interrupt line 9
|
||||
#define EXTI_Line10 ((u32)0x0000400) ///< External interrupt line 10
|
||||
#define EXTI_Line11 ((u32)0x0000800) ///< External interrupt line 11
|
||||
#define EXTI_Line12 ((u32)0x0001000) ///< External interrupt line 12
|
||||
#define EXTI_Line13 ((u32)0x0002000) ///< External interrupt line 13
|
||||
#define EXTI_Line14 ((u32)0x0004000) ///< External interrupt line 14
|
||||
#define EXTI_Line15 ((u32)0x0008000) ///< External interrupt line 15
|
||||
#define EXTI_Line16 ((u32)0x0010000) ///< External interrupt line 16 Connected to the PVD Output
|
||||
#define EXTI_Line17 ((u32)0x0020000) ///< External interrupt line 17 Connected to the RTC Alarm event
|
||||
#define EXTI_Line18 ((u32)0x0040000) ///< External interrupt line 18 Connected to the USB Wakeup from suspend event
|
||||
#define EXTI_Line19 ((u32)0x0080000) ///< External interrupt line 19
|
||||
#define EXTI_Line20 ((u32)0x0100000) ///< External interrupt line 20
|
||||
#define EXTI_Line21 ((u32)0x0200000) ///< External interrupt line 21
|
||||
#define EXTI_Line22 ((u32)0x0400000) ///< External interrupt line 22
|
||||
#define EXTI_Line23 ((u32)0x0800000) ///< External interrupt line 23
|
||||
#define EXTI_Line24 ((u32)0x1000000) ///< External interrupt line 24
|
||||
|
||||
#define EXTI_PortSourceGPIOA (0x00U)
|
||||
#define EXTI_PortSourceGPIOB (0x01U)
|
||||
#define EXTI_PortSourceGPIOC (0x02U)
|
||||
#define EXTI_PortSourceGPIOD (0x03U)
|
||||
#define EXTI_PortSourceGPIOE (0x04U)
|
||||
#define EXTI_PortSourceGPIOF (0x05U)
|
||||
|
||||
#define EXTI_PinSource0 (0x00U)
|
||||
#define EXTI_PinSource1 (0x01U)
|
||||
#define EXTI_PinSource2 (0x02U)
|
||||
#define EXTI_PinSource3 (0x03U)
|
||||
#define EXTI_PinSource4 (0x04U)
|
||||
#define EXTI_PinSource5 (0x05U)
|
||||
#define EXTI_PinSource6 (0x06U)
|
||||
#define EXTI_PinSource7 (0x07U)
|
||||
#define EXTI_PinSource8 (0x08U)
|
||||
#define EXTI_PinSource9 (0x09U)
|
||||
#define EXTI_PinSource10 (0x0AU)
|
||||
#define EXTI_PinSource11 (0x0BU)
|
||||
#define EXTI_PinSource12 (0x0CU)
|
||||
#define EXTI_PinSource13 (0x0DU)
|
||||
#define EXTI_PinSource14 (0x0EU)
|
||||
#define EXTI_PinSource15 (0x0FU)
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup EXTI_Exported_Variables
|
||||
/// @{
|
||||
|
||||
#ifdef _HAL_EXTI_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup EXTI_Exported_Functions
|
||||
/// @{
|
||||
|
||||
FlagStatus EXTI_GetFlagStatus(u32 line);
|
||||
ITStatus EXTI_GetITStatus(u32 line);
|
||||
|
||||
void EXTI_DeInit(void);
|
||||
void EXTI_Init(EXTI_InitTypeDef* init_struct);
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* init_struct);
|
||||
void EXTI_GenerateSWInterrupt(u32 line);
|
||||
void EXTI_ClearFlag(u32 line);
|
||||
void EXTI_ClearITPendingBit(u32 line);
|
||||
void exEXTI_LineDisable(u32 line);
|
||||
u32 exEXTI_GetAllFlagStatus(void);
|
||||
|
||||
|
||||
void EXTI_MemoryRemapConfig(u32 memory_remap);
|
||||
void EXTI_LineConfig(u8 port_source_gpio, u8 pin_source);
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_EXTI_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,230 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_flash.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE FLASH
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_FLASH_H
|
||||
#define __HAL_FLASH_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
#include "reg_flash.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup FLASH_HAL
|
||||
/// @brief FLASH HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup FLASH_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief FLASH Status
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
FLASH_BUSY = 1, ///< FLASH busy status
|
||||
FLASH_ERROR_PG, ///< FLASH programming error status
|
||||
FLASH_ERROR_WRP, ///< FLASH write protection error status
|
||||
FLASH_COMPLETE, ///< FLASH end of operation status
|
||||
FLASH_TIMEOUT ///< FLASH Last operation timed out status
|
||||
} FLASH_Status;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief FLASH Latency
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
FLASH_Latency_0 = FLASH_ACR_LATENCY_0, ///< FLASH Zero Latency cycle
|
||||
FLASH_Latency_1 = FLASH_ACR_LATENCY_1, ///< FLASH One Latency cycle
|
||||
FLASH_Latency_2 = FLASH_ACR_LATENCY_2, ///< FLASH Two Latency cycles
|
||||
FLASH_Latency_3 = FLASH_ACR_LATENCY_3 ///< FLASH Three Latency cycles
|
||||
} FLASH_Latency_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Half_Cycle_Enable_Disable
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
FLASH_HalfCycleAccess_Enable = FLASH_ACR_HLFCYA, ///< FLASH Half Cycle Enable
|
||||
FLASH_HalfCycleAccess_Disable = (s32)~FLASH_ACR_HLFCYA ///< FLASH Half Cycle Disable
|
||||
} FLASH_HalfCycleAccess_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Prefetch_Buffer_Enable_Disable
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
FLASH_PrefetchBuffer_Enable = FLASH_ACR_PRFTBE, ///< FLASH Prefetch Buffer Enable
|
||||
FLASH_PrefetchBuffer_Disable = (s32)~FLASH_ACR_PRFTBE ///< FLASH Prefetch Buffer Disable
|
||||
} FLASH_PrefetchBuffer_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Option_Bytes_IWatchdog
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
OB_IWDG_SW = 0x0001, ///< Software IWDG selected
|
||||
OB_IWDG_HW = 0x0000 ///< Hardware IWDG selected
|
||||
} OB_IWDG_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Option_Bytes_nRST_STOP
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
OB_STOP_NoRST = 0x0002, ///< No reset generated when entering in STOP
|
||||
OB_STOP_RST = 0x0000 ///< Reset generated when entering in STOP
|
||||
} OB_STOP_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Option_Bytes_nRST_STDBY
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
OB_STDBY_NoRST = 0x0004, ///< No reset generated when entering in STANDBY
|
||||
OB_STDBY_RST = 0x0000 ///< Reset generated when entering in STANDBY
|
||||
} OB_STDBY_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief FLASH_Interrupts
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
FLASH_IT_ERROR = FLASH_CR_ERRIE, ///< FPEC error interrupt source
|
||||
FLASH_IT_EOP = FLASH_CR_EOPIE ///< End of FLASH Operation Interrupt source
|
||||
} FLASH_IT_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief FLASH_Flags
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
FLASH_FLAG_EOP = FLASH_SR_EOP, ///< FLASH End of Operation flag
|
||||
FLASH_FLAG_PGERR = FLASH_SR_PGERR, ///< FLASH Program error flag
|
||||
FLASH_FLAG_WRPRTERR = FLASH_SR_WRPRTERR, ///< FLASH Write protected error flag
|
||||
FLASH_FLAG_BSY = FLASH_SR_BUSY, ///< FLASH Busy flag
|
||||
FLASH_FLAG_OPTERR = FLASH_OBR_OPTERR ///< FLASH Option Byte error flag
|
||||
} FLASH_FLAG_TypeDef;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup FLASH_Exported_Constants
|
||||
/// @{
|
||||
|
||||
|
||||
#define RDP_Key ((u16)0x00A5)
|
||||
#define FLASH_KEY1 ((u32)0x45670123)
|
||||
#define FLASH_KEY2 ((u32)0xCDEF89AB)
|
||||
#define EraseTimeout ((u32)0x00000FFF)
|
||||
#define ProgramTimeout ((u32)0x0000000F)
|
||||
|
||||
#define FLASH_WRProt_Pages0to3 ((u32)0x00000001) ///< Write protection of page 0 to 3
|
||||
#define FLASH_WRProt_Pages4to7 ((u32)0x00000002) ///< Write protection of page 4 to 7
|
||||
#define FLASH_WRProt_Pages8to11 ((u32)0x00000004) ///< Write protection of page 8 to 11
|
||||
#define FLASH_WRProt_Pages12to15 ((u32)0x00000008) ///< Write protection of page 12 to 15
|
||||
#define FLASH_WRProt_Pages16to19 ((u32)0x00000010) ///< Write protection of page 16 to 19
|
||||
#define FLASH_WRProt_Pages20to23 ((u32)0x00000020) ///< Write protection of page 20 to 23
|
||||
#define FLASH_WRProt_Pages24to27 ((u32)0x00000040) ///< Write protection of page 24 to 27
|
||||
#define FLASH_WRProt_Pages28to31 ((u32)0x00000080) ///< Write protection of page 28 to 31
|
||||
#define FLASH_WRProt_Pages32to35 ((u32)0x00000100) ///< Write protection of page 32 to 35
|
||||
#define FLASH_WRProt_Pages36to39 ((u32)0x00000200) ///< Write protection of page 36 to 39
|
||||
#define FLASH_WRProt_Pages40to43 ((u32)0x00000400) ///< Write protection of page 40 to 43
|
||||
#define FLASH_WRProt_Pages44to47 ((u32)0x00000800) ///< Write protection of page 44 to 47
|
||||
#define FLASH_WRProt_Pages48to51 ((u32)0x00001000) ///< Write protection of page 48 to 51
|
||||
#define FLASH_WRProt_Pages52to55 ((u32)0x00002000) ///< Write protection of page 52 to 55
|
||||
#define FLASH_WRProt_Pages56to59 ((u32)0x00004000) ///< Write protection of page 56 to 59
|
||||
#define FLASH_WRProt_Pages60to63 ((u32)0x00008000) ///< Write protection of page 60 to 63
|
||||
#define FLASH_WRProt_Pages64to67 ((u32)0x00010000) ///< Write protection of page 64 to 67
|
||||
#define FLASH_WRProt_Pages68to71 ((u32)0x00020000) ///< Write protection of page 68 to 71
|
||||
#define FLASH_WRProt_Pages72to75 ((u32)0x00040000) ///< Write protection of page 72 to 75
|
||||
#define FLASH_WRProt_Pages76to79 ((u32)0x00080000) ///< Write protection of page 76 to 79
|
||||
#define FLASH_WRProt_Pages80to83 ((u32)0x00100000) ///< Write protection of page 80 to 83
|
||||
#define FLASH_WRProt_Pages84to87 ((u32)0x00200000) ///< Write protection of page 84 to 87
|
||||
#define FLASH_WRProt_Pages88to91 ((u32)0x00400000) ///< Write protection of page 88 to 91
|
||||
#define FLASH_WRProt_Pages92to95 ((u32)0x00800000) ///< Write protection of page 92 to 95
|
||||
#define FLASH_WRProt_Pages96to99 ((u32)0x01000000) ///< Write protection of page 96 to 99
|
||||
#define FLASH_WRProt_Pages100to103 ((u32)0x02000000) ///< Write protection of page 100 to 103
|
||||
#define FLASH_WRProt_Pages104to107 ((u32)0x04000000) ///< Write protection of page 104 to 107
|
||||
#define FLASH_WRProt_Pages108to111 ((u32)0x08000000) ///< Write protection of page 108 to 111
|
||||
#define FLASH_WRProt_Pages112to115 ((u32)0x10000000) ///< Write protection of page 112 to 115
|
||||
#define FLASH_WRProt_Pages116to119 ((u32)0x20000000) ///< Write protection of page 115 to 119
|
||||
#define FLASH_WRProt_Pages120to123 ((u32)0x40000000) ///< Write protection of page 120 to 123
|
||||
#define FLASH_WRProt_Pages124to127 ((u32)0x80000000) ///< Write protection of page 124 to 127
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup FLASH_Exported_Variables
|
||||
/// @{
|
||||
|
||||
#ifdef _HAL_FLASH_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup FLASH_Exported_Functions
|
||||
/// @{
|
||||
void FLASH_SetLatency(FLASH_Latency_TypeDef latency);
|
||||
void FLASH_HalfCycleAccessCmd(FLASH_HalfCycleAccess_TypeDef half_cycle_access);
|
||||
void FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_TypeDef prefetch_buffer);
|
||||
void FLASH_Unlock(void);
|
||||
void FLASH_Lock(void);
|
||||
void FLASH_OPTB_Enable(void);
|
||||
void FLASH_ITConfig(FLASH_IT_TypeDef interrupt, FunctionalState state);
|
||||
void FLASH_ClearFlag(u16 flag);
|
||||
void exFLASH_EraseEE(u32 page_address);
|
||||
void exFLASH_ProgramEE(u16* buf, u32 address, u16 len);
|
||||
void exFLASH_WriteEE(u16* buf, u32 page_address, u16 len);
|
||||
void* exFLASH_Locate(u32 page_address, u16 len);
|
||||
void* exFLASH_ReadEE(u32 page_address, u16 len);
|
||||
|
||||
u8 exFLASH_FindEmpty(u16* ptr, u16 len);
|
||||
u32 FLASH_GetUserOptionByte(void);
|
||||
u32 FLASH_GetWriteProtectionOptionByte(void);
|
||||
|
||||
FLASH_Status FLASH_ErasePage(u32 page_address);
|
||||
FLASH_Status FLASH_EraseAllPages(void);
|
||||
FLASH_Status FLASH_EraseOptionBytes(void);
|
||||
FLASH_Status FLASH_EraseProtect(void);
|
||||
FLASH_Status FLASH_ProgramHalfWord(u32 address, u16 data);
|
||||
FLASH_Status FLASH_ProgramWord(u32 address, u32 data);
|
||||
FLASH_Status FLASH_ProgramOptionHalfWord(u32 address, u16 data);
|
||||
FLASH_Status FLASH_ProgramOptionByteData(u32 address, u8 data);
|
||||
FLASH_Status FLASH_ProgramProtect(u32 address, u16 data);
|
||||
FLASH_Status FLASH_EnableWriteProtection(u32 page);
|
||||
FLASH_Status FLASH_UserOptionByteConfig(OB_IWDG_TypeDef ob_iwdg, OB_STOP_TypeDef ob_stop, OB_STDBY_TypeDef ob_standby);
|
||||
FLASH_Status FLASH_GetStatus(void);
|
||||
FLASH_Status FLASH_WaitForLastOperation(u32 time_out);
|
||||
FLASH_Status FLASH_ReadOutProtection(FunctionalState state);
|
||||
FlagStatus FLASH_GetPrefetchBufferStatus(void);
|
||||
FlagStatus FLASH_GetFlagStatus(u16 flag);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_FLASH_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,147 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_fsmc.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SDIO
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_FSMC_H
|
||||
#define __HAL_FSMC_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
#include "reg_fsmc.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup FSMC_HAL
|
||||
/// @brief FSMC HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup FSMC_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief FSMC_interrupts_define
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// Timing parameter configuration register set selection register set0 register set1 register set2
|
||||
|
||||
#define FSMC_TimingRegSelect_0 ((u32)0x00000000)
|
||||
#define FSMC_TimingRegSelect_1 ((u32)0x00000100)
|
||||
#define FSMC_TimingRegSelect_2 ((u32)0x00000200)
|
||||
|
||||
// Capacity of external device
|
||||
#define FSMC_MemSize_None ((u32)0x00000000)
|
||||
#define FSMC_MemSize_64KB ((u32)0x00000001)
|
||||
#define FSMC_MemSize_128KB ((u32)0x00000002)
|
||||
#define FSMC_MemSize_256KB ((u32)0x00000002)
|
||||
#define FSMC_MemSize_512KB ((u32)0x00000004)
|
||||
#define FSMC_MemSize_1MB ((u32)0x00000005)
|
||||
#define FSMC_MemSize_2MB ((u32)0x00000006)
|
||||
#define FSMC_MemSize_4MB ((u32)0x00000007)
|
||||
#define FSMC_MemSize_8MB ((u32)0x00000008)
|
||||
#define FSMC_MemSize_16MB ((u32)0x00000009)
|
||||
#define FSMC_MemSize_32MB ((u32)0x0000000A)
|
||||
#define FSMC_MemSize_64MB ((u32)0x0000000B)
|
||||
#define FSMC_MemSize_128MB ((u32)0x0000000C)
|
||||
#define FSMC_MemSize_256MB ((u32)0x0000000D)
|
||||
#define FSMC_MemSize_512MB ((u32)0x0000000E)
|
||||
#define FSMC_MemSize_1GB ((u32)0x0000000F)
|
||||
#define FSMC_MemSize_2GB ((u32)0x00000010)
|
||||
#define FSMC_MemSize_4GB ((u32)0x00000011)
|
||||
|
||||
|
||||
// Memory data bus bit width setting
|
||||
typedef enum {
|
||||
FSMC_DataWidth_16bits = (0x0000), //16bits
|
||||
FSMC_DataWidth_32bits = (0x0001), //32bits
|
||||
FSMC_DataWidth_64bits = (0x0002), //64bits
|
||||
FSMC_DataWidth_128bits = (0x0003), //128bits
|
||||
FSMC_DataWidth_8bits = (0x0004), //8bits
|
||||
} FSMC_NORSRAM_DataWidth_TypeDef;
|
||||
|
||||
typedef enum {
|
||||
FSMC_NORSRAM_BANK0 = 0,
|
||||
FSMC_NORSRAM_BANK1 = 1,
|
||||
FSMC_NORSRAM_BANK2 = 2,
|
||||
} FSMC_NORSRAM_BANK_TypeDef;
|
||||
|
||||
typedef struct {
|
||||
u32 FSMC_SMReadPipe; //sm_read_pipe[1:0] The cycle of latching read data, that is, the cycle when ready_resp is pulled high
|
||||
|
||||
u32 FSMC_ReadyMode; //Select whether the hready_resp signal comes from the FSMC IP internal or external DEVICE, only for writing and reading external DEVICE operations.
|
||||
//0: Internal FSMC 1: External DEVICE (ie from FSMC_NWAIT)
|
||||
u32 FSMC_WritePeriod; //Write cycle
|
||||
|
||||
u32 FSMC_WriteHoldTime; //Address/data hold time during write operation
|
||||
|
||||
u32 FSMC_AddrSetTime; //Address establishment time
|
||||
|
||||
u32 FSMC_ReadPeriod; //Read cycle
|
||||
|
||||
FSMC_NORSRAM_DataWidth_TypeDef FSMC_DataWidth;
|
||||
|
||||
} FSMC_NORSRAM_Bank_InitTypeDef;
|
||||
|
||||
typedef struct {
|
||||
u32 FSMC_Mode;
|
||||
u32 FSMC_TimingRegSelect;
|
||||
u32 FSMC_MemSize;
|
||||
u32 FSMC_MemType;
|
||||
u32 FSMC_AddrDataMode;
|
||||
} FSMC_InitTypeDef;
|
||||
|
||||
|
||||
#define FSMC_MemType_SDRAM ((u32)0x0<<5)
|
||||
#define FSMC_MemType_NorSRAM ((u32)0x1<<5)
|
||||
#define FSMC_MemType_FLASH ((u32)0x2<<5)
|
||||
#define FSMC_MemType_RESERVED ((u32)0x3<<5)
|
||||
//SYSCFG_CFGR1
|
||||
#define FSMC_Mode_6800 ((u32)0x40000000)
|
||||
#define FSMC_Mode_8080 ((u32)0x20000000)
|
||||
#define FSMC_Mode_NorFlash ((u32)0x00000000)
|
||||
|
||||
#define FSMC_AddrDataMUX ((u32)0x00000000)
|
||||
#define FSMC_AddrDataDeMUX ((u32)0x10000000)
|
||||
|
||||
|
||||
|
||||
|
||||
void FSMC_NORSRAMStructInit(FSMC_InitTypeDef* init_struct);
|
||||
void FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef* init_struct);
|
||||
void FSMC_NORSRAMInit(FSMC_InitTypeDef* init_struct);
|
||||
void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_TypeDef bank);
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_FSMC_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,198 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_gpio.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GPIO
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_GPIO_H
|
||||
#define __HAL_GPIO_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_gpio.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup GPIO_HAL
|
||||
/// @brief GPIO HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup GPIO_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Output Maximum frequency selection
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
GPIO_Speed_50MHz = 1, ///< Maximum speed is 50MHz
|
||||
GPIO_Speed_20MHz, ///< Maximum speed is 20MHz
|
||||
GPIO_Speed_10MHz ///< Maximum speed is 10MHz
|
||||
} GPIOSpeed_TypeDef;
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configuration Mode enumeration
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
GPIO_Mode_AIN = 0x00, ///< Analog input
|
||||
GPIO_Mode_FLOATING = 0x04, ///< Floating input
|
||||
GPIO_Mode_IPD = 0x28, ///< Pull down input
|
||||
GPIO_Mode_IPU = 0x48, ///< Pull up input
|
||||
GPIO_Mode_Out_OD = 0x14, ///< Universal open drain output
|
||||
GPIO_Mode_Out_PP = 0x10, ///< Universal push-pull output
|
||||
GPIO_Mode_AF_OD = 0x1C, ///< Multiplex open drain output
|
||||
GPIO_Mode_AF_PP = 0x18 ///< Multiplexed push-pull output
|
||||
} GPIOMode_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Bit_SET and Bit_RESET enumeration
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
Bit_RESET = 0, ///< bit reset
|
||||
Bit_SET ///< bit set
|
||||
} BitAction;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief GPIO Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u16 GPIO_Pin; ///< GPIO_Pin
|
||||
GPIOSpeed_TypeDef GPIO_Speed; ///< GPIO_Speed
|
||||
GPIOMode_TypeDef GPIO_Mode; ///< GPIO_Mode
|
||||
} GPIO_InitTypeDef;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup GPIO_Exported_Constants
|
||||
/// @{
|
||||
|
||||
#define GPIO_Speed_2MHz GPIO_Speed_20MHz
|
||||
|
||||
#define GPIO_Pin_0 (0x0001U) ///< Pin 0 selected
|
||||
#define GPIO_Pin_1 (0x0002U) ///< Pin 1 selected
|
||||
#define GPIO_Pin_2 (0x0004U) ///< Pin 2 selected
|
||||
#define GPIO_Pin_3 (0x0008U) ///< Pin 3 selected
|
||||
#define GPIO_Pin_4 (0x0010U) ///< Pin 4 selected
|
||||
#define GPIO_Pin_5 (0x0020U) ///< Pin 5 selected
|
||||
#define GPIO_Pin_6 (0x0040U) ///< Pin 6 selected
|
||||
#define GPIO_Pin_7 (0x0080U) ///< Pin 7 selected
|
||||
#define GPIO_Pin_8 (0x0100U) ///< Pin 8 selected
|
||||
#define GPIO_Pin_9 (0x0200U) ///< Pin 9 selected
|
||||
#define GPIO_Pin_10 (0x0400U) ///< Pin 10 selected
|
||||
#define GPIO_Pin_11 (0x0800U) ///< Pin 11 selected
|
||||
#define GPIO_Pin_12 (0x1000U) ///< Pin 12 selected
|
||||
#define GPIO_Pin_13 (0x2000U) ///< Pin 13 selected
|
||||
#define GPIO_Pin_14 (0x4000U) ///< Pin 14 selected
|
||||
#define GPIO_Pin_15 (0x8000U) ///< Pin 15 selected
|
||||
#define GPIO_Pin_All (0xFFFFU) ///< All pins selected
|
||||
|
||||
|
||||
#define GPIO_AF_0 (0x00U) ///< Alternative function 0
|
||||
#define GPIO_AF_1 (0x01U) ///< Alternative function 1
|
||||
#define GPIO_AF_2 (0x02U) ///< Alternative function 2
|
||||
#define GPIO_AF_3 (0x03U) ///< Alternative function 3
|
||||
#define GPIO_AF_4 (0x04U) ///< Alternative function 4
|
||||
#define GPIO_AF_5 (0x05U) ///< Alternative function 5
|
||||
#define GPIO_AF_6 (0x06U) ///< Alternative function 6
|
||||
#define GPIO_AF_7 (0x07U) ///< Alternative function 7
|
||||
#define GPIO_AF_8 (0x08U) ///< Alternative function 8
|
||||
#define GPIO_AF_9 (0x09U) ///< Alternative function 9
|
||||
#define GPIO_AF_10 (0x0AU) ///< Alternative function 10
|
||||
#define GPIO_AF_11 (0x0BU) ///< Alternative function 11
|
||||
#define GPIO_AF_12 (0x0CU) ///< Alternative function 12
|
||||
#define GPIO_AF_13 (0x0DU) ///< Alternative function 13
|
||||
#define GPIO_AF_14 (0x0EU) ///< Alternative function 14
|
||||
#define GPIO_AF_15 (0x0FU) ///< Alternative function 15
|
||||
#define GPIO_PortSourceGPIOA (0x00U)
|
||||
#define GPIO_PortSourceGPIOB (0x01U)
|
||||
#define GPIO_PortSourceGPIOC (0x02U)
|
||||
#define GPIO_PortSourceGPIOD (0x03U)
|
||||
|
||||
#define GPIO_PinSource0 (0x00U)
|
||||
#define GPIO_PinSource1 (0x01U)
|
||||
#define GPIO_PinSource2 (0x02U)
|
||||
#define GPIO_PinSource3 (0x03U)
|
||||
#define GPIO_PinSource4 (0x04U)
|
||||
#define GPIO_PinSource5 (0x05U)
|
||||
#define GPIO_PinSource6 (0x06U)
|
||||
#define GPIO_PinSource7 (0x07U)
|
||||
#define GPIO_PinSource8 (0x08U)
|
||||
#define GPIO_PinSource9 (0x09U)
|
||||
#define GPIO_PinSource10 (0x0AU)
|
||||
#define GPIO_PinSource11 (0x0BU)
|
||||
#define GPIO_PinSource12 (0x0CU)
|
||||
#define GPIO_PinSource13 (0x0DU)
|
||||
#define GPIO_PinSource14 (0x0EU)
|
||||
#define GPIO_PinSource15 (0x0FU)
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup GPIO_Exported_Variables
|
||||
/// @{
|
||||
|
||||
#ifdef _HAL_GPIO_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup GPIO_Exported_Functions
|
||||
/// @{
|
||||
void GPIO_DeInit(GPIO_TypeDef* gpio);
|
||||
void GPIO_AFIODeInit(void);
|
||||
void GPIO_Init(GPIO_TypeDef* gpio, GPIO_InitTypeDef* init_struct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* init_struct);
|
||||
void GPIO_SetBits(GPIO_TypeDef* gpio, u16 pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef* gpio, u16 pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef* gpio, u16 pin, BitAction value);
|
||||
void GPIO_Write(GPIO_TypeDef* gpio, u16 value);
|
||||
void GPIO_PinLock(GPIO_TypeDef* gpio, u16 pin, FunctionalState state);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* gpio, u16 pin);
|
||||
bool GPIO_ReadInputDataBit(GPIO_TypeDef* gpio, u16 pin);
|
||||
bool GPIO_ReadOutputDataBit(GPIO_TypeDef* gpio, u16 pin);
|
||||
|
||||
u16 GPIO_ReadInputData(GPIO_TypeDef* gpio);
|
||||
u16 GPIO_ReadOutputData(GPIO_TypeDef* gpio);
|
||||
|
||||
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* gpio, u8 pin, u8 alternate_function);
|
||||
|
||||
void exGPIO_PinAFConfig(GPIO_TypeDef* gpio, u16 pin, s32 remap, s8 alternate_function);
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_GPIO_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,255 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_i2c.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE I2C
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_I2C_H
|
||||
#define __HAL_I2C_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_i2c.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_HAL
|
||||
/// @brief I2C HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DRV_Exported_Constants
|
||||
/// @{
|
||||
|
||||
#define I2C_OWN_ADDRESS 0x20
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief I2C Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
union {
|
||||
u16 Mode; ///< Specifies the I2C mode. This parameter can be a value of I2C_mode.
|
||||
u16 I2C_Mode;
|
||||
};
|
||||
union {
|
||||
u16 Speed; ///< Specifies the I2C speed. This parameter can be a value of I2C_speed.
|
||||
u16 I2C_Speed;
|
||||
};
|
||||
union {
|
||||
u16 OwnAddress; ///< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.
|
||||
u16 I2C_OwnAddress;
|
||||
};
|
||||
|
||||
union {
|
||||
u32 ClockSpeed; ///< Specifies the clock speed.
|
||||
u32 I2C_ClockSpeed;
|
||||
};
|
||||
} I2C_InitTypeDef;
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_Exported_Constants
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief I2C DMA Direction
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RDMAE_SET = 1, // 1 - DMA read
|
||||
TDMAE_SET // 2 - DMA transmit
|
||||
} I2C_DMA_Dir_TypeDef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief I2C Transfer Direction
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
I2C_Direction_Transmitter, // I2C Transmitter
|
||||
I2C_Direction_Receiver // I2C Receiver
|
||||
} I2C_Trans_Dir_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief I2C Acknowledged Address
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
I2C_AcknowledgedAddress_7bit = 0x4000, // 7-bit address
|
||||
I2C_AcknowledgedAddress_10bit = 0xC000 // 10-bit address
|
||||
} I2C_ACKaddr_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_Private_Defines
|
||||
/// @{
|
||||
#define INTR_MASK ((u16)0xC000)
|
||||
#define FLAG_Mask ((u32)0x00793FFF)
|
||||
#define IC_TAR_ENDUAL_Set ((u16)0x1000)
|
||||
#define IC_TAR_ENDUAL_Reset ((u16)0xEFFF)
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_modes
|
||||
/// @{
|
||||
#define TX_EMPTY_CTRL I2C_CR_EMPINT
|
||||
#define IC_SLAVE_DISABLE I2C_CR_SLAVEDIS
|
||||
#define IC_RESTART_EN I2C_CR_REPEN
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_interrupts_definition
|
||||
/// @{
|
||||
#define I2C_IT_RX_UNDER ((u16)0x0001)
|
||||
#define I2C_IT_RX_OVER ((u16)0x0002)
|
||||
#define I2C_IT_RX_FULL ((u16)0x0004)
|
||||
#define I2C_IT_TX_OVER ((u16)0x0008)
|
||||
#define I2C_IT_TX_EMPTY ((u16)0x0010)
|
||||
#define I2C_IT_RD_REQ ((u16)0x0020)
|
||||
#define I2C_IT_TX_ABRT ((u16)0x0040)
|
||||
#define I2C_IT_RX_DONE ((u16)0x0080)
|
||||
#define I2C_IT_ACTIVITY ((u16)0x0100)
|
||||
#define I2C_IT_STOP_DET ((u16)0x0200)
|
||||
#define I2C_IT_START_DET ((u16)0x0400)
|
||||
#define I2C_IT_GEN_CALL ((u16)0x0800)
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_flags_definition
|
||||
/// @{
|
||||
#define I2C_FLAG_RX_UNDER ((u16)0x0001)
|
||||
#define I2C_FLAG_RX_OVER ((u16)0x0002)
|
||||
#define I2C_FLAG_RX_FULL ((u16)0x0004)
|
||||
#define I2C_FLAG_TX_OVER ((u16)0x0008)
|
||||
#define I2C_FLAG_TX_EMPTY ((u16)0x0010)
|
||||
#define I2C_FLAG_RD_REQ ((u16)0x0020)
|
||||
#define I2C_FLAG_TX_ABRT ((u16)0x0040)
|
||||
#define I2C_FLAG_RX_DONE ((u16)0x0080)
|
||||
#define I2C_FLAG_ACTIVITY ((u16)0x0100)
|
||||
#define I2C_FLAG_STOP_DET ((u16)0x0200)
|
||||
#define I2C_FLAG_START_DET ((u16)0x0400)
|
||||
#define I2C_FLAG_GEN_CALL ((u16)0x0800)
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_Events
|
||||
/// @{
|
||||
#define I2C_EVENT_RX_UNDER ((u16)0x0001)
|
||||
#define I2C_EVENT_RX_OVER ((u16)0x0002)
|
||||
#define I2C_EVENT_RX_FULL ((u16)0x0004)
|
||||
#define I2C_EVENT_TX_OVER ((u16)0x0008)
|
||||
#define I2C_EVENT_TX_EMPTY ((u16)0x0010)
|
||||
#define I2C_EVENT_RD_REQ ((u16)0x0020)
|
||||
#define I2C_EVENT_TX_ABRT ((u16)0x0040)
|
||||
#define I2C_EVENT_RX_DONE ((u16)0x0080)
|
||||
#define I2C_EVENT_ACTIVITY ((u16)0x0100)
|
||||
#define I2C_EVENT_STOP_DET ((u16)0x0200)
|
||||
#define I2C_EVENT_START_DET ((u16)0x0400)
|
||||
#define I2C_EVENT_GEN_CALL ((u16)0x0800)
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_Statusflags_definition
|
||||
/// @{
|
||||
#define I2C_STATUS_FLAG_ACTIVITY ((u16)0x8001)
|
||||
#define I2C_STATUS_FLAG_TFNF ((u16)0x8002)
|
||||
#define I2C_STATUS_FLAG_TFE ((u16)0x8004)
|
||||
#define I2C_STATUS_FLAG_RFNE ((u16)0x8008)
|
||||
#define I2C_STATUS_FLAG_RFF ((u16)0x8010)
|
||||
#define I2C_STATUS_FLAG_M_ACTIVITY ((u16)0x8020)
|
||||
#define I2C_STATUS_FLAG_S_ACTIVITY ((u16)0x8040)
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
#define IC_SLAVE_ENABLE (0x0000<<6)
|
||||
#define IC_7BITADDR_MASTER (0x0000<<4)
|
||||
#define IC_7BITADDR_SLAVE (0x0000<<3)
|
||||
#define I2C_Speed_STANDARD ((u16)0x0002)
|
||||
#define I2C_Speed_FAST ((u16)0x0004)
|
||||
#define I2C_Mode_MASTER ((u16)0x0001)
|
||||
#define I2C_Mode_SLAVE ((u16)0x0000)
|
||||
#define CMD_READ ((u16)0x0100)
|
||||
#define CMD_WRITE ((u16)0x0000)
|
||||
#define I2C_Mode_I2C ((u16)0x0000)
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_I2C_C_
|
||||
|
||||
#define GLOBAL
|
||||
|
||||
static u8 I2C_CMD_DIR = 0;
|
||||
u16 I2C_DMA_DIR = 0;
|
||||
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_Exported_Functions
|
||||
/// @{
|
||||
void I2C_DeInit(I2C_TypeDef* i2c);
|
||||
void I2C_Init(I2C_TypeDef* i2c, I2C_InitTypeDef* init_struct);
|
||||
void I2C_StructInit(I2C_InitTypeDef* init_struct);
|
||||
void I2C_Cmd(I2C_TypeDef* i2c, FunctionalState state);
|
||||
void I2C_DMACmd(I2C_TypeDef* i2c, FunctionalState state);
|
||||
void I2C_GenerateSTART(I2C_TypeDef* i2c, FunctionalState state);
|
||||
void I2C_GenerateSTOP(I2C_TypeDef* i2c, FunctionalState state);
|
||||
void I2C_OwnAddress2Config(I2C_TypeDef* i2c, u8 addr);
|
||||
void I2C_DualAddressCmd(I2C_TypeDef* i2c, FunctionalState state);
|
||||
void I2C_GeneralCallCmd(I2C_TypeDef* i2c, FunctionalState state);
|
||||
void I2C_ITConfig(I2C_TypeDef* i2c, u16 it, FunctionalState state);
|
||||
void I2C_SendData(I2C_TypeDef* i2c, u8 dat);
|
||||
void I2C_ReadCmd(I2C_TypeDef* i2c);
|
||||
void I2C_Send7bitAddress(I2C_TypeDef* i2c, u8 addr, u8 dir);
|
||||
void I2C_ClearFlag(I2C_TypeDef* i2c, u32 flag);
|
||||
void I2C_ClearITPendingBit(I2C_TypeDef* i2c, u32 it);
|
||||
|
||||
u8 I2C_ReceiveData(I2C_TypeDef* i2c);
|
||||
u16 I2C_ReadRegister(I2C_TypeDef* i2c, u8 reg);
|
||||
u32 I2C_GetLastEvent(I2C_TypeDef* i2c);
|
||||
|
||||
ErrorStatus I2C_CheckEvent(I2C_TypeDef* i2c, u32 event);
|
||||
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* i2c, u32 flag);
|
||||
ITStatus I2C_GetITStatus(I2C_TypeDef* i2c, u32 it);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Extended function interface
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_SendSlaveAddress(I2C_TypeDef* i2c, u8 addr);
|
||||
void I2C_SlaveConfigure(I2C_TypeDef* i2c, FunctionalState state);
|
||||
void I2C_DMAConfigure(I2C_TypeDef* i2c, u8 dir);
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_I2C_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,130 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_iwdg.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE IWDG
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_IWDG_H
|
||||
#define __HAL_IWDG_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_iwdg.h"
|
||||
#include "reg_common.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup IWDG_HAL
|
||||
/// @brief IWDG HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup IWDG_Exported_Constants
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief IWDG prescaler
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
IWDG_Prescaler_4 = IWDG_PR_PRE_DIV4,
|
||||
IWDG_Prescaler_8 = IWDG_PR_PRE_DIV8,
|
||||
IWDG_Prescaler_16 = IWDG_PR_PRE_DIV16,
|
||||
IWDG_Prescaler_32 = IWDG_PR_PRE_DIV32,
|
||||
IWDG_Prescaler_64 = IWDG_PR_PRE_DIV64,
|
||||
IWDG_Prescaler_128 = IWDG_PR_PRE_DIV128,
|
||||
IWDG_Prescaler_256 = IWDG_PR_PRE_DIV256
|
||||
} IWDGPrescaler_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief IWDG flag
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
IWDG_FLAG_PVU = 0x0001, // IWDG prescaler value update flag
|
||||
IWDG_FLAG_RVU = 0x0002 // IWDG counter reload value update flag
|
||||
} IWDGFlag_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Write access to IWDG_PR and IWDG_RLR registers
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
IWDG_WriteAccess_Enable = 0x5555, // Enable write
|
||||
IWDG_WriteAccess_Disable = 0x0000 // Disable write
|
||||
} IWDGWriteAccess_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief IWDG Key Reload
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
KR_KEY_Reload = 0xAAAA, // Reload value
|
||||
KR_KEY_Enable = 0xCCCC // Start IWDG
|
||||
} IWDGKey_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief IWDG Overflow Configration
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
IWDG_Overflow_Reset = 0, //
|
||||
IWDG_Overflow_Interrupt = IWDG_CR_IRQSEL //
|
||||
} IWDGOverflowConfig_TypeDef;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup IWDG_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_IWDG_C_
|
||||
#define GLOBAL
|
||||
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup IWDG_Exported_Functions
|
||||
/// @{
|
||||
FlagStatus IWDG_GetFlagStatus(u16 flag);
|
||||
|
||||
void IWDG_WriteAccessCmd(u16 write_access);
|
||||
void IWDG_SetPrescaler(u8 prescaler);
|
||||
void IWDG_SetReload(u16 reload);
|
||||
u32 IWDG_GetReload(void);
|
||||
void IWDG_ReloadCounter(void);
|
||||
void IWDG_Enable(void);
|
||||
void PVU_CheckStatus(void);
|
||||
void RVU_CheckStatus(void);
|
||||
|
||||
void IWDG_OverflowConfig(IWDGOverflowConfig_TypeDef overflow_config);
|
||||
void IWDG_ClearITPendingBit(void);
|
||||
void IWDG_EnableIT(void);
|
||||
void IWDG_Reset(void);
|
||||
void IWDG_ClearIT(void);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_IWDG_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,128 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_misc.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE NVIC
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_MISC_H
|
||||
#define __HAL_MISC_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup NVIC_HAL
|
||||
/// @brief NVIC HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup NVIC_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief NVIC Init Structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u8 NVIC_IRQChannel;
|
||||
u8 NVIC_IRQChannelPreemptionPriority;
|
||||
u8 NVIC_IRQChannelSubPriority;
|
||||
FunctionalState NVIC_IRQChannelCmd;
|
||||
} NVIC_InitTypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief NVIC New Init Structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u8 NVIC_IRQChannel;
|
||||
u8 NVIC_IRQChannelPreemptionPriority; // Cortex-M0 not used
|
||||
u8 NVIC_IRQChannelSubPriority;
|
||||
FunctionalState NVIC_IRQChannelCmd;
|
||||
} exNVIC_Init_TypeDef;
|
||||
|
||||
/// @}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup NVIC_Exported_Constants
|
||||
/// @{
|
||||
|
||||
#define NVIC_VectTab_RAM (0x20000000U)
|
||||
#define NVIC_VectTab_FLASH (0x08000000U)
|
||||
|
||||
#define NVIC_LP_SEVONPEND (0x10U)
|
||||
#define NVIC_LP_SLEEPDEEP (0x04U)
|
||||
#define NVIC_LP_SLEEPONEXIT (0x02U)
|
||||
|
||||
#define NVIC_PriorityGroup_0 (0x0700U) // 0 bits for pre-emption priority 4 bits for subpriority
|
||||
#define NVIC_PriorityGroup_1 (0x0600U) // 1 bits for pre-emption priority 3 bits for subpriority
|
||||
#define NVIC_PriorityGroup_2 (0x0500U) // 2 bits for pre-emption priority 2 bits for subpriority
|
||||
#define NVIC_PriorityGroup_3 (0x0400U) // 3 bits for pre-emption priority 1 bits for subpriority
|
||||
#define NVIC_PriorityGroup_4 (0x0300U) // 4 bits for pre-emption priority 0 bits for subpriority
|
||||
|
||||
#define AIRCR_VECTKEY_MASK (0x05FA0000U)
|
||||
|
||||
#define SysTick_CLKSource_HCLK_Div8 (0xFFFFFFFBU)
|
||||
|
||||
|
||||
#define SysTick_CLKSource_EXTCLK (0xFFFFFFFBU)
|
||||
#define SysTick_CLKSource_HCLK (0x00000004U)
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup NVIC_Exported_Variables
|
||||
/// @{
|
||||
|
||||
#ifdef _HAL_NVIC_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup NVIC_Exported_Functions
|
||||
/// @{
|
||||
|
||||
void NVIC_PriorityGroupConfig(u32 priority_group);
|
||||
void NVIC_SetVectorTable(u32 vect_tab, u32 offset);
|
||||
|
||||
void NVIC_SystemLPConfig(u8 low_power_mode, FunctionalState state);
|
||||
void NVIC_Init(NVIC_InitTypeDef* init_struct);
|
||||
|
||||
void SysTick_CLKSourceConfig(u32 systick_clk_source);
|
||||
|
||||
void exNVIC_Init(exNVIC_Init_TypeDef* init_struct);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_NVIC_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,156 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_pwr.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE PWR
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_PWR_H
|
||||
#define __HAL_PWR_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_pwr.h"
|
||||
#include "reg_syscfg.h"
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup PWR_HAL
|
||||
/// @brief PWR HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup PWR_Exported_Types
|
||||
/// @{
|
||||
|
||||
typedef enum {
|
||||
emWUP_Pin1 = 0,
|
||||
emWUP_Pin2 = 1,
|
||||
emWUP_Pin3,
|
||||
emWUP_Pin4,
|
||||
emWUP_Pin5,
|
||||
emWUP_Pin6,
|
||||
} emWUP_Pin_Typedef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief PVD_detection_level
|
||||
|
||||
typedef enum {
|
||||
emPVD_LEVEL0 = SYSCFG_PDETCSR_PLS_1V7,
|
||||
emPVD_LEVEL1 = SYSCFG_PDETCSR_PLS_2V0,
|
||||
emPVD_LEVEL2 = SYSCFG_PDETCSR_PLS_2V3,
|
||||
emPVD_LEVEL3 = SYSCFG_PDETCSR_PLS_2V6,
|
||||
emPVD_LEVEL4 = SYSCFG_PDETCSR_PLS_2V9,
|
||||
emPVD_LEVEL5 = SYSCFG_PDETCSR_PLS_3V2,
|
||||
emPVD_LEVEL6 = SYSCFG_PDETCSR_PLS_3V5,
|
||||
emPVD_LEVEL7 = SYSCFG_PDETCSR_PLS_3V8,
|
||||
emPVD_LEVEL8 = SYSCFG_PDETCSR_PLS_4V1,
|
||||
emPVD_LEVEL9 = SYSCFG_PDETCSR_PLS_4V4,
|
||||
emPVD_LEVEL10 = SYSCFG_PDETCSR_PLS_4V7
|
||||
} emPVD_Level_Typedef;
|
||||
#define PWR_PVDLevel_1V7 SYSCFG_PDETCSR_PLS_1V7
|
||||
#define PWR_PVDLevel_2V0 SYSCFG_PDETCSR_PLS_2V0
|
||||
#define PWR_PVDLevel_2V3 SYSCFG_PDETCSR_PLS_2V3
|
||||
#define PWR_PVDLevel_2V6 SYSCFG_PDETCSR_PLS_2V6
|
||||
#define PWR_PVDLevel_2V9 SYSCFG_PDETCSR_PLS_2V9
|
||||
#define PWR_PVDLevel_3V2 SYSCFG_PDETCSR_PLS_3V2
|
||||
#define PWR_PVDLevel_3V5 SYSCFG_PDETCSR_PLS_3V5
|
||||
#define PWR_PVDLevel_3V8 SYSCFG_PDETCSR_PLS_3V8
|
||||
#define PWR_PVDLevel_4V1 SYSCFG_PDETCSR_PLS_4V1
|
||||
#define PWR_PVDLevel_4V4 SYSCFG_PDETCSR_PLS_4V4
|
||||
#define PWR_PVDLevel_4V7 SYSCFG_PDETCSR_PLS_4V7
|
||||
/// @brief Regulator_state_is_STOP_mode
|
||||
typedef enum {
|
||||
PWR_Regulator_ON = 0x00000000,
|
||||
PWR_Regulator_LowPower = 0x00000001
|
||||
|
||||
} emPWR_Reg_Stop_mode_Typedef;
|
||||
|
||||
/// @brief STOP_mode_entry
|
||||
typedef enum {
|
||||
PWR_STOPEntry_WFI = 0x00000001,
|
||||
PWR_STOPEntry_WFE = 0x00000002
|
||||
|
||||
} emPWR_STOP_ModeEn_Typedef;
|
||||
|
||||
/// @brief Low Power Mode
|
||||
typedef enum {
|
||||
LP_STOP_MODE = 0,
|
||||
LP_SLEEP_MODE = 1,
|
||||
LP_STANDBY_MODE = 2
|
||||
} emPWR_LP_Mode_Typedef;
|
||||
|
||||
/// @brief Wait_for_mode
|
||||
typedef enum {
|
||||
LP_WFI,
|
||||
LP_WFE
|
||||
} emPWR_Wait_Mode_Typedef;
|
||||
//typedef enum {
|
||||
// PWR_FLAG_WU = PWR_CSR_WUF,
|
||||
// PWR_FLAG_SB = PWR_CSR_SBF,
|
||||
|
||||
// PWR_FLAG_PVDO = PWR_CSR_PVDO
|
||||
|
||||
|
||||
//} emPWR_PWR_Flag_Typedef;
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup PWR_Exported_Variables
|
||||
/// @{
|
||||
|
||||
#ifdef _HAL_PWR_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup PWR_Exported_Functions
|
||||
/// @{
|
||||
|
||||
void PWR_DeInit(void);
|
||||
|
||||
void PWR_BackupAccessCmd(FunctionalState state);
|
||||
|
||||
void PWR_PVDCmd(FunctionalState state);
|
||||
void PWR_PVDLevelConfig(emPVD_Level_Typedef pvd_level);
|
||||
void PWR_WakeUpPinCmd(FunctionalState state);
|
||||
void PWR_EnterSTOPMode(emPWR_Reg_Stop_mode_Typedef regulator, emPWR_STOP_ModeEn_Typedef stop_entry);
|
||||
void PWR_EnterSTANDBYMode(void);
|
||||
|
||||
|
||||
void PWR_ClearFlag(u32 flag);
|
||||
FlagStatus PWR_GetFlagStatus(u32 flag);
|
||||
FlagStatus PWR_GetPVDOFlagStatus(u32 flag);
|
||||
void exPWR_EnterLowPowerMode(emPWR_LP_Mode_Typedef lp_mode, emPWR_Wait_Mode_Typedef wait_mode);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_PWR_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,329 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_rcc.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE RCC
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_RCC_H
|
||||
#define __HAL_RCC_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
#include "mm32_reg.h"
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RCC_HAL
|
||||
/// @brief RCC HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RCC_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RCC_Exported_Constants
|
||||
/// @{
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RCC_Exported_Enumeration
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief HSE configuration
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_HSE_OFF = 0, // HSE OFF
|
||||
RCC_HSE_ON = RCC_CR_HSEON, // HSE ON
|
||||
RCC_HSE_Bypass = RCC_CR_HSEBYP // HSE Bypass
|
||||
} RCCHSE_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Used for flags
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CR_REG_INDEX = 1, //
|
||||
BDCR_REG_INDEX = 2, //
|
||||
CSR_REG_INDEX = 3, //
|
||||
RCC_FLAG_MASK = 0x1FU //
|
||||
} RCC_RegisterFlag_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief RCC Flag
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
// Flags in the CR register
|
||||
RCC_FLAG_HSIRDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)), ///< Internal High Speed clock ready flag
|
||||
RCC_FLAG_HSERDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)), ///< External High Speed clock ready flag
|
||||
|
||||
RCC_FLAG_PLLRDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)), ///< PLL clock ready flag
|
||||
|
||||
// Flags in the CSR register
|
||||
RCC_FLAG_LSIRDY = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)), ///< Internal Low Speed oscillator Ready
|
||||
RCC_FLAG_PINRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)), ///< PIN reset flag
|
||||
RCC_FLAG_PORRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)), ///< POR/PDR reset flag
|
||||
RCC_FLAG_SFTRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)), ///< Software Reset flag
|
||||
RCC_FLAG_IWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)), ///< Independent Watchdog reset flag
|
||||
RCC_FLAG_WWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)), ///< Window watchdog reset flag
|
||||
|
||||
// Flags in the BDCR register
|
||||
RCC_FLAG_LSERDY = ((u8)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) ///< External Low Speed oscillator Ready
|
||||
} RCC_FLAG_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief System clock source
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_HSI = 0, // Set HSI as systemCLOCK
|
||||
RCC_HSE = 1, // Set HSE as systemCLOCK
|
||||
RCC_PLL = 2, // Set PLL as systemCLOCK
|
||||
RCC_LSI = 3 // Set LSI as systemCLOCK
|
||||
} SYSCLK_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief PLL entry clock source
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef enum {
|
||||
RCC_HSI_Div4 = 0,
|
||||
RCC_HSI_Div = 0,
|
||||
RCC_HSE_Div1 = RCC_PLLCFGR_PLLSRC,
|
||||
RCC_HSE_Div2 = (RCC_PLLCFGR_PLLXTPRE | RCC_PLLCFGR_PLLSRC),
|
||||
} RCC_PLLSource_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief PLL multiplication factor
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_PLLMul_2 = 0x00000000U,
|
||||
RCC_PLLMul_3 = 0x00040000U,
|
||||
RCC_PLLMul_4 = 0x00080000U,
|
||||
RCC_PLLMul_5 = 0x000C0000U,
|
||||
RCC_PLLMul_6 = 0x00100000U,
|
||||
RCC_PLLMul_7 = 0x00140000U,
|
||||
RCC_PLLMul_8 = 0x00180000U,
|
||||
RCC_PLLMul_9 = 0x001C0000U,
|
||||
RCC_PLLMul_10 = 0x00200000U,
|
||||
RCC_PLLMul_11 = 0x00240000U,
|
||||
RCC_PLLMul_12 = 0x00280000U,
|
||||
RCC_PLLMul_13 = 0x002C0000U,
|
||||
RCC_PLLMul_14 = 0x00300000U,
|
||||
RCC_PLLMul_15 = 0x00340000U,
|
||||
RCC_PLLMul_16 = 0x00380000U
|
||||
} RCC_PLLMul_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief AHB clock source
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_SYSCLK_Div1 = RCC_CFGR_HPRE_DIV1,
|
||||
RCC_SYSCLK_Div2 = RCC_CFGR_HPRE_DIV2,
|
||||
RCC_SYSCLK_Div4 = RCC_CFGR_HPRE_DIV4,
|
||||
RCC_SYSCLK_Div8 = RCC_CFGR_HPRE_DIV8,
|
||||
RCC_SYSCLK_Div16 = RCC_CFGR_HPRE_DIV16,
|
||||
RCC_SYSCLK_Div64 = RCC_CFGR_HPRE_DIV64,
|
||||
RCC_SYSCLK_Div128 = RCC_CFGR_HPRE_DIV128,
|
||||
RCC_SYSCLK_Div256 = RCC_CFGR_HPRE_DIV256,
|
||||
RCC_SYSCLK_Div512 = RCC_CFGR_HPRE_DIV512
|
||||
} RCC_AHB_CLK_TypeDef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief APB1 and APB2clock source
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_HCLK_Div1 = RCC_CFGR_PPRE1_DIV1,
|
||||
RCC_HCLK_Div2 = RCC_CFGR_PPRE1_DIV2,
|
||||
RCC_HCLK_Div4 = RCC_CFGR_PPRE1_DIV4,
|
||||
RCC_HCLK_Div8 = RCC_CFGR_PPRE1_DIV8,
|
||||
RCC_HCLK_Div16 = RCC_CFGR_PPRE1_DIV16
|
||||
} RCC_APB1_APB2_CLK_TypeDef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief USB Device clock source
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_USBCLKSource_PLLCLK_Div1 = 0,
|
||||
RCC_USBCLKSource_PLLCLK_Div2 = 1,
|
||||
RCC_USBCLKSource_PLLCLK_Div3 = 2,
|
||||
RCC_USBCLKSource_PLLCLK_Div4 = 3
|
||||
} RCC_USBCLKSOURCE_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief ADC clock source
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_PCLK2_Div2 = (0x00000000),
|
||||
RCC_PCLK2_Div4 = (0x00004000),
|
||||
RCC_PCLK2_Div6 = (0x00008000),
|
||||
RCC_PCLK2_Div8 = (0x0000C000)
|
||||
} RCC_ADCCLKSOURCE_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief LSE configuration
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_LSE_OFF = 0, // LSE OFF
|
||||
RCC_LSE_ON = RCC_BDCR_LSEON, // LSE ON
|
||||
RCC_LSE_Bypass = RCC_BDCR_LSEBYP // LSE Bypass
|
||||
} RCC_LSE_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief RTC clock source
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_RTCCLKSource_LSE = RCC_BDCR_RTCSEL_LSE,
|
||||
RCC_RTCCLKSource_LSI = RCC_BDCR_RTCSEL_LSI,
|
||||
RCC_RTCCLKSource_HSE_Div128 = RCC_BDCR_RTCSEL_HSE
|
||||
} RCC_RTCCLKSOURCE_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clock source to output on MCO pin
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_MCO_NoClock = RCC_CFGR_MCO_NOCLOCK,
|
||||
RCC_MCO_LSI = RCC_CFGR_MCO_LSI,
|
||||
RCC_MCO_LSE = RCC_CFGR_MCO_LSE,
|
||||
RCC_MCO_SYSCLK = RCC_CFGR_MCO_SYSCLK,
|
||||
RCC_MCO_HSI = RCC_CFGR_MCO_HSI,
|
||||
RCC_MCO_HSE = RCC_CFGR_MCO_HSE,
|
||||
RCC_MCO_PLLCLK_Div2 = RCC_CFGR_MCO_PLL
|
||||
} RCC_MCO_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief RCC Interrupt source
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_IT_LSIRDY = RCC_CIR_LSIRDYF,
|
||||
RCC_IT_LSERDY = RCC_CIR_LSERDYF,
|
||||
RCC_IT_HSIRDY = RCC_CIR_HSIRDYF,
|
||||
RCC_IT_HSERDY = RCC_CIR_HSERDYF,
|
||||
RCC_IT_PLLRDY = RCC_CIR_PLLRDYF,
|
||||
RCC_IT_CSS = RCC_CIR_CSSF
|
||||
} RCC_IT_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief RCC clock frequency type definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u32 SYSCLK_Frequency; ///< returns SYSCLK clock frequency.
|
||||
u32 HCLK_Frequency; ///< returns hclk clock frequency.
|
||||
u32 PCLK1_Frequency; ///< returns PCLK1 clock frequency.
|
||||
u32 PCLK2_Frequency; ///< returns PCLK2 clock frequency.
|
||||
u32 ADCCLK_Frequency; ///< returns ADCCLK clock frequency.
|
||||
} RCC_ClocksTypeDef;
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RCC_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_RCC_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RCC_Exported_Functions
|
||||
/// @{
|
||||
void RCC_DeInit(void);
|
||||
void RCC_HSEConfig(RCCHSE_TypeDef state);
|
||||
void RCC_HSICmd(FunctionalState state);
|
||||
void RCC_SYSCLKConfig(SYSCLK_TypeDef sys_clk_src);
|
||||
void RCC_PLLDMDNConfig(u32 plldn, u32 plldm);
|
||||
void RCC_PLLConfig(RCC_PLLSource_TypeDef pll_src, RCC_PLLMul_TypeDef pll_mul);
|
||||
void RCC_PLLCmd(FunctionalState state);
|
||||
void RCC_HCLKConfig(RCC_AHB_CLK_TypeDef sys_clk);
|
||||
void RCC_PCLK1Config(RCC_APB1_APB2_CLK_TypeDef hclk);
|
||||
void RCC_PCLK2Config(RCC_APB1_APB2_CLK_TypeDef hclk);
|
||||
void RCC_USBCLKConfig(RCC_USBCLKSOURCE_TypeDef usb_clk_src);
|
||||
void RCC_ADCCLKConfig(RCC_ADCCLKSOURCE_TypeDef pclk2);
|
||||
void RCC_LSICmd(FunctionalState state);
|
||||
|
||||
void RCC_RTCCLKCmd(FunctionalState state);
|
||||
void RCC_LSEConfig(RCC_LSE_TypeDef state);
|
||||
void RCC_RTCCLKConfig(RCC_RTCCLKSOURCE_TypeDef rtc_clk_src);
|
||||
void RCC_BackupResetCmd(FunctionalState state);
|
||||
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef* clk);
|
||||
void RCC_AHBPeriphClockCmd(u32 ahb_periph, FunctionalState state);
|
||||
void RCC_AHB2PeriphClockCmd(u32 ahb_periph, FunctionalState state);
|
||||
void RCC_AHB3PeriphClockCmd(u32 ahb_periph, FunctionalState state);
|
||||
void RCC_AHBPeriphResetCmd(u32 ahb_periph, FunctionalState state);
|
||||
void RCC_AHB2PeriphResetCmd(u32 ahb_periph, FunctionalState state);
|
||||
void RCC_AHB3PeriphResetCmd(u32 ahb_periph, FunctionalState state);
|
||||
void RCC_APB2PeriphClockCmd(u32 apb2_periph, FunctionalState state);
|
||||
void RCC_APB1PeriphClockCmd(u32 apb1_periph, FunctionalState state);
|
||||
void RCC_APB2PeriphResetCmd(u32 apb2_periph, FunctionalState state);
|
||||
void RCC_APB1PeriphResetCmd(u32 apb1_periph, FunctionalState state);
|
||||
|
||||
void RCC_ClockSecuritySystemCmd(FunctionalState state);
|
||||
void RCC_MCOConfig(RCC_MCO_TypeDef mco_src);
|
||||
void RCC_ClearFlag(void);
|
||||
void RCC_ITConfig(RCC_IT_TypeDef it, FunctionalState state);
|
||||
void RCC_ClearITPendingBit(u8 it);
|
||||
|
||||
u8 RCC_GetSYSCLKSource(void);
|
||||
u32 RCC_GetSysClockFreq(void);
|
||||
u32 RCC_GetHCLKFreq(void);
|
||||
|
||||
u32 RCC_GetPCLK1Freq(void);
|
||||
u32 RCC_GetPCLK2Freq(void);
|
||||
FlagStatus RCC_GetFlagStatus(RCC_FLAG_TypeDef flag);
|
||||
ErrorStatus RCC_WaitForHSEStartUp(void);
|
||||
ErrorStatus RCC_WaitForFlagStartUp(RCC_FLAG_TypeDef flag);
|
||||
ITStatus RCC_GetITStatus(RCC_IT_TypeDef it);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Extended function interface
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//ErrorStatus exRCC_Init(RCCInitStruct_TypeDef* para);
|
||||
void exRCC_SystickDisable(void);
|
||||
void exRCC_SystickEnable(u32 sys_tick_period);
|
||||
void exRCC_APB1PeriphReset(u32 apb1_periph);
|
||||
void exRCC_APB2PeriphReset(u32 apb2_periph);
|
||||
void exRCC_BackupReset(void);
|
||||
void RCC_ADC_ClockCmd(ADC_TypeDef* peripheral, FunctionalState state);
|
||||
void RCC_GPIO_ClockCmd(GPIO_TypeDef* peripheral, FunctionalState state);
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_RCC_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
@@ -0,0 +1,102 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_redefine.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE REDEFINE
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_REDEFINE_H
|
||||
#define __HAL_REDEFINE_H
|
||||
|
||||
// Files includes
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
/////////////////////////////////////1///////////////////////////////////////////
|
||||
/// @defgroup REDEFINE_HAL
|
||||
/// @brief REDEFINE HAL modules
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup REDEFINE_Exported_Types
|
||||
/// @{
|
||||
///
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup REDEFINE_Exported_Constants
|
||||
/// @{
|
||||
//Lib redefine
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief HAL_lib Version compatibility definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM compatibility definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define TIM_TRGOSource_Reset TIM_TRIGSource_Reset
|
||||
#define TIM_TRGOSource_Enable TIM_TRIGSource_Enable
|
||||
#define TIM_TRGOSource_Update TIM_TRIGSource_Update
|
||||
#define TIM_TRGOSource_OC1 TIM_TRIGSource_OC1
|
||||
#define TIM_TRGOSource_OC1Ref TIM_TRIGSource_OC1Ref
|
||||
#define TIM_TRGOSource_OC2Ref TIM_TRIGSource_OC2Ref
|
||||
#define TIM_TRGOSource_OC3Ref TIM_TRIGSource_OC3Ref
|
||||
#define TIM_TRGOSource_OC4Ref TIM_TRIGSource_OC4Ref
|
||||
///< The UG bit in the TIM_EGR register is used as the trigger output (TRIG).
|
||||
///< The Counter Enable CEN is used as the trigger output (TRIG).
|
||||
///< The update event is used as the trigger output (TRIG).
|
||||
///< The trigger output sends a positive pulse when the CC1IF flag ///< is to be set, as soon as a capture or compare match occurs (TRIG).
|
||||
///< OC1REF signal is used as the trigger output (TRIG).
|
||||
///< OC2REF signal is used as the trigger output (TRIG).
|
||||
///< OC3REF signal is used as the trigger output (TRIG).
|
||||
///< OC4REF signal is used as the trigger output (TRIG).
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup REDEFINE_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_REDEFINE_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup REDEFINE_Exported_Functions
|
||||
/// @{
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_REDEFINE_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,114 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_rtc.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE RTC
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_RTC_H
|
||||
#define __HAL_RTC_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
#include "reg_rtc.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RTC_HAL
|
||||
/// @brief RTC HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RTC_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief RTC_interrupts_define
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RTC_IT_OW = RTC_CR_OWIE, ///< Overflow interrupt
|
||||
RTC_IT_ALR = RTC_CR_ALRIE, ///< Alarm interrupt
|
||||
RTC_IT_SEC = RTC_CR_SECIE ///< Second interrupt
|
||||
} RTC_IT_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief RTC_interrupts_flags
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RTC_FLAG_RTOFF = RTC_CSR_RTOFF, ///< RTC Operation OFF flag
|
||||
RTC_FLAG_RSF = RTC_CSR_RSF, ///< Registers Synchronized flag
|
||||
RTC_FLAG_OW = RTC_CSR_OWF, ///< Overflow flag
|
||||
RTC_FLAG_ALR = RTC_CSR_ALRF, ///< Alarm flag
|
||||
RTC_FLAG_SEC = RTC_CSR_SECF ///< Second flag
|
||||
} RTC_FLAG_TypeDef;
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RTC_Exported_Constants
|
||||
/// @{
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RTC_Exported_Variables
|
||||
/// @{
|
||||
|
||||
#ifdef _HAL_RTC_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
GLOBAL bool accessRTC;
|
||||
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RTC_Exported_Functions
|
||||
/// @{
|
||||
void RTC_ITConfig(RTC_IT_TypeDef it, FunctionalState state);
|
||||
void RTC_ClearFlag(RTC_FLAG_TypeDef flag);
|
||||
void RTC_ClearITPendingBit(RTC_IT_TypeDef it);
|
||||
void RTC_EnterConfigMode(void);
|
||||
void RTC_SetCounter(u32 count);
|
||||
void RTC_SetPrescaler(u32 prescaler);
|
||||
void RTC_SetAlarm(u32 alarm);
|
||||
void RTC_ExitConfigMode(void);
|
||||
void RTC_WaitForLastTask(void);
|
||||
void RTC_WaitForSynchro(void);
|
||||
|
||||
u32 RTC_GetCounter(void);
|
||||
u32 RTC_GetDivider(void);
|
||||
|
||||
FlagStatus RTC_GetFlagStatus(RTC_FLAG_TypeDef flag);
|
||||
ITStatus RTC_GetITStatus(RTC_IT_TypeDef it);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_RTC_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,503 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_gpio.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GPIO
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_SDIO_H
|
||||
#define __HAL_SDIO_H
|
||||
|
||||
// Files includes
|
||||
#include "mm32_reg.h"
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup GPIO_HAL
|
||||
/// @brief GPIO HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup GPIO_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Output Maximum frequency selection
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#define SDIO_FLAG_CCRCFAIL ((u32)0x00000001)
|
||||
#define SDIO_FLAG_DCRCFAIL ((u32)0x00000002)
|
||||
#define SDIO_FLAG_CTIMEOUT ((u32)0x00000004)
|
||||
#define SDIO_FLAG_DTIMEOUT ((u32)0x00000008)
|
||||
#define SDIO_FLAG_TXUNDERR ((u32)0x00000010)
|
||||
#define SDIO_FLAG_RXOVERR ((u32)0x00000020)
|
||||
#define SDIO_FLAG_CMDREND ((u32)0x00000040)
|
||||
#define SDIO_FLAG_CMDSENT ((u32)0x00000080)
|
||||
#define SDIO_FLAG_DATAEND ((u32)0x00000100)
|
||||
#define SDIO_FLAG_STBITERR ((u32)0x00000200)
|
||||
#define SDIO_FLAG_DBCKEND ((u32)0x00000400)
|
||||
#define SDIO_FLAG_CMDACT ((u32)0x00000800)
|
||||
#define SDIO_FLAG_TXACT ((u32)0x00001000)
|
||||
#define SDIO_FLAG_RXACT ((u32)0x00002000)
|
||||
#define SDIO_FLAG_TXFIFOHE ((u32)0x00004000)
|
||||
#define SDIO_FLAG_RXFIFOHF ((u32)0x00008000)
|
||||
#define SDIO_FLAG_TXFIFOF ((u32)0x00010000)
|
||||
#define SDIO_FLAG_RXFIFOF ((u32)0x00020000)
|
||||
#define SDIO_FLAG_TXFIFOE ((u32)0x00040000)
|
||||
#define SDIO_FLAG_RXFIFOE ((u32)0x00080000)
|
||||
#define SDIO_FLAG_TXDAVL ((u32)0x00100000)
|
||||
#define SDIO_FLAG_RXDAVL ((u32)0x00200000)
|
||||
#define SDIO_FLAG_SDIOIT ((u32)0x00400000)
|
||||
#define SDIO_FLAG_CEATAEND ((u32)0x00800000)
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//SDIO working mode define ,SDIO working mode definition, set through the SD_SetDevice Mode function.
|
||||
#define SD_POLLING_MODE 0 /// Query mode. In this mode, it is recommended to increase the setting of SDIO_TRANSFER_CLK_DIV if there are problems with reading and writing.
|
||||
#define SD_DMA_MODE 1 /// In DMA mode, it is recommended to increase the setting of SDIO_TRANSFER_CLK_DIV if there are problems with reading and writing.
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SDIO Various error enumeration definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef enum {
|
||||
SD_CMD_CRC_FAIL = 1, ///< Command response received (but CRC check failed)
|
||||
SD_DATA_CRC_FAIL, ///< Data bock sent/received (CRC check Failed)
|
||||
SD_CMD_RSP_TIMEOUT, ///< Command response timeout
|
||||
SD_DATA_TIMEOUT, ///< Data time out
|
||||
SD_TX_UNDERRUN, ///< Transmit FIFO under-run
|
||||
SD_RX_OVERRUN, ///< Receive FIFO over-run
|
||||
SD_START_BIT_ERR, ///< Start bit not detected on all data signals in widE bus mode
|
||||
SD_CMD_OUT_OF_RANGE, ///< CMD's argument was out of range.
|
||||
SD_ADDR_MISALIGNED, ///< Misaligned address
|
||||
SD_BLOCK_LEN_ERR, ///< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length
|
||||
SD_ERASE_SEQ_ERR, ///< An error in the sequence of erase command occurs.
|
||||
SD_BAD_ERASE_PARAM, ///< An Invalid selection for erase groups
|
||||
SD_WRITE_PROT_VIOLATION, ///< Attempt to program a write protect block
|
||||
SD_LOCK_UNLOCK_FAILED, ///< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card
|
||||
SD_COM_CRC_FAILED, ///< CRC check of the previous command failed
|
||||
SD_ILLEGAL_CMD, ///< Command is not legal for the card state
|
||||
SD_CARD_ECC_FAILED, ///< Card internal ECC was applied but failed to correct the data
|
||||
SD_CC_ERROR, ///< Internal card controller error
|
||||
SD_GENERAL_UNKNOWN_ERROR, ///< General or Unknown error
|
||||
SD_STREAM_READ_UNDERRUN, ///< The card could not sustain data transfer in stream read operation.
|
||||
SD_STREAM_WRITE_OVERRUN, ///< The card could not sustain data programming in stream mode
|
||||
SD_CID_CSD_OVERWRITE, ///< CID/CSD overwrite error
|
||||
SD_WP_ERASE_SKIP, ///< only partial address space was erased
|
||||
SD_CARD_ECC_DISABLED, ///< Command has been executed without using internal ECC
|
||||
SD_ERASE_RESET, ///< Erase sequence was cleared before executing because an out of erase sequence command was received
|
||||
SD_AKE_SEQ_ERROR, ///< Error in sequence of authentication.
|
||||
SD_INVALID_VOLTRANGE, ///< SD invalid voltage range,
|
||||
SD_ADDR_OUT_OF_RANGE, ///< SD addresses are out of range,
|
||||
SD_SWITCH_ERROR, ///< SD switch error,
|
||||
SD_SDIO_DISABLED, ///< SD SDIO disability,
|
||||
SD_SDIO_FUNCTION_BUSY, ///< SD SDIO function busy,
|
||||
SD_SDIO_FUNCTION_FAILED, ///< SD SDIO failed,
|
||||
SD_SDIO_UNKNOWN_FUNCTION, ///< SDIO unknown function,
|
||||
SD_INTERNAL_ERROR, ///< SD internal error,
|
||||
SD_NOT_CONFIGURED, ///< SD is not configured,
|
||||
SD_REQUEST_PENDING, ///< The SD request waits,
|
||||
SD_REQUEST_NOT_APPLICABLE, ///< The SD requirement does not apply,
|
||||
SD_INVALID_PARAMETER, ///< Invalid SD parameter,
|
||||
SD_UNSUPPORTED_FEATURE, ///< Features not supported by SD,
|
||||
SD_UNSUPPORTED_HW, ///< HW not supported by SD,
|
||||
SD_ERROR, ///< SD error
|
||||
SD_OK = 0 ///< SD OK
|
||||
} SD_Error;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SD card CSD register data
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u8 CSDStruct; ///< CSD structure
|
||||
u8 SysSpecVersion; ///< System specification version
|
||||
u8 Reserved1; ///< Reserved
|
||||
u8 TAAC; ///< Data read access-time 1
|
||||
u8 NSAC; ///< Data read access-time 2 in CLK cycles
|
||||
u8 MaxBusClkFrec; ///< Max. bus clock frequency
|
||||
u16 CardComdClasses; ///< Card command classes
|
||||
u8 RdBlockLen; ///< Max. read data block length
|
||||
u8 PartBlockRead; ///< Partial blocks for read allowed
|
||||
u8 WrBlockMisalign; ///< Write block misalignment
|
||||
u8 RdBlockMisalign; ///< Read block misalignment
|
||||
u8 DSRImpl; ///< DSR implemented
|
||||
u8 Reserved2; ///< Reserved
|
||||
u32 DeviceSize; ///< Device Size
|
||||
u8 MaxRdCurrentVDDMin; ///< Max. read current @ VDD min
|
||||
u8 MaxRdCurrentVDDMax; ///< Max. read current @ VDD max
|
||||
u8 MaxWrCurrentVDDMin; ///< Max. write current @ VDD min
|
||||
u8 MaxWrCurrentVDDMax; ///< Max. write current @ VDD max
|
||||
u8 DeviceSizeMul; ///< Device size multiplier
|
||||
u8 EraseGrSize; ///< Erase group size
|
||||
u8 EraseGrMul; ///< Erase group size multiplier
|
||||
u8 WrProtectGrSize; ///< Write protect group size
|
||||
u8 WrProtectGrEnable; ///< Write protect group enable
|
||||
u8 ManDeflECC; ///< Manufacturer default ECC
|
||||
u8 WrSpeedFact; ///< Write speed factor
|
||||
u8 MaxWrBlockLen; ///< Max. write data block length
|
||||
u8 WriteBlockPaPartial; ///< Partial blocks for write allowed
|
||||
u8 Reserved3; ///< Reserded
|
||||
u8 ContentProtectAppli; ///< Content protection application
|
||||
u8 FileFormatGrouop; ///< File format group
|
||||
u8 CopyFlag; ///< Copy flag (OTP)
|
||||
u8 PermWrProtect; ///< Permanent write protection
|
||||
u8 TempWrProtect; ///< Temporary write protection
|
||||
u8 FileFormat; ///< File Format
|
||||
u8 ECC; ///< ECC code
|
||||
u8 CSD_CRC; ///< CSD CRC
|
||||
u8 Reserved4; ///< always 1
|
||||
} SD_CSD;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SD card CID register data
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u8 ManufacturerID; ///< ManufacturerID
|
||||
u16 OEM_AppliID; ///< OEM/Application ID
|
||||
u32 ProdName1; ///< Product Name part1
|
||||
u8 ProdName2; ///< Product Name part2
|
||||
u8 ProdRev; ///< Product Revision
|
||||
u32 ProdSN; ///< Product Serial Number
|
||||
u8 Reserved1; ///< Reserved1
|
||||
u16 ManufactDate; ///< Manufacturing Date
|
||||
u8 CID_CRC; ///< CID CRC
|
||||
u8 Reserved2; ///< always 1
|
||||
} SD_CID;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SD state
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SD_CARD_READY = ((u32)0x00000001),
|
||||
SD_CARD_IDENTIFICATION = ((u32)0x00000002),
|
||||
SD_CARD_STANDBY = ((u32)0x00000003),
|
||||
SD_CARD_TRANSFER = ((u32)0x00000004),
|
||||
SD_CARD_SENDING = ((u32)0x00000005),
|
||||
SD_CARD_RECEIVING = ((u32)0x00000006),
|
||||
SD_CARD_PROGRAMMING = ((u32)0x00000007),
|
||||
SD_CARD_DISCONNECTED = ((u32)0x00000008),
|
||||
SD_CARD_ERROR = ((u32)0x000000FF)
|
||||
} SDCardState;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SD message ,include CSD,CID data
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
SD_CSD SD_csd;
|
||||
SD_CID SD_cid;
|
||||
long long CardCapacity;
|
||||
u32 CardBlockSize;
|
||||
u16 RCA;
|
||||
u8 CardType;
|
||||
} SD_CardInfo;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SDIO init
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u8 SDIO_MDEN;
|
||||
u8 SDIO_DATWT;
|
||||
u8 SDIO_SelPTSM;
|
||||
u8 SDIO_CLKSP;
|
||||
u8 SDIO_OUTM;
|
||||
u8 SDIO_SelSM;
|
||||
u8 SDIO_OPMSel;
|
||||
} SDIO_InitTypeDef;
|
||||
|
||||
typedef struct {
|
||||
u32 SDIO_Argument; ///Specifies the SDIO command argument which is sent
|
||||
///to a card as part of a command message. If a command
|
||||
///contains an argument, it must be loaded into this register
|
||||
///before writing the command to the command register
|
||||
|
||||
u32 SDIO_CmdIndex; ///Specifies the SDIO command index. It must be lower than 0x40.
|
||||
|
||||
u32 SDIO_Response; ///Specifies the SDIO response type.
|
||||
///This parameter can be a value of @ref SDIO_Response_Type
|
||||
|
||||
u32 SDIO_Wait; ///Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
|
||||
///This parameter can be a value of @ref SDIO_Wait_Interrupt_State
|
||||
|
||||
/// u32 SDIO_CPSM; ///Specifies whether SDIO Command path state machine (CPSM)
|
||||
///is enabled or disabled.
|
||||
///This parameter can be a value of @ref SDIO_CPSM_State
|
||||
} SDIO_CmdInitTypeDef;
|
||||
typedef struct {
|
||||
u32 SDIO_DataTimeOut; // < Specifies the data timeout period in card bus clock periods.
|
||||
//
|
||||
u32 SDIO_DataLength; // < Specifies the number of data bytes to be transferred.
|
||||
//
|
||||
u32 SDIO_DataBlockSize; // < Specifies the data block size for block transfer.
|
||||
// This parameter can be a value of @ref SDIO_Data_Block_Size
|
||||
//
|
||||
u32 SDIO_TransferDir; // < Specifies the data transfer direction, whether the transfer
|
||||
// is a read or write.
|
||||
// This parameter can be a value of @ref SDIO_Transfer_Direction
|
||||
//
|
||||
// u32 SDIO_TransferMode; // < Specifies whether data transfer is in stream or block mode.
|
||||
// // This parameter can be a value of @ref SDIO_Transfer_Type
|
||||
// //
|
||||
// u32 SDIO_DPSM; // < Specifies whether SDIO Data path state machine (DPSM)
|
||||
// // is enabled or disabled.
|
||||
// // This parameter can be a value of @ref SDIO_DPSM_State
|
||||
} SDIO_DataInitTypeDef;
|
||||
|
||||
|
||||
|
||||
extern SD_CardInfo SDCardInfo;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SDIO ָinstruction set
|
||||
/// @{
|
||||
#define SD_CMD_GO_IDLE_STATE ((u8)0)
|
||||
#define SD_CMD_SEND_OP_COND ((u8)1)
|
||||
#define SD_CMD_ALL_SEND_CID ((u8)2)
|
||||
#define SD_CMD_SET_REL_ADDR ((u8)3)
|
||||
#define SD_CMD_SET_DSR ((u8)4)
|
||||
#define SD_CMD_SDIO_SEN_OP_COND ((u8)5)
|
||||
#define SD_CMD_HS_SWITCH ((u8)6)
|
||||
#define SD_CMD_SEL_DESEL_CARD ((u8)7)
|
||||
#define SD_CMD_HS_SEND_EXT_CSD ((u8)8)
|
||||
#define SD_CMD_SEND_CSD ((u8)9)
|
||||
#define SD_CMD_SEND_CID ((u8)10)
|
||||
#define SD_CMD_READ_DAT_UNTIL_STOP ((u8)11)
|
||||
#define SD_CMD_STOP_TRANSMISSION ((u8)12)
|
||||
#define SD_CMD_SEND_STATUS ((u8)13)
|
||||
#define SD_CMD_HS_BUSTEST_READ ((u8)14)
|
||||
#define SD_CMD_GO_INACTIVE_STATE ((u8)15)
|
||||
#define SD_CMD_SET_BLOCKLEN ((u8)16)
|
||||
#define SD_CMD_READ_SINGLE_BLOCK ((u8)17)
|
||||
#define SD_CMD_READ_MULT_BLOCK ((u8)18)
|
||||
#define SD_CMD_HS_BUSTEST_WRITE ((u8)19)
|
||||
#define SD_CMD_WRITE_DAT_UNTIL_STOP ((u8)20)
|
||||
#define SD_CMD_SET_BLOCK_COUNT ((u8)23)
|
||||
#define SD_CMD_WRITE_SINGLE_BLOCK ((u8)24)
|
||||
#define SD_CMD_WRITE_MULT_BLOCK ((u8)25)
|
||||
#define SD_CMD_PROG_CID ((u8)26)
|
||||
#define SD_CMD_PROG_CSD ((u8)27)
|
||||
#define SD_CMD_SET_WRITE_PROT ((u8)28)
|
||||
#define SD_CMD_CLR_WRITE_PROT ((u8)29)
|
||||
#define SD_CMD_SEND_WRITE_PROT ((u8)30)
|
||||
#define SD_CMD_SD_ERASE_GRP_START ((u8)32)
|
||||
#define SD_CMD_SD_ERASE_GRP_END ((u8)33)
|
||||
#define SD_CMD_ERASE_GRP_START ((u8)35)
|
||||
#define SD_CMD_ERASE_GRP_END ((u8)36)
|
||||
#define SD_CMD_ERASE ((u8)38)
|
||||
#define SD_CMD_FAST_IO ((u8)39)
|
||||
#define SD_CMD_GO_IRQ_STATE ((u8)40)
|
||||
#define SD_CMD_LOCK_UNLOCK ((u8)42)
|
||||
#define SD_CMD_APP_CMD ((u8)55)
|
||||
#define SD_CMD_GEN_CMD ((u8)56)
|
||||
#define SD_CMD_NO_CMD ((u8)64)
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup Following commands are SD Card Specific commands.
|
||||
/// @{
|
||||
#define SD_CMD_APP_SD_SET_BUSWIDTH ((u8)6)
|
||||
#define SD_CMD_SD_APP_STAUS ((u8)13)
|
||||
#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((u8)22)
|
||||
#define SD_CMD_SD_APP_OP_COND ((u8)41)
|
||||
#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((u8)42)
|
||||
#define SD_CMD_SD_APP_SEND_SCR ((u8)51)
|
||||
#define SD_CMD_SDIO_RW_DIRECT ((u8)52)
|
||||
#define SD_CMD_SDIO_RW_EXTENDED ((u8)53)
|
||||
|
||||
#define SD_CMD_SD_APP_GET_MKB ((u8)43)
|
||||
#define SD_CMD_SD_APP_GET_MID ((u8)44)
|
||||
#define SD_CMD_SD_APP_SET_CER_RN1 ((u8)45)
|
||||
#define SD_CMD_SD_APP_GET_CER_RN2 ((u8)46)
|
||||
#define SD_CMD_SD_APP_SET_CER_RES2 ((u8)47)
|
||||
#define SD_CMD_SD_APP_GET_CER_RES1 ((u8)48)
|
||||
#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((u8)18)
|
||||
#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((u8)25)
|
||||
#define SD_CMD_SD_APP_SECURE_ERASE ((u8)38)
|
||||
#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((u8)49)
|
||||
#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((u8)48)
|
||||
/// @}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SD support define.
|
||||
/// @{
|
||||
#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((u32)0x00000000)
|
||||
#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((u32)0x00000001)
|
||||
#define SDIO_HIGH_CAPACITY_SD_CARD ((u32)0x00000002)
|
||||
#define SDIO_MULTIMEDIA_CARD ((u32)0x00000003)
|
||||
#define SDIO_SECURE_DIGITAL_IO_CARD ((u32)0x00000004)
|
||||
#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((u32)0x00000005)
|
||||
#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((u32)0x00000006)
|
||||
#define SDIO_HIGH_CAPACITY_MMC_CARD ((u32)0x00000007)
|
||||
/// @}
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0
|
||||
#endif
|
||||
#define SDIO_STATIC_FLAGS ((u32)0x000005FF)
|
||||
#define SDIO_CMD0TIMEOUT ((u32)0x00010000)
|
||||
#define SDIO_DATATIMEOUT ((u32)0xFFFFFFFF)
|
||||
#define SDIO_FIFO_Address ((u32)0x40018080)
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup Mask for errors Card Status R1 (OCR Register)
|
||||
/// @{
|
||||
#define SD_OCR_ADDR_OUT_OF_RANGE ((u32)0x80000000)
|
||||
#define SD_OCR_ADDR_MISALIGNED ((u32)0x40000000)
|
||||
#define SD_OCR_BLOCK_LEN_ERR ((u32)0x20000000)
|
||||
#define SD_OCR_ERASE_SEQ_ERR ((u32)0x10000000)
|
||||
#define SD_OCR_BAD_ERASE_PARAM ((u32)0x08000000)
|
||||
#define SD_OCR_WRITE_PROT_VIOLATION ((u32)0x04000000)
|
||||
#define SD_OCR_LOCK_UNLOCK_FAILED ((u32)0x01000000)
|
||||
#define SD_OCR_COM_CRC_FAILED ((u32)0x00800000)
|
||||
#define SD_OCR_ILLEGAL_CMD ((u32)0x00400000)
|
||||
#define SD_OCR_CARD_ECC_FAILED ((u32)0x00200000)
|
||||
#define SD_OCR_CC_ERROR ((u32)0x00100000)
|
||||
#define SD_OCR_GENERAL_UNKNOWN_ERROR ((u32)0x00080000)
|
||||
#define SD_OCR_STREAM_READ_UNDERRUN ((u32)0x00040000)
|
||||
#define SD_OCR_STREAM_WRITE_OVERRUN ((u32)0x00020000)
|
||||
#define SD_OCR_CID_CSD_OVERWRIETE ((u32)0x00010000)
|
||||
#define SD_OCR_WP_ERASE_SKIP ((u32)0x00008000)
|
||||
#define SD_OCR_CARD_ECC_DISABLED ((u32)0x00004000)
|
||||
#define SD_OCR_ERASE_RESET ((u32)0x00002000)
|
||||
#define SD_OCR_AKE_SEQ_ERROR ((u32)0x00000008)
|
||||
#define SD_OCR_ERRORBITS ((u32)0xFDFFE008)
|
||||
/// @}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup Masks for R6 Response
|
||||
/// @{
|
||||
#define SD_R6_GENERAL_UNKNOWN_ERROR ((u32)0x00002000)
|
||||
#define SD_R6_ILLEGAL_CMD ((u32)0x00004000)
|
||||
#define SD_R6_COM_CRC_FAILED ((u32)0x00008000)
|
||||
/// @}
|
||||
#define SD_VOLTAGE_WINDOW_SD ((u32)0x80100000)
|
||||
#define SD_HIGH_CAPACITY ((u32)0x40000000)
|
||||
#define SD_STD_CAPACITY ((u32)0x00000000)
|
||||
#define SD_CHECK_PATTERN ((u32)0x000001AA)
|
||||
#define SD_VOLTAGE_WINDOW_MMC ((u32)0x80FF8000)
|
||||
|
||||
#define SD_MAX_VOLT_TRIAL ((u32)0x0000FFFF)
|
||||
#define SD_ALLZERO ((u32)0x00000000)
|
||||
|
||||
#define SD_WIDE_BUS_SUPPORT ((u32)0x00040000)
|
||||
#define SD_SINGLE_BUS_SUPPORT ((u32)0x00010000)
|
||||
#define SD_CARD_LOCKED ((u32)0x02000000)
|
||||
#define SD_CARD_PROGRAMMING ((u32)0x00000007)
|
||||
#define SD_CARD_RECEIVING ((u32)0x00000006)
|
||||
#define SD_DATATIMEOUT ((u32)0xFFFFFFFF)
|
||||
#define SD_0TO7BITS ((u32)0x000000FF)
|
||||
#define SD_8TO15BITS ((u32)0x0000FF00)
|
||||
#define SD_16TO23BITS ((u32)0x00FF0000)
|
||||
#define SD_24TO31BITS ((u32)0xFF000000)
|
||||
#define SD_MAX_DATA_LENGTH ((u32)0x01FFFFFF)
|
||||
|
||||
#define SD_HALFFIFO ((u32)0x00000008)
|
||||
#define SD_HALFFIFOBYTES ((u32)0x00000020)
|
||||
|
||||
#define SD_CCCC_LOCK_UNLOCK ((u32)0x00000080)
|
||||
#define SD_CCCC_WRITE_PROT ((u32)0x00000040)
|
||||
#define SD_CCCC_ERASE ((u32)0x00000020)
|
||||
|
||||
|
||||
#define SDIO_SEND_IF_COND ((u32)0x00000008)
|
||||
|
||||
#define SDIO_Response_No ((u32)0x00)
|
||||
#define SDIO_Response_Short ((u32)0x01)
|
||||
#define SDIO_Response_Long ((u32)0x03)
|
||||
|
||||
#define SDIO_DataBlockSize_1b ((u32)0x00000000)
|
||||
#define SDIO_DataBlockSize_2b ((u32)0x00000001)
|
||||
#define SDIO_DataBlockSize_4b ((u32)0x00000002)
|
||||
#define SDIO_DataBlockSize_8b ((u32)0x00000003)
|
||||
#define SDIO_DataBlockSize_16b ((u32)0x00000004)
|
||||
#define SDIO_DataBlockSize_32b ((u32)0x00000005)
|
||||
#define SDIO_DataBlockSize_64b ((u32)0x00000006)
|
||||
#define SDIO_DataBlockSize_128b ((u32)0x00000007)
|
||||
#define SDIO_DataBlockSize_256b ((u32)0x00000008)
|
||||
#define SDIO_DataBlockSize_512b ((u32)0x00000009)
|
||||
#define SDIO_DataBlockSize_1024b ((u32)0x0000000A)
|
||||
#define SDIO_DataBlockSize_2048b ((u32)0x0000000B)
|
||||
#define SDIO_DataBlockSize_4096b ((u32)0x0000000C)
|
||||
#define SDIO_DataBlockSize_8192b ((u32)0x0000000D)
|
||||
#define SDIO_DataBlockSize_16384b ((u32)0x0000000E)
|
||||
//Define the data block length when the block data transfer mode is selected:
|
||||
//0000: (0 decimal) lock length = 2^0 = 1 byte
|
||||
//0001: (1 decimal) lock length = 2^1 = 2 bytes
|
||||
//0010: (2 decimal) lock length = 2^2 = 4 bytes
|
||||
//0011: (3 decimal) lock length = 2^3 = 8 bytes
|
||||
//0100: (4 decimal) lock length = 2^4 = 16 bytes
|
||||
//0101: (5 decimal) lock length = 2^5 = 32 bytes
|
||||
//0110: (6 decimal) lock length = 2^6 = 64 bytes
|
||||
//0111: (7 decimal) lock length = 2^7 = 128 bytes
|
||||
//1000: (8 decimal) lock length = 2^8 = 256 bytes
|
||||
//1001: (9 decimal) lock length = 2^9 = 512 bytes
|
||||
//1010: (10 decimal) lock length = 2^10 = 1024 bytes
|
||||
//1011: (11 decimal) lock length = 2^11 = 2048 bytes
|
||||
//1100: (12 decimal) lock length = 2^12 = 4096 bytes
|
||||
//1101: (13 decimal) lock length = 2^13 = 8192 bytes
|
||||
//1110: (14 decimal) lock length = 2^14 = 16384 bytes
|
||||
//1111: (15 decimal) reserved
|
||||
|
||||
|
||||
#define SDIO_TransferDir_ToCard ((u32)0x00000000)
|
||||
#define SDIO_TransferDir_ToSDIO ((u32)0x00000002)
|
||||
|
||||
#define SDIO_Wait_No ((u32)0x00000000) // SDIO No Wait, TimeOut is enabled
|
||||
#define SDIO_Wait_IT ((u32)0x00000100) //SDIO Wait Interrupt Request
|
||||
#define SDIO_Wait_Pend ((u32)0x00000200) // SDIO Wait End of transfer
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_Exported_Functions
|
||||
/// @{
|
||||
void SDIO_DeInit(void);
|
||||
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||
void SDIO_ClockSet(u32 value);
|
||||
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||
void SDIO_ITConfig(u32 SDIO_IT, FunctionalState state);
|
||||
void SDIO_CRCConfig(u32 SDIO_CRC, FunctionalState state);
|
||||
void SDIO_Clock_Set(u8 clkdiv);
|
||||
void SDIO_Send_Cmd(u8 cmdindex, u8 waitrsp, u32 arg);
|
||||
SD_Error SD_PowerOFF(void);
|
||||
SD_Error CmdError(void);
|
||||
SD_Error CmdResp2Error(void);
|
||||
SD_Error CmdResp3Error(void);
|
||||
SD_Error CmdResp6Error(u8 cmd, u16* prca);
|
||||
SD_Error CmdResp7Error(void);
|
||||
SD_Error CmdResp1Error(u8 cmd);
|
||||
void SDIO_Send_Data_Cfg(u32 datatimeout, u32 datalen, u8 blksize, u8 dir);
|
||||
void SDIO_ClearITPendingBit(u32 SDIO_IT);
|
||||
FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG);
|
||||
u32 SDIO_GetTimeOutCounter(void);
|
||||
u32 SDIO_ReadData(void);
|
||||
void SDIO_WriteData(u32 tempbuff);
|
||||
void SDIO_DMACmd(FunctionalState state);
|
||||
/// @}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,351 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_spi.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SPI
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_SPI_H
|
||||
#define __HAL_SPI_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_spi.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SPI_HAL
|
||||
/// @brief SPI HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SPI_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI mode enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_Mode_Slave = 0x0000, ///< SPI slave mode
|
||||
SPI_Mode_Master = SPI_GCR_MODE ///< SPI master mode
|
||||
} SPI_Mode_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI data size enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_DataSize_8b = 0x0000, ///< 8 bits valid data
|
||||
SPI_DataSize_32b = SPI_GCR_DWSEL ///< 32 bits valid data
|
||||
} SPI_DataSize_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI clock polarity enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_CPOL_Low = 0x0000, ///< The clock is low in idle state.
|
||||
SPI_CPOL_High = SPI_CCR_CPOL ///< The clock is high in idle state.
|
||||
} SPI_CPOL_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI clock phase enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_CPHA_2Edge = 0x0000, ///< Data sampling starts from the second clock edge.
|
||||
SPI_CPHA_1Edge = SPI_CCR_CPHA ///< Data sampling starts from the first clock edge.
|
||||
} SPI_CPHA_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI nss control mode enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_NSS_Soft = 0x0000,
|
||||
SPI_NSS_Hard = SPI_GCR_NSS
|
||||
} SPI_NSS_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI baud rate prescaler enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_BaudRatePrescaler_2 = 0x0002, ///< SCK clock devide by 2
|
||||
SPI_BaudRatePrescaler_4 = 0x0004, ///< SCK clock devide by 4
|
||||
SPI_BaudRatePrescaler_8 = 0x0008, ///< SCK clock devide by 7
|
||||
SPI_BaudRatePrescaler_16 = 0x0010, ///< SCK clock devide by 16
|
||||
SPI_BaudRatePrescaler_32 = 0x0020, ///< SCK clock devide by 32
|
||||
SPI_BaudRatePrescaler_64 = 0x0040, ///< SCK clock devide by 64
|
||||
SPI_BaudRatePrescaler_128 = 0x0080, ///< SCK clock devide by 128
|
||||
SPI_BaudRatePrescaler_256 = 0x0100 ///< SCK clock devide by 256
|
||||
} SPI_BaudRatePrescaler_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI first bit enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_FirstBit_MSB = 0x0000, ///< Data transfers start from MSB
|
||||
SPI_FirstBit_LSB = SPI_CCR_LSBFE ///< Data transfers start from LSB
|
||||
} SPI_FirstBit_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI FIFO trigger level enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_RXTLF = SPI_GCR_RXTLF_Half, ///< RX FIFO trigger level
|
||||
SPI_TXTLF = SPI_GCR_TXTLF_Half ///< TX FIFO trigger level
|
||||
} SPI_TLF_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI bit derection enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_Direction_Rx, ///< Receive enable
|
||||
SPI_Direction_Tx, ///< Transmit enable
|
||||
SPI_Disable_Rx, ///< Receive disable
|
||||
SPI_Disable_Tx ///< Transmit disable
|
||||
} SPI_Direction_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI flag enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_FLAG_RXAVL = SPI_SR_RXAVL, ///< Receive 1 byte available data flag
|
||||
SPI_FLAG_TXEPT = SPI_SR_TXEPT, ///< Transmitter empty flag
|
||||
SPI_FLAG_TXFULL = SPI_SR_TXFULL, ///< Transmitter FIFO full status flag
|
||||
SPI_FLAG_RXAVL_4BYTE = SPI_SR_RXAVL_4BYTE ///< Receive 4 bytes available data flag
|
||||
} SPI_FLAG_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI slave mode data edge adjust enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_SlaveAdjust_LOW, ///< SPI slave mode data edge adjust in low speed mode
|
||||
SPI_SlaveAdjust_FAST ///< SPI slave mode data edge adjust in fast speed mode
|
||||
} SPI_SlaveAdjust_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI data edge adjust enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_DataEdgeAdjust_LOW, ///< SPI data edge adjust in low speed mode
|
||||
SPI_DataEdgeAdjust_FAST ///< SPI data edge adjust in fast speed mode
|
||||
} SPI_DataEdgeAdjust_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI interruput enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_IT_TXEPT = 0x40, ///< Transmitter empty interrupt
|
||||
SPI_IT_RXFULL = 0x20, ///< RX FIFO full interrupt
|
||||
SPI_IT_RXMATCH = 0x10, ///< Receive data match the RXDNR number interrut
|
||||
SPI_IT_RXOERR = 0x08, ///< Receive overrun error interrupt
|
||||
SPI_IT_UNDERRUN = 0x04, ///< Underrun interrupt
|
||||
SPI_IT_RX = 0x02, ///< Receive available data interrupt
|
||||
SPI_IT_TX = 0x01 ///< Transmit FIFO available interrupt
|
||||
} SPI_IT_TypeDef;
|
||||
|
||||
|
||||
typedef enum {
|
||||
I2S_Standard_Phillips = 0x0000,
|
||||
I2S_Standard_MSB = 0x0010,
|
||||
I2S_Standard_LSB = 0x0020,
|
||||
I2S_Standard_PCMShort = 0x0030,
|
||||
I2S_Standard_PCMLong = 0x00B0,
|
||||
} SPI_I2S_STANDARD_TypeDef;
|
||||
|
||||
|
||||
typedef enum {
|
||||
I2S_DataFormat_16b = 0x0000,
|
||||
I2S_DataFormat_16bextended = 0x0001,
|
||||
I2S_DataFormat_24b = 0x0003,
|
||||
I2S_DataFormat_32b = 0x0005,
|
||||
} SPI_I2S_DATAFORMAT_TypeDef;
|
||||
typedef enum {
|
||||
I2S_AudioFreq_192k = (192000),
|
||||
I2S_AudioFreq_96k = (96000),
|
||||
I2S_AudioFreq_48k = (48000),
|
||||
I2S_AudioFreq_44k = (44100),
|
||||
I2S_AudioFreq_32k = (32000),
|
||||
I2S_AudioFreq_24k = (24000),
|
||||
I2S_AudioFreq_22k = (22050),
|
||||
I2S_AudioFreq_16k = (16000),
|
||||
I2S_AudioFreq_11k = (11025),
|
||||
I2S_AudioFreq_12k = (12000),
|
||||
I2S_AudioFreq_8k = (8000),
|
||||
I2S_AudioFreq_4k = (4000),
|
||||
I2S_AudioFreq_Default = (2),
|
||||
} SPI_I2S_AUDIO_FREQ_TypeDef;
|
||||
typedef enum {
|
||||
I2S_Mode_SlaveTx = 0x0000,
|
||||
I2S_Mode_SlaveRx = 0x0100,
|
||||
I2S_Mode_MasterTx = 0x0200,
|
||||
I2S_Mode_MasterRx = 0x0300,
|
||||
} SPI_I2S_TRANS_MODE_TypeDef;
|
||||
|
||||
typedef enum {
|
||||
I2S_MCLKOutput_Enable = 0x0800,
|
||||
I2S_MCLKOutput_Disable = 0x0000,
|
||||
} SPI_I2S_MCLK_OUTPUT_TypeDef;
|
||||
|
||||
typedef enum {
|
||||
I2S_CPOL_Low = 0x0000, ///< The clock is low in idle state.
|
||||
I2S_CPOL_High = SPI_CCR_CPOL ///< The clock is high in idle state.
|
||||
} SPI_I2S_CPOL_TypeDef;
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
SPI_Mode_TypeDef SPI_Mode; ///< Specifies the SPI operating mode
|
||||
SPI_DataSize_TypeDef SPI_DataSize; ///< Specifies the SPI available data size
|
||||
u8 SPI_DataWidth; ///< SPI data length
|
||||
SPI_CPOL_TypeDef SPI_CPOL; ///< Specifies the serial clock steady state
|
||||
SPI_CPHA_TypeDef SPI_CPHA; ///< Specifies the clock active edge for the bit capture
|
||||
SPI_NSS_TypeDef SPI_NSS; ///< Specifies whether the NSS signal is managed by hardware or by software
|
||||
SPI_BaudRatePrescaler_TypeDef SPI_BaudRatePrescaler; ///< Specifies the Baud Rate prescaler value which will be
|
||||
///< used to configure the transmit and receive SCK clock
|
||||
SPI_FirstBit_TypeDef SPI_FirstBit; ///< Specifies whether data transfers start from MSB or LSB bit
|
||||
// u16 SPI_length;
|
||||
} SPI_InitTypeDef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief I2S Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
SPI_I2S_TRANS_MODE_TypeDef I2S_Mode; ///< Specifies the I2S operating mode.
|
||||
SPI_I2S_STANDARD_TypeDef I2S_Standard; ///< Specifies the standard used for the I2S communication.
|
||||
SPI_I2S_DATAFORMAT_TypeDef I2S_DataFormat; ///< Specifies the data format for the I2S communication.
|
||||
SPI_I2S_MCLK_OUTPUT_TypeDef I2S_MCLKOutput; ///< Specifies whether the I2S MCLK output is enabled or not.
|
||||
SPI_I2S_AUDIO_FREQ_TypeDef I2S_AudioFreq; ///< Specifies the frequency selected for the I2S communication.
|
||||
SPI_I2S_CPOL_TypeDef I2S_CPOL; ///< Specifies the idle state of the I2S clock.
|
||||
} I2S_InitTypeDef;
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SPI_Exported_Constants
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SPI_Register_Mask
|
||||
/// @{
|
||||
|
||||
#define GCR_Mask ((u32)0x0FFF)
|
||||
#define CCR_Mask ((u32)0x003F)
|
||||
#define BRR_Mask ((u32)0xFFFF)
|
||||
#define ECR_Mask ((u32)0x001F)
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
// SPI_7bit_8bit data width
|
||||
#define SPI_DataWidth_1b ((u16)0x0001)
|
||||
#define SPI_DataWidth_2b ((u16)0x0002)
|
||||
#define SPI_DataWidth_3b ((u16)0x0003)
|
||||
#define SPI_DataWidth_4b ((u16)0x0004)
|
||||
#define SPI_DataWidth_5b ((u16)0x0005)
|
||||
#define SPI_DataWidth_6b ((u16)0x0006)
|
||||
#define SPI_DataWidth_7b ((u16)0x0007)
|
||||
#define SPI_DataWidth_8b ((u16)0x0008)
|
||||
#define SPI_DataWidth_9b ((u16)0x0009)
|
||||
#define SPI_DataWidth_10b ((u16)0x000a)
|
||||
#define SPI_DataWidth_11b ((u16)0x000b)
|
||||
#define SPI_DataWidth_12b ((u16)0x000c)
|
||||
#define SPI_DataWidth_13b ((u16)0x000d)
|
||||
#define SPI_DataWidth_14b ((u16)0x000e)
|
||||
#define SPI_DataWidth_15b ((u16)0x000f)
|
||||
#define SPI_DataWidth_16b ((u16)0x0010)
|
||||
#define SPI_DataWidth_17b ((u16)0x0011)
|
||||
#define SPI_DataWidth_18b ((u16)0x0012)
|
||||
#define SPI_DataWidth_19b ((u16)0x0013)
|
||||
#define SPI_DataWidth_20b ((u16)0x0014)
|
||||
#define SPI_DataWidth_21b ((u16)0x0015)
|
||||
#define SPI_DataWidth_22b ((u16)0x0016)
|
||||
#define SPI_DataWidth_23b ((u16)0x0017)
|
||||
#define SPI_DataWidth_24b ((u16)0x0018)
|
||||
#define SPI_DataWidth_25b ((u16)0x0019)
|
||||
#define SPI_DataWidth_26b ((u16)0x001a)
|
||||
#define SPI_DataWidth_27b ((u16)0x001b)
|
||||
#define SPI_DataWidth_28b ((u16)0x001c)
|
||||
#define SPI_DataWidth_29b ((u16)0x001d)
|
||||
#define SPI_DataWidth_30b ((u16)0x001e)
|
||||
#define SPI_DataWidth_31b ((u16)0x001f)
|
||||
#define SPI_DataWidth_32b ((u16)0x0000)
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SPI_Exported_Variables
|
||||
/// @{
|
||||
|
||||
#ifdef _HAL_SPI_C_
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SPI_Exported_Functions
|
||||
/// @{
|
||||
|
||||
void SPI_DeInit(SPI_TypeDef* spi);
|
||||
void SPI_Init(SPI_TypeDef* spi, SPI_InitTypeDef* init_struct);
|
||||
void SPI_StructInit(SPI_InitTypeDef* init_struct);
|
||||
void SPI_Cmd(SPI_TypeDef* spi, FunctionalState state);
|
||||
void SPI_ITConfig(SPI_TypeDef* spi, u8 interrupt, FunctionalState state);
|
||||
void SPI_DMACmd(SPI_TypeDef* spi, FunctionalState state);
|
||||
void SPI_FifoTrigger(SPI_TypeDef* spi, SPI_TLF_TypeDef fifo_trigger_value, FunctionalState state);
|
||||
void SPI_SendData(SPI_TypeDef* spi, u32 data);
|
||||
void SPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state);
|
||||
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* spi, SPI_NSS_TypeDef nss);
|
||||
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef* spi, SPI_Direction_TypeDef direction);
|
||||
void SPI_ClearITPendingBit(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt);
|
||||
void SPI_RxBytes(SPI_TypeDef* spi, u16 number);
|
||||
void SPI_SlaveAdjust(SPI_TypeDef* spi, SPI_SlaveAdjust_TypeDef adjust_value);
|
||||
|
||||
bool SPI_DataSizeConfig(SPI_TypeDef* spi, u8 data_size);
|
||||
void SPI_DataSizeTypeConfig(SPI_TypeDef* spi, SPI_DataSize_TypeDef SPI_DataSize);
|
||||
u32 SPI_ReceiveData(SPI_TypeDef* spi);
|
||||
|
||||
FlagStatus SPI_GetFlagStatus(SPI_TypeDef* spi, SPI_FLAG_TypeDef flag);
|
||||
|
||||
ITStatus SPI_GetITStatus(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Extended function interface
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exSPI_ITCmd(SPI_TypeDef* spi, FunctionalState state);
|
||||
void exSPI_ITConfig(SPI_TypeDef* spi, SPI_IT_TypeDef interrput, FunctionalState state);
|
||||
void exSPI_DMACmd(SPI_TypeDef* spi, FunctionalState state);
|
||||
void exSPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state);
|
||||
void exSPI_DataEdgeAdjust(SPI_TypeDef* spi, SPI_DataEdgeAdjust_TypeDef adjust_value);
|
||||
void I2S_Cmd(SPI_TypeDef* spi, FunctionalState state);
|
||||
void I2S_Init(SPI_TypeDef* spi, I2S_InitTypeDef* I2S_InitStruct);
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_SPI_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,83 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_syscfg.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE EXTI
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_SYSCFG_H
|
||||
#define __HAL_SYSCFG_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "mm32_device.h"
|
||||
#include "hal_EXTI.H"
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SYSCFG_HAL
|
||||
/// @brief SYSCFG HAL modules
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SYSCFG_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SYSCFG mode enumeration
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// @defgroup SYSCFG_Memory_Remap_Config
|
||||
#define SYSCFG_MemoryRemap_Flash ((u8)0x00)
|
||||
#define SYSCFG_MemoryRemap_SystemMemory ((u8)0x01)
|
||||
#define SYSCFG_MemoryRemap_SRAM ((u8)0x03)
|
||||
|
||||
|
||||
|
||||
|
||||
///
|
||||
/// @}
|
||||
///
|
||||
|
||||
|
||||
|
||||
|
||||
// Exported macro ------------------------------------------------------------
|
||||
// Exported functions -------------------------------------------------------
|
||||
|
||||
// Function used to set the SYSCFG configuration to the default reset state
|
||||
#define SYSCFG_DeInit EXTI_DeInit
|
||||
#define SYSCFG_MemoryRemapConfig EXTI_MemoryRemapConfig
|
||||
#define SYSCFG_EXTILineConfig EXTI_LineConfig
|
||||
u32 SYSCFG_GetPendingIT(u32 ITSourceLine);
|
||||
void SYSCFG_BreakConfig(u32 SYSCFG_Break);
|
||||
FlagStatus SYSCFG_GetFlagStatus(u32 SYSCFG_Flag);
|
||||
void SYSCFG_ClearFlag(u32 SYSCFG_Flag);
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_SYSCFG_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,755 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_tim.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE TIM
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_TIM_H
|
||||
#define __HAL_TIM_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_tim.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup TIM_HAL
|
||||
/// @brief TIM HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup TIM_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Channel
|
||||
/// @anchor TIM_Channel
|
||||
typedef enum {
|
||||
TIM_Channel_1 = 0x0000, ///< TIM Channel 1
|
||||
TIM_Channel_2 = 0x0004, ///< TIM Channel 2
|
||||
TIM_Channel_3 = 0x0008, ///< TIM Channel 3
|
||||
TIM_Channel_4 = 0x000C, ///< TIM Channel 4
|
||||
TIM_Channel_5 = 0x0010 ///< TIM Channel 5
|
||||
} TIMCHx_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Counter_Mode
|
||||
/// @anchor TIM_Counter_Mode
|
||||
typedef enum {
|
||||
TIM_CounterMode_Up = 0x0000, ///< TIM Up Counting Mode
|
||||
TIM_CounterMode_Down = TIM_CR1_DIR, ///< TIM Down Counting Mode
|
||||
TIM_CounterMode_CenterAligned1 = TIM_CR1_CMS_CENTERALIGNED1, ///< TIM Center Aligned Mode1
|
||||
TIM_CounterMode_CenterAligned2 = TIM_CR1_CMS_CENTERALIGNED2, ///< TIM Center Aligned Mode2
|
||||
TIM_CounterMode_CenterAligned3 = TIM_CR1_CMS_CENTERALIGNED3 ///< TIM Center Aligned Mode3
|
||||
} TIMCOUNTMODE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_and_PWM_modes_and_Forced_Action
|
||||
/// @anchor TIM_Output_Compare_and_PWM_modes_and_Forced_Action
|
||||
typedef enum {
|
||||
TIM_OCMode_Timing = 0x0000, ///< Output compare mode: Timing
|
||||
TIM_OCMode_Active = 0x0010, ///< Output compare mode: Active
|
||||
TIM_OCMode_Inactive = 0x0020, ///< Output compare mode: Inactive
|
||||
TIM_OCMode_Toggle = 0x0030, ///< Output compare mode: Toggle
|
||||
TIM_OCMode_PWM1 = 0x0060, ///< Output compare mode: PWM1
|
||||
TIM_OCMode_PWM2 = 0x0070, ///< Output compare mode: PWM2
|
||||
TIM_ForcedAction_Active = 0x0050, ///< Force active level on OCnREF
|
||||
TIM_ForcedAction_InActive = 0x0040 ///< Force inactive level on OCnREF
|
||||
} TIMOCMODE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Clock_Division_CKD
|
||||
/// @anchor TIM_Clock_Division_CKD
|
||||
typedef enum {
|
||||
TIM_CKD_DIV1 = TIM_CR1_CKD_DIV1, ///< TDTS = Tck_tim
|
||||
TIM_CKD_DIV2 = TIM_CR1_CKD_DIV2, ///< TDTS = 2 * Tck_tim
|
||||
TIM_CKD_DIV4 = TIM_CR1_CKD_DIV4 ///< TDTS = 4 * Tck_tim
|
||||
} TIMCKD_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Internal_Trigger_Selection
|
||||
/// @anchor TIM_Internal_Trigger_Selection
|
||||
typedef enum {
|
||||
TIM_TS_ITR0 = TIM_SMCR_TS_ITR0, ///< Internal Trigger 0
|
||||
TIM_TS_ITR1 = TIM_SMCR_TS_ITR1, ///< Internal Trigger 1
|
||||
TIM_TS_ITR2 = TIM_SMCR_TS_ITR2, ///< Internal Trigger 2
|
||||
TIM_TS_ITR3 = TIM_SMCR_TS_ITR3, ///< Internal Trigger 3
|
||||
TIM_TS_TI1F_ED = TIM_SMCR_TS_TI1F_ED, ///< TI1 Edge Detector
|
||||
TIM_TS_TI1FP1 = TIM_SMCR_TS_TI1FP1, ///< Filtered Timer Input 1
|
||||
TIM_TS_TI2FP2 = TIM_SMCR_TS_TI2FP2, ///< Filtered Timer Input 2
|
||||
TIM_TS_ETRF = TIM_SMCR_TS_ETRF ///< TI1 Edge Detector
|
||||
} TIMTS_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Trigger_Output_Source
|
||||
/// @anchor TIM_Trigger_Output_Source
|
||||
typedef enum {
|
||||
TIM_TRIGSource_Reset = TIM_CR2_MMS_RESET, ///< The UG bit in the TIM_EGR register is used as the trigger output (TRIG).
|
||||
TIM_TRIGSource_Enable = TIM_CR2_MMS_ENABLE, ///< The Counter Enable CEN is used as the trigger output (TRIG).
|
||||
TIM_TRIGSource_Update = TIM_CR2_MMS_UPDATE, ///< The update event is used as the trigger output (TRIG).
|
||||
TIM_TRIGSource_OC1 = TIM_CR2_MMS_OC1, ///< The trigger output sends a positive pulse when the CC1IF flag
|
||||
///< is to be set, as soon as a capture or compare match occurs (TRIG).
|
||||
TIM_TRIGSource_OC1Ref = TIM_CR2_MMS_OC1REF, ///< OC1REF signal is used as the trigger output (TRIG).
|
||||
TIM_TRIGSource_OC2Ref = TIM_CR2_MMS_OC2REF, ///< OC2REF signal is used as the trigger output (TRIG).
|
||||
TIM_TRIGSource_OC3Ref = TIM_CR2_MMS_OC3REF, ///< OC3REF signal is used as the trigger output (TRIG).
|
||||
TIM_TRIGSource_OC4Ref = TIM_CR2_MMS_OC4REF ///< OC4REF signal is used as the trigger output (TRIG).
|
||||
} TIMMMS_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Slave_Mode
|
||||
/// @anchor TIM_Slave_Mode
|
||||
typedef enum {
|
||||
TIM_SlaveMode_Reset = TIM_SMCR_SMS_RESET, ///< Rising edge of the selected trigger signal (TRGI) re-initializes
|
||||
///< the counter and triggers an update of the registers.
|
||||
TIM_SlaveMode_Gated = TIM_SMCR_SMS_GATED, ///< The counter clock is enabled when the trigger signal (TRGI) is high.
|
||||
TIM_SlaveMode_Trigger = TIM_SMCR_SMS_TRIGGER, ///< The counter starts at a rising edge of the trigger TRGI.
|
||||
TIM_SlaveMode_External1 = TIM_SMCR_SMS_EXTERNAL1 ///< Rising edges of the selected trigger (TRGI) clock the counter.
|
||||
} TIMSMSMODE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Event_Source
|
||||
/// @anchor TIM_Event_Source
|
||||
typedef enum {
|
||||
TIM_EventSource_Update = TIM_EGR_UG, ///< Timer update Event source
|
||||
TIM_EventSource_CC1 = TIM_EGR_CC1G, ///< Timer Capture Compare 1 Event source
|
||||
TIM_EventSource_CC2 = TIM_EGR_CC2G, ///< Timer Capture Compare 2 Event source
|
||||
TIM_EventSource_CC3 = TIM_EGR_CC3G, ///< Timer Capture Compare 3 Event source
|
||||
TIM_EventSource_CC4 = TIM_EGR_CC4G, ///< Timer Capture Compare 4 Event source
|
||||
TIM_EventSource_COM = TIM_EGR_COMG, ///< Timer COM event source
|
||||
TIM_EventSource_Trigger = TIM_EGR_TG, ///< Timer Trigger Event source
|
||||
TIM_EventSource_Break = TIM_EGR_BG, ///< Timer Break event source
|
||||
TIM_EventSource_CC5 = (s32)0x00010000, ///< Timer Capture Compare 5 Event source
|
||||
} TIMEGR_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_External_Trigger_Prescaler
|
||||
/// @anchor TIM_External_Trigger_Prescaler
|
||||
typedef enum {
|
||||
TIM_ExtTRGPSC_OFF = TIM_SMCR_ETPS_OFF, ///< ETRP Prescaler OFF
|
||||
TIM_ExtTRGPSC_DIV2 = TIM_SMCR_ETPS_DIV2, ///< ETRP frequency divided by 2
|
||||
TIM_ExtTRGPSC_DIV4 = TIM_SMCR_ETPS_DIV4, ///< ETRP frequency divided by 4
|
||||
TIM_ExtTRGPSC_DIV8 = TIM_SMCR_ETPS_DIV8 ///< ETRP frequency divided by 8
|
||||
} TIMEXTTRGPSC_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_TIx_External_Clock_Source
|
||||
/// @anchor TIM_TIx_External_Clock_Source
|
||||
typedef enum {
|
||||
TIM_TIxExternalCLK1Source_TI1 = TIM_SMCR_TS_TI1FP1, ///< Filtered Timer Input 1
|
||||
TIM_TIxExternalCLK1Source_TI2 = TIM_SMCR_TS_TI2FP2, ///< Filtered Timer Input 2
|
||||
TIM_TIxExternalCLK1Source_TI1ED = TIM_SMCR_TS_TI1F_ED ///< TI1 Edge Detector
|
||||
} TIM_TIEXTCLKSRC_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Lock_level
|
||||
/// @anchor Lock_level
|
||||
typedef enum {
|
||||
TIM_LOCKLevel_OFF = TIM_BDTR_LOCK_OFF, ///< No bit is write protected.
|
||||
TIM_LOCKLevel_1 = TIM_BDTR_LOCK_1, ///< DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
|
||||
///< register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
|
||||
TIM_LOCKLevel_2 = TIM_BDTR_LOCK_2, ///< LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
|
||||
///< register, as s32 as the related channel is configured in output through the CCxS
|
||||
///< bits) as well as OSSR and OSSI bits can no longer be written.
|
||||
TIM_LOCKLevel_3 = TIM_BDTR_LOCK_3 ///< LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers,
|
||||
///< as s32 as the related channel is configured in output through the CCxS bits)
|
||||
///< can no longer be written.
|
||||
} TIMLOCKLEVEL_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_One_Pulse_Mode
|
||||
/// @anchor TIM_One_Pulse_Mode
|
||||
typedef enum {
|
||||
TIM_OPMode_Repetitive = 0, ///< Counter is not stopped at update event
|
||||
TIM_OPMode_Single = TIM_CR1_OPM ///< Counter stops counting at the next update event (clearing the bit CEN)
|
||||
} TIMOPMODE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_Polarity
|
||||
/// @anchor TIM_Output_Compare_Polarity
|
||||
typedef enum {
|
||||
TIM_OCPolarity_High, ///< Output Compare active high
|
||||
TIM_OCPolarity_Low = TIM_CCER_CC1P ///< Output Compare active low
|
||||
} TIMCCxP_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_N_Polarity
|
||||
/// @anchor TIM_Output_Compare_N_Polarity
|
||||
typedef enum {
|
||||
TIM_OCNPolarity_High, ///< Output Compare active high
|
||||
TIM_OCNPolarity_Low = TIM_CCER_CC1NP ///< Output Compare active low
|
||||
} TIMCCxNP_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_state
|
||||
/// @anchor TIM_Output_Compare_state
|
||||
typedef enum {
|
||||
TIM_OutputState_Disable = 0, ///< Output Compare Disable
|
||||
TIM_OutputState_Enable = TIM_CCER_CC1EN ///< Output Compare Enable
|
||||
} TIMOUTPUTSTATE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_N_state
|
||||
/// @anchor TIM_Output_Compare_N_state
|
||||
typedef enum {
|
||||
TIM_OutputNState_Disable = 0, ///< Output Compare N Disable
|
||||
TIM_OutputNState_Enable = TIM_CCER_CC1NEN ///< Output Compare N Enable
|
||||
} TIMOUTPUTNSTATE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Capture_Compare_state
|
||||
/// @anchor TIM_Capture_Compare_state
|
||||
typedef enum {
|
||||
TIM_CCx_Disable = 0, ///< Capture/Compare Enable
|
||||
TIM_CCx_Enable = TIM_CCER_CC1EN ///< Capture/Compare Enable
|
||||
} TIMCCxE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Capture_Compare_N_state
|
||||
/// @anchor TIM_Capture_Compare_N_state
|
||||
typedef enum {
|
||||
TIM_CCxN_Disable = 0, ///< Capture/Compare N Enable
|
||||
TIM_CCxN_Enable = TIM_CCER_CC1NEN ///< Capture/Compare N Enable
|
||||
} TIMCCxNE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Break_Input_enable_disable
|
||||
/// @anchor Break_Input_enable_disable
|
||||
typedef enum {
|
||||
TIM_Break_Disable = 0, ///< Break inputs (BRK and CSS clock failure event) disabled
|
||||
TIM_Break_Enable = TIM_BDTR_BKEN ///< Break inputs (BRK and CSS clock failure event) enabled
|
||||
} TIMBKE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Break_Polarity
|
||||
/// @anchor Break_Polarity
|
||||
typedef enum {
|
||||
TIM_BreakPolarity_Low = 0, ///< Break input BRK is active low
|
||||
TIM_BreakPolarity_High = TIM_BDTR_BKP ///< Break input BRK is active high
|
||||
} TIMBKP_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_AOE_Bit_Set_Reset
|
||||
/// @anchor TIM_AOE_Bit_Set_Reset
|
||||
typedef enum {
|
||||
TIM_AutomaticOutput_Disable = 0, ///< MOE can be set only by software.
|
||||
TIM_AutomaticOutput_Enable = TIM_BDTR_AOEN ///< MOE can be set by software or automatically at the next
|
||||
///< update event (if the break input is not be active).
|
||||
} TIMAOE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_DOE_Bit_Set_Reset
|
||||
/// @anchor TIM_DOE_Bit_Set_Reset
|
||||
typedef enum {
|
||||
TIM_DirectOutput_Disable = 0, ///< Direct output disable, output waiting for dead time
|
||||
TIM_DirectOutput_Enable = TIM_BDTR_DOEN ///< Direct output enable, no longer waiting for output after dead time
|
||||
} TIMDOE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief OSSI_Off_State_Selection_for_Idle_mode_state
|
||||
/// @anchor OSSI_Off_State_Selection_for_Idle_mode_state
|
||||
typedef enum {
|
||||
TIM_OSSIState_Disable = 0, ///< When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
|
||||
TIM_OSSIState_Enable = TIM_BDTR_OSSI ///< When inactive, OC/OCN outputs are forced first with their idle level
|
||||
///< as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1).
|
||||
} TIMOSSI_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief OSSR_Off_State_Selection_for_Run_mode_state
|
||||
/// @anchor OSSR_Off_State_Selection_for_Run_mode_state
|
||||
typedef enum {
|
||||
TIM_OSSRState_Disable = 0, ///< When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
|
||||
TIM_OSSRState_Enable = TIM_BDTR_OSSR ///< When inactive, OC/OCN outputs are enabled with their inactive level
|
||||
///< as soon as CCxE=1 or CCxNE=1. Then, OC/OCN enable output signal=1.
|
||||
} TIMOSSR_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_Idle_State
|
||||
/// @anchor TIM_Output_Compare_Idle_State
|
||||
typedef enum {
|
||||
TIM_OCIdleState_Reset = 0, ///< OCn=0 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4)
|
||||
TIM_OCIdleState_Set = TIM_CR2_OIS1 ///< OCn=1 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4)
|
||||
} TIMOIS_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_N_Idle_State
|
||||
/// @anchor TIM_Output_Compare_N_Idle_State
|
||||
typedef enum {
|
||||
TIM_OCNIdleState_Reset = 0, ///< OCnN=0 after a dead-time when MOE=0.(n= 0 : 4)
|
||||
TIM_OCNIdleState_Set = TIM_CR2_OIS1N ///< OCnN=1 after a dead-time when MOE=0.(n= 0 : 4)
|
||||
} TIMOISN_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Input_Capture_Selection
|
||||
/// @anchor TIM_Input_Capture_Selection
|
||||
typedef enum {
|
||||
TIM_ICSelection_DirectTI = TIM_CCMR1_CC1S_DIRECTTI,
|
||||
TIM_ICSelection_IndirectTI = TIM_CCMR1_CC1S_INDIRECTTI,
|
||||
TIM_ICSelection_TRC = TIM_CCMR1_CC1S_TRC ///< TIM Input is selected to be connected to TRC.
|
||||
} TIMICSEL_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Input_Capture_Prescaler
|
||||
/// @anchor TIM_Input_Capture_Prescaler
|
||||
typedef enum {
|
||||
TIM_ICPSC_DIV1 = 0x0000, ///< no prescaler
|
||||
TIM_ICPSC_DIV2 = 0x0004, ///< capture is done once every 2 events
|
||||
TIM_ICPSC_DIV4 = 0x0008, ///< capture is done once every 4 events
|
||||
TIM_ICPSC_DIV8 = 0x000C ///< capture is done once every 8 events
|
||||
} TIMICPSC_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Input_Capture_Polarity
|
||||
/// @anchor TIM_Input_Capture_Polarity
|
||||
typedef enum {
|
||||
TIM_ICPolarity_Rising = 0, ///< IC Rising edge
|
||||
TIM_ICPolarity_Falling = TIM_CCER_CC1P, ///< IC Falling edge
|
||||
TIM_ICPolarity_BothEdge = TIM_CCER_CC1P | TIM_CCER_CC1NP
|
||||
} TIMICP_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_External_Trigger_Polarity
|
||||
/// @anchor TIM_External_Trigger_Polarity
|
||||
typedef enum {
|
||||
TIM_ExtTRGPolarity_NonInverted = 0, ///< Active high or rising edge active
|
||||
TIM_ExtTRGPolarity_Inverted = TIM_SMCR_ETP ///< Active low or falling edge active
|
||||
} TIMETP_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Prescaler_Reload_Mode
|
||||
/// @anchor TIM_Prescaler_Reload_Mode
|
||||
typedef enum {
|
||||
TIM_PSCReloadMode_Update = 0, ///< The Prescaler is loaded at the update event
|
||||
TIM_PSCReloadMode_Immediate = TIM_EGR_UG ///< The Prescaler is loaded immediately
|
||||
} TIMUG_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Encoder_Mode
|
||||
/// @anchor TIM_Encoder_Mode
|
||||
typedef enum {
|
||||
TIM_EncoderMode_TI1 = TIM_SMCR_SMS_ENCODER1, ///< Counter counts on TI1FP1 edge depending on TI2FP2 level.
|
||||
TIM_EncoderMode_TI2 = TIM_SMCR_SMS_ENCODER2, ///< Counter counts on TI2FP2 edge depending on TI1FP1 level.
|
||||
TIM_EncoderMode_TI12 = TIM_SMCR_SMS_ENCODER3 ///< Counter counts on both TI1FP1 and TI2FP2 edges depending
|
||||
///< on the level of the other input.
|
||||
} TIMSMSENCODER_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Update_Source
|
||||
/// @anchor TIM_Update_Source
|
||||
typedef enum {
|
||||
TIM_UpdateSource_Global = 0, ///< Source of update is counter overflow/underflow.
|
||||
TIM_UpdateSource_Regular = TIM_CR1_URS ///< Source of update is the counter overflow/underflow
|
||||
///< or the setting of UG bit, or an update generation
|
||||
///< through the slave mode controller.
|
||||
} TIMURS_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_Preload_State
|
||||
/// @anchor TIM_Output_Compare_Preload_State
|
||||
typedef enum {
|
||||
TIM_OCPreload_Disable = 0, ///< TIM output compare preload disable
|
||||
TIM_OCPreload_Enable = TIM_CCMR1_OC1PEN ///< TIM output compare preload enable
|
||||
} TIMOCPE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_Fast_State
|
||||
/// @anchor TIM_Output_Compare_Fast_State
|
||||
typedef enum {
|
||||
TIM_OCFast_Disable = 0, ///< TIM output compare fast disable
|
||||
TIM_OCFast_Enable = TIM_CCMR1_OC1FEN, ///< TIM output compare fast enable
|
||||
} TIMOCFE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_Clear_State
|
||||
/// @anchor TIM_Output_Compare_Clear_State
|
||||
typedef enum {
|
||||
TIM_OCClear_Disable = 0, ///< TIM Output clear disable
|
||||
TIM_OCClear_Enable = TIM_CCMR1_OC1CEN ///< TIM Output clear enable
|
||||
} TIMOCCE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Master_Slave_Mode
|
||||
/// @anchor TIM_Master_Slave_Mode
|
||||
typedef enum {
|
||||
TIM_MasterSlaveMode_Disable = 0, ///< No action
|
||||
TIM_MasterSlaveMode_Enable = TIM_SMCR_MSM ///< synchronization between the current timer and its slaves (through TRIG)
|
||||
} TIMMSM_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_interrupt_sources
|
||||
/// @anchor TIM_Master_Slave_Mode
|
||||
typedef enum {
|
||||
TIM_IT_Update = TIM_DIER_UI, ///< TIM update Interrupt source
|
||||
TIM_IT_CC1 = TIM_DIER_CC1I, ///< TIM Capture Compare 1 Interrupt source
|
||||
TIM_IT_CC2 = TIM_DIER_CC2I, ///< TIM Capture Compare 2 Interrupt source
|
||||
TIM_IT_CC3 = TIM_DIER_CC3I, ///< TIM Capture Compare 3 Interrupt source
|
||||
TIM_IT_CC4 = TIM_DIER_CC4I, ///< TIM Capture Compare 4 Interrupt source
|
||||
TIM_IT_COM = TIM_DIER_COMI, ///< TIM Commutation Interrupt source
|
||||
TIM_IT_Trigger = TIM_DIER_TI, ///< TIM Trigger Interrupt source
|
||||
TIM_IT_Break = TIM_DIER_BI ///< TIM Break Interrupt source
|
||||
, TIM_IT_CC5 = TIM_DIER_CC5I ///< TIM Capture Compare 5 Interrupt source
|
||||
} TIMIT_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Flags
|
||||
/// @anchor TIM_Flags
|
||||
typedef enum {
|
||||
TIM_FLAG_Update = TIM_SR_UI, ///< TIM update Flag
|
||||
TIM_FLAG_CC1 = TIM_SR_CC1I, ///< TIM Capture Compare 1 Flag
|
||||
TIM_FLAG_CC2 = TIM_SR_CC2I, ///< TIM Capture Compare 2 Flag
|
||||
TIM_FLAG_CC3 = TIM_SR_CC3I, ///< TIM Capture Compare 3 Flag
|
||||
TIM_FLAG_CC4 = TIM_SR_CC4I, ///< TIM Capture Compare 4 Flag
|
||||
TIM_FLAG_COM = TIM_SR_COMI, ///< TIM Commutation Flag
|
||||
TIM_FLAG_Trigger = TIM_SR_TI, ///< TIM Trigger Flag
|
||||
TIM_FLAG_Break = TIM_SR_BI, ///< TIM Break Flag
|
||||
TIM_FLAG_CC1OF = TIM_SR_CC1O, ///< TIM Capture Compare 1 overcapture Flag
|
||||
TIM_FLAG_CC2OF = TIM_SR_CC2O, ///< TIM Capture Compare 2 overcapture Flag
|
||||
TIM_FLAG_CC3OF = TIM_SR_CC3O, ///< TIM Capture Compare 3 overcapture Flag
|
||||
TIM_FLAG_CC4OF = TIM_SR_CC4O ///< TIM Capture Compare 4 overcapture Flag
|
||||
, TIM_FLAG_CC5 = TIM_SR_CC5I ///< TIM Capture Compare 5 Flag
|
||||
} TIMFLAG_Typedef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_DMA_sources
|
||||
/// @anchor TIM_DMA_sources
|
||||
typedef enum {
|
||||
TIM_DMA_Update = TIM_DIER_UD, ///< TIM update Interrupt source
|
||||
TIM_DMA_CC1 = TIM_DIER_CC1D, ///< TIM Capture Compare 1 DMA source
|
||||
TIM_DMA_CC2 = TIM_DIER_CC2D, ///< TIM Capture Compare 2 DMA source
|
||||
TIM_DMA_CC3 = TIM_DIER_CC3D, ///< TIM Capture Compare 3 DMA source
|
||||
TIM_DMA_CC4 = TIM_DIER_CC4D, ///< TIM Capture Compare 4 DMA source
|
||||
TIM_DMA_COM = TIM_DIER_COMD, ///< TIM Commutation DMA source
|
||||
TIM_DMA_Trigger = TIM_DIER_TD ///< TIM Trigger DMA source
|
||||
} TIMDMASRC_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_DMA_Base_address
|
||||
/// @anchor TIM_DMA_Base_address
|
||||
typedef enum {
|
||||
TIM_DMABase_CR1 = 0x0000,
|
||||
TIM_DMABase_CR2 = 0x0001,
|
||||
TIM_DMABase_SMCR = 0x0002,
|
||||
TIM_DMABase_DIER = 0x0003,
|
||||
TIM_DMABase_SR = 0x0004,
|
||||
TIM_DMABase_EGR = 0x0005,
|
||||
TIM_DMABase_CCMR1 = 0x0006,
|
||||
TIM_DMABase_CCMR2 = 0x0007,
|
||||
TIM_DMABase_CCER = 0x0008,
|
||||
TIM_DMABase_CNT = 0x0009,
|
||||
TIM_DMABase_PSC = 0x000A,
|
||||
TIM_DMABase_ARR = 0x000B,
|
||||
TIM_DMABase_RCR = 0x000C,
|
||||
TIM_DMABase_CCR1 = 0x000D,
|
||||
TIM_DMABase_CCR2 = 0x000E,
|
||||
TIM_DMABase_CCR3 = 0x000F,
|
||||
TIM_DMABase_CCR4 = 0x0010,
|
||||
TIM_DMABase_BDTR = 0x0011,
|
||||
TIM_DMABase_DCR = 0x0012
|
||||
} TIMDMABASE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_DMA_Burst_Length
|
||||
/// @anchor TIM_DMA_Burst_Length
|
||||
typedef enum {
|
||||
TIM_DMABurstLength_1Byte = 0x0000,
|
||||
TIM_DMABurstLength_2Bytes = 0x0100,
|
||||
TIM_DMABurstLength_3Bytes = 0x0200,
|
||||
TIM_DMABurstLength_4Bytes = 0x0300,
|
||||
TIM_DMABurstLength_5Bytes = 0x0400,
|
||||
TIM_DMABurstLength_6Bytes = 0x0500,
|
||||
TIM_DMABurstLength_7Bytes = 0x0600,
|
||||
TIM_DMABurstLength_8Bytes = 0x0700,
|
||||
TIM_DMABurstLength_9Bytes = 0x0800,
|
||||
TIM_DMABurstLength_10Bytes = 0x0900,
|
||||
TIM_DMABurstLength_11Bytes = 0x0A00,
|
||||
TIM_DMABurstLength_12Bytes = 0x0B00,
|
||||
TIM_DMABurstLength_13Bytes = 0x0C00,
|
||||
TIM_DMABurstLength_14Bytes = 0x0D00,
|
||||
TIM_DMABurstLength_15Bytes = 0x0E00,
|
||||
TIM_DMABurstLength_16Bytes = 0x0F00,
|
||||
TIM_DMABurstLength_17Bytes = 0x1000,
|
||||
TIM_DMABurstLength_18Bytes = 0x1100
|
||||
} TIMDMABURSTLENGTH_Typedef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM Time Base Init structure definition
|
||||
/// @note This structure is used with all tim.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u16 TIM_Prescaler; ///< Specifies the prescaler value used to divide the TIM clock.
|
||||
///< This parameter can be a number between 0x0000 and 0xFFFF
|
||||
TIMCOUNTMODE_Typedef TIM_CounterMode; ///< Specifies the counter mode.
|
||||
///< This parameter can be a value of @ref TIM_Counter_Mode
|
||||
u32 TIM_Period; ///< Specifies the period value to be loaded into the active
|
||||
///< Auto-Reload Register at the next update event.
|
||||
///< This parameter must be a number between 0x0000 and 0xFFFF/0xFFFFFFFF.
|
||||
///< @note 0xFFFFFFFF is valid only for MM32 32bit Timers: eg.TIM2 or TIM5.
|
||||
TIMCKD_TypeDef TIM_ClockDivision; ///< Specifies the clock division.
|
||||
///< This parameter can be a value of @ref TIM_Clock_Division_CKD
|
||||
u8 TIM_RepetitionCounter; ///< Specifies the repetition counter value. Each time the RCR downcounter
|
||||
///< reaches zero, an update event is generated and counting restarts
|
||||
///< from the RCR value (N).
|
||||
///< This means in PWM mode that (N+1) corresponds to:
|
||||
///< - the number of PWM periods in edge-aligned mode
|
||||
///< - the number of half PWM period in center-aligned mode
|
||||
///< This parameter must be a number between 0x00 and 0xFF.
|
||||
///< @note This parameter is valid only for TIM1 and TIM8.
|
||||
} TIM_TimeBaseInitTypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM Output Compare Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
TIMOCMODE_Typedef TIM_OCMode; ///< Specifies the TIM mode.
|
||||
///< This parameter can be a value of TIM_Output_Compare_and_PWM_modes
|
||||
TIMOUTPUTSTATE_Typedef TIM_OutputState; ///< Specifies the TIM Output Compare state.
|
||||
///< This parameter can be a value of TIM_Output_Compare_state
|
||||
TIMOUTPUTNSTATE_Typedef TIM_OutputNState; ///< Specifies the TIM complementary Output Compare state.
|
||||
///< This parameter can be a value of TIM_Output_Compare_N_state
|
||||
///< @note This parameter is valid only for TIM1 and TIM8.
|
||||
u32 TIM_Pulse; ///< Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||
///< This parameter can be a number between 0x0000 and 0xFFFF/0xFFFFFFFF
|
||||
///< @note 0xFFFFFFFF is valid only for MM32 32bit Timers: eg.TIM2 or TIM5.
|
||||
TIMCCxP_Typedef TIM_OCPolarity; ///< Specifies the output polarity.
|
||||
///< This parameter can be a value of @ref TIM_Output_Compare_Polarity
|
||||
TIMCCxNP_Typedef TIM_OCNPolarity; ///< Specifies the complementary output polarity.
|
||||
///< This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
|
||||
///< @note This parameter is valid only for TIM1 and TIM8.
|
||||
TIMOIS_Typedef TIM_OCIdleState; ///< Specifies the TIM Output Compare pin state during Idle state.
|
||||
///< This parameter can be a value of @ref TIM_Output_Compare_Idle_State
|
||||
///< @note This parameter is valid only for TIM1 and TIM8.
|
||||
TIMOISN_Typedef TIM_OCNIdleState; ///< Specifies the TIM Output Compare pin state during Idle state.
|
||||
///< This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
|
||||
///< @note This parameter is valid only for TIM1 and TIM8.
|
||||
} TIM_OCInitTypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM Input Capture Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
TIMCHx_Typedef TIM_Channel; ///< Specifies the TIM channel.
|
||||
///< This parameter can be a value of @ref TIM_Channel
|
||||
TIMICP_Typedef TIM_ICPolarity; ///< Specifies the active edge of the input signal.
|
||||
///< This parameter can be a value of @ref TIM_Input_Capture_Polarity
|
||||
TIMICSEL_Typedef TIM_ICSelection; ///< Specifies the input.
|
||||
///< This parameter can be a value of @ref TIM_Input_Capture_Selection
|
||||
TIMICPSC_Typedef TIM_ICPrescaler; ///< Specifies the Input Capture Prescaler.
|
||||
///< This parameter can be a value of @ref TIM_Input_Capture_Prescaler
|
||||
u16 TIM_ICFilter; ///< Specifies the input capture filter.
|
||||
///< This parameter can be a number between 0x0 and 0xF
|
||||
} TIM_ICInitTypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief BDTR structure definition
|
||||
/// @note This structure is used only with TIM1 and TIM8.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
TIMOSSR_Typedef TIM_OSSRState; ///< Specifies the Off-State selection used in Run mode.
|
||||
///< This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state
|
||||
TIMOSSI_Typedef TIM_OSSIState; ///< Specifies the Off-State used in Idle state.
|
||||
///< This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state
|
||||
TIMLOCKLEVEL_Typedef TIM_LOCKLevel; ///< Specifies the LOCK level parameters.
|
||||
///< This parameter can be a value of @ref Lock_level
|
||||
u16 TIM_DeadTime; ///< Specifies the delay time between the switching-off and
|
||||
///< the switching-on of the outputs.
|
||||
///< This parameter can be a number between 0x00 and 0xFF
|
||||
TIMBKE_Typedef TIM_Break; ///< Specifies whether the TIM Break input is enabled or not.
|
||||
///< This parameter can be a value of @ref Break_Input_enable_disable
|
||||
TIMBKP_Typedef TIM_BreakPolarity; ///< Specifies the TIM Break Input pin polarity.
|
||||
///< This parameter can be a value of @ref Break_Polarity
|
||||
TIMAOE_Typedef TIM_AutomaticOutput; ///< Specifies whether the TIM Automatic Output feature is enabled or not.
|
||||
///< This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset
|
||||
} TIM_BDTRInitTypeDef;
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup TIM_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_TIM_C_
|
||||
#define GLOBAL
|
||||
|
||||
static void TI1_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
|
||||
static void TI2_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
|
||||
static void TI3_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
|
||||
static void TI4_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
|
||||
|
||||
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup TIM_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//================= TimeBase management ======================================
|
||||
void TIM_DeInit(TIM_TypeDef* tim);
|
||||
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* init_struct);
|
||||
void TIM_TimeBaseInit(TIM_TypeDef* tim, TIM_TimeBaseInitTypeDef* init_struct);
|
||||
void TIM_PrescalerConfig(TIM_TypeDef* tim, u16 prescaler, TIMUG_Typedef reload_mode);
|
||||
void TIM_CounterModeConfig(TIM_TypeDef* tim, TIMCOUNTMODE_Typedef counter_mode);
|
||||
void TIM_SetCounter(TIM_TypeDef* tim, u32 counter);
|
||||
void TIM_SetAutoreload(TIM_TypeDef* tim, u16 auto_reload);
|
||||
void TIM_UpdateDisableConfig(TIM_TypeDef* tim, FunctionalState state);
|
||||
void TIM_UpdateRequestConfig(TIM_TypeDef* tim, TIMURS_Typedef source);
|
||||
void TIM_ARRPreloadConfig(TIM_TypeDef* tim, FunctionalState state);
|
||||
void TIM_SelectOnePulseMode(TIM_TypeDef* tim, TIMOPMODE_Typedef mode);
|
||||
void TIM_SetClockDivision(TIM_TypeDef* tim, TIMCKD_TypeDef clock_div);
|
||||
void TIM_Cmd(TIM_TypeDef* tim, FunctionalState state);
|
||||
|
||||
u32 TIM_GetCounter(TIM_TypeDef* tim);
|
||||
u16 TIM_GetPrescaler(TIM_TypeDef* tim);
|
||||
|
||||
//================= Advanced-control timers specific features ================
|
||||
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* init_struct);
|
||||
void TIM_BDTRConfig(TIM_TypeDef* tim, TIM_BDTRInitTypeDef* init_struct);
|
||||
void TIM_CtrlPWMOutputs(TIM_TypeDef* tim, FunctionalState state);
|
||||
|
||||
//================= Output Compare management ================================
|
||||
void TIM_OCStructInit(TIM_OCInitTypeDef* init_struct);
|
||||
void TIM_OC1Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
|
||||
void TIM_OC2Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
|
||||
void TIM_OC3Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
|
||||
void TIM_OC4Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
|
||||
void TIM_SelectOCxM(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMOCMODE_Typedef mode);
|
||||
void TIM_SetCompare1(TIM_TypeDef* tim, u32 compare);
|
||||
void TIM_SetCompare2(TIM_TypeDef* tim, u32 compare);
|
||||
void TIM_SetCompare3(TIM_TypeDef* tim, u32 compare);
|
||||
void TIM_SetCompare4(TIM_TypeDef* tim, u32 compare);
|
||||
void TIM_ForcedOC1Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
|
||||
void TIM_ForcedOC2Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
|
||||
void TIM_ForcedOC3Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
|
||||
void TIM_ForcedOC4Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
|
||||
void TIM_CCPreloadControl(TIM_TypeDef* tim, FunctionalState state);
|
||||
void TIM_OC1PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
|
||||
void TIM_OC2PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
|
||||
void TIM_OC3PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
|
||||
void TIM_OC4PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
|
||||
void TIM_OC1FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
|
||||
void TIM_OC2FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
|
||||
void TIM_OC3FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
|
||||
void TIM_OC4FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
|
||||
void TIM_ClearOC1Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
|
||||
void TIM_ClearOC2Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
|
||||
void TIM_ClearOC3Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
|
||||
void TIM_ClearOC4Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
|
||||
void TIM_OC1PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
|
||||
void TIM_OC1NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity);
|
||||
void TIM_OC2PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
|
||||
void TIM_OC2NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity);
|
||||
void TIM_OC3PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
|
||||
void TIM_OC3NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity);
|
||||
void TIM_OC4PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
|
||||
void TIM_CCxCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxE_Typedef ccx_en);
|
||||
void TIM_CCxNCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxNE_Typedef ccxn_en);
|
||||
void TIM_SelectCOM(TIM_TypeDef* tim, FunctionalState state);
|
||||
|
||||
//================= Input Capture management =================================
|
||||
void TIM_ICStructInit(TIM_ICInitTypeDef* init_struct);
|
||||
void TIM_ICInit(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct);
|
||||
void TIM_PWMIConfig(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct);
|
||||
void TIM_SetIC1Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
|
||||
void TIM_SetIC2Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
|
||||
void TIM_SetIC3Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
|
||||
void TIM_SetIC4Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
|
||||
|
||||
u32 TIM_GetCapture1(TIM_TypeDef* tim);
|
||||
u32 TIM_GetCapture2(TIM_TypeDef* tim);
|
||||
u32 TIM_GetCapture3(TIM_TypeDef* tim);
|
||||
u32 TIM_GetCapture4(TIM_TypeDef* tim);
|
||||
|
||||
//================= Interrupts, DMA and flags management =====================
|
||||
void TIM_ITConfig(TIM_TypeDef* tim, u32 it, FunctionalState state);//TIMIT_TypeDef
|
||||
void TIM_GenerateEvent(TIM_TypeDef* tim, TIMEGR_Typedef source);
|
||||
void TIM_ClearFlag(TIM_TypeDef* tim, TIMFLAG_Typedef flag);
|
||||
void TIM_ClearITPendingBit(TIM_TypeDef* tim, u32 it);//TIMIT_TypeDef
|
||||
void TIM_DMAConfig(TIM_TypeDef* tim, TIMDMABASE_Typedef dma_base, TIMDMABURSTLENGTH_Typedef length);
|
||||
void TIM_DMACmd(TIM_TypeDef* tim, TIMDMASRC_Typedef source, FunctionalState state);
|
||||
void TIM_SelectCCDMA(TIM_TypeDef* tim, FunctionalState state);
|
||||
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* tim, TIMFLAG_Typedef flag);
|
||||
ITStatus TIM_GetITStatus(TIM_TypeDef* tim, TIMIT_TypeDef it);
|
||||
|
||||
//================= Clocks management ========================================
|
||||
void TIM_InternalClockConfig(TIM_TypeDef* tim);
|
||||
void TIM_ITRxExternalClockConfig(TIM_TypeDef* tim, TIMTS_TypeDef source);
|
||||
void TIM_TIxExternalClockConfig(TIM_TypeDef* tim, TIM_TIEXTCLKSRC_Typedef source, TIMICP_Typedef polarity, u16 filter);
|
||||
void TIM_ETRClockMode1Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter);
|
||||
void TIM_ETRClockMode2Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter);
|
||||
|
||||
//================= Synchronization management ===============================
|
||||
void TIM_SelectInputTrigger(TIM_TypeDef* tim, TIMTS_TypeDef source);
|
||||
void TIM_SelectOutputTrigger(TIM_TypeDef* tim, TIMMMS_Typedef source);
|
||||
void TIM_SelectSlaveMode(TIM_TypeDef* tim, TIMSMSMODE_Typedef mode);
|
||||
void TIM_SelectMasterSlaveMode(TIM_TypeDef* tim, TIMMSM_Typedef mode);
|
||||
void TIM_ETRConfig(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter);
|
||||
|
||||
//================= Specific interface management ============================
|
||||
void TIM_EncoderInterfaceConfig(TIM_TypeDef* tim,
|
||||
TIMSMSENCODER_Typedef encoder_mode,
|
||||
TIMICP_Typedef ic1_polarity,
|
||||
TIMICP_Typedef iC2_polarity);
|
||||
void TIM_SelectHallSensor(TIM_TypeDef* tim, FunctionalState state);
|
||||
|
||||
//================= extend Channel IC management ==============================
|
||||
void TIM_SetIC1Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
|
||||
void TIM_SetIC2Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
|
||||
void TIM_SetIC3Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
|
||||
void TIM_SetIC4Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
|
||||
|
||||
#define exTIM_SetIC1Plority TIM_SetIC1Plority
|
||||
#define exTIM_SetIC2Plority TIM_SetIC2Plority
|
||||
#define exTIM_SetIC3Plority TIM_SetIC3Plority
|
||||
#define exTIM_SetIC4Plority TIM_SetIC4Plority
|
||||
//================= extend Channel 5 management ==============================
|
||||
|
||||
void TIM_SetCompare5(TIM_TypeDef* tim, u32 compare);
|
||||
void TIM_OC5Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
|
||||
void TIM_OC5PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
|
||||
void TIM_OC5PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
|
||||
void TIM_OC5FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
|
||||
void TIM_ClearOC5Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
|
||||
u32 TIM_GetCapture5(TIM_TypeDef* tim);
|
||||
|
||||
#define exTIM_SetCompare5 TIM_SetCompare5
|
||||
#define exTIM_OC5Init TIM_OC5Init
|
||||
#define exTIM_OC5PreloadConfig TIM_OC5PreloadConfig
|
||||
#define exTIM_OC5PolarityConfig TIM_OC5PolarityConfig
|
||||
#define exTIM_OC5FastConfig TIM_OC5FastConfig
|
||||
#define exTIM_ClearOC5Ref TIM_ClearOC5Ref
|
||||
#define exTIM_GetCapture5 TIM_GetCapture5
|
||||
|
||||
//============= extend Advanced-control timers specific features ==============
|
||||
void TIM_DirectOutput(TIM_TypeDef* tim, FunctionalState state);
|
||||
#define exTIM_DirectOutput TIM_DirectOutput
|
||||
void TIM_PWMShiftConfig(TIM_TypeDef* tim, u32 it, FunctionalState state);
|
||||
void TIM_SetCCR1FALL(TIM_TypeDef* tim, u32 shift);
|
||||
void TIM_SetCCR2FALL(TIM_TypeDef* tim, u32 shift);
|
||||
void TIM_SetCCR3FALL(TIM_TypeDef* tim, u32 shift);
|
||||
void TIM_SetCCR4FALL(TIM_TypeDef* tim, u32 shift);
|
||||
void TIM_SetCCR5FALL(TIM_TypeDef* tim, u32 shift);
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_TIM_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,211 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_uart.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UART
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_UART_H
|
||||
#define __HAL_UART_H
|
||||
|
||||
// Files includes
|
||||
#include "reg_uart.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
/////////////////////////////////////1///////////////////////////////////////////
|
||||
/// @defgroup UART_HAL
|
||||
/// @brief UART HAL modules
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UART_Exported_Types
|
||||
/// @{
|
||||
///
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief UART Word Length Enumerate definition
|
||||
/// @anchor UART_Word_Length
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
UART_WordLength_5b = 0U,
|
||||
UART_WordLength_6b = 1U << UART_CCR_CHAR_Pos,
|
||||
UART_WordLength_7b = 2U << UART_CCR_CHAR_Pos,
|
||||
UART_WordLength_8b = 3U << UART_CCR_CHAR_Pos
|
||||
} UART_WordLength_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief UART Stop Bits Enumerate definition
|
||||
/// @anchor UART_Stop_Bits
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
UART_StopBits_1 = 0U,
|
||||
UART_StopBits_2 = UART_CCR_SPB,
|
||||
|
||||
UART_StopBits_0_5 = UART_CCR_SPB1,
|
||||
UART_StopBits_1_5 = UART_CCR_SPB1 | UART_CCR_SPB0,
|
||||
} UART_Stop_Bits_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief UART Parity Enumerate definition
|
||||
/// @anchor UART_Parity
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
UART_Parity_No = 0U,
|
||||
UART_Parity_Even = UART_CCR_PEN | UART_CCR_PSEL,
|
||||
UART_Parity_Odd = UART_CCR_PEN
|
||||
} UART_Parity_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief UART Hardware Flow Control Enumerate definition
|
||||
/// @anchor UART_Hardware_Flow_Control
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
UART_HWFlowControl_None = 0U,
|
||||
|
||||
// UART_HWFlowControl_RTS = UART_GCR_AUTOFLOW,
|
||||
// UART_HWFlowControl_CTS = UART_GCR_AUTOFLOW,
|
||||
|
||||
UART_HWFlowControl_RTS_CTS = UART_GCR_AUTOFLOW
|
||||
} UART_HW_FLOWCONTROL_TypeDef;
|
||||
|
||||
typedef enum {
|
||||
UART_WakeUp_IdleLine = 0U, //
|
||||
UART_WakeUp_AddressMark = UART_CCR_WAKE
|
||||
} UART_WakeUp_TypeDef;
|
||||
|
||||
typedef enum {
|
||||
UART_9bit_Polarity_Low = 0U, //
|
||||
UART_9bit_Polarity_High = UART_CCR_B8POL
|
||||
} UART_9bit_Polarity_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief UART Auto BaudRate definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
Data_F8 = 0,
|
||||
Data_FE,
|
||||
ABRMODE_FALLING_TO_RISINGEDGE1BIT,
|
||||
ABRMODE_FALLING_TO_RISINGEDGE2BIT,
|
||||
ABRMODE_FALLING_TO_RISINGEDGE4BIT,
|
||||
ABRMODE_FALLING_TO_RISINGEDGE8BIT,
|
||||
ABRMODE_FALLING_TO_FALLINGEDGE2BIT,
|
||||
ABRMODE_FALLING_TO_FALLINGEDGE4BIT,
|
||||
ABRMODE_FALLING_TO_FALLINGEDGE8BIT,
|
||||
ABRMODE_STARTBIT,
|
||||
ABRMODE_VALUE0X55,
|
||||
ABRMODE_VALUE0x7F,
|
||||
ABRMODE_VALUE0X80,
|
||||
ABRMODE_VALUE0XF7,
|
||||
ABRMODE_VALUE0XF8 = Data_F8,
|
||||
ABRMODE_VALUE0XFE = Data_FE,
|
||||
ABRMODE_VALUE0XFF,
|
||||
} UART_AutoBaud_TypeDef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief UART Init Structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
union {
|
||||
u32 BaudRate; ///< This member configures the UART communication baud rate.
|
||||
u32 UART_BaudRate;
|
||||
};
|
||||
union {
|
||||
UART_WordLength_TypeDef WordLength; ///< Specifies the number of data bits transmitted or received in a frame.
|
||||
u16 UART_WordLength;
|
||||
};
|
||||
union {
|
||||
UART_Stop_Bits_TypeDef StopBits; ///< Specifies the number of stop bits transmitted.
|
||||
u16 UART_StopBits;
|
||||
};
|
||||
union {
|
||||
UART_Parity_TypeDef Parity; ///< Specifies the parity mode.
|
||||
u16 UART_Parity;
|
||||
};
|
||||
union {
|
||||
u16 Mode; ///< Specifies wether the Receive or Transmit mode is
|
||||
u16 UART_Mode;
|
||||
};
|
||||
union {
|
||||
UART_HW_FLOWCONTROL_TypeDef HWFlowControl; ///< Specifies wether the hardware flow control mode is enabled or disabled.
|
||||
u16 UART_HardwareFlowControl;
|
||||
};
|
||||
} UART_InitTypeDef;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UART_Exported_Constants
|
||||
/// @{
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UART_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_UART_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UART_Exported_Functions
|
||||
/// @{
|
||||
void UART_DeInit(UART_TypeDef* uart);
|
||||
void UART_Init(UART_TypeDef* uart, UART_InitTypeDef* init_struct);
|
||||
void UART_StructInit(UART_InitTypeDef* init_struct);
|
||||
void UART_Cmd(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_ITConfig(UART_TypeDef* uart, u16 it, FunctionalState state);
|
||||
void UART_DMACmd(UART_TypeDef* uart, u16 dma_request, FunctionalState state);
|
||||
void UART_SendData(UART_TypeDef* uart, u16 Data);
|
||||
void UART_ClearITPendingBit(UART_TypeDef* uart, u16 it);
|
||||
|
||||
u16 UART_ReceiveData(UART_TypeDef* uart);
|
||||
FlagStatus UART_GetFlagStatus(UART_TypeDef* uart, u16 flag);
|
||||
|
||||
ITStatus UART_GetITStatus(UART_TypeDef* uart, u16 it);
|
||||
|
||||
void UART_WakeUpConfig(UART_TypeDef* uart, UART_WakeUp_TypeDef mode);
|
||||
void UART_ReceiverWakeUpCmd(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_SetRXAddress(UART_TypeDef* uart, u8 address);
|
||||
void UART_SetRXMASK(UART_TypeDef* uart, u8 address);
|
||||
void UART_Enable9bit(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_Set9bitLevel(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_Set9bitPolarity(UART_TypeDef* uart, UART_9bit_Polarity_TypeDef polarity);
|
||||
void UART_Set9bitAutomaticToggle(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_HalfDuplexCmd(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_SetGuardTime(UART_TypeDef* uart, u8 guard_time);
|
||||
void UART_SmartCardCmd(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_SmartCardNACKCmd(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_SendBreak(UART_TypeDef* uart);
|
||||
void UART_AutoBaudRateCmd(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_AutoBaudRateSet(UART_TypeDef* uart, UART_AutoBaud_TypeDef value, FunctionalState state);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_UART_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,71 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_uid.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UID
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_UID_H
|
||||
#define __HAL_UID_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UID_HAL
|
||||
/// @brief UID HAL modules
|
||||
/// @{
|
||||
|
||||
|
||||
/////////////////////////////////////1///////////////////////////////////////////
|
||||
/// @defgroup UID_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_UID_C_
|
||||
#define GLOBAL
|
||||
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
|
||||
|
||||
#endif
|
||||
GLOBAL u8 device_id_data[12];
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UID_Exported_Functions
|
||||
/// @{
|
||||
void GetChipUID(void);
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_UID_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
@@ -0,0 +1,89 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_ver.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UART
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_VER_H
|
||||
#define __HAL_VER_H
|
||||
|
||||
// Files includes
|
||||
#include "reg_common.h"
|
||||
#include "reg_dbg.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
/////////////////////////////////////1///////////////////////////////////////////
|
||||
/// @defgroup UART_HAL
|
||||
/// @brief UART HAL modules
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UART_Exported_Types
|
||||
/// @{
|
||||
///
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief UART Word Length Enumerate definition
|
||||
/// @anchor UART_Word_Length
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UART_Exported_Constants
|
||||
/// @{
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UART_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_VER_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UART_Exported_Functions
|
||||
/// @{
|
||||
|
||||
u32 Get_MM32LibVersion(void);
|
||||
u32 Get_ChipsetREVID(void);
|
||||
u32 Get_ChipsetDEVID(void);
|
||||
u32 Get_ChipsetUIDw0(void);
|
||||
u32 Get_ChipsetUIDw1(void);
|
||||
u32 Get_ChipsetUIDw2(void);
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_VER_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,90 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_wwdg.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE WWDG
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT O
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDER
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_WWDG_H
|
||||
#define __HAL_WWDG_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_wwdg.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup WWDG_HAL
|
||||
/// @brief WWDG HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup WWDG_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief WWDG_Prescaler
|
||||
/// @anchor WWDG_Prescaler
|
||||
|
||||
typedef enum {
|
||||
WWDG_Prescaler_1 = WWDG_CFGR_WDGTB_1,
|
||||
WWDG_Prescaler_2 = WWDG_CFGR_WDGTB_2,
|
||||
WWDG_Prescaler_4 = WWDG_CFGR_WDGTB_4,
|
||||
WWDG_Prescaler_8 = WWDG_CFGR_WDGTB_8
|
||||
} WWDG_Prescaler_Typedef;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup WWDG_Exported_Variables
|
||||
/// @{
|
||||
|
||||
#ifdef _HAL_WWDG_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup WWDG_Exported_Functions
|
||||
/// @{
|
||||
|
||||
void WWDG_DeInit(void);
|
||||
void WWDG_SetPrescaler(u32 prescaler);
|
||||
void WWDG_SetWindowValue(u8 window_value);
|
||||
void WWDG_EnableIT(void);
|
||||
void WWDG_SetCounter(u8 count);
|
||||
u32 WWDG_GetCounter(void);
|
||||
void WWDG_Enable(u8 count);
|
||||
FlagStatus WWDG_GetFlagStatus(void);
|
||||
void WWDG_ClearFlag(void);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_WWDG_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,563 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_adc.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE ADC FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_ADC_C_
|
||||
|
||||
// Files includes
|
||||
#include "hal_adc.h"
|
||||
#include "hal_rcc.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup ADC_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup ADC_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Deinitializes the adc peripheral registers to their default
|
||||
/// reset values.
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_DeInit(ADC_TypeDef* adc)
|
||||
{
|
||||
|
||||
switch (*(vu32*)&adc) {
|
||||
|
||||
case ADC1_BASE:
|
||||
exRCC_APB2PeriphReset(RCC_APB2ENR_ADC1);
|
||||
break;
|
||||
case ADC2_BASE:
|
||||
exRCC_APB2PeriphReset(RCC_APB2ENR_ADC2);
|
||||
break;
|
||||
case ADC3_BASE:
|
||||
exRCC_APB2PeriphReset(RCC_APB2ENR_ADC3);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Initializes the adc peripheral according to the specified parameters
|
||||
/// in the init_struct, Please use this function if you want to be
|
||||
/// compatible with older versions of the library.
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @param init_struct: pointer to an ADC_InitTypeDef structure that contains
|
||||
/// the configuration information for the specified ADC peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_Init(ADC_TypeDef* adc, ADC_InitTypeDef* init_struct)
|
||||
{
|
||||
adc->ADCFG &= ~(ADC_CFGR_PRE | ADC_CFGR_RSLTCTL);
|
||||
adc->ADCFG |= (u32)(init_struct->ADC_PRESCARE) | init_struct->ADC_Resolution;
|
||||
|
||||
adc->ADCR &= ~(ADC_CR_ALIGN | ADC_CR_MODE | ADC_CR_TRGSEL);
|
||||
adc->ADCR |= ((u32)init_struct->ADC_DataAlign) | init_struct->ADC_ExternalTrigConv | ((u32)init_struct->ADC_Mode);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Fills each init_struct member with its default value.
|
||||
/// @param init_struct : pointer to an ADC_InitTypeDef structure which will be
|
||||
/// initialized.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_StructInit(ADC_InitTypeDef* init_struct)
|
||||
{
|
||||
init_struct->ADC_Resolution = ADC_Resolution_12b;
|
||||
init_struct->ADC_PRESCARE = ADC_PCLK2_PRESCARE_2;
|
||||
init_struct->ADC_Mode = ADC_CR_IMM; //ADC_Mode_Single;
|
||||
init_struct->ADC_ContinuousConvMode = DISABLE; // useless
|
||||
init_struct->ADC_ExternalTrigConv = ADC1_ExternalTrigConv_T1_CC1;
|
||||
init_struct->ADC_DataAlign = ADC_DataAlign_Right;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified ADC peripheral.
|
||||
/// @param adc:select the ADC peripheral.
|
||||
/// @param state: new state of the adc peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_Cmd(ADC_TypeDef* adc, FunctionalState state)
|
||||
{
|
||||
(state) ? (adc->ADCFG |= ADC_CFGR_ADEN) : (adc->ADCFG &= ~ADC_CFGR_ADEN);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified ADC DMA request.
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @param state: New state of the selected ADC DMA transfer.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_DMACmd(ADC_TypeDef* adc, FunctionalState state)
|
||||
{
|
||||
(state) ? (adc->ADCR |= ADC_CR_DMAEN) : (adc->ADCR &= ~ADC_CR_DMAEN);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified ADC interrupts.
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @param adc_interrupt: specifies the ADC interrupt sources to be enabled or disabled.
|
||||
/// @param state: New state of the specified ADC interrupts.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_ITConfig(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt, FunctionalState state)
|
||||
{
|
||||
if (adc_interrupt == ADC_IT_EOC)
|
||||
(state) ? (adc->ADCR |= ADC_CR_ADIE) : (adc->ADCR &= ~ADC_CR_ADIE);
|
||||
else
|
||||
(state) ? (adc->ADCR |= ADC_CR_ADWIE) : (adc->ADCR &= ~ADC_CR_ADWIE);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the selected ADC software start conversion .
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @param state: New state of the selected ADC software start conversion.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_SoftwareStartConvCmd(ADC_TypeDef* adc, FunctionalState state)
|
||||
{
|
||||
(state) ? (adc->ADCR |= ADC_CR_ADST) : (adc->ADCR &= ~ADC_CR_ADST);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Gets the selected ADC Software start conversion Status.
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @retval The new state of ADC software start conversion (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* adc)
|
||||
{
|
||||
return (((adc->ADCR & ADC_CR_ADST) != (u32)RESET) ? SET : RESET);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enable the selected ADC channel and configure its sample time. Please
|
||||
/// use this function if you want to be compatible with older versions
|
||||
/// of the library.
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @param channel: the ADC channel to configure.
|
||||
/// @param sample_time: the ADC Channel n Sample time to configure.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_RegularChannelConfig(ADC_TypeDef* adc, u32 channel, u8 rank, u32 sample_time) //ADCSAM_TypeDef
|
||||
{
|
||||
|
||||
u32 tempchan;
|
||||
sample_time = sample_time & 0xF;
|
||||
tempchan = channel;
|
||||
if(tempchan > 8) {
|
||||
tempchan = tempchan & 0xF;
|
||||
tempchan = tempchan - 8;
|
||||
adc->SMPR2 &= ~(0xF << tempchan);
|
||||
adc->SMPR2 |= (sample_time << tempchan);
|
||||
}
|
||||
else {
|
||||
adc->SMPR1 &= ~(0xF << tempchan);
|
||||
adc->SMPR1 |= (sample_time << tempchan);
|
||||
}
|
||||
adc->ADCHS &= ~(1 << channel);
|
||||
adc->ADCHS |= (1 << channel);
|
||||
|
||||
if (channel & ADC_CHSR_CHT)
|
||||
ADC_TempSensorVrefintCmd(ENABLE);
|
||||
else if (channel & ADC_CHSR_CHV)
|
||||
ADC_TempSensorVrefintCmd(ENABLE);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the adc conversion through external trigger.
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @param state: New state of the selected ADC external trigger.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_ExternalTrigConvCmd(ADC_TypeDef* adc, FunctionalState state)
|
||||
{
|
||||
(state) ? (adc->ADCR |= ADC_CR_TRGEN) : (adc->ADCR &= ~ADC_CR_TRGEN);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the adc external trigger for injected channels conversion.
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @param adc_external_trig_source: Configuring the external trigger source
|
||||
/// for the ADC.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_ExternalTrigConvConfig(ADC_TypeDef* adc, EXTERTRIG_TypeDef adc_external_trig_source)
|
||||
{
|
||||
adc->ADCR &= ~ADC_CR_TRGSEL;
|
||||
adc->ADCR |= adc_external_trig_source;
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the last adc conversion result data for regular channel.
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @retval The data conversion value.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u16 ADC_GetConversionValue(ADC_TypeDef* adc)
|
||||
{
|
||||
return (u16)adc->ADDATA;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the last ADC conversion result data in dual mode.
|
||||
/// @param None
|
||||
/// @retval The Data conversion value.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 ADC_GetDualModeConversionValue()
|
||||
{
|
||||
return (*(vu32*)ADC1_BASE);
|
||||
}
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the analog watchdog.
|
||||
/// @param adc: to select the ADC peripheral.
|
||||
/// @param state: New state of the selected ADC analog watchdog.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_AnalogWatchdogCmd(ADC_TypeDef* adc, FunctionalState state)
|
||||
{
|
||||
(state) ? (adc->ADCFG |= ADC_CFGR_ADWEN) : (adc->ADCFG &= ~ADC_CFGR_ADWEN);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the high and low thresholds of the analog watchdog.
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @param high_threshold: the ADC analog watchdog High threshold value.
|
||||
/// This parameter must be a 12bit value.
|
||||
/// @param low_threshold: the ADC analog watchdog Low threshold value.
|
||||
/// This parameter must be a 12bit value.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* adc, u16 high_threshold, u16 low_threshold)
|
||||
{
|
||||
u32 tempThreshold;
|
||||
tempThreshold = high_threshold;
|
||||
adc->ADCMPR = (tempThreshold << 16) | low_threshold;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the analog watchdog guarded single channel
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @param channel: the ADC channel to configure for the analog watchdog.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel)
|
||||
{
|
||||
adc->ADCR &= ~ADC_CR_CMPCH;
|
||||
adc->ADCR |= (channel << ADC_CR_CMPCH_Pos);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the temperature sensor and Vrefint channel.
|
||||
/// @param state: New state of the temperature sensor.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_TempSensorVrefintCmd(FunctionalState state)
|
||||
{
|
||||
(state) ? (ADC1->ADCFG |= (ADC_CFGR_TEN | ADC_CFGR_VEN))
|
||||
: (ADC1->ADCFG &= ~(ADC_CFGR_TEN | ADC_CFGR_VEN));
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the temperature sensor .
|
||||
/// @param state: New state of the temperature sensor.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_TempSensorCmd(FunctionalState state)
|
||||
{
|
||||
ADC_TempSensorVrefintCmd(state);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the Vrefint channel.
|
||||
/// @param state: New state of the Vrefint channel.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_VrefintCmd(FunctionalState state)
|
||||
{
|
||||
ADC_TempSensorVrefintCmd(state);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the temperature sensor and Vrefint channel.
|
||||
/// @param chs: temperature sensor bit & Vrefint bit.
|
||||
/// @param state: New state of the temperature sensor.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exADC_TempSensorVrefintCmd(u32 chs, FunctionalState state)
|
||||
{
|
||||
if (chs & ADC_CHSR_CHT) {
|
||||
(state) ? (ADC1->ADCFG |= ADC_CFGR_TEN)
|
||||
: (ADC1->ADCFG &= ~ADC_CFGR_TEN);
|
||||
}
|
||||
else if (chs & ADC_CHSR_CHV) {
|
||||
(state) ? (ADC1->ADCFG |= ADC_CFGR_VEN)
|
||||
: (ADC1->ADCFG &= ~ADC_CFGR_VEN);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified ADC flag is set or not.
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @param adc_flag: specifies the flag to check.
|
||||
/// @retval The New state of adc_flag (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag)
|
||||
{
|
||||
return (adc_flag == ADC_IT_EOC) ? ((adc->ADSTA & ADC_SR_ADIF) ? SET : RESET) : ((adc->ADSTA & ADC_SR_ADWIF) ? SET : RESET);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the adc's pending flags.
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @param adc_flag: specifies the flag to clear.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_ClearFlag(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag)
|
||||
{
|
||||
(adc_flag == ADC_IT_EOC) ? (adc->ADSTA |= ADC_SR_ADIF) : (adc->ADSTA |= ADC_SR_ADWIF);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified adc's interrupt has occurred or not.
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @param adc_interrupt: specifies the ADC interrupt source to check.
|
||||
/// @retval The new state of adc_interrupt (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt)
|
||||
{
|
||||
return (adc_interrupt == ADC_IT_EOC) ? ((adc->ADSTA & ADC_SR_ADIF) ? SET : RESET) : ((adc->ADSTA & ADC_SR_ADWIF) ? SET : RESET);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the adc's interrupt pending bits.
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @param adc_interrupt: specifies the ADC interrupt pending bit to clear.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_ClearITPendingBit(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt)
|
||||
{
|
||||
(adc_interrupt == ADC_IT_EOC) ? (adc->ADSTA |= ADC_SR_ADIF) : (adc->ADSTA |= ADC_SR_ADWIF);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the adc any channels conversion rank and channel.
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @param rank: rank can be 0x0~0xf for the convert sequence.
|
||||
/// @param adc_channel: Configuring the target channel to be converted.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_ANY_CH_Config(ADC_TypeDef* adc, u8 rank, ADCCHANNEL_TypeDef adc_channel)
|
||||
{
|
||||
rank = rank & 0xF;
|
||||
if(rank < 8) {
|
||||
adc->CHANY0 &= ~(0x0F << (4 * rank));
|
||||
adc->CHANY0 |= (adc_channel << (4 * rank));
|
||||
}
|
||||
else {
|
||||
adc->CHANY1 &= ~(0x0F << (4 * (rank - 8)));
|
||||
adc->CHANY1 |= (adc_channel << (4 * (rank - 8)));
|
||||
}
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the adc any channels conversion Max rank number
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @param num: Configuring the max rank number for the ADC.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_ANY_NUM_Config(ADC_TypeDef* adc, u8 num)
|
||||
{
|
||||
if(num > 15) num = 15; //15 ? 16 need to be confirmed
|
||||
adc->ANYCFG = num;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the ANY channel converter.
|
||||
/// @param state: enable or disable the ANY channel converter mode.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_ANY_Cmd(ADC_TypeDef* adc, FunctionalState state)
|
||||
{
|
||||
(state) ? (adc->ANYCR |= ADC1_CHANY_CR_MDEN) : (adc->ANYCR &= ~ADC1_CHANY_CR_MDEN);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the selected ADC automatic injected group
|
||||
/// conversion after regular one.
|
||||
/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral.
|
||||
/// @param state: new state of the selected ADC auto injected conversion
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_AutoInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
|
||||
{
|
||||
(state) ? (adc->ANYCR |= ADC_ANY_CR_JAUTO) : (adc->ANYCR &= ~ADC_ANY_CR_JAUTO);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the adc external trigger for injected channels conversion.
|
||||
/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral.
|
||||
/// @param ADC_ExtInjTrigSource: specifies the ADC trigger to start injected conversion.
|
||||
|
||||
/// @retval None
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_ExternalTrigInjectedConvertConfig(ADC_TypeDef* adc, EXTER_INJ_TRIG_TypeDef ADC_ExtInjTrigSource)
|
||||
{
|
||||
u32 tmpreg = 0;
|
||||
// Get the old register value
|
||||
tmpreg = adc->ANYCR;
|
||||
// Clear the old external event selection for injected group
|
||||
tmpreg &= ADC_ANY_CR_JTRGSEL;
|
||||
// Set the external event selection for injected group
|
||||
tmpreg |= ADC_ExtInjTrigSource;
|
||||
// Store the new register value
|
||||
adc->ANYCR = tmpreg;
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the adc injected channels conversion through
|
||||
/// external trigger
|
||||
/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral.
|
||||
/// @param state: new state of the selected ADC external trigger start of
|
||||
/// injected conversion.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
|
||||
{
|
||||
(state) ? (adc->ANYCR |= ADC_ANY_CR_JTRGEN) : (adc->ANYCR &= ~ADC_ANY_CR_JTRGEN);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the selected ADC start of the injected
|
||||
/// channels conversion.
|
||||
/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral.
|
||||
/// @param state: new state of the selected ADC software start injected conversion.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_InjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
|
||||
{
|
||||
(state) ? (adc->ANYCR |= ADC_ANY_CR_JCEN) : (adc->ANYCR &= ~ADC_ANY_CR_JCEN);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the selected ADC start of the injected
|
||||
/// channels conversion.
|
||||
/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral.
|
||||
/// @param NewState: new state of the selected ADC software start injected conversion.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
|
||||
{
|
||||
(state) ? (adc->ANYCR |= ADC_ANY_CR_JADST) : (adc->ANYCR &= ~ADC_ANY_CR_JADST);
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enable the selected ADC channel and configure its sample time. Please
|
||||
/// use this function if you want to be compatible with older versions
|
||||
/// of the library.
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @param event: the ADC external event to configure.
|
||||
/// @param sample_time: the ADC Channel n Sample time to configure.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_InjectedSequencerConfig(ADC_TypeDef* adc, u32 event, u32 sample_time)
|
||||
{
|
||||
adc->ANYCR &= ~(ADC_ANY_CR_JCEN | ADC_ANY_CR_CHANY_MDEN | ADC_ANY_CR_JTRGSEL_EXTI12 \
|
||||
| ADC_ANY_CR_JTRGSHIFT_512 | ADC_ANY_CR_JTRGEN);
|
||||
adc->ANYCR |= (ADC_ANY_CR_JCEN | ADC_ANY_CR_CHANY_MDEN | sample_time | event | ADC_ANY_CR_JTRGEN);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Injection channel length configuration.
|
||||
/// @param adc: select the ADC peripheral.
|
||||
/// @param Length: Injection channel length.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_LEN_TypeDef Length)
|
||||
{
|
||||
adc->JSQR &= ~(0x03 << ADC_JSQR_JL_Pos);
|
||||
adc->JSQR |= Length << ADC_JSQR_JL_Pos;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Injection channel configuration.
|
||||
/// @param adc : select the ADC peripheral.
|
||||
/// @param off_addr : Injection channel offset address.
|
||||
/// @param channel: The sampling channel.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_InjectedSequencerChannelConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, ADCCHANNEL_TypeDef channel)
|
||||
{
|
||||
adc->JSQR &= ~(0x1F << (off_addr >> 2) * 5);
|
||||
adc->JSQR |= (channel << (off_addr >> 2) * 5);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Injection channel converted value.
|
||||
/// @param adc : select the ADC peripheral.
|
||||
/// @param off_addr : Injection channel offset address.
|
||||
/// @retval value.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u16 ADC_GetInjectedConversionValue(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr)
|
||||
{
|
||||
u32 value;
|
||||
value = (*(vu32*)(*(vu32*)&adc + 0xB0 + off_addr)) - (*(vu32*)(*(vu32*)&adc + 0x7C + off_addr));
|
||||
|
||||
return (u16)value;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Injection current converted value.
|
||||
/// @param adc : select the ADC peripheral.
|
||||
/// @retval value. Returns the last adc conversion result data for injected channel.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u16 ADC_GetInjectedCurrentConvertedValue(ADC_TypeDef* adc)
|
||||
{
|
||||
return (u16)adc->JDATA;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Injection channel compensation configuration.
|
||||
/// @param adc : select the ADC peripheral.
|
||||
/// @param off_addr : Injection channel.
|
||||
/// @param value : compensation value.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ADC_SetInjectedOffset(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, u16 value)
|
||||
{
|
||||
*(vu32*)(*(vu32*)&adc + 0x7C + off_addr) = value;
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Get channel convertion result.
|
||||
/// @param adc : select the ADC peripheral.
|
||||
/// @param channel : Converted channel.
|
||||
/// @retval The Data conversion value.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u16 ADC_GetChannelConvertedValue(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel)
|
||||
{
|
||||
return (u16)(*(vu32*) ((u32)adc + 0x18 + ((u32)channel << 2)));
|
||||
}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
@@ -0,0 +1,231 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_bkp.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE BKP FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_BKP_C_
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "hal_pwr.h"
|
||||
#include "hal_rcc.h"
|
||||
#include "hal_bkp.h"
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup BKP_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup BKP_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Deinitializes the BKP peripheral registers to their default reset
|
||||
/// values.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void BKP_DeInit(void)
|
||||
{
|
||||
RCC_BackupResetCmd(ENABLE);
|
||||
RCC_BackupResetCmd(DISABLE);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the Tamper Pin active level.
|
||||
/// @param tamper_pin_level: specifies the Tamper Pin active level.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg BKP_TamperPinLevel_High: Tamper pin active on high level
|
||||
/// @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void BKP_TamperPinLevelConfig(BKPTPAL_Typedef tamper_pin_level)
|
||||
{
|
||||
BKP->CR = tamper_pin_level;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the Tamper Pin activation.
|
||||
/// @param state: new state of the Tamper Pin activation.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void BKP_TamperPinCmd(FunctionalState state)
|
||||
{
|
||||
(state) ? SET_BIT(BKP->CR, BKP_CR_TPE) : CLEAR_BIT(BKP->CR, BKP_CR_TPE);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the Tamper Pin Interrupt.
|
||||
/// @param state: new state of the Tamper Pin Interrupt.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void BKP_ITConfig(FunctionalState state)
|
||||
{
|
||||
(state) ? SET_BIT(BKP->CSR, BKP_CSR_TPIE) : CLEAR_BIT(BKP->CSR, BKP_CSR_TPIE);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Select the RTC output source to output on the Tamper pin.
|
||||
/// @param rtc_output_source: specifies the RTC output source.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
|
||||
/// @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
|
||||
/// divided by 64 on the Tamper pin.
|
||||
/// @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
|
||||
/// the Tamper pin.
|
||||
/// @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
|
||||
/// the Tamper pin.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void BKP_RTCOutputConfig(BKPRTCOUTPUTSRC_Typedef rtc_output_source)
|
||||
{
|
||||
MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS, rtc_output_source);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Sets RTC Clock Calibration value.
|
||||
/// @param calibration_value: specifies the RTC Clock Calibration value.
|
||||
/// This parameter must be a number between 0 and 0x7F.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void BKP_SetRTCCalibrationValue(u8 calibration_value)
|
||||
{
|
||||
MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CAL, calibration_value);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the Tamper Pin Event flag is set or not.
|
||||
/// @param None.
|
||||
/// @retval State: The new state of the Tamper Pin Event flag (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus BKP_GetFlagStatus(void)
|
||||
{
|
||||
return ((BKP->CSR & BKP_CSR_TEF) ? SET : RESET);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears Tamper Pin Event pending flag.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void BKP_ClearFlag(void)
|
||||
{
|
||||
SET_BIT(BKP->CSR, BKP_CSR_CTE);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the Tamper Pin Interrupt has occurred or not.
|
||||
/// @param None.
|
||||
/// @retval State: The new state of the Tamper Pin Interrupt (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
ITStatus BKP_GetITStatus(void)
|
||||
{
|
||||
return ((BKP->CSR & BKP_CSR_TIF) ? SET : RESET);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears Tamper Pin Interrupt pending bit.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void BKP_ClearITPendingBit(void)
|
||||
{
|
||||
SET_BIT(BKP->CSR, BKP_CSR_CTI);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Writes user data to the specified data Backup Register.
|
||||
/// @param bkp_dr: specifies the data Backup Register.
|
||||
/// This parameter can be BKP_DRx where x:[1, 10]
|
||||
/// @param data: data to write
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void BKP_WriteBackupRegister(BKPDR_Typedef bkp_dr, u16 data)
|
||||
{
|
||||
*(vu16*)(BKP_BASE + bkp_dr) = data;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Reads data from the specified data Backup Register.
|
||||
/// @param bkp_dr: specifies the data Backup Register.
|
||||
/// This parameter can be BKP_DRx where x:[1, 10]
|
||||
/// @retval data: The content of the specified data Backup Register
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u16 BKP_ReadBackupRegister(BKPDR_Typedef bkp_dr)
|
||||
{
|
||||
return (*(vu16*)(BKP_BASE + bkp_dr));
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Extended function interface
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Initializes the BKP peripheral, enable access to the backup
|
||||
/// registers.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exBKP_Init(void)
|
||||
{
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1ENR_PWR, ENABLE);
|
||||
//COMMON_EnableIpClock(emCLOCK_PWR);
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1ENR_BKP, ENABLE);
|
||||
//COMMON_EnableIpClock(emCLOCK_BKP);
|
||||
|
||||
RCC->BDCR |= RCC_BDCR_DBP;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Writes user data to the specified data Backup Register immediately.
|
||||
/// @param bkp_dr: specifies the data Backup Register.
|
||||
/// This parameter can be BKP_DRx where x:[1, 10]
|
||||
/// @param data: data to write
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exBKP_ImmWrite(BKPDR_Typedef bkp_dr, u16 dat)
|
||||
{
|
||||
RCC->BDCR |= RCC_BDCR_DBP;
|
||||
*(vu16*)(BKP_BASE + bkp_dr) = dat;
|
||||
RCC->BDCR &= ~RCC_BDCR_DBP;
|
||||
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Reads data from the specified data Backup Register immediately.
|
||||
/// @param bkp_dr: specifies the data Backup Register.
|
||||
/// This parameter can be BKP_DRx where x:[1, 10]
|
||||
/// @retval data: The content of the specified data Backup Register
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u16 exBKP_ImmRead(BKPDR_Typedef bkp_dr)
|
||||
{
|
||||
u16 dat;
|
||||
RCC->BDCR |= RCC_BDCR_DBP;
|
||||
dat = (*(vu16*)(BKP_BASE + bkp_dr));
|
||||
RCC->BDCR &= ~RCC_BDCR_DBP;
|
||||
return dat;
|
||||
}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
@@ -0,0 +1,696 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_can.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE CAN FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define __HAL_CAN_C
|
||||
|
||||
// Files includes
|
||||
#include "hal_can.h"
|
||||
#include "hal_rcc.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup CAN_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup CAN_Exported_Functions
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Deinitializes the CAN peripheral registers to their default reset
|
||||
/// values.
|
||||
/// @param can: select the CAN peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_DeInit(CAN_TypeDef* can)
|
||||
{
|
||||
exRCC_APB1PeriphReset(RCC_APB1ENR_CAN);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Initializes the CAN peripheral according to the specified
|
||||
/// parameters in the CAN_InitStruct.
|
||||
/// @param can: select the CAN peripheral.
|
||||
/// @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
|
||||
/// contains the configuration information for the CAN peripheral.
|
||||
/// @retval Constant indicates initialization succeed which will be
|
||||
/// CANINITFAILED or CANINITOK.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u8 CAN_Init(CAN_TypeDef* can, CAN_Basic_InitTypeDef* init_struct)
|
||||
{
|
||||
u8 InitStatus = CANINITFAILED;
|
||||
|
||||
can->BTR0 = ((u32)(init_struct->SJW) << 6) | ((u32)(init_struct->BRP));
|
||||
can->BTR1 = ((u32)(init_struct->SAM) << 7) | ((u32)(init_struct->TESG2) << 4) | ((u32)(init_struct->TESG1));
|
||||
|
||||
if (init_struct->GTS == ENABLE) {
|
||||
can->CMR |= (u32)CAN_SleepMode;
|
||||
InitStatus = CANINITFAILED;
|
||||
}
|
||||
else {
|
||||
can->CMR &= ~(u32)CAN_SleepMode;
|
||||
InitStatus = CANINITOK;
|
||||
}
|
||||
|
||||
(init_struct->GTS == ENABLE) ? (can->CMR |= (u32)CAN_SleepMode) : (can->CMR &= ~(u32)CAN_SleepMode);
|
||||
|
||||
can->CDR |=
|
||||
((init_struct->CBP) << 6) | ((init_struct->RXINTEN) << 5) | ((init_struct->CLOSE_OPEN_CLK) << 3) | (init_struct->CDCLK);
|
||||
|
||||
return InitStatus;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the CAN_Basic reception filter according to the specified
|
||||
/// parameters in the basic_filter_init_struct.
|
||||
/// @param basic_filter_init_struct: pointer to a CAN_Basic_FilterInitTypeDef
|
||||
/// structure that contains the configuration information.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* basic_filter_init_struct)
|
||||
{
|
||||
// Filter Mode
|
||||
CAN1->ACR = basic_filter_init_struct->CAN_FilterId;
|
||||
CAN1->AMR = basic_filter_init_struct->CAN_FilterMaskId;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Fills each init_struct member with its default value.
|
||||
/// @param init_struct : pointer to a CAN_Basic_InitTypeDef structure which will be initialized.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_StructInit(CAN_Basic_InitTypeDef* init_struct)
|
||||
{
|
||||
// Reset CAN_Basic init structure parameters values
|
||||
|
||||
// initialize the BRP member(where can be set with (0..63))
|
||||
init_struct->BRP = 0x0;
|
||||
// initialize the SJW member(where can be set with (0..3))
|
||||
init_struct->SJW = 0x0;
|
||||
// Initialize the TESG1 member(where can be set with (0..15))
|
||||
init_struct->TESG1 = 0x0;
|
||||
// Initialize the TESG2 member(where can be set with(0..7))
|
||||
init_struct->TESG2 = 0x0;
|
||||
// Initialize the SAM member(where can be set (SET or RESET))
|
||||
init_struct->SAM = RESET;
|
||||
// Initialize the GTS member to Sleep Mode(where can be set (ENABLE or
|
||||
// DISABLE))
|
||||
init_struct->GTS = DISABLE;
|
||||
// Initialize the external pin CLKOUT frequence
|
||||
init_struct->CDCLK = 0x0;
|
||||
// Initialize the external clk is open or close
|
||||
init_struct->CLOSE_OPEN_CLK = 0x0;
|
||||
// Initialize the TX1 pin work as rx interrupt output
|
||||
init_struct->RXINTEN = 0x0;
|
||||
// Initialize the CBP of CDR register
|
||||
init_struct->CBP = 0x0;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified CAN interrupts.
|
||||
/// @param can: select the CAN peripheral.
|
||||
/// @param it: specifies the CAN interrupt sources to be enabled or
|
||||
/// disabled.
|
||||
/// This parameter can be: CAN_IT_OIE, CAN_IT_EIE, CAN_IT_TIE,
|
||||
/// CAN_IT_RIE.
|
||||
/// @param state: new state of the CAN interrupts.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_ITConfig(CAN_TypeDef* can, u32 it, FunctionalState state)
|
||||
{
|
||||
(state) ? (can->CR |= it) : (can->CR &= ~it);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Initiates and transmits a CAN frame message.
|
||||
/// @param can:select the CAN peripheral.
|
||||
/// @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and
|
||||
/// CAN data.
|
||||
/// @retval CANTXOK if the CAN driver transmits the message
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u8 CAN_Transmit(CAN_TypeDef* can, CanBasicTxMsg* basic_transmit_message)
|
||||
{
|
||||
can->TXID0 = (basic_transmit_message->IDH);
|
||||
can->TXID1 = (basic_transmit_message->IDL << 5) | (basic_transmit_message->RTR << 4) | (basic_transmit_message->DLC);
|
||||
if ((FunctionalState)(basic_transmit_message->RTR) != ENABLE) {
|
||||
can->TXDR0 = basic_transmit_message->Data[0];
|
||||
can->TXDR1 = basic_transmit_message->Data[1];
|
||||
can->TXDR2 = basic_transmit_message->Data[2];
|
||||
can->TXDR3 = basic_transmit_message->Data[3];
|
||||
can->TXDR4 = basic_transmit_message->Data[4];
|
||||
can->TXDR5 = basic_transmit_message->Data[5];
|
||||
can->TXDR6 = basic_transmit_message->Data[6];
|
||||
can->TXDR7 = basic_transmit_message->Data[7];
|
||||
}
|
||||
|
||||
can->CMR = CAN_CMR_TR;
|
||||
|
||||
return (can->SR & 0x01);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Cancels a transmit request.
|
||||
/// @param can: select the CAN peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_CancelTransmit(CAN_TypeDef* can)
|
||||
{
|
||||
// abort transmission
|
||||
can->CMR = CAN_AT;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Releases the specified receive FIFO.
|
||||
/// @param can: select the CAN peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_FIFORelease(CAN_TypeDef* can)
|
||||
{
|
||||
// Release FIFO
|
||||
can->CMR |= (u32)CAN_RRB;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Receives a correct CAN frame.
|
||||
/// @param can: select the CAN peripheral.
|
||||
/// @param RxMessage: pointer to a structure receive frame which contains CAN
|
||||
/// Id,CAN DLC, CAN data and FMI number.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_Receive(CAN_TypeDef* can, CanBasicRxMsg* basic_receive_message)
|
||||
{
|
||||
u16 tempid;
|
||||
|
||||
basic_receive_message->RTR = (u8)((can->RXID1) >> 4) & 0x1;
|
||||
basic_receive_message->DLC = (u8)((can->RXID1) & 0xf);
|
||||
tempid = (u16)(((can->RXID1) & 0xe0) >> 5);
|
||||
tempid |= (u16)(can->RXID0 << 3);
|
||||
basic_receive_message->ID = tempid;
|
||||
basic_receive_message->Data[0] = CAN1->RXDR0;
|
||||
basic_receive_message->Data[1] = CAN1->RXDR1;
|
||||
basic_receive_message->Data[2] = CAN1->RXDR2;
|
||||
basic_receive_message->Data[3] = CAN1->RXDR3;
|
||||
basic_receive_message->Data[4] = CAN1->RXDR4;
|
||||
basic_receive_message->Data[5] = CAN1->RXDR5;
|
||||
basic_receive_message->Data[6] = CAN1->RXDR6;
|
||||
basic_receive_message->Data[7] = CAN1->RXDR7;
|
||||
CAN_FIFORelease(can);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Select the Sleep mode or not in Basic workmode
|
||||
/// @param state to go into the Sleep mode or go out
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u8 CAN_Sleep(CAN_TypeDef* can)
|
||||
{
|
||||
can->CMR |= CAN_SleepMode;
|
||||
// At this step, sleep mode status
|
||||
return (u8)((can->CMR & 0x10) == CAN_SleepMode) ? CANSLEEPOK : CANSLEEPFAILED;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Wakes the CAN up.
|
||||
/// @param can: where x can be 1 to select the CAN peripheral.
|
||||
/// @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u8 CAN_WakeUp(CAN_TypeDef* can)
|
||||
{
|
||||
// Wake up request
|
||||
can->CMR &= ~CAN_SleepMode;
|
||||
return (u8)((can->CMR & 0x01) == 0) ? CANWAKEUPOK : CANWAKEUPFAILED;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified CAN flag is set or not.
|
||||
/// @param can: select the CAN peripheral.
|
||||
/// @param flag: specifies the flag to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg CAN_STATUS_RBS: Receive buffer status
|
||||
/// @arg CAN_STATUS_DOS: Data overflow status
|
||||
/// @arg CAN_STATUS_TBS: Transmit buffer status
|
||||
/// @arg CAN_STATUS_TCS: Transmit complete status
|
||||
/// @arg CAN_STATUS_RS: Receiving status
|
||||
/// @arg CAN_STATUS_TS: Transmiting status
|
||||
/// @arg CAN_STATUS_ES: Error status
|
||||
/// @arg CAN_STATUS_BS: bus status, close or open
|
||||
/// @retval The new state of CAN_FLAG (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* can, u32 flag)
|
||||
{
|
||||
return (FlagStatus)(((can->SR & flag) == flag) ? SET : RESET);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified CAN interrupt has occurred or not.
|
||||
/// @param can: where x can be 1 to select the CAN peripheral.
|
||||
/// @param it: specifies the CAN interrupt source to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg CAN_IT_RI: Receive FIFO not empty Interrupt
|
||||
/// @arg CAN_IT_TI: Transmit Interrupt
|
||||
/// @arg CAN_IT_EI: ERROR Interrupt
|
||||
/// @arg CAN_IT_DOI: Data voerflow Interrupt
|
||||
/// @arg CAN_IT_WUI: Wakeup Interrupt
|
||||
/// @arg CAN_IT_ALL: use it can enble all Interrupt
|
||||
/// @retval The current state of it (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
ITStatus CAN_GetITStatus(CAN_TypeDef* can, u32 it)
|
||||
{
|
||||
return (ITStatus)((can->IR & it) != it) ? RESET : SET;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Select the can work as peli mode or basic mode
|
||||
/// @param can: where x can be 1 or 2 to to select the CAN peripheral.
|
||||
/// @param CAN_MODE: specifies the work mode:CAN_BASICMode,CAN_PELIMode
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_Mode_Cmd(CAN_TypeDef* can, u32 mode)
|
||||
{
|
||||
can->CDR |= mode;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Select the Reset mode or not
|
||||
/// @param can: where x can be 1 or 2 to to select the CAN peripheral.
|
||||
/// @param state to go into the Reset mode or go out
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_ResetMode_Cmd(CAN_TypeDef* can, FunctionalState state)
|
||||
{
|
||||
(state == ENABLE) ? (can->CR |= CAN_ResetMode) : (can->CR &= ~CAN_ResetMode);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clear the data overflow.
|
||||
/// @param can: where x can be 1 or 2 to to select the CAN peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_ClearDataOverflow(CAN_TypeDef* can)
|
||||
{
|
||||
can->CMR |= (u32)CAN_CDO;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the CAN's IT pending.
|
||||
/// @param can: where x can be 1 or 2 to to select the CAN peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_ClearITPendingBit(CAN_TypeDef* can)
|
||||
{
|
||||
u32 temp = 0;
|
||||
temp = temp;
|
||||
temp = can->IR; // read this register clear all interrupt
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Select the Sleep mode or not in Peli workmode
|
||||
/// @param state to go into the Sleep mode or go out
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_Peli_SleepMode_Cmd(FunctionalState state)
|
||||
{
|
||||
(state == ENABLE) ? (CAN1_PELI->MOD |= CAN_SleepMode) : (CAN1_PELI->MOD &= ~CAN_SleepMode);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Fills each CAN1_PELI_InitStruct member with its default value.
|
||||
/// @param init_struct : pointer to a CAN_Peli_InitTypeDef structure
|
||||
/// which will be initialized.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* init_struct)
|
||||
{
|
||||
//--------------- Reset CAN_Peli init structure parameters values
|
||||
//---------------
|
||||
init_struct->BRP = 0x0; // initialize the BRP member(where can be set with (0..63))
|
||||
init_struct->SJW = 0x0; // initialize the SJW member(where can be set with (0..3))
|
||||
init_struct->TESG1 = 0x0; // Initialize the TESG1 member(where can be set with (0..15))
|
||||
init_struct->TESG2 = 0x0; // Initialize the TESG2 member(where can be set with(0..7))
|
||||
init_struct->SAM = RESET; // Initialize the SAM member(where can be set (SET or RESET))
|
||||
init_struct->LOM = DISABLE; // Initialize the LOM member
|
||||
init_struct->STM = DISABLE; // Initialize the STM member
|
||||
init_struct->SM = DISABLE; // Initialize the SM member
|
||||
init_struct->SRR = DISABLE;
|
||||
init_struct->EWLR = 0x96;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Initializes the CAN_Peli peripheral according to the specified
|
||||
/// parameters in the init_struct.
|
||||
/// @param init_struct: pointer to a CAN_Peli_InitTypeDef structure that
|
||||
/// contains the configuration information for the CAN peripheral in the peli workmode.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_Peli_Init(CAN_Peli_InitTypeDef* init_struct)
|
||||
{
|
||||
CAN1_PELI->BTR0 = ((u32)init_struct->SJW << 6) | ((u32)init_struct->BRP);
|
||||
CAN1_PELI->BTR1 = ((u32)init_struct->SAM << 7) | ((u32)init_struct->TESG2 << 4) | ((u32)init_struct->TESG1);
|
||||
if (init_struct->LOM == ENABLE)
|
||||
CAN1_PELI->MOD |= (u32)CAN_ListenOnlyMode;
|
||||
else
|
||||
CAN1_PELI->MOD &= ~(u32)CAN_ListenOnlyMode;
|
||||
if (init_struct->STM == ENABLE)
|
||||
CAN1_PELI->MOD |= (u32)CAN_SeftTestMode;
|
||||
else
|
||||
CAN1_PELI->MOD &= ~(u32)CAN_SeftTestMode;
|
||||
if (init_struct->SM == ENABLE)
|
||||
CAN1_PELI->MOD |= (u32)CAN_SleepMode;
|
||||
else
|
||||
CAN1_PELI->MOD &= ~(u32)CAN_SleepMode;
|
||||
CAN1_PELI->EWLR = (u32)init_struct->EWLR;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the CAN_Peli reception filter according to the specified
|
||||
/// parameters in the peli_filter_init_struct.
|
||||
/// @param peli_filter_init_struct: pointer to a CAN_Peli_FilterInitTypeDef
|
||||
/// structure that contains the configuration information.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct)
|
||||
{
|
||||
(peli_filter_init_struct->AFM == CAN_FilterMode_Singal) ? (CAN1_PELI->MOD |= (u32)CAN_FilterMode_Singal)
|
||||
: (CAN1_PELI->MOD &= (u32)CAN_FilterMode_Double);
|
||||
|
||||
CAN1_PELI->FF = peli_filter_init_struct->CAN_FilterId0;
|
||||
CAN1_PELI->ID0 = peli_filter_init_struct->CAN_FilterId1;
|
||||
CAN1_PELI->ID1 = peli_filter_init_struct->CAN_FilterId2;
|
||||
CAN1_PELI->DATA0 = peli_filter_init_struct->CAN_FilterId3;
|
||||
|
||||
CAN1_PELI->DATA1 = peli_filter_init_struct->CAN_FilterMaskId0;
|
||||
CAN1_PELI->DATA2 = peli_filter_init_struct->CAN_FilterMaskId1;
|
||||
CAN1_PELI->DATA3 = peli_filter_init_struct->CAN_FilterMaskId2;
|
||||
CAN1_PELI->DATA4 = peli_filter_init_struct->CAN_FilterMaskId3;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Fills each peli_filter_init_struct member with its default value.
|
||||
/// @param peli_filter_init_struct: pointer to a CAN_InitTypeDef structure
|
||||
/// which ill be initialized.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct)
|
||||
{
|
||||
peli_filter_init_struct->CAN_FilterId0 = 0;
|
||||
peli_filter_init_struct->CAN_FilterId1 = 0;
|
||||
peli_filter_init_struct->CAN_FilterId2 = 0;
|
||||
peli_filter_init_struct->CAN_FilterId3 = 0;
|
||||
|
||||
peli_filter_init_struct->CAN_FilterMaskId0 = 0;
|
||||
peli_filter_init_struct->CAN_FilterMaskId1 = 0;
|
||||
peli_filter_init_struct->CAN_FilterMaskId2 = 0;
|
||||
peli_filter_init_struct->CAN_FilterMaskId3 = 0;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Initiates and transmits a CAN frame message.
|
||||
/// @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and
|
||||
/// CAN data.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_Peli_Transmit(CanPeliTxMsg* peli_transmit_message)
|
||||
{
|
||||
CAN1_PELI->FF = (peli_transmit_message->FF << 7) | (peli_transmit_message->RTR << 6) | (peli_transmit_message->DLC);
|
||||
if (((FunctionalState)peli_transmit_message->FF) != ENABLE) {
|
||||
CAN1_PELI->ID0 = (peli_transmit_message->IDHH);
|
||||
|
||||
CAN1_PELI->ID1 = (peli_transmit_message->IDHL & 0xE0);
|
||||
if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
|
||||
CAN1_PELI->DATA0 = peli_transmit_message->Data[0];
|
||||
CAN1_PELI->DATA1 = peli_transmit_message->Data[1];
|
||||
CAN1_PELI->DATA2 = peli_transmit_message->Data[2];
|
||||
CAN1_PELI->DATA3 = peli_transmit_message->Data[3];
|
||||
CAN1_PELI->DATA4 = peli_transmit_message->Data[4];
|
||||
CAN1_PELI->DATA5 = peli_transmit_message->Data[5];
|
||||
CAN1_PELI->DATA6 = peli_transmit_message->Data[6];
|
||||
CAN1_PELI->DATA7 = peli_transmit_message->Data[7];
|
||||
}
|
||||
}
|
||||
else {
|
||||
CAN1_PELI->ID0 = peli_transmit_message->IDHH;
|
||||
CAN1_PELI->ID1 = peli_transmit_message->IDHL;
|
||||
CAN1_PELI->DATA0 = peli_transmit_message->IDLH;
|
||||
CAN1_PELI->DATA1 = peli_transmit_message->IDLL;
|
||||
if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
|
||||
CAN1_PELI->DATA2 = peli_transmit_message->Data[0];
|
||||
CAN1_PELI->DATA3 = peli_transmit_message->Data[1];
|
||||
CAN1_PELI->DATA4 = peli_transmit_message->Data[2];
|
||||
CAN1_PELI->DATA5 = peli_transmit_message->Data[3];
|
||||
CAN1_PELI->DATA6 = peli_transmit_message->Data[4];
|
||||
CAN1_PELI->DATA7 = peli_transmit_message->Data[5];
|
||||
CAN1_PELI->DATA8 = peli_transmit_message->Data[6];
|
||||
CAN1_PELI->DATA9 = peli_transmit_message->Data[7];
|
||||
}
|
||||
}
|
||||
|
||||
(CAN1_PELI->MOD & CAN_MOD_STM) ? (CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT) : (CAN1->CMR = CAN_CMR_TR | CAN_CMR_AT);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Initiates and transmits a CAN frame message.
|
||||
/// @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and
|
||||
/// CAN data.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_Peli_TransmitRepeat(CanPeliTxMsg* peli_transmit_message)
|
||||
{
|
||||
CAN1_PELI->FF = (peli_transmit_message->FF << 7) | (peli_transmit_message->RTR << 6) | (peli_transmit_message->DLC);
|
||||
if (((FunctionalState)peli_transmit_message->FF) != ENABLE) {
|
||||
CAN1_PELI->ID0 = (peli_transmit_message->IDHH);
|
||||
|
||||
CAN1_PELI->ID1 = (peli_transmit_message->IDHL & 0xE0);
|
||||
if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
|
||||
CAN1_PELI->DATA0 = peli_transmit_message->Data[0];
|
||||
CAN1_PELI->DATA1 = peli_transmit_message->Data[1];
|
||||
CAN1_PELI->DATA2 = peli_transmit_message->Data[2];
|
||||
CAN1_PELI->DATA3 = peli_transmit_message->Data[3];
|
||||
CAN1_PELI->DATA4 = peli_transmit_message->Data[4];
|
||||
CAN1_PELI->DATA5 = peli_transmit_message->Data[5];
|
||||
CAN1_PELI->DATA6 = peli_transmit_message->Data[6];
|
||||
CAN1_PELI->DATA7 = peli_transmit_message->Data[7];
|
||||
}
|
||||
}
|
||||
else {
|
||||
CAN1_PELI->ID0 = peli_transmit_message->IDHH;
|
||||
CAN1_PELI->ID1 = peli_transmit_message->IDHL;
|
||||
CAN1_PELI->DATA0 = peli_transmit_message->IDLH;
|
||||
CAN1_PELI->DATA1 = peli_transmit_message->IDLL;
|
||||
if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
|
||||
CAN1_PELI->DATA2 = peli_transmit_message->Data[0];
|
||||
CAN1_PELI->DATA3 = peli_transmit_message->Data[1];
|
||||
CAN1_PELI->DATA4 = peli_transmit_message->Data[2];
|
||||
CAN1_PELI->DATA5 = peli_transmit_message->Data[3];
|
||||
CAN1_PELI->DATA6 = peli_transmit_message->Data[4];
|
||||
CAN1_PELI->DATA7 = peli_transmit_message->Data[5];
|
||||
CAN1_PELI->DATA8 = peli_transmit_message->Data[6];
|
||||
CAN1_PELI->DATA9 = peli_transmit_message->Data[7];
|
||||
}
|
||||
}
|
||||
|
||||
(CAN1_PELI->MOD & CAN_MOD_STM) ? (CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT) : (CAN1->CMR = CAN_CMR_TR);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Receives a correct CAN frame.
|
||||
/// @param RxMessage: pointer to a structure receive frame which contains CAN
|
||||
/// Id,CAN DLC, CAN data and FMI number.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_Peli_Receive(CanPeliRxMsg* peli_receive_message)
|
||||
{
|
||||
u32 tempid;
|
||||
peli_receive_message->FF = (CAN1_PELI->FF) >> 7;
|
||||
peli_receive_message->RTR = ((CAN1_PELI->FF) >> 6) & 0x1;
|
||||
peli_receive_message->DLC = (CAN1_PELI->FF) & 0xf;
|
||||
|
||||
if (((FunctionalState)peli_receive_message->FF) != ENABLE) {
|
||||
tempid = (u32)(CAN1_PELI->ID1 >> 5);
|
||||
tempid |= (u32)(CAN1_PELI->ID0 << 3);
|
||||
peli_receive_message->ID = tempid;
|
||||
peli_receive_message->Data[0] = CAN1_PELI->DATA0;
|
||||
peli_receive_message->Data[1] = CAN1_PELI->DATA1;
|
||||
peli_receive_message->Data[2] = CAN1_PELI->DATA2;
|
||||
peli_receive_message->Data[3] = CAN1_PELI->DATA3;
|
||||
peli_receive_message->Data[4] = CAN1_PELI->DATA4;
|
||||
peli_receive_message->Data[5] = CAN1_PELI->DATA5;
|
||||
peli_receive_message->Data[6] = CAN1_PELI->DATA6;
|
||||
peli_receive_message->Data[7] = CAN1_PELI->DATA7;
|
||||
}
|
||||
else {
|
||||
tempid = (u32)((CAN1_PELI->DATA1 & 0xf8) >> 3);
|
||||
tempid |= (u32)(CAN1_PELI->DATA0 << 5);
|
||||
tempid |= (u32)(CAN1_PELI->ID1 << 13);
|
||||
tempid |= (u32)(CAN1_PELI->ID0 << 21);
|
||||
peli_receive_message->ID = tempid;
|
||||
peli_receive_message->Data[0] = CAN1_PELI->DATA2;
|
||||
peli_receive_message->Data[1] = CAN1_PELI->DATA3;
|
||||
peli_receive_message->Data[2] = CAN1_PELI->DATA4;
|
||||
peli_receive_message->Data[3] = CAN1_PELI->DATA5;
|
||||
peli_receive_message->Data[4] = CAN1_PELI->DATA6;
|
||||
peli_receive_message->Data[5] = CAN1_PELI->DATA7;
|
||||
peli_receive_message->Data[6] = CAN1_PELI->DATA8;
|
||||
peli_receive_message->Data[7] = CAN1_PELI->DATA9;
|
||||
}
|
||||
CAN_FIFORelease(CAN1);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Get available current informatoin in receive FIFO only in Peli
|
||||
/// workmode.
|
||||
/// @retval The value in reg RMC
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 CAN_Peli_GetRxFIFOInfo(void)
|
||||
{
|
||||
return CAN1_PELI->RMC;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the CAN's last error code (LEC).
|
||||
/// @retval Error code:
|
||||
/// - CAN_ERRORCODE_NoErr: No Error
|
||||
/// - CAN_ERRORCODE_StuffErr: Stuff Error
|
||||
/// - CAN_ERRORCODE_FormErr: Form Error
|
||||
/// - CAN_ERRORCODE_ACKErr : Acknowledgment Error
|
||||
/// - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
|
||||
/// - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
|
||||
/// - CAN_ERRORCODE_CRCErr: CRC Error
|
||||
/// - CAN_ERRORCODE_SoftwareSetErr: Software Set Error
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u8 CAN_Peli_GetLastErrorCode(void)
|
||||
{
|
||||
// Return the error code
|
||||
return (u8)CAN1_PELI->ECC;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the CAN Receive Error Counter (REC).
|
||||
/// @note In case of an error during reception, this counter is incremented
|
||||
/// by 1 or by 8 depending on the error condition as defined by the CAN
|
||||
/// standard. After every successful reception, the counter is
|
||||
/// decremented by 1 or reset to 120 if its value was higher than 128.
|
||||
/// When the counter value exceeds 127, the CAN controller enters the
|
||||
/// error passive state.
|
||||
/// @retval CAN Receive Error Counter.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u8 CAN_Peli_GetReceiveErrorCounter(void)
|
||||
{
|
||||
// Return the Receive Error Counter
|
||||
return (u8)(CAN1_PELI->RXERR);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the LSB of the 9-bit can Transmit Error Counter(TEC).
|
||||
/// @retval LSB of the 8-bit CAN Transmit Error Counter.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u8 CAN_Peli_GetLSBTransmitErrorCounter(void)
|
||||
{
|
||||
// Return the LSB of the 8-bit CAN Transmit Error Counter(TEC)
|
||||
return (u8)(CAN1_PELI->TXERR);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified CAN interrupts in peli workmode.
|
||||
/// @param it: specifies the CAN interrupt sources to be enabled or
|
||||
/// disabled.
|
||||
/// This parameter can be:
|
||||
/// @arg CAN_IT_RI: Receive FIFO not empty Interrupt
|
||||
/// @arg CAN_IT_TI: Transmit Interrupt
|
||||
/// @arg CAN_IT_EI: ERROR Interrupt
|
||||
/// @arg CAN_IT_DOI: Data voerflow Interrupt
|
||||
/// @arg CAN_IT_WUI: Wakeup Interrupt
|
||||
/// @arg CAN_IT_EPI(only Peli): passive error Interrupt
|
||||
/// @arg CAN_IT_ALI(only Peli): arbiter lose Interrupt
|
||||
/// @arg CAN_IT_BEI(only Peli): bus error Interrupt
|
||||
/// @arg CAN_IT_ALL: use it can enble all Interrupt
|
||||
/// @param state: new state of the CAN interrupts.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_Peli_ITConfig(u32 it, FunctionalState state)
|
||||
{
|
||||
(state) ? (CAN1_PELI->IER |= it) : (CAN1_PELI->IER &= ~it);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified CAN interrupt has occurred or not.
|
||||
/// @param it: specifies the CAN interrupt source to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg CAN_IT_RI: Receive FIFO not empty Interrupt
|
||||
/// @arg CAN_IT_TI: Transmit Interrupt
|
||||
/// @arg CAN_IT_EI: ERROR Interrupt
|
||||
/// @arg CAN_IT_DOI: Data voerflow Interrupt
|
||||
/// @arg CAN_IT_WUI: Wakeup Interrupt
|
||||
/// @arg CAN_IT_EPI(only Peli): passive error Interrupt
|
||||
/// @arg CAN_IT_ALI(only Peli): arbiter lose Interrupt
|
||||
/// @arg CAN_IT_BEI(only Peli): bus error Interrupt
|
||||
/// @arg CAN_IT_ALL: use it can enble all Interrupt
|
||||
/// @retval The current state of it (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
ITStatus CAN_Peli_GetITStatus(u32 it)
|
||||
{
|
||||
return (ITStatus)(((CAN1_PELI->IR & it) != it) ? RESET : SET);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Config CAN_Peli_InitTypeDef baud parameter.
|
||||
/// @param CAN_Peli_InitTypeDef: CAN struct.
|
||||
/// @param src_clk: CAN module clock.
|
||||
/// @param baud: specified baud.
|
||||
/// @retval The current state of it (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef* init_struct, u32 src_clk, u32 baud)
|
||||
{
|
||||
u32 i, value = baud, record = 1;
|
||||
u32 remain = 0, sumPrescaler = 0;
|
||||
while ((baud == 0) || (src_clk == 0))
|
||||
;
|
||||
sumPrescaler = src_clk / baud;
|
||||
sumPrescaler = sumPrescaler / 2;
|
||||
for (i = 25; i > 3; i--) {
|
||||
remain = sumPrescaler - ((sumPrescaler / i) * i);
|
||||
if (remain == 0) {
|
||||
record = i;
|
||||
break;
|
||||
}
|
||||
else {
|
||||
if (remain < value) {
|
||||
value = remain;
|
||||
record = i;
|
||||
}
|
||||
}
|
||||
}
|
||||
init_struct->SJW = 0;
|
||||
init_struct->BRP = (sumPrescaler / record) - 1;
|
||||
init_struct->TESG2 = (record - 3) / 3;
|
||||
init_struct->TESG1 = (record - 3) - init_struct->TESG2;
|
||||
}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,226 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_comp.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE COMP FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_COMP_C_
|
||||
|
||||
// Files includes
|
||||
#include "hal_comp.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup COMP_HAL
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup COMP_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Deinitializes COMP peripheral registers to their default reset
|
||||
/// values.
|
||||
/// @param selection: the selected comparator.
|
||||
/// select the COMP peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void COMP_DeInit(COMP_Selection_TypeDef selection)
|
||||
{
|
||||
*(vu32*)(COMP_BASE + selection) = 0;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Initializes the COMP peripheral according to the specified
|
||||
/// @param selection: the selected comparator.
|
||||
/// select the COMP peripheral.
|
||||
/// @param init_struct: pointer to an COMP_InitTypeDef structure that
|
||||
/// contains the configuration information for the specified COMP
|
||||
/// peripheral.
|
||||
/// - COMP_InvertingInput specifies the inverting input of COMP
|
||||
/// - COMP_NonInvertingInput specifies the non inverting input of COMP
|
||||
/// - COMP_Output connect COMP output to selected timer
|
||||
/// input (Input capture / Output Compare Reference Clear / Break
|
||||
/// Input)
|
||||
/// - COMP_BlankingSrce specifies the blanking source of COMP
|
||||
/// - COMP_OutputPol select output polarity
|
||||
/// - COMP_Hysteresis configures COMP hysteresis value
|
||||
/// - COMP_Mode configures COMP power mode
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void COMP_Init(COMP_Selection_TypeDef selection, COMP_InitTypeDef* init_struct)
|
||||
{
|
||||
*(vu32*)(COMP_BASE + selection) = init_struct->Invert |
|
||||
init_struct->NonInvert |
|
||||
init_struct->Output |
|
||||
init_struct->OutputPol |
|
||||
init_struct->BlankingSrce |
|
||||
init_struct->Hysteresis |
|
||||
init_struct->Mode |
|
||||
init_struct->OFLT;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Fills each init_struct member with its default value.
|
||||
/// @param init_struct: pointer to an COMP_InitTypeDef structure which will
|
||||
/// be initialized.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void COMP_StructInit(COMP_InitTypeDef* init_struct)
|
||||
{
|
||||
|
||||
init_struct->Invert = COMP_InvertingInput_IO1;
|
||||
init_struct->NonInvert = COMP_NonInvertingInput_IO1;
|
||||
init_struct->Output = COMP_Output_None;
|
||||
init_struct->BlankingSrce = COMP_BlankingSrce_None;
|
||||
init_struct->OutputPol = COMP_NonInverted;
|
||||
init_struct->Hysteresis = COMP_Hysteresis_No;
|
||||
init_struct->Mode = COMP_Mode_UltraLowPower;
|
||||
init_struct->OFLT = COMP_Filter_4_Period; ///< to adjust the speed/consumption.
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enable or disable the COMP peripheral.
|
||||
/// @param selection: the selected comparator.
|
||||
/// select the COMP peripheral.
|
||||
/// @param NewState: new state of the COMP peripheral.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// When enabled, the comparator compares the non inverting input with
|
||||
/// the inverting input and the comparison result is available on
|
||||
/// comparator output.
|
||||
/// When disabled, the comparator doesn't perform comparison and the
|
||||
/// output level is low.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void COMP_Cmd(COMP_Selection_TypeDef selection, FunctionalState state)
|
||||
{
|
||||
(state) ? (*(vu32*)(COMP_BASE + selection) |= COMP_CSR_EN) :
|
||||
(*(vu32*)(COMP_BASE + selection) &= ~COMP_CSR_EN);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Select CRV param.
|
||||
/// @param crv_select: Select source for CRV.
|
||||
/// @param crv_level: Set level for CRV.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void COMP_SetCrv(u8 crv_select, u8 crv_level)
|
||||
{
|
||||
u32 temreg = 0;
|
||||
temreg = COMP->CRV;
|
||||
temreg &= ~COMP_CRV_MASK;
|
||||
// Load config to CRV and enable
|
||||
temreg |= crv_select | crv_level | (1 << 4);
|
||||
COMP->CRV = temreg;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Close or Open the SW1 switch.
|
||||
/// @param selection: the selected comparator.
|
||||
/// select the COMP peripheral.
|
||||
/// @param state: new state of the COMP peripheral.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// When enabled, the comparator compares the non inverting input with
|
||||
/// the inverting input and the comparison result is available on
|
||||
/// comparator output.
|
||||
/// When disabled, the comparator doesn't perform comparison and the
|
||||
/// output level is low.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void COMP_SwitchCmd(COMP_Selection_TypeDef selection, FunctionalState state)
|
||||
{
|
||||
(state) ?
|
||||
(*(vu32*)(COMP_BASE + selection) |= COMP_CSR_COMPSW1) :
|
||||
(*(vu32*)(COMP_BASE + selection) &= ~COMP_CSR_COMPSW1);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Return the output level (high or low) of the selected comparator.
|
||||
/// The output level depends on the selected polarity.
|
||||
/// If the polarity is not inverted:
|
||||
/// - Comparator output is low when the non-inverting input is at a
|
||||
/// lower voltage than the inverting input
|
||||
/// - Comparator output is high when the non-inverting input is at a
|
||||
/// higher voltage than the inverting input
|
||||
/// If the polarity is inverted:
|
||||
/// - Comparator output is high when the non-inverting input is at a
|
||||
/// lower voltage than the inverting input
|
||||
/// - Comparator output is low when the non-inverting input is at a
|
||||
/// higher voltage than the inverting input
|
||||
/// @param comp: the selected comparator.
|
||||
/// select the COMP peripheral.
|
||||
/// @retval The selected comparator output level: low or high.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 COMP_GetOutputLevel(COMP_Selection_TypeDef selection)
|
||||
{
|
||||
return (((*(vu32*)(COMP_BASE + selection) & COMP_CSR_STA) != 0) ?
|
||||
COMP_OutputLevel_High :
|
||||
COMP_OutputLevel_Low );
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Lock the selected comparator (COMP1/COMP2) configuration.
|
||||
/// @param selection: the selected comparator.
|
||||
/// select the COMP peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void COMP_LockConfig(COMP_Selection_TypeDef selection)
|
||||
{
|
||||
*(vu32*)(COMP_BASE + selection) |= COMP_CSR_LOCK;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enable or disable the COMP register.
|
||||
/// @param state: new state of the COMP peripheral.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exCOMP_CrvCmd(FunctionalState state)
|
||||
{
|
||||
(state) ? (COMP->CRV |= COMP_CRV_EN_ENABLE) : (COMP->CRV &= ~COMP_CRV_EN_ENABLE);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Select comparator external reference voltage.
|
||||
/// @param selection: the selected external reference voltage.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exCOMP_SwitchCrv(u32 crv)
|
||||
{
|
||||
COMP->CRV |= crv;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Select comparator external reference voltage source.
|
||||
/// @param selection: the selected external reference voltage source.
|
||||
/// This parameter can be: COMP_CRV_SRC_AVDD or COMP_CRV_SRC_VREF.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exCOMP_CrvSrc(u32 src)
|
||||
{
|
||||
COMP->CRV |= src;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
@@ -0,0 +1,108 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_crc.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE CRC FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_CRC_C_
|
||||
|
||||
// Files includes
|
||||
#include "hal_crc.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup CRC_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup CRC_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Resets the CRC Data register (DR).
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CRC_ResetDR()
|
||||
{
|
||||
CRC->CR = CRC_CR_RESET;
|
||||
}
|
||||
//#pragma optimize(0)
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Computes the 32-bit CRC of a given data word(32-bit).
|
||||
/// @param Data: data word(32-bit) to compute its CRC
|
||||
/// @retval 32-bit CRC
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 CRC_CalcCRC(u32 data)
|
||||
{
|
||||
CRC->DR = data;
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
|
||||
/// @param buffer: pointer to the buffer containing the data to be computed
|
||||
/// @param length: length of the buffer to be computed
|
||||
/// @retval 32-bit CRC
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 CRC_CalcBlockCRC(u32* buffer, u32 length)
|
||||
{
|
||||
u32 i;
|
||||
for (i = 0; i < length; i++) {
|
||||
CRC->DR = buffer[i];
|
||||
}
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the current CRC value.
|
||||
/// @param None.
|
||||
/// @retval 32-bit CRC
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 CRC_GetCRC(void)
|
||||
{
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Stores a 8-bit data in the Independent Data(ID) register.
|
||||
/// @param id_value: 8-bit value to be stored in the ID register
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void CRC_SetIDRegister(u8 id_value)
|
||||
{
|
||||
CRC->IDR = id_value;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the 8-bit data stored in the Independent Data(ID) register
|
||||
/// @param None.
|
||||
/// @retval 8-bit value of the ID register
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u8 CRC_GetIDRegister()
|
||||
{
|
||||
return (CRC->IDR);
|
||||
}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
@@ -0,0 +1,43 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_crs.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE CRS FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_CRS_C_
|
||||
|
||||
// Files includes
|
||||
#include "hal_rcc.h"
|
||||
#include "hal_crs.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup CRS_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup CRS_Exported_Functions
|
||||
/// @{
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
@@ -0,0 +1,184 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_dac.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE DAC FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_DAC_C_
|
||||
|
||||
// Files includes
|
||||
#include "hal_dac.h"
|
||||
#include "hal_rcc.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup DAC_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup DAC_Exported_Functions
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DAC_DeInit(void)
|
||||
{
|
||||
exRCC_APB1PeriphReset(RCC_APB1ENR_DAC);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
|
||||
/// @param channel: the selected DAC channel.
|
||||
/// @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains the configuration information for the specified
|
||||
/// DAC channel.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DAC_Init(emDACCH_TypeDef channel, DAC_InitTypeDef* init_struct)
|
||||
{
|
||||
DAC->CR &= ~((DAC_CR_BOFF1 | DAC_CR_TEN1 | DAC_CR_TSEL1 | DAC_CR_WAVE1 | DAC_CR_MAMP1) << channel);
|
||||
DAC->CR |= (((u32)(init_struct->DAC_Trigger) | (u32)(init_struct->DAC_WaveGeneration) |
|
||||
(u32)(init_struct->DAC_LFSRUnmask_TriangleAmplitude) | (u32)(init_struct->DAC_OutputBuffer))
|
||||
<< channel);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Fills each DAC_InitStruct member with its default value.
|
||||
/// @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will be initialized.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DAC_StructInit(DAC_InitTypeDef* init_struct)
|
||||
{
|
||||
init_struct->DAC_Trigger = DAC_Trigger_None;
|
||||
init_struct->DAC_WaveGeneration = DAC_WaveGeneration_None;
|
||||
init_struct->DAC_LFSRUnmask_TriangleAmplitude = DAC_TriangleAmplitude_1;
|
||||
init_struct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified DAC channel.
|
||||
/// @param channel: the selected DAC channel.
|
||||
/// @param state: new state of the DAC channel.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DAC_Cmd(emDACCH_TypeDef channel, FunctionalState state)
|
||||
{
|
||||
(state) ? (DAC->CR |= DAC_CR_EN1 << channel) : (DAC->CR &= ~(DAC_CR_EN1 << channel));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified DAC channel DMA request.
|
||||
/// @param channel: the selected DAC channel.
|
||||
/// @param state: new state of the selected DAC channel DMA request.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DAC_DMACmd(emDACCH_TypeDef channel, FunctionalState state)
|
||||
{
|
||||
(state) ? (DAC->CR |= DAC_CR_DMAEN1 << channel) : (DAC->CR &= ~(DAC_CR_DMAEN1 << channel));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the selected DAC channel software trigger.
|
||||
/// @param channel: the selected DAC channel.
|
||||
/// @param state: new state of the selected DAC channel software trigger.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DAC_SoftwareTriggerCmd(emDACCH_TypeDef channel, FunctionalState state)
|
||||
{
|
||||
(state) ? (DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 << (channel >> 4)))
|
||||
: (DAC->SWTRIGR &= ~(DAC_SWTRIGR_SWTRIG1 << (channel >> 4)));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables simultaneously the two DAC channels software triggers.
|
||||
/// @param state: new state of the DAC channels software triggers.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState state)
|
||||
{
|
||||
(state) ? (DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2))
|
||||
: (DAC->SWTRIGR &= ~(DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the selected DAC channel wave generation.
|
||||
/// @param channel: the selected DAC channel.
|
||||
/// @param wave: Specifies the wave type to enable or disable.
|
||||
/// @param state: new state of the selected DAC channel wave generation.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DAC_WaveGenerationCmd(emDACCH_TypeDef channel, emDACWAVE_TypeDef wave, FunctionalState state)
|
||||
{
|
||||
(state) ? (DAC->CR |= wave << channel) : (DAC->CR &= ~(wave << channel));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Set the specified data holding register value for DAC channel1.
|
||||
/// @param alignement: Specifies the data alignement for DAC channel1.
|
||||
/// @param data : data to be loaded in the selected data holding register.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DAC_SetChannel1Data(emDACALIGN_TypeDef alignement, u16 data)
|
||||
{
|
||||
*((u32*)(DAC_BASE + DHR12R1_Offset + alignement)) = data;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Set the specified data holding register value for DAC channel2.
|
||||
/// @param alignement: Specifies the data alignement for DAC channel2.
|
||||
/// @param data : data to be loaded in the selected data holding
|
||||
/// register.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DAC_SetChannel2Data(emDACALIGN_TypeDef alignement, u16 data)
|
||||
{
|
||||
*((u32*)(DAC_BASE + DHR12R2_Offset + alignement)) = data;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Set the specified data holding register value for dual channel DAC.
|
||||
/// @param alignement: Specifies the data alignement for dual channel DAC.
|
||||
/// @param data2: data for DAC Channel2 to be loaded in the selected data holding register.
|
||||
/// @param data1: data for DAC Channel1 to be loaded in the selected data holding register.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DAC_SetDualChannelData(emDACALIGN_TypeDef alignement, u16 data2, u16 data1)
|
||||
{
|
||||
u32 data = ((alignement == DAC_Align_8b_R) ? ((data2 << 8) | data1) : ((data2 << 16) | data1));
|
||||
*((u32*)(DAC_BASE + DHR12RD_Offset + alignement)) = data;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the last data output value of the selected DAC cahnnel.
|
||||
/// @param channel: the selected DAC channel.
|
||||
/// @retval The selected DAC channel data output value.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u16 DAC_GetDataOutputValue(emDACCH_TypeDef channel)
|
||||
{
|
||||
return (*(vu32*)(DAC_BASE + DOR_Offset + (channel >> 2)));
|
||||
}
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
@@ -0,0 +1,53 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_dbg.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE DBG FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_DBG_C
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "hal_dbg.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup DBG_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup DBG_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified DBG peripheral.
|
||||
/// @param periph: DBG peripheral.
|
||||
/// @param state: new state of the specified DBG peripheral.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DBGMCU_Configure(u32 periph, FunctionalState state)
|
||||
{
|
||||
(state) ? (DBGMCU->CR |= periph) : (DBGMCU->CR &= ~periph);
|
||||
}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
@@ -0,0 +1,319 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_dma.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE DMA FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_DMA_C_
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "hal_dma.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup DMA_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup DMA_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Deinitializes the DMA Channeln registers to their default reset
|
||||
/// values.
|
||||
/// @param select the DMA Channel.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* channel)
|
||||
{
|
||||
channel->CCR &= ~DMA_CCR_EN;
|
||||
channel->CCR = 0;
|
||||
channel->CNDTR = 0;
|
||||
channel->CPAR = 0;
|
||||
channel->CMAR = 0;
|
||||
if((*(vu32*)&channel) >= (*(vu32*)DMA2_Channel1_BASE)) {
|
||||
DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
|
||||
}
|
||||
else {
|
||||
DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Initializes the DMA Channeln according to the specified
|
||||
/// parameters in the init_struct.
|
||||
/// @param select the DMA Channel.
|
||||
/// @param init_struct: pointer to a DMA_InitTypeDef structure that
|
||||
/// contains the configuration information for the specified DMA
|
||||
/// Channel.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DMA_Init(DMA_Channel_TypeDef* channel, DMA_InitTypeDef* init_struct)
|
||||
{
|
||||
MODIFY_REG(
|
||||
channel->CCR,
|
||||
(DMA_CCR_DIR | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL | DMA_CCR_M2M),
|
||||
((u32)init_struct->DMA_DIR | (u32)init_struct->DMA_Mode | (u32)init_struct->DMA_PeripheralInc |
|
||||
(u32)init_struct->DMA_MemoryInc | (u32)init_struct->DMA_PeripheralDataSize | (u32)init_struct->DMA_MemoryDataSize |
|
||||
(u32)init_struct->DMA_Priority | (u32)init_struct->DMA_M2M));
|
||||
|
||||
MODIFY_REG(channel->CCR, DMA_CCR_ARE, init_struct->DMA_Auto_reload);
|
||||
channel->CNDTR = init_struct->DMA_BufferSize;
|
||||
channel->CPAR = init_struct->DMA_PeripheralBaseAddr;
|
||||
channel->CMAR = init_struct->DMA_MemoryBaseAddr;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Fills each init_struct member with its default value.
|
||||
/// @param init_struct : pointer to a DMA_InitTypeDef structure which will
|
||||
/// be initialized.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DMA_StructInit(DMA_InitTypeDef* init_struct)
|
||||
{
|
||||
init_struct->DMA_PeripheralBaseAddr = 0;
|
||||
init_struct->DMA_MemoryBaseAddr = 0;
|
||||
init_struct->DMA_DIR = DMA_DIR_PeripheralSRC;
|
||||
init_struct->DMA_BufferSize = 0;
|
||||
init_struct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
init_struct->DMA_MemoryInc = DMA_MemoryInc_Disable;
|
||||
init_struct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
init_struct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
init_struct->DMA_Mode = DMA_Mode_Normal;
|
||||
init_struct->DMA_Priority = DMA_Priority_Low;
|
||||
init_struct->DMA_M2M = DMA_M2M_Disable;
|
||||
|
||||
init_struct->DMA_Auto_reload = DMA_Auto_Reload_Disable;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified DMA Channeln.
|
||||
/// @param channel: select the DMA Channel.
|
||||
/// @param state: new state of the DMA Channeln.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* channel, FunctionalState state)
|
||||
{
|
||||
MODIFY_REG(channel->CCR, DMA_CCR_EN, state << DMA_CCR_EN_Pos);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified DMA Channeln interrupts.
|
||||
/// @param channel: select the DMA Channel.
|
||||
/// @param it: specifies the DMA interrupts sources to be enabled
|
||||
/// or disabled.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
/// @arg DMA_IT_HT: Half transfer interrupt mask
|
||||
/// @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
/// @param state: new state of the specified DMA interrupts.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* channel, DMA_Interrupt_EN_TypeDef it, FunctionalState state)
|
||||
{
|
||||
(state) ? (channel->CCR |= it) : (channel->CCR &= ~it);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Sets the number of data units in the select the DMA Channel .
|
||||
/// @param channel: select the DMA Channel
|
||||
/// @param DataNumber: The number of data units in the current DMAy Channelx
|
||||
/// transfer.
|
||||
/// @note This function can only be used when the DMAy_Channelx is disabled.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* channel, u16 length)
|
||||
{
|
||||
channel->CNDTR = length;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the number of remaining data units in the current
|
||||
/// DMA Channeln transfer.
|
||||
/// @param channel: select the DMA Channel.
|
||||
/// @retval The number of remaining data units in the current DMA Channeln
|
||||
/// transfer.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* channel)
|
||||
{
|
||||
return channel->CNDTR;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified DMA Channeln flag is set or not.
|
||||
/// @param flag: specifies the flag to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg DMA1_FLAG_GLn: DMA1 Channeln global flag(n = 1..7).
|
||||
/// @arg DMA1_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..7).
|
||||
/// @arg DMA1_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..7).
|
||||
/// @arg DMA1_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..7).
|
||||
/// @arg DMA2_FLAG_GLn: DMA1 Channeln global flag(n = 1..5).
|
||||
/// @arg DMA2_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
|
||||
/// @arg DMA2_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..5).
|
||||
/// @arg DMA2_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..5).
|
||||
/// @retval The new state of DMAy_FLAG (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus DMA_GetFlagStatus(DMA_Flags_TypeDef flag)
|
||||
{
|
||||
if(flag >= DMA2_FLAG_GL1 ) {
|
||||
return (DMA2->ISR & flag) ? SET : RESET;
|
||||
}
|
||||
return (DMA1->ISR & flag) ? SET : RESET;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the DMA Channeln's pending flags.
|
||||
/// @param flag: specifies the flag to clear.
|
||||
/// This parameter can be any combination (for the same DMA) of the
|
||||
/// following values:
|
||||
/// @arg DMA1_FLAG_GLn: DMA1 Channeln global flag(n = 1..7).
|
||||
/// @arg DMA1_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..7).
|
||||
/// @arg DMA1_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..7).
|
||||
/// @arg DMA1_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..7).
|
||||
/// @arg DMA2_FLAG_GLn: DMA1 Channeln global flag(n = 1..5).
|
||||
/// @arg DMA2_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
|
||||
/// @arg DMA2_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..5).
|
||||
/// @arg DMA2_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..5).
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DMA_ClearFlag(DMA_Flags_TypeDef flag)
|
||||
{
|
||||
if(flag >= DMA2_FLAG_GL1 ) {
|
||||
DMA2->IFCR = flag;
|
||||
return ;
|
||||
}
|
||||
DMA1->IFCR = flag;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified DMA Channeln interrupt has occurred or
|
||||
/// not.
|
||||
/// @param it: specifies the DMA interrupt source to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
|
||||
/// @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
|
||||
/// @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
|
||||
/// @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
|
||||
/// @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
|
||||
/// @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
|
||||
/// @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
|
||||
/// @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
|
||||
/// @retval The new state of DMAy_IT (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
ITStatus DMA_GetITStatus(DMA_Interrupts_TypeDef it)
|
||||
{
|
||||
if(it >= DMA2_IT_GL1 ) {
|
||||
return (DMA2->ISR & it) ? SET : RESET;
|
||||
}
|
||||
return (DMA1->ISR & it) ? SET : RESET;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the DMA Channeln's interrupt pending bits.
|
||||
/// @param it: specifies the DMA interrupt pending bit to clear.
|
||||
/// This parameter can be any combination (for the same DMA) of the
|
||||
/// following values:
|
||||
/// @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
|
||||
/// @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
|
||||
/// @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
|
||||
/// @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
|
||||
/// @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
|
||||
/// @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
|
||||
/// @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
|
||||
/// @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void DMA_ClearITPendingBit(DMA_Interrupts_TypeDef it)
|
||||
{
|
||||
if(it >= DMA2_IT_GL1 ) {
|
||||
DMA2->IFCR = it;
|
||||
return ;
|
||||
}
|
||||
DMA1->IFCR = it;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Set the DMA Channeln's Peripheral address.
|
||||
/// @param channel : where n can be 1 to 7 for DMA1 to select the DMA Channel.
|
||||
/// @param address : DMA Peripheral address.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exDMA_SetPeripheralAddress(DMA_Channel_TypeDef* channel, u32 address)
|
||||
{
|
||||
channel->CPAR = address;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Set the DMA Channeln's Peripheral address.
|
||||
/// @param channel : select the DMA Channel.
|
||||
/// @param length : Transmit lengths.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exDMA_SetTransmitLen(DMA_Channel_TypeDef* channel, u16 length)
|
||||
{
|
||||
channel->CNDTR = length;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Set the DMA Channeln's Peripheral address.
|
||||
/// @param channel :select the DMA Channel.
|
||||
/// @param address : DMA memery address.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exDMA_SetMemoryAddress(DMA_Channel_TypeDef* channel, u32 address)
|
||||
{
|
||||
channel->CMAR = address;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the DMA Channeln's interrupt pending bits.
|
||||
/// @param it: specifies the DMA interrupt pending bit to clear.
|
||||
/// This parameter can be any combination (for the same DMA) of the
|
||||
/// following values:
|
||||
/// @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
|
||||
/// @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
|
||||
/// @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
|
||||
/// @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
|
||||
/// @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
|
||||
/// @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
|
||||
/// @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
|
||||
/// @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exDMA_ClearITPendingBit(DMA_Channel_TypeDef* channel, u32 it)
|
||||
{
|
||||
if(it >= DMA2_IT_GL1 ) {
|
||||
DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
|
||||
DMA2->IFCR = it;
|
||||
return ;
|
||||
}
|
||||
DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
|
||||
DMA1->IFCR = it;
|
||||
}
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
@@ -0,0 +1,836 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_eth.c
|
||||
/// @author AE TEM
|
||||
/// @brief THIS FILE PROVIDES ALL THE HAL_eth.c EXAMPLE.
|
||||
/// ////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define _HAL_ETH_C_
|
||||
#include "hal_rcc.h"
|
||||
#include "hal_eth.h"
|
||||
#include "reg_eth.h"
|
||||
|
||||
|
||||
void ETH_DeInit(void)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBENR_ETHMAC, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBENR_ETHMAC, DISABLE);
|
||||
}
|
||||
|
||||
void ETH_StructInit(ETH_InitTypeDef* ptr)
|
||||
{
|
||||
ptr->ETH_AutoNegotiation = ETH_AutoNegotiation_Enable; ///< PHY Auto-negotiation enabled
|
||||
ptr->ETH_Watchdog = ETH_Watchdog_Enable; ///< MAC watchdog enabled: cuts off long frame
|
||||
ptr->ETH_Jabber = ETH_Jabber_Enable; ///< MAC Jabber enabled in Half-duplex mode
|
||||
ptr->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; ///< Ethernet interframe gap set to 96 bits
|
||||
ptr->ETH_CarrierSense = ETH_CarrierSense_Enable; ///< Carrier Sense Enabled in Half-Duplex mode
|
||||
ptr->ETH_Speed = ETH_Speed_100M; ///< PHY speed configured to 100Mbit/s
|
||||
ptr->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; ///< Receive own Frames in Half-Duplex mode enabled
|
||||
ptr->ETH_LoopbackMode = ETH_LoopbackMode_Disable; ///< MAC MII loopback disabled
|
||||
ptr->ETH_Mode = ETH_Mode_FullDuplex; ///< Full-Duplex mode selected
|
||||
ptr->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; ///< IPv4 and TCP/UDP/ICMP frame Checksum Offload disabled
|
||||
ptr->ETH_RetryTransmission = ETH_RetryTransmission_Enable; ///< Retry Transmission enabled for half-duplex mode
|
||||
ptr->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; ///< Automatic PAD/CRC strip disable
|
||||
ptr->ETH_BackOffLimit = ETH_BackOffLimit_10; ///< half-duplex mode retransmission Backoff time_limit = 10 slot time
|
||||
ptr->ETH_DeferralCheck = ETH_DeferralCheck_Disable; ///< half-duplex mode Deferral check disabled
|
||||
ptr->ETH_ReceiveAll = ETH_ReceiveAll_Disable; ///< Receive all frames disabled
|
||||
ptr->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; ///< Source address filtering (on the optional MAC addresses) disabled
|
||||
ptr->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; ///< Do not forward control frames that do not pass the address filtering
|
||||
ptr->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; ///< Disable reception of Broadcast frames
|
||||
ptr->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; ///< Normal Destination address filtering (not reverse addressing)
|
||||
ptr->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; ///< Promiscuous address filtering mode disabled
|
||||
ptr->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; ///< Perfect address filtering for multicast addresses
|
||||
ptr->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; ///< Perfect address filtering for unicast addresses
|
||||
ptr->ETH_HashTableHigh = 0x0; ///< Initialize hash table high and low regs
|
||||
ptr->ETH_HashTableLow = 0x0;
|
||||
ptr->ETH_PauseTime = 0x0; ///< Flow control config (flow control disabled)
|
||||
ptr->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Enable;
|
||||
ptr->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;
|
||||
ptr->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
|
||||
ptr->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
|
||||
ptr->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
|
||||
ptr->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; ///< VLANtag config (VLAN field not checked)
|
||||
ptr->ETH_VLANTagIdentifier = 0x0;
|
||||
|
||||
ptr->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; ///< Drops frames with with TCP/IP checksum errors
|
||||
ptr->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; ///< Store and forward mode enabled for receive
|
||||
ptr->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable; ///< Flush received frame that created FIFO overflow
|
||||
ptr->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; ///< Store and forward mode enabled for transmit
|
||||
ptr->ETH_TransmitThresholdControl = ETH_ReceiveThresholdControl_64Bytes; ///< Threshold TXFIFO level set to 64 bytes (used when threshold mode is enabled)
|
||||
ptr->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; ///< Disable forwarding frames with errors (short frames, CRC,...)
|
||||
ptr->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; ///< Disable undersized good frames
|
||||
ptr->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; ///< Threshold RXFIFO level set to 64 bytes (used when Cut through mode is enabled)
|
||||
ptr->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; ///< Disable Operate on second frame (transmit a second frame to FIFO without waiting status of previous frame
|
||||
ptr->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; ///< DMA works on 32-bit aligned start source and destinations addresses
|
||||
ptr->ETH_FixedBurst = ETH_FixedBurst_Enable; ///< Enabled Fixed Burst Mode (mix of INC4, INC8, INC16 and SINGLE DMA transactions
|
||||
ptr->ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; ///< DMA transfer max burst length = 32 beats = 32 x 32bits
|
||||
ptr->ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
|
||||
ptr->ETH_DescriptorSkipLength = 0x0; ///< DMA Ring mode skip length = 0
|
||||
ptr->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; ///< Equal priority (round-robin) between transmit and receive DMA engines
|
||||
}
|
||||
|
||||
u32 ETH_Init(ETH_InitTypeDef* ptr, u16 phy_addr)
|
||||
{
|
||||
u32 hclk = RCC_GetHCLKFreq();
|
||||
u32 reg = ETH->MACMIIAR & MACMIIAR_CR_MASK;
|
||||
u32 temp_val = 0;
|
||||
hclk = 100000000;
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
if (hclk >= 20000000 && hclk < 35000000) {
|
||||
reg |= ETH_MACMIIAR_CR_Div16; ///< HCLK 20 ~ 35 MHz, /16
|
||||
}
|
||||
else if (hclk >= 35000000 && hclk < 60000000) {
|
||||
reg |= ETH_MACMIIAR_CR_Div26; ///< HCLK 35 ~ 60 MHz, /26
|
||||
}
|
||||
else if (hclk >= 60000000 && hclk < 100000000) {
|
||||
reg |= ETH_MACMIIAR_CR_Div42; ///< HCLK 60 ~ 100 MHz, /42
|
||||
}
|
||||
else if (hclk >= 100000000 && hclk < 150000000) {
|
||||
reg |= ETH_MACMIIAR_CR_Div62; ///< HCLK 100 ~ 150 MHz, /62
|
||||
}
|
||||
else {
|
||||
reg |= ETH_MACMIIAR_CR_Div102; ///< HCLK 150 ~ 168 MHz, /102
|
||||
}
|
||||
|
||||
ETH->MACMIIAR = reg;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_Reset);
|
||||
if (ptr->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable) {
|
||||
// Wait for linked status
|
||||
while (!(ETH_ReadPHYRegister(phy_addr, PHY_BSR) & PHY_Linked_Status));
|
||||
ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_AutoNegotiation);
|
||||
// Enable Auto-Negitation
|
||||
while (!(ETH_ReadPHYRegister(phy_addr, PHY_BSR) & PHY_AutoNego_Complete)) {
|
||||
|
||||
}
|
||||
// Read the result of the Auto-Negitation
|
||||
temp_val = ETH_ReadPHYRegister(phy_addr, 31);
|
||||
|
||||
if ((temp_val & 0x1C) == 0x4) {
|
||||
ptr->ETH_Speed = ETH_Speed_10M;
|
||||
ptr->ETH_Mode = ETH_Mode_HalfDuplex;
|
||||
SYSCFG->CFGR2 &= ~(1 << 21);
|
||||
}
|
||||
else if((temp_val & 0x1C) == 0x14) {
|
||||
ptr->ETH_Speed = ETH_Speed_10M;
|
||||
ptr->ETH_Mode = ETH_Mode_FullDuplex;
|
||||
SYSCFG->CFGR2 |= 1 << 21;
|
||||
}
|
||||
else if((temp_val & 0x1C) == 0x8) {
|
||||
ptr->ETH_Speed = ETH_Speed_100M;
|
||||
ptr->ETH_Mode = ETH_Mode_HalfDuplex;
|
||||
SYSCFG->CFGR2 &= ~(1 << 21);
|
||||
}
|
||||
else if((temp_val & 0x1C) == 0x18) {
|
||||
ptr->ETH_Speed = ETH_Speed_100M;
|
||||
ptr->ETH_Mode = ETH_Mode_FullDuplex;
|
||||
SYSCFG->CFGR2 |= 1 << 21;
|
||||
}
|
||||
}
|
||||
else {
|
||||
ETH_WritePHYRegister(phy_addr, PHY_BCR, ((u16)(ptr->ETH_Mode >> 3) |
|
||||
(u16)(ptr->ETH_Speed >> 1)));
|
||||
if(ptr->ETH_Speed == ETH_Speed_10M) {
|
||||
SYSCFG->CFGR2 &= ~(1 << 21);
|
||||
}
|
||||
else {
|
||||
SYSCFG->CFGR2 |= 1 << 21;
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
ETH->MACCR = ETH->MACCR & MACCR_CLEAR_MASK | (ptr->ETH_Watchdog |
|
||||
ptr->ETH_Jabber |
|
||||
ptr->ETH_InterFrameGap |
|
||||
ptr->ETH_CarrierSense |
|
||||
ptr->ETH_Speed |
|
||||
ptr->ETH_ReceiveOwn |
|
||||
ptr->ETH_LoopbackMode |
|
||||
ptr->ETH_Mode |
|
||||
ptr->ETH_ChecksumOffload |
|
||||
ptr->ETH_RetryTransmission |
|
||||
ptr->ETH_AutomaticPadCRCStrip |
|
||||
ptr->ETH_DeferralCheck);
|
||||
|
||||
ETH->MACFFR = ptr->ETH_ReceiveAll |
|
||||
ptr->ETH_SourceAddrFilter |
|
||||
ptr->ETH_PassControlFrames |
|
||||
ptr->ETH_BroadcastFramesReception |
|
||||
ptr->ETH_DestinationAddrFilter |
|
||||
ptr->ETH_PromiscuousMode |
|
||||
ptr->ETH_MulticastFramesFilter |
|
||||
ptr->ETH_UnicastFramesFilter;
|
||||
|
||||
ETH->MACHTHR = ptr->ETH_HashTableHigh;
|
||||
ETH->MACHTLR = ptr->ETH_HashTableLow;
|
||||
|
||||
ETH->MACFCR = ETH->MACFCR & MACFCR_CLEAR_MASK | ((ptr->ETH_PauseTime << ETH_MACFCR_PT_Pos) |
|
||||
ptr->ETH_ZeroQuantaPause |
|
||||
ptr->ETH_PauseLowThreshold |
|
||||
ptr->ETH_UnicastPauseFrameDetect |
|
||||
ptr->ETH_ReceiveFlowControl |
|
||||
ptr->ETH_TransmitFlowControl);
|
||||
|
||||
ETH->MACVLANTR = ptr->ETH_VLANTagComparison | ptr->ETH_VLANTagIdentifier;
|
||||
|
||||
ETH->DMAOMR = 0x00200004;
|
||||
ETH->DMAIER = 0x0001A040;
|
||||
ETH->DMABMR = ( ptr->ETH_AddressAlignedBeats |
|
||||
ptr->ETH_FixedBurst |
|
||||
ptr->ETH_RxDMABurstLength | // !! if 4xPBL is selected for Tx or Rx it is applied for the other
|
||||
ptr->ETH_TxDMABurstLength |
|
||||
ptr->ETH_DescriptorSkipLength << 2 |
|
||||
ptr->ETH_DMAArbitration);// |
|
||||
// ETH_DMABMR_USP); // Enable use of separate PBL for Rx and Tx
|
||||
|
||||
return ETH_SUCCESS;
|
||||
}
|
||||
|
||||
void ETH_Start(void)
|
||||
{
|
||||
ETH_MACTransmissionCmd(ENABLE);
|
||||
ETH_MACReceptionCmd(ENABLE);
|
||||
ETH_FlushTransmitFIFO();
|
||||
ETH_DMATransmissionCmd(ENABLE);
|
||||
ETH_DMAReceptionCmd(ENABLE);
|
||||
}
|
||||
|
||||
void ETH_Stop(void)
|
||||
{
|
||||
ETH_DMATransmissionCmd(DISABLE);
|
||||
ETH_DMAReceptionCmd(DISABLE);
|
||||
ETH_MACReceptionCmd(DISABLE);
|
||||
ETH_FlushTransmitFIFO();
|
||||
ETH_MACTransmissionCmd(DISABLE);
|
||||
}
|
||||
|
||||
void ETH_MACTransmissionCmd(FunctionalState sta)
|
||||
{
|
||||
sta ? (ETH->MACCR |= ETH_MACCR_TE) : (ETH->MACCR &= ~ETH_MACCR_TE);
|
||||
}
|
||||
|
||||
void ETH_MACReceptionCmd(FunctionalState sta)
|
||||
{
|
||||
sta ? (ETH->MACCR |= ETH_MACCR_RE) : (ETH->MACCR &= ~ETH_MACCR_RE);
|
||||
}
|
||||
|
||||
FlagStatus ETH_GetFlowControlBusyStatus(void)
|
||||
{
|
||||
return (FlagStatus)(ETH->MACFCR & ETH_MACFCR_FCBBPA);
|
||||
}
|
||||
|
||||
void ETH_InitiatePauseControlFrame(void)
|
||||
{
|
||||
ETH->MACFCR |= ETH_MACFCR_FCBBPA;
|
||||
}
|
||||
|
||||
void ETH_BackPressureActivationCmd(FunctionalState sta)
|
||||
{
|
||||
sta ? (ETH->MACFCR |= ETH_MACFCR_FCBBPA) : (ETH->MACFCR &= ~ETH_MACFCR_FCBBPA);
|
||||
}
|
||||
|
||||
void ETH_MACAddressConfig(u32 reg_addr, u8* mac_addr)
|
||||
{
|
||||
*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) =
|
||||
(u32)mac_addr[5] << 8 |
|
||||
(u32)mac_addr[4];
|
||||
|
||||
*(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) =
|
||||
(u32)mac_addr[3] << 24 |
|
||||
(u32)mac_addr[2] << 16 |
|
||||
(u32)mac_addr[1] << 8 |
|
||||
(u32)mac_addr[0];
|
||||
}
|
||||
|
||||
void ETH_GetMACAddress(u32 reg_addr, u8* mac_addr)
|
||||
{
|
||||
mac_addr[5] = *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) >> 8 & 0xFF;
|
||||
mac_addr[4] = *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) & 0xFF;
|
||||
mac_addr[3] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 24 & 0xFF;
|
||||
mac_addr[2] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 16 & 0xFF;
|
||||
mac_addr[1] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 8 & 0xFF;
|
||||
mac_addr[0] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) & 0xFF;
|
||||
}
|
||||
|
||||
void ETH_MACAddressPerfectFilterCmd(u32 reg_addr, FunctionalState sta)
|
||||
{
|
||||
sta ? ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_AE) :
|
||||
((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) &= ~ETH_MACA1HR_AE);
|
||||
}
|
||||
|
||||
void ETH_MACAddressFilterConfig(u32 reg_addr, u32 sta)
|
||||
{
|
||||
sta ? ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_SA) :
|
||||
((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_SA);
|
||||
}
|
||||
|
||||
void ETH_MACAddressMaskBytesFilterConfig(u32 reg_addr, u32 mask_byte)
|
||||
{
|
||||
(*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) &= ~ETH_MACA1HR_MBC;
|
||||
|
||||
(*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= mask_byte;
|
||||
}
|
||||
|
||||
FrameTypeDef ETH_Get_Received_Frame(void)
|
||||
{
|
||||
FrameTypeDef frame;
|
||||
|
||||
frame.len = ((DMARxDescToGet->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FL_Pos) - 4;
|
||||
frame.buf = (DMA_RX_FRAME_infos->ptrFS_Rx_Desc)->BUF1ADDR;
|
||||
frame.ptrDesc = DMA_RX_FRAME_infos->ptrFS_Rx_Desc;
|
||||
|
||||
|
||||
DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
|
||||
|
||||
return frame;
|
||||
}
|
||||
|
||||
FrameTypeDef ETH_Get_Received_Frame_interrupt(void)
|
||||
{
|
||||
FrameTypeDef frame = {0};
|
||||
__IO u32 desc_cnt = 0;
|
||||
|
||||
while(!(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) && desc_cnt < ETH_RX_BUF_NUM) {
|
||||
desc_cnt++;
|
||||
|
||||
if ( (DMARxDescToGet->CS & ETH_DMA_RDES_FS) &&
|
||||
!(DMARxDescToGet->CS & ETH_DMA_RDES_LS)) {
|
||||
DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
|
||||
DMA_RX_FRAME_infos->cnt = 1;
|
||||
DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
|
||||
|
||||
}
|
||||
else if ( (DMARxDescToGet->CS & ETH_DMA_RDES_FS) &&
|
||||
(DMARxDescToGet->CS & ETH_DMA_RDES_LS)) {
|
||||
DMA_RX_FRAME_infos->cnt++;
|
||||
DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
|
||||
}
|
||||
else {
|
||||
DMA_RX_FRAME_infos->ptrLS_Rx_Desc = DMARxDescToGet;
|
||||
DMA_RX_FRAME_infos->cnt++;
|
||||
|
||||
if (DMA_RX_FRAME_infos->cnt == 1)
|
||||
DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
|
||||
|
||||
frame.len = ((DMARxDescToGet->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FL_Pos) - 4;
|
||||
|
||||
frame.buf = (DMA_RX_FRAME_infos->cnt > 1) ?
|
||||
(DMA_RX_FRAME_infos->ptrFS_Rx_Desc->BUF1ADDR) :
|
||||
(DMARxDescToGet->BUF1ADDR);
|
||||
|
||||
frame.ptrDesc = DMA_RX_FRAME_infos->ptrFS_Rx_Desc;
|
||||
|
||||
DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
|
||||
|
||||
return frame;
|
||||
}
|
||||
}
|
||||
|
||||
return frame;
|
||||
}
|
||||
|
||||
u32 ETH_Prepare_Transmit_Descriptors(u16 len)
|
||||
{
|
||||
u32 cnt = 0, i = 0;
|
||||
__IO ETH_DMADESCTypeDef* temp_desc = DMATxDescToSet;
|
||||
|
||||
if (DMATxDescToSet->CS & ETH_DMA_TDES_OWN)
|
||||
return ETH_ERROR;
|
||||
|
||||
if(len > ETH_TX_BUF_SIZE) {
|
||||
cnt = len / ETH_TX_BUF_SIZE;
|
||||
|
||||
if (len % ETH_TX_BUF_SIZE)
|
||||
cnt++;
|
||||
}
|
||||
else {
|
||||
cnt = 1;
|
||||
}
|
||||
|
||||
if (cnt == 1) {
|
||||
temp_desc->BL &= ~(ETH_DMA_TDES_FS | ETH_DMA_TDES_LS | ETH_DMA_TDES_TBS1);
|
||||
|
||||
temp_desc->BL |= ETH_DMA_TDES_FS |
|
||||
ETH_DMA_TDES_LS |
|
||||
(len & ETH_DMA_TDES_TBS1);
|
||||
|
||||
temp_desc->CS |= ETH_DMA_TDES_OWN;
|
||||
temp_desc = (ETH_DMADESCTypeDef*)(temp_desc->BUF2NDADDR);
|
||||
}
|
||||
else {
|
||||
for (i = 0; i < cnt; i++) {
|
||||
temp_desc->BL &= ~(ETH_DMA_TDES_FS | ETH_DMA_TDES_LS);
|
||||
|
||||
if (i == 0)
|
||||
temp_desc->BL |= ETH_DMA_TDES_FS;
|
||||
|
||||
temp_desc->BL = ETH_TX_BUF_SIZE & ETH_DMA_TDES_TBS1;
|
||||
|
||||
if (i == (cnt - 1)) {
|
||||
temp_desc->BL &= ~ETH_DMA_TDES_TBS1;
|
||||
temp_desc->BL |= ETH_DMA_TDES_LS |
|
||||
((len - (cnt - 1) * ETH_TX_BUF_SIZE) & ETH_DMA_TDES_TBS1);
|
||||
}
|
||||
|
||||
temp_desc->CS |= ETH_DMA_TDES_OWN;
|
||||
temp_desc = (ETH_DMADESCTypeDef*)(temp_desc->BUF2NDADDR);
|
||||
}
|
||||
}
|
||||
|
||||
DMATxDescToSet = temp_desc;
|
||||
|
||||
if (ETH->DMASR & ETH_DMASR_TBUS) {
|
||||
ETH->DMASR = ETH_DMASR_TBUS;
|
||||
ETH->DMATPDR = 0;
|
||||
}
|
||||
|
||||
return ETH_SUCCESS;
|
||||
}
|
||||
|
||||
void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt)
|
||||
{
|
||||
u32 i = 0;
|
||||
ETH_DMADESCTypeDef* temp_desc;
|
||||
|
||||
DMARxDescToGet = ptr_desc;
|
||||
|
||||
for (i = 0; i < cnt; i++) {
|
||||
temp_desc = ptr_desc + i;
|
||||
temp_desc->CS = ETH_DMA_RDES_OWN;
|
||||
temp_desc->BL = ETH_DMA_RDES_RCH | ETH_RX_BUF_SIZE;
|
||||
temp_desc->BUF1ADDR = (u32)&buf[i * ETH_RX_BUF_SIZE];
|
||||
|
||||
if (i < cnt - 1) {
|
||||
temp_desc->BUF2NDADDR = (u32)(ptr_desc + i + 1);
|
||||
}
|
||||
else {
|
||||
temp_desc->BUF2NDADDR = (u32)(ptr_desc);
|
||||
}
|
||||
}
|
||||
|
||||
ETH->DMARDLAR = (u32)ptr_desc;
|
||||
|
||||
DMA_RX_FRAME_infos = &RX_Frame_Descriptor;
|
||||
}
|
||||
|
||||
u32 ETH_CheckFrameReceived(void)
|
||||
{
|
||||
if(!(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) &&
|
||||
(DMARxDescToGet->CS & ETH_DMA_RDES_LS)) {
|
||||
|
||||
DMA_RX_FRAME_infos->cnt++;
|
||||
|
||||
if (DMA_RX_FRAME_infos->cnt == 1) {
|
||||
DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
|
||||
}
|
||||
DMA_RX_FRAME_infos->ptrLS_Rx_Desc = DMARxDescToGet;
|
||||
return 1;
|
||||
}
|
||||
else if ( !(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) &&
|
||||
!(DMARxDescToGet->CS & ETH_DMA_RDES_LS) &&
|
||||
(DMARxDescToGet->CS & ETH_DMA_RDES_FS)) {
|
||||
DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
|
||||
DMA_RX_FRAME_infos->ptrLS_Rx_Desc = (void*)0;
|
||||
DMA_RX_FRAME_infos->cnt = 1;
|
||||
}
|
||||
else if ( !(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) &&
|
||||
!(DMARxDescToGet->CS & ETH_DMA_RDES_LS) &&
|
||||
!(DMARxDescToGet->CS & ETH_DMA_RDES_FS)) {
|
||||
DMA_RX_FRAME_infos->cnt++;
|
||||
DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt)
|
||||
{
|
||||
u32 i = 0;
|
||||
ETH_DMADESCTypeDef* temp_desc;
|
||||
|
||||
DMATxDescToSet = ptr_desc;
|
||||
|
||||
for (i = 0; i < cnt; i++) {
|
||||
temp_desc = ptr_desc + i;
|
||||
temp_desc->BL = ETH_DMA_TDES_TCH;
|
||||
temp_desc->BUF1ADDR = (u32)(&buf[i * ETH_TX_BUF_SIZE]);
|
||||
|
||||
if (i < cnt - 1) {
|
||||
temp_desc->BUF2NDADDR = (u32)(ptr_desc + i + 1);
|
||||
}
|
||||
else {
|
||||
temp_desc->BUF2NDADDR = (u32)(ptr_desc);
|
||||
}
|
||||
}
|
||||
|
||||
ETH->DMATDLAR = (u32)ptr_desc;
|
||||
}
|
||||
|
||||
FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag)
|
||||
{
|
||||
return (FlagStatus)(ptr_desc->CS & flag);
|
||||
}
|
||||
|
||||
u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef* ptr_desc)
|
||||
{
|
||||
return (ptr_desc->CS & ETH_DMA_TDES_CC) >> ETH_DMA_TDES_COLLISION_COUNTSHIFT;
|
||||
}
|
||||
|
||||
void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc)
|
||||
{
|
||||
ptr_desc->CS |= ETH_DMA_TDES_OWN;
|
||||
}
|
||||
|
||||
void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
|
||||
{
|
||||
sta ? (ptr_desc->BL |= ETH_DMA_TDES_IC) : (ptr_desc->BL &= ~ETH_DMA_TDES_IC);
|
||||
}
|
||||
|
||||
void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val)
|
||||
{
|
||||
ptr_desc->CS |= val;
|
||||
}
|
||||
|
||||
void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val)
|
||||
{
|
||||
ptr_desc->CS |= val;
|
||||
}
|
||||
|
||||
void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
|
||||
{
|
||||
sta ? (ptr_desc->BL &= ~ETH_DMA_TDES_DC) : (ptr_desc->BL |= ETH_DMA_TDES_DC);
|
||||
}
|
||||
|
||||
void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
|
||||
{
|
||||
sta ? (ptr_desc->BL |= ETH_DMA_TDES_TCH) : (ptr_desc->BL &= ~ETH_DMA_TDES_TCH);
|
||||
}
|
||||
|
||||
void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
|
||||
{
|
||||
sta ? (ptr_desc->BL &= ~ETH_DMA_TDES_DP) : (ptr_desc->BL |= ETH_DMA_TDES_DP);
|
||||
}
|
||||
|
||||
void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef* ptr_desc, u32 buf1_size, u32 buf2_size)
|
||||
{
|
||||
ptr_desc->BL |= buf1_size | (buf2_size << ETH_DMA_TDES_BUFFER2_SIZESHIFT);
|
||||
}
|
||||
|
||||
FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag)
|
||||
{
|
||||
return (FlagStatus)(ptr_desc->CS & flag);
|
||||
}
|
||||
|
||||
void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc)
|
||||
{
|
||||
ptr_desc->CS |= ETH_DMA_RDES_OWN;
|
||||
}
|
||||
|
||||
u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef* ptr_desc)
|
||||
{
|
||||
return (ptr_desc->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FRAME_LENGTHSHIFT;
|
||||
}
|
||||
|
||||
void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
|
||||
{
|
||||
sta ? (ptr_desc->CS &= ~ETH_DMA_RDES_DIC) : (ptr_desc->CS |= ETH_DMA_RDES_DIC);
|
||||
}
|
||||
|
||||
u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef* ptr_desc, u32 buf)
|
||||
{
|
||||
return (buf != ETH_DMA_RDES_Buffer1 ?
|
||||
((ptr_desc->BL & ETH_DMA_RDES_RBS2) >> ETH_DMA_RDES_BUFFER2_SIZESHIFT) :
|
||||
(ptr_desc->BL & ETH_DMA_RDES_RBS1));
|
||||
}
|
||||
|
||||
u32 ETH_GetRxPktSize(ETH_DMADESCTypeDef* ptr_desc)
|
||||
{
|
||||
u32 len = 0;
|
||||
|
||||
if ( !(ptr_desc->CS & ETH_DMA_RDES_OWN) &&
|
||||
!(ptr_desc->CS & ETH_DMA_RDES_ES) &&
|
||||
(ptr_desc->CS & ETH_DMA_RDES_LS)) {
|
||||
len = ETH_GetDMARxDescFrameLength(ptr_desc);
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void ETH_SoftwareReset(void)
|
||||
{
|
||||
ETH->DMABMR |= ETH_DMABMR_SR;
|
||||
}
|
||||
|
||||
FlagStatus ETH_GetSoftwareResetStatus(void)
|
||||
{
|
||||
return (FlagStatus)(ETH->DMABMR & ETH_DMABMR_SR);
|
||||
}
|
||||
|
||||
FlagStatus ETH_GetDMAFlagStatus(u32 flag)
|
||||
{
|
||||
return (FlagStatus)(ETH->DMASR & flag);
|
||||
}
|
||||
|
||||
void ETH_DMAClearFlag(u32 flag)
|
||||
{
|
||||
ETH->DMASR = flag;
|
||||
}
|
||||
|
||||
void ETH_DMAITConfig(u32 it, FunctionalState sta)
|
||||
{
|
||||
sta ? (ETH->DMAIER |= it) : (ETH->DMAIER &= ~it);
|
||||
}
|
||||
|
||||
ITStatus ETH_GetDMAITStatus(u32 it)
|
||||
{
|
||||
return (ITStatus)(ETH->DMASR & it);
|
||||
}
|
||||
|
||||
void ETH_DMAClearITPendingBit(u32 it)
|
||||
{
|
||||
ETH->DMASR = it;
|
||||
}
|
||||
|
||||
u32 ETH_GetTransmitProcessState(void)
|
||||
{
|
||||
return ETH->DMASR & ETH_DMASR_TS;
|
||||
}
|
||||
|
||||
u32 ETH_GetReceiveProcessState(void)
|
||||
{
|
||||
return ETH->DMASR & ETH_DMASR_RS;
|
||||
}
|
||||
|
||||
void ETH_FlushTransmitFIFO(void)
|
||||
{
|
||||
ETH->DMAOMR |= ETH_DMAOMR_FTF;
|
||||
}
|
||||
|
||||
FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
|
||||
{
|
||||
return (FlagStatus)(ETH->DMAOMR & ETH_DMAOMR_FTF);
|
||||
}
|
||||
|
||||
void ETH_DMATransmissionCmd(FunctionalState sta)
|
||||
{
|
||||
sta ? (ETH->DMAOMR |= ETH_DMAOMR_ST) : (ETH->DMAOMR &= ~ETH_DMAOMR_ST);
|
||||
}
|
||||
|
||||
void ETH_DMAReceptionCmd(FunctionalState sta)
|
||||
{
|
||||
sta ? (ETH->DMAOMR |= ETH_DMAOMR_SR) : (ETH->DMAOMR &= ~ETH_DMAOMR_SR);
|
||||
}
|
||||
|
||||
FlagStatus ETH_GetDMAOverflowStatus(u32 val)
|
||||
{
|
||||
return (FlagStatus)(ETH->DMAMFBOCR & val);
|
||||
}
|
||||
|
||||
u32 ETH_GetRxOverflowMissedFrameCounter(void)
|
||||
{
|
||||
return (ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA) >>
|
||||
ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT;
|
||||
}
|
||||
|
||||
u32 ETH_GetBufferUnavailableMissedFrameCounter(void)
|
||||
{
|
||||
return ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFC;
|
||||
}
|
||||
|
||||
u32 ETH_GetCurrentTxDescStartAddress(void)
|
||||
{
|
||||
return ETH->DMACHTDR;
|
||||
}
|
||||
|
||||
u32 ETH_GetCurrentRxDescStartAddress(void)
|
||||
{
|
||||
return ETH->DMACHRDR;
|
||||
}
|
||||
|
||||
u32 ETH_GetCurrentTxBufferAddress(void)
|
||||
{
|
||||
return ETH->DMACHTBAR;
|
||||
}
|
||||
|
||||
u32 ETH_GetCurrentRxBufferAddress(void)
|
||||
{
|
||||
return ETH->DMACHRBAR;
|
||||
}
|
||||
|
||||
void ETH_ResumeDMATransmission(void)
|
||||
{
|
||||
ETH->DMATPDR = 0;
|
||||
}
|
||||
|
||||
void ETH_ResumeDMAReception(void)
|
||||
{
|
||||
ETH->DMARPDR = 0;
|
||||
}
|
||||
|
||||
void ETH_SetReceiveWatchdogTimer(u8 val)
|
||||
{
|
||||
ETH->DMARSWTR = val;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u16 ETH_ReadPHYRegister(u16 addr, u16 reg)
|
||||
{
|
||||
u32 dat;
|
||||
// Set phy address and reg address, clear write flag
|
||||
ETH->MACMIIAR = (((ETH->MACMIIAR & ~MACMIIAR_CR_MASK) |
|
||||
(addr << ETH_MACMIIAR_PA_Pos & ETH_MACMIIAR_PA) |
|
||||
(reg << ETH_MACMIIAR_MR_Pos & ETH_MACMIIAR_MR)) &
|
||||
(~ETH_MACMIIAR_MW)) | ETH_MACMIIAR_MB;
|
||||
|
||||
// Check busy flag
|
||||
while(ETH->MACMIIAR & ETH_MACMIIAR_MB);
|
||||
dat = (u16)ETH->MACMIIDR;
|
||||
if(dat == 0xFFFF) {
|
||||
dat = 0;
|
||||
}
|
||||
return dat;
|
||||
}
|
||||
|
||||
u16 ETH_WritePHYRegister(u16 addr, u16 reg, u16 val)
|
||||
{
|
||||
// Load data
|
||||
ETH->MACMIIDR = val;
|
||||
|
||||
// Set phy address, reg address and write flag
|
||||
ETH->MACMIIAR = (ETH->MACMIIAR & ~MACMIIAR_CR_MASK) |
|
||||
(addr << ETH_MACMIIAR_PA_Pos & ETH_MACMIIAR_PA) |
|
||||
(reg << ETH_MACMIIAR_MR_Pos & ETH_MACMIIAR_MR) |
|
||||
ETH_MACMIIAR_MW |
|
||||
ETH_MACMIIAR_MB;
|
||||
|
||||
// Check busy flag
|
||||
while(ETH->MACMIIAR & ETH_MACMIIAR_MB);
|
||||
|
||||
return ETH->MACMIIDR;
|
||||
}
|
||||
|
||||
u32 ETH_PHYLoopBackCmd(u16 addr, FunctionalState sta)
|
||||
{
|
||||
u16 temp_val = ETH_ReadPHYRegister(addr, PHY_BCR);
|
||||
|
||||
sta ? (temp_val |= PHY_Loopback) : (temp_val &= ~PHY_Loopback);
|
||||
|
||||
if(ETH_WritePHYRegister(addr, PHY_BCR, temp_val))
|
||||
return ETH_SUCCESS;
|
||||
|
||||
return ETH_ERROR;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
|
||||
{
|
||||
ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;
|
||||
}
|
||||
|
||||
void ETH_SetWakeUpFrameFilterRegister(u32* buf)
|
||||
{
|
||||
u32 i = 0;
|
||||
|
||||
for (i = 0; i < ETH_WAKEUP_REGISTER_LENGTH; i++) {
|
||||
ETH->MACRWUFFR = buf[i];
|
||||
}
|
||||
}
|
||||
|
||||
void ETH_GlobalUnicastWakeUpCmd(FunctionalState sta)
|
||||
{
|
||||
sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_GU) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU);
|
||||
}
|
||||
|
||||
FlagStatus ETH_GetPMTFlagStatus(u32 flag)
|
||||
{
|
||||
return (FlagStatus)(ETH->MACPMTCSR & flag);
|
||||
}
|
||||
|
||||
void ETH_WakeUpFrameDetectionCmd(FunctionalState sta)
|
||||
{
|
||||
sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE);
|
||||
}
|
||||
|
||||
void ETH_MagicPacketDetectionCmd(FunctionalState sta)
|
||||
{
|
||||
sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE);
|
||||
}
|
||||
|
||||
void ETH_PowerDownCmd(FunctionalState sta)
|
||||
{
|
||||
sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_PD) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
void ETH_MMCCounterFullPreset(void)
|
||||
{
|
||||
ETH->MMCCR |= ETH_MMCCR_MCFHP | ETH_MMCCR_MCP;
|
||||
}
|
||||
|
||||
void ETH_MMCCounterHalfPreset(void)
|
||||
{
|
||||
ETH->MMCCR &= ~ETH_MMCCR_MCFHP;
|
||||
|
||||
ETH->MMCCR |= ETH_MMCCR_MCP;
|
||||
}
|
||||
|
||||
void ETH_MMCCounterFreezeCmd(FunctionalState sta)
|
||||
{
|
||||
sta ? (ETH->MMCCR |= ETH_MMCCR_MCF) : (ETH->MMCCR &= ~ETH_MMCCR_MCF);
|
||||
}
|
||||
|
||||
void ETH_MMCResetOnReadCmd(FunctionalState sta)
|
||||
{
|
||||
sta ? (ETH->MMCCR |= ETH_MMCCR_ROR) : (ETH->MMCCR &= ~ETH_MMCCR_ROR);
|
||||
}
|
||||
|
||||
void ETH_MMCCounterRolloverCmd(FunctionalState sta)
|
||||
{
|
||||
sta ? (ETH->MMCCR &= ~ETH_MMCCR_CSR) : (ETH->MMCCR |= ETH_MMCCR_CSR);
|
||||
}
|
||||
|
||||
void ETH_MMCCountersReset(void)
|
||||
{
|
||||
ETH->MMCCR |= ETH_MMCCR_CR;
|
||||
}
|
||||
|
||||
void ETH_MMCITConfig(u32 it, FunctionalState sta)
|
||||
{
|
||||
if (it & 0x10000000) {
|
||||
it &= 0xEFFFFFFF;
|
||||
|
||||
sta ? (ETH->MMCRIMR &= ~it) : (ETH->MMCRIMR |= it);
|
||||
}
|
||||
else {
|
||||
sta ? (ETH->MMCTIMR &= ~it) : (ETH->MMCTIMR |= it);
|
||||
}
|
||||
}
|
||||
|
||||
ITStatus ETH_GetMMCITStatus(u32 it)
|
||||
{
|
||||
if (it & 0x10000000) {
|
||||
return (ITStatus)((ETH->MMCRIR & it) && !(ETH->MMCRIMR & it));
|
||||
}
|
||||
else {
|
||||
return (ITStatus)((ETH->MMCTIR & it) && !(ETH->MMCTIMR & it));
|
||||
}
|
||||
}
|
||||
|
||||
u32 ETH_GetMMCRegister(u32 reg)
|
||||
{
|
||||
return *(vu32*)(ETH_BASE + reg);
|
||||
}
|
||||
@@ -0,0 +1,222 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_exti.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE EXTI FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_EXTI_C_
|
||||
|
||||
// Files includes
|
||||
#include "hal_exti.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup EXTI_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup EXTI_Exported_Functions
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Deinitializes the EXTI peripheral registers to their default reset
|
||||
/// values.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Deinitializes the EXTI registers to their default reset values.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
/// @note MEM_MODE bits are not affected by APB reset.
|
||||
/// @note MEM_MODE bits took the value from the user option bytes.
|
||||
/// @note CFGR2 register is not affected by APB reset.
|
||||
/// @note CLABBB configuration bits are locked when set.
|
||||
/// @note To unlock the configuration, perform a system reset.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void EXTI_DeInit(void)
|
||||
{
|
||||
u16 i;
|
||||
// Clear all
|
||||
exEXTI_LineDisable(~0x00000000);
|
||||
|
||||
// rc_w1
|
||||
EXTI->PR = EXTI->PR;
|
||||
|
||||
// Set EXTI_CFGR1 register to reset value without affecting MEM_MODE bits
|
||||
EXTI->CFGR &= EXTI_CFGR_MEMMODE;
|
||||
|
||||
// Set EXTICRx registers to reset value
|
||||
for (i = 0; i < 4; i++) {
|
||||
EXTI->CR[i] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Selects the GPIO pin used as EXTI Line.
|
||||
/// @param port_source_gpio: selects the GPIO port to be used as source for EXTI lines .
|
||||
/// @param pin_source: specifies the EXTI line to be configured.
|
||||
/// @note This parameter can be pin_source where x can be:
|
||||
/// For MCU: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOD.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void EXTI_LineConfig(u8 port_source_gpio, u8 pin_source)
|
||||
{
|
||||
EXTI->CR[pin_source >> 0x02] &= ~(0x0F << (0x04 * (pin_source & 0x03)));
|
||||
EXTI->CR[pin_source >> 0x02] |= ((port_source_gpio) << (0x04 * (pin_source & 0x03)));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Initializes the EXTI peripheral according to the specified
|
||||
/// parameters in the init_struct.
|
||||
/// @param init_struct: pointer to a EXTI_InitTypeDef structure that
|
||||
/// contains the configuration information for the EXTI peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void EXTI_Init(EXTI_InitTypeDef* init_struct)
|
||||
{
|
||||
if (init_struct->EXTI_LineCmd != DISABLE) {
|
||||
EXTI->IMR &= ~init_struct->EXTI_Line;
|
||||
EXTI->EMR &= ~init_struct->EXTI_Line;
|
||||
if (init_struct->EXTI_Mode == EXTI_Mode_Interrupt) {
|
||||
EXTI->IMR |= init_struct->EXTI_Line;
|
||||
}
|
||||
else {
|
||||
EXTI->EMR |= init_struct->EXTI_Line;
|
||||
}
|
||||
EXTI->RTSR &= ~init_struct->EXTI_Line;
|
||||
EXTI->FTSR &= ~init_struct->EXTI_Line;
|
||||
if (init_struct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) {
|
||||
EXTI->RTSR |= init_struct->EXTI_Line;
|
||||
EXTI->FTSR |= init_struct->EXTI_Line; // Rising and Faling afio
|
||||
}
|
||||
else if (init_struct->EXTI_Trigger == EXTI_Trigger_Rising) {
|
||||
EXTI->RTSR |= init_struct->EXTI_Line;
|
||||
}
|
||||
else {
|
||||
EXTI->FTSR |= init_struct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
else {
|
||||
if (init_struct->EXTI_Mode == EXTI_Mode_Interrupt) {
|
||||
EXTI->IMR &= ~init_struct->EXTI_Line;
|
||||
}
|
||||
else {
|
||||
EXTI->EMR &= ~init_struct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Fills each init_struct member with its reset value.
|
||||
/// @param init_struct: pointer to a EXTI_InitTypeDef structure which will
|
||||
/// be initialized.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* init_struct)
|
||||
{
|
||||
init_struct->EXTI_Line = EXTI_LineNone;
|
||||
init_struct->EXTI_Mode = EXTI_Mode_Interrupt;
|
||||
init_struct->EXTI_Trigger = EXTI_Trigger_Falling;
|
||||
init_struct->EXTI_LineCmd = DISABLE;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Generates a Software interrupt on selected EXTI line.
|
||||
/// @param line: specifies the EXTI line on which the software interrupt
|
||||
/// will be generated.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void EXTI_GenerateSWInterrupt(u32 line)
|
||||
{
|
||||
EXTI->SWIER |= line;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified EXTI line flag is set or not.
|
||||
/// @param line: specifies the EXTI line flag to check.
|
||||
/// @retval The new state of line (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus EXTI_GetFlagStatus(u32 line)
|
||||
{
|
||||
return (EXTI->PR & line) ? SET : RESET;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the EXTI's line pending flags.
|
||||
/// @param line: specifies the EXTI lines flags to clear.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void EXTI_ClearFlag(u32 line)
|
||||
{
|
||||
EXTI->PR = line;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified EXTI line is asserted or not.
|
||||
/// @param line: specifies the EXTI line to check.
|
||||
/// @retval The new state of line (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
ITStatus EXTI_GetITStatus(u32 line)
|
||||
{
|
||||
return ((EXTI->PR & line) && (EXTI->IMR & line)) ? SET : RESET;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the EXTI's line pending bits.
|
||||
/// @param line: specifies the EXTI lines to clear.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void EXTI_ClearITPendingBit(u32 line)
|
||||
{
|
||||
EXTI->PR = line;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief EXTI Line Disable
|
||||
/// @param line: specifies the EXTI lines to clear.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exEXTI_LineDisable(u32 line)
|
||||
{
|
||||
EXTI->IMR &= ~line;
|
||||
EXTI->EMR &= ~line;
|
||||
EXTI->RTSR &= ~line;
|
||||
EXTI->FTSR &= ~line;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the EXTI's line all pending bits.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 exEXTI_GetAllFlagStatus(void)
|
||||
{
|
||||
return EXTI->PR;
|
||||
}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
@@ -0,0 +1,548 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_flash.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE FLASH FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_FLASH_C_
|
||||
|
||||
// Files includes
|
||||
#include "hal_flash.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup FLASH_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup FLASH_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Sets the code latency value.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param latency: specifies the FLASH Latency value.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg FLASH_Latency_0: FLASH Zero Latency cycle
|
||||
/// @arg FLASH_Latency_1: FLASH One Latency cycle
|
||||
/// @arg FLASH_Latency_2: FLASH Two Latency cycles
|
||||
/// @arg FLASH_Latency_3: FLASH Three Latency cycles
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void FLASH_SetLatency(FLASH_Latency_TypeDef latency)
|
||||
{
|
||||
FLASH->ACR = (FLASH->ACR & (~FLASH_ACR_LATENCY)) | latency;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the Half cycle flash access.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param half_cycle_access: specifies the FLASH Half cycle Access mode.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
|
||||
/// @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void FLASH_HalfCycleAccessCmd(FLASH_HalfCycleAccess_TypeDef half_cycle_access)
|
||||
{
|
||||
FLASH->ACR &= ~FLASH_ACR_HLFCYA;
|
||||
FLASH->ACR |= half_cycle_access;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the Prefetch Buffer.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param prefetch_buffer: specifies the Prefetch buffer status.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
|
||||
/// @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_TypeDef prefetch_buffer)
|
||||
{
|
||||
FLASH->ACR &= ~FLASH_ACR_PRFTBE;
|
||||
FLASH->ACR |= prefetch_buffer;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Locks the FLASH Program Erase Controller.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void FLASH_Lock(void)
|
||||
{
|
||||
FLASH->CR |= FLASH_CR_LOCK;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Unlocks the FLASH Program Erase Controller.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void FLASH_Unlock()
|
||||
{
|
||||
FLASH->KEYR = FLASH_KEY1;
|
||||
FLASH->KEYR = FLASH_KEY2;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enable to program the FLASH Option Byte.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void FLASH_OPTB_Enable(void)
|
||||
{
|
||||
FLASH->OPTKEYR = FLASH_KEY1;
|
||||
FLASH->OPTKEYR = FLASH_KEY2;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Erases a specified FLASH page.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param page_address: The page address to be erased.
|
||||
/// @retval FLASH Status: The returned value can be: FLASH_BUSY,
|
||||
/// FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FLASH_Status FLASH_ErasePage(u32 page_address)
|
||||
{
|
||||
FLASH->CR |= FLASH_CR_PER;
|
||||
FLASH->AR = page_address;
|
||||
FLASH->CR |= FLASH_CR_STRT;
|
||||
return FLASH_WaitForLastOperation(EraseTimeout);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Erases all FLASH pages.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param None.
|
||||
/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
|
||||
/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FLASH_Status FLASH_EraseAllPages()
|
||||
{
|
||||
FLASH->AR = FLASH_BASE;
|
||||
FLASH->CR |= (FLASH_CR_MER | FLASH_CR_STRT);
|
||||
return FLASH_WaitForLastOperation(EraseTimeout);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Erases the FLASH option bytes.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param None.
|
||||
/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
|
||||
/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FLASH_Status FLASH_EraseOptionBytes()
|
||||
{
|
||||
FLASH_OPTB_Enable();
|
||||
FLASH->AR = OB_BASE;
|
||||
FLASH->CR |= (FLASH_CR_OPTER | FLASH_CR_STRT);
|
||||
return FLASH_WaitForLastOperation(EraseTimeout);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Programs a half word at a specified address.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param address: specifies the address to be programmed.
|
||||
/// @param data: specifies the data to be programmed.
|
||||
/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
|
||||
/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FLASH_Status FLASH_ProgramHalfWord(u32 address, u16 data)
|
||||
{
|
||||
FLASH->CR |= FLASH_CR_PG;
|
||||
|
||||
*(vu16*)address = data;
|
||||
|
||||
|
||||
return FLASH_WaitForLastOperation(ProgramTimeout);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Programs a word at a specified address.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param address: specifies the address to be programmed.
|
||||
/// @param data: specifies the data to be programmed.
|
||||
/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
|
||||
/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FLASH_Status FLASH_ProgramWord(u32 address, u32 data)
|
||||
{
|
||||
FLASH_Status ret = FLASH_ProgramHalfWord(address, data);
|
||||
if (ret == FLASH_COMPLETE) {
|
||||
ret = FLASH_ProgramHalfWord(address + 2, data >> 16);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Programs a byte at a specified Option Byte Data address.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param address: specifies the address to be programmed.
|
||||
/// This parameter can be 0x1FFFF804 or 0x1FFFF806.
|
||||
/// @param data: specifies the data to be programmed.
|
||||
/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
|
||||
/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FLASH_Status FLASH_ProgramOptionByteData(u32 address, u8 data)
|
||||
{
|
||||
FLASH_Status ret;
|
||||
__IO u16 temp;
|
||||
FLASH_OPTB_Enable();
|
||||
FLASH->CR |= FLASH_CR_OPTPG;
|
||||
temp = (u16)(~data);
|
||||
temp = (temp << 8) & 0xFF00;
|
||||
temp = temp | (u16)data;
|
||||
address = address & (~0x1);
|
||||
*(vu16*)address = temp;
|
||||
ret = FLASH_WaitForLastOperation(ProgramTimeout);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Programs a half word at a specified Option Byte Data address.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param address: specifies the address to be programmed.
|
||||
/// This parameter can be 0x1FFFF804 or 0x1FFFF806.
|
||||
/// @param data: specifies the data to be programmed.
|
||||
/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
|
||||
/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FLASH_Status FLASH_ProgramOptionHalfWord(u32 address, u16 data)
|
||||
{
|
||||
FLASH_Status ret;
|
||||
FLASH_OPTB_Enable();
|
||||
FLASH->CR |= FLASH_CR_OPTPG;
|
||||
*(vu16*)address = data;
|
||||
ret = FLASH_WaitForLastOperation(ProgramTimeout);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Read protection for the specified address
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FLASH_Status FLASH_ProgramProtect(u32 address, u16 data)
|
||||
{
|
||||
return FLASH_ProgramOptionHalfWord(address, data);
|
||||
|
||||
// FLASH_Status ret;
|
||||
// ret = FLASH_ProgramOptionHalfWord(address, 0x7F80);
|
||||
//
|
||||
// if (ret == FLASH_COMPLETE) {
|
||||
// ret = FLASH_ProgramOptionHalfWord(address + 2, 0xFF00);
|
||||
// }
|
||||
// return ret;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Write protection for the specified address
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param page: specifies the address of the pages to be write
|
||||
/// protected.
|
||||
/// This parameter is (0x01 << ((Absolute address - 0x08000000)/0x1000))
|
||||
/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
|
||||
/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FLASH_Status FLASH_EnableWriteProtection(u32 page)
|
||||
{
|
||||
FLASH_Status ret;
|
||||
u8 i;
|
||||
for (i = 0; i < 4; i++) {
|
||||
ret = FLASH_ProgramOptionHalfWord((OB_BASE + 8 + i * 2), ~(page >> (i * 8)));
|
||||
if (ret != FLASH_COMPLETE) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param ob_iwdg: Selects the IWDG mode
|
||||
/// @param ob_stop: Reset event when entering STOP mode.
|
||||
/// @param standby: Reset event when entering Standby mode.
|
||||
/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
|
||||
/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FLASH_Status FLASH_UserOptionByteConfig(OB_IWDG_TypeDef ob_iwdg, OB_STOP_TypeDef ob_stop, OB_STDBY_TypeDef standby)
|
||||
{
|
||||
FLASH_OPTB_Enable();
|
||||
FLASH->CR |= FLASH_CR_OPTPG;
|
||||
OB->USER = ob_iwdg;
|
||||
OB->USER |= ob_stop;
|
||||
OB->USER |= standby;
|
||||
OB->USER |= 0xF8;
|
||||
// OB->USER = iwdg | stop | stdby | 0xF8;
|
||||
return FLASH_WaitForLastOperation(ProgramTimeout);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the FLASH User Option Bytes values.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param None.
|
||||
/// @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
|
||||
/// and RST_STDBY(Bit2).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 FLASH_GetUserOptionByte()
|
||||
{
|
||||
return (FLASH->OBR >> 2);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the FLASH Write Protection Option Bytes Register value.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param None.
|
||||
/// @retval The FLASH Write Protection Option Bytes Register value.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 FLASH_GetWriteProtectionOptionByte()
|
||||
{
|
||||
return (FLASH->WRPR);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the FLASH Prefetch Buffer status is set or not.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param None.
|
||||
/// @retval FLASH Prefetch Buffer Status (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus FLASH_GetPrefetchBufferStatus(void)
|
||||
{
|
||||
return (FLASH->ACR & FLASH_ACR_PRFTBS) ? SET : RESET;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified FLASH interrupts.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param interrupt: specifies the FLASH interrupt sources to be enabled or
|
||||
/// disabled.
|
||||
/// @param state: new state of the specified Flash interrupts.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void FLASH_ITConfig(FLASH_IT_TypeDef interrupt, FunctionalState state)
|
||||
{
|
||||
(state) ? (FLASH->CR |= interrupt) : (FLASH->CR &= ~interrupt);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified FLASH flag is set or not.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param flag: specifies the FLASH flags to clear.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg FLASH_FLAG_BSY: FLASH Busy flag
|
||||
/// @arg FLASH_FLAG_PGERR: FLASH Program error flag
|
||||
/// @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
|
||||
/// @arg FLASH_FLAG_EOP: FLASH End of Operation flag
|
||||
/// @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag
|
||||
/// @retval The new state of FLASH_FLAG (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus FLASH_GetFlagStatus(u16 flag)
|
||||
{
|
||||
return ((flag == FLASH_FLAG_OPTERR) ? (FLASH->OBR & FLASH_FLAG_OPTERR) : (FLASH->SR & flag)) ? SET : RESET;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the FLASH's pending flags.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param flag: specifies the FLASH flags to clear.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @arg FLASH_FLAG_PGERR: FLASH Program error flag
|
||||
/// @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
|
||||
/// @arg FLASH_FLAG_EOP: FLASH End of Operation flag
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void FLASH_ClearFlag(u16 flag)
|
||||
{
|
||||
FLASH->SR = flag;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the FLASH Status.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param None.
|
||||
/// @retval FLASH Status: The returned value can be: FLASH_BUSY,
|
||||
/// FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FLASH_Status FLASH_GetStatus()
|
||||
{
|
||||
return (FLASH_Status)((FLASH->SR & FLASH_FLAG_BSY))
|
||||
? FLASH_BUSY
|
||||
: ((FLASH->SR & FLASH_FLAG_PGERR) ? FLASH_ERROR_PG
|
||||
: ((FLASH->SR & FLASH_FLAG_WRPRTERR) ? FLASH_ERROR_WRP : FLASH_COMPLETE));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Waits for a Flash operation to complete or a TIMEOUT to occur.
|
||||
/// @note This function can be used for all MM32 devices
|
||||
/// @param time_out: FLASH programming time_out
|
||||
/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
|
||||
/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FLASH_Status FLASH_WaitForLastOperation(u32 time_out)
|
||||
{
|
||||
u32 i;
|
||||
FLASH_Status ret;
|
||||
do {
|
||||
ret = FLASH_GetStatus();
|
||||
time_out--;
|
||||
for (i = 0xFF; i != 0; i--)
|
||||
;
|
||||
} while ((ret == FLASH_BUSY) && (time_out != 0x00));
|
||||
|
||||
FLASH->CR = 0;
|
||||
FLASH->SR = FLASH_SR_EOP | FLASH_SR_WRPRTERR | FLASH_SR_PGERR;
|
||||
return (FLASH_Status)((time_out == 0x00) ? FLASH_TIMEOUT : ret);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Erases a specified FLASH page.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param Page_Address: The page address to be erased.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exFLASH_EraseEE(u32 page_address)
|
||||
{
|
||||
FLASH_Unlock();
|
||||
FLASH_ErasePage(page_address);
|
||||
FLASH_Lock();
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Programs a buffer at a specified address.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param *buf: the pointer of the buffer to be programmed.
|
||||
/// @param addr: specifies the address to be programmed.
|
||||
/// @param len: the number of bytes in the buffer.
|
||||
/// This parameter can only be even.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exFLASH_ProgramEE(u16* buf, u32 addr, u16 len)
|
||||
{
|
||||
u16 i;
|
||||
FLASH_Unlock();
|
||||
for (i = 0; i < len / 2; i++) {
|
||||
FLASH_ProgramHalfWord(addr, *buf);
|
||||
addr += 2;
|
||||
buf++;
|
||||
}
|
||||
FLASH_Lock();
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Determine if the data that at the ptr address with the length is len
|
||||
/// is empty.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param *ptr: the pointer of the starting address.
|
||||
/// @param len: the number of bytes.
|
||||
/// This parameter can only be even.
|
||||
/// @retval 1 presents the data is empty,
|
||||
/// 0 presents the data has been written.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u8 exFLASH_FindEmpty(u16* ptr, u16 len)
|
||||
{
|
||||
u16 i;
|
||||
for (i = 0; i < (len / 2); i++) {
|
||||
if (*(ptr + i) != 0xffff)
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Locate the writable area on the specified address.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param page_address: specifies the beginning of the EEprom.
|
||||
/// The EEprom can be some continuously pages in the flash.
|
||||
/// @param len: the number of bytes to be written.
|
||||
/// This parameter can only be even.
|
||||
/// @retval the pointer of the starting address.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void* exFLASH_Locate(u32 page_address, u16 len)
|
||||
{
|
||||
u16 i;
|
||||
u16* ptr = (u16*)page_address;
|
||||
for (i = 0; i < (0x0800 / len); i++) {
|
||||
if (exFLASH_FindEmpty(ptr, len)) {
|
||||
if (i == 0)
|
||||
return 0;
|
||||
break;
|
||||
}
|
||||
ptr += len / 2;
|
||||
}
|
||||
return ptr;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Programs a buffer at a specified address.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param *buf: the pointer of the buffer to be programmed.
|
||||
/// @param page_address: specifies the beginning of the EEprom.
|
||||
/// The EEprom can be some continuously pages in the flash.
|
||||
/// @param len: the number of bytes in the buffer.
|
||||
/// This parameter can only be even.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exFLASH_WriteEE(u16* buf, u32 page_address, u16 len)
|
||||
{
|
||||
u16* ptr = exFLASH_Locate(page_address, len);
|
||||
if (ptr == 0) {
|
||||
exFLASH_EraseEE(page_address + 0x000);
|
||||
exFLASH_EraseEE(page_address + 0x400);
|
||||
exFLASH_ProgramEE(buf, page_address, len);
|
||||
}
|
||||
else {
|
||||
if (ptr == (u16*)(page_address + ((0x0400 / len) - 1) * len)) {
|
||||
exFLASH_EraseEE(page_address + 0x400);
|
||||
exFLASH_ProgramEE(buf, (u32)ptr, len);
|
||||
}
|
||||
else if (ptr == (u16*)(page_address + 0x0800)) {
|
||||
exFLASH_EraseEE(page_address + 0x000);
|
||||
exFLASH_ProgramEE(buf, (u32)page_address, len);
|
||||
}
|
||||
else {
|
||||
exFLASH_ProgramEE(buf, (u32)ptr, len);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Read the beginning address of the last written data.
|
||||
/// @note This function can be used for all MM32 devices.
|
||||
/// @param page_address: specifies the beginning of the EEprom.
|
||||
/// The EEprom can be some continuously pages in the flash.
|
||||
/// @param len: the number of bytes have been written.
|
||||
/// This parameter can only be even.
|
||||
/// @retval the beginning address of the last written data.
|
||||
/// 0 presents that this is the first time to use this as EEprom.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void* exFLASH_ReadEE(u32 page_address, u16 len)
|
||||
{
|
||||
u16* ptr = exFLASH_Locate(page_address, len);
|
||||
return (ptr == 0) ? 0 : (ptr - len / 2);
|
||||
}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
@@ -0,0 +1,124 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_fsmc.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE FSMC FIRMWARE FUNCTIONS.
|
||||
/// Interface with SRAM, PSRAM, NOR memories
|
||||
/// Interrupts and flags management
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_FSMC_C_
|
||||
|
||||
// Files includes
|
||||
#include "reg_rcc.h"
|
||||
#include "reg_syscfg.h"
|
||||
#include "hal_fsmc.h"
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup FSMC_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup FSMC_Exported_Functions
|
||||
/// @{
|
||||
|
||||
|
||||
void FSMC_NORSRAMStructInit(FSMC_InitTypeDef* init_struct)
|
||||
{
|
||||
init_struct->FSMC_Mode = FSMC_Mode_NorFlash;
|
||||
init_struct->FSMC_AddrDataMode = FSMC_AddrDataDeMUX;
|
||||
|
||||
init_struct->FSMC_TimingRegSelect = FSMC_TimingRegSelect_0;
|
||||
init_struct->FSMC_MemSize = FSMC_MemSize_64MB;
|
||||
init_struct->FSMC_MemType = FSMC_MemType_NorSRAM;
|
||||
}
|
||||
void FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef* init_struct)
|
||||
{
|
||||
|
||||
init_struct->FSMC_SMReadPipe = 0;
|
||||
init_struct->FSMC_ReadyMode = 0;
|
||||
init_struct->FSMC_WritePeriod = 0x2;
|
||||
init_struct->FSMC_WriteHoldTime = 1;
|
||||
init_struct->FSMC_AddrSetTime = 3;
|
||||
init_struct->FSMC_ReadPeriod = 0x1;
|
||||
init_struct->FSMC_DataWidth = FSMC_DataWidth_16bits;
|
||||
}
|
||||
void FSMC_NORSRAMInit(FSMC_InitTypeDef* init_struct)
|
||||
{
|
||||
SYSCFG->CFGR &= ~(SYSCFG_CFGR_FSMC_MODE | SYSCFG_CFGR_FSMC_AF_ADDR | SYSCFG_CFGR_FSMC_SYNC_EN);
|
||||
SYSCFG->CFGR |= (u32)init_struct->FSMC_Mode | \
|
||||
(u32)init_struct->FSMC_AddrDataMode;
|
||||
|
||||
FSMC->SMSKR = (u32)init_struct->FSMC_TimingRegSelect | \
|
||||
(u32)init_struct->FSMC_MemSize | \
|
||||
(u32)init_struct->FSMC_MemType;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Initialize the FSMC_NORSRAM Timing according to the specified
|
||||
/// parameters in the FSMC_NORSRAM_TimingTypeDef
|
||||
/// @param FSMC_Bank_InitStruct: Timing Pointer to NORSRAM Timing structure
|
||||
/// @param Bank: NORSRAM bank number
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_TypeDef bank)
|
||||
{
|
||||
// Set FSMC_NORSRAM device timing parameters
|
||||
if(bank == FSMC_NORSRAM_BANK0) {
|
||||
FSMC->SMTMGR_SET0 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \
|
||||
(u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \
|
||||
(u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \
|
||||
(u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \
|
||||
(u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \
|
||||
(u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
|
||||
FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET0;
|
||||
FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos;
|
||||
}
|
||||
else if(bank == FSMC_NORSRAM_BANK1) {
|
||||
FSMC->SMTMGR_SET1 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \
|
||||
(u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \
|
||||
(u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \
|
||||
(u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \
|
||||
(u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \
|
||||
(u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
|
||||
FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET1;
|
||||
FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos;
|
||||
}
|
||||
else if(bank == FSMC_NORSRAM_BANK2) {
|
||||
FSMC->SMTMGR_SET2 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \
|
||||
(u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \
|
||||
(u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \
|
||||
(u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \
|
||||
(u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \
|
||||
(u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
|
||||
FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET2;
|
||||
FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,344 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_gpio.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE GPIO FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_GPIO_C_
|
||||
|
||||
// Files includes
|
||||
#include "reg_exti.h"
|
||||
#include "hal_rcc.h"
|
||||
#include "hal_gpio.h"
|
||||
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup GPIO_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup GPIO_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Deinitializes the gpio peripheral registers to their default reset
|
||||
/// values.
|
||||
/// @param gpio: select the GPIO peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void GPIO_DeInit(GPIO_TypeDef* gpio)
|
||||
{
|
||||
switch (*(vu32*)&gpio) {
|
||||
case (u32)GPIOA:
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, DISABLE);
|
||||
break;
|
||||
case (u32)GPIOB:
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOB, DISABLE);
|
||||
break;
|
||||
case (u32)GPIOC:
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOC, DISABLE);
|
||||
break;
|
||||
case (u32)GPIOD:
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOD, DISABLE);
|
||||
break;
|
||||
case (u32)GPIOE:
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOE, DISABLE);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Deinitializes the Alternate Functions (remap, event control
|
||||
/// and EXTI configuration) registers to their default reset values.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void GPIO_AFIODeInit()
|
||||
{
|
||||
GPIOA->AFRL = 0xFFFFFFFF;
|
||||
GPIOA->AFRH = 0xF00FFFFF; // PA14:SWCLK, PA13:PSWDIO
|
||||
GPIOB->AFRL = 0xFFFFFFFF;
|
||||
GPIOB->AFRH = 0xFFFFFFFF;
|
||||
GPIOC->AFRL = 0xFFFFFFFF;
|
||||
GPIOC->AFRH = 0xFFFFFFFF;
|
||||
GPIOD->AFRL = 0xFFFFFFFF;
|
||||
GPIOD->AFRH = 0xFFFFFFFF;
|
||||
GPIOE->AFRL = 0xFFFFFFFF;
|
||||
GPIOE->AFRH = 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Initializes the gpio peripheral according to the specified
|
||||
/// parameters in the init_struct.
|
||||
/// @param gpio: select the GPIO peripheral.
|
||||
/// @param init_struct: pointer to a GPIO_InitTypeDef structure that
|
||||
/// contains the configuration information for the specified GPIO
|
||||
/// peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void GPIO_Init(GPIO_TypeDef* gpio, GPIO_InitTypeDef* init_struct)
|
||||
{
|
||||
u8 idx;
|
||||
u8 i;
|
||||
u32 tmp;
|
||||
__IO u32* reg ;
|
||||
|
||||
// 1x
|
||||
u32 dat = init_struct->GPIO_Mode & 0x0F;
|
||||
if (init_struct->GPIO_Mode & 0x10)
|
||||
dat |= init_struct->GPIO_Speed;
|
||||
|
||||
// 0x
|
||||
reg = &gpio->CRL;
|
||||
for (i = 0; i < 8; i++) {
|
||||
idx = i * 4;
|
||||
if ((init_struct->GPIO_Pin) & (1 << i)) {
|
||||
*reg = (*reg & ~(0xF << idx)) | (dat << idx);
|
||||
}
|
||||
}
|
||||
|
||||
reg = &gpio->CRH;
|
||||
tmp = init_struct->GPIO_Pin >> 8;
|
||||
for (i = 0; i < 8; i++) {
|
||||
idx = i * 4;
|
||||
if (tmp & (1 << i)) {
|
||||
*reg = (*reg & ~(0xF << idx)) | (dat << idx);
|
||||
}
|
||||
}
|
||||
|
||||
// 2x,4x
|
||||
if (init_struct->GPIO_Mode == GPIO_Mode_IPD)
|
||||
gpio->BRR |= init_struct->GPIO_Pin;
|
||||
else if (init_struct->GPIO_Mode == GPIO_Mode_IPU)
|
||||
gpio->BSRR |= init_struct->GPIO_Pin;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Fills each init_struct member with its default value.
|
||||
/// @param init_struct : pointer to a GPIO_InitTypeDef structure
|
||||
/// which will be initialized.
|
||||
/// @retval : None
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* init_struct)
|
||||
{
|
||||
// Reset GPIO init structure parameters values
|
||||
init_struct->GPIO_Pin = GPIO_Pin_All;
|
||||
init_struct->GPIO_Speed = GPIO_Speed_2MHz;
|
||||
init_struct->GPIO_Mode = GPIO_Mode_FLOATING;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Reads the input data of specified GPIO port pin.
|
||||
/// @param gpio: select the GPIO peripheral.
|
||||
/// @param pin: specifies the port pin to be read.
|
||||
/// This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
/// @retval The input port pin value.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
bool GPIO_ReadInputDataBit(GPIO_TypeDef* gpio, u16 pin)
|
||||
{
|
||||
return ((gpio->IDR & pin)) ? Bit_SET : Bit_RESET;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Reads all GPIO port pins input data.
|
||||
/// @param gpio: select the GPIO peripheral.
|
||||
/// @retval GPIO port input data value.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u16 GPIO_ReadInputData(GPIO_TypeDef* gpio)
|
||||
{
|
||||
return gpio->IDR;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Reads the output data of specified GPIO port pin.
|
||||
/// @param gpio: select the GPIO peripheral.
|
||||
/// @param pin: specifies the port bit to be read.
|
||||
/// This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
/// @retval The output port pin value.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
bool GPIO_ReadOutputDataBit(GPIO_TypeDef* gpio, u16 pin)
|
||||
{
|
||||
return (gpio->ODR & pin) ? Bit_SET : Bit_RESET;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Reads all GPIO port pins output data.
|
||||
/// @param gpio: select the GPIO peripheral.
|
||||
/// @retval GPIO port output data value.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u16 GPIO_ReadOutputData(GPIO_TypeDef* gpio)
|
||||
{
|
||||
return gpio->ODR;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Sets the selected GPIO port pin.
|
||||
/// @param gpio: where x can be (A..D) to select the GPIO peripheral.
|
||||
/// @param pin: specifies the port pins to be written.
|
||||
/// This parameter can be any combination of GPIO_Pin_x where x can be
|
||||
/// (0..15).
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void GPIO_SetBits(GPIO_TypeDef* gpio, u16 pin)
|
||||
{
|
||||
gpio->BSRR = pin;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the selected GPIO port bit.
|
||||
/// @param gpio: where x can be (A..D) to select the GPIO peripheral.
|
||||
/// @param pin: specifies the port pins to be written.
|
||||
/// This parameter can be any combination of GPIO_Pin_x where x can be
|
||||
/// (0..15).
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void GPIO_ResetBits(GPIO_TypeDef* gpio, u16 pin)
|
||||
{
|
||||
gpio->BRR = pin;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Sets or clears the selected GPIO port pin.
|
||||
/// @param gpio: select the GPIO peripheral.
|
||||
/// @param pin: specifies the port bit to be written.
|
||||
/// This parameter can be one of GPIO_Pin_x where x can be (0..15).
|
||||
/// @param value: specifies the value to be written to the selected bit.
|
||||
/// This parameter can be one of the BitAction enum values:
|
||||
/// @arg Bit_RESET: to clear the port pin
|
||||
/// @arg Bit_SET: to set the port pin
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void GPIO_WriteBit(GPIO_TypeDef* gpio, u16 pin, BitAction value)
|
||||
{
|
||||
(value) ? (gpio->BSRR = pin) : (gpio->BRR = pin);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Writes data to all GPIO port pins.
|
||||
/// @param gpio: where x can be (A..D) to select the GPIO peripheral.
|
||||
/// @param value: specifies the value to be written to the port output data
|
||||
/// register.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void GPIO_Write(GPIO_TypeDef* gpio, u16 value)
|
||||
{
|
||||
gpio->ODR = value;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Locks GPIO Pins configuration.
|
||||
/// @param gpio: to select the GPIO peripheral.
|
||||
/// @param pin: specifies the port bit to be written.
|
||||
/// This parameter can be any combination of GPIO_Pin_x where x can be
|
||||
/// (0..15).
|
||||
/// @param state: new lock state of the port pin.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void GPIO_PinLock(GPIO_TypeDef* gpio, u16 pin, FunctionalState state)
|
||||
{
|
||||
(state) ? (gpio->LCKR |= pin) : (gpio->LCKR &= ~pin);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Locks GPIO Pins configuration registers until next system reset.
|
||||
/// @param gpio: to select the GPIO peripheral.
|
||||
/// @param pin: specifies the port bit to be written.
|
||||
/// This parameter can be any combination of GPIO_Pin_x where x can be
|
||||
/// (0..15).
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* gpio, u16 pin)
|
||||
{
|
||||
gpio->LCKR = GPIO_LCKR_LCKK | pin;
|
||||
gpio->LCKR = pin;
|
||||
gpio->LCKR = GPIO_LCKR_LCKK | pin;
|
||||
gpio->LCKR;
|
||||
gpio->LCKR;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the port pin remapping.
|
||||
/// @param remap: selects the pin to remap.
|
||||
/// @param mask: the corresponding remapping mask of the remapping pin.
|
||||
/// @param state: new state of the port pin remapping.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Writes data to the specified GPIO data port.
|
||||
/// @param gpio: select the GPIO peripheral.
|
||||
/// @param pin: specifies the pin for the Alternate function.
|
||||
/// This parameter can be GPIO_PinSourcex where x can be (0..15) for
|
||||
/// GPIOA, GPIOB, GPIOD and (0..12) for GPIOC .
|
||||
/// @param alternate_function: selects the pin to used as Alternate function.
|
||||
/// This parameter can be the GPIO_AF_x where x can be (0..7).
|
||||
/// @note The pin should be used for Digital IP.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* gpio, u8 pin, u8 alternate_function)
|
||||
{
|
||||
u8 shift = (pin & 0x07) * 4;
|
||||
u32* ptr = (pin < 8) ? (u32*)&gpio->AFRL : (u32*)&gpio->AFRH;
|
||||
*ptr = (*ptr & ~(0x0F << shift)) | (alternate_function << shift);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Set the remap function and AF function of the GPIO pin.
|
||||
/// @param gpio:select the GPIO peripheral.
|
||||
/// @param pin: specifies the pin for the Alternate function.
|
||||
/// This parameter can be GPIO_Pin_x where x can be (0..15) for
|
||||
/// GPIOA, GPIOB, GPIOD and (0..12) for GPIOC .
|
||||
/// @param remap: selects the pin to remap.
|
||||
/// @param alternate_function: selects the pin to used as Alternate function.
|
||||
/// This parameter can be the GPIO_AF_x where x can be (0..7).
|
||||
/// @note The pin should be used for Digital IP.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exGPIO_PinAFConfig(GPIO_TypeDef* gpio, u16 pin, s32 remap, s8 alternate_function)
|
||||
{
|
||||
u8 i;
|
||||
u8 shift;
|
||||
u32* ptr;
|
||||
|
||||
if (alternate_function >= 0) {
|
||||
for (i = 0; i < 32; i++) {
|
||||
if (pin & 0x01) {
|
||||
pin = i;
|
||||
break;
|
||||
}
|
||||
pin >>= 1;
|
||||
}
|
||||
|
||||
shift = (pin & 0x07) * 4;
|
||||
ptr = (pin < 8) ? (u32*)&gpio->AFRL : (u32*)&gpio->AFRH;
|
||||
*ptr = (*ptr & ~(0x0F << shift)) | (alternate_function << shift);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
@@ -0,0 +1,526 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_i2c.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE I2C FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_I2C_C_
|
||||
|
||||
// Files includes
|
||||
#include "hal_i2c.h"
|
||||
#include "hal_rcc.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup I2C_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup I2C_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Deinitializes the i2c peripheral registers to their default
|
||||
/// reset values.
|
||||
/// @param i2c: where n can be 1 or 2 to select the I2C peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_DeInit(I2C_TypeDef* i2c)
|
||||
{
|
||||
switch (*(vu32*)&i2c) {
|
||||
case (u32)I2C1: // I2C1_BASE:
|
||||
exRCC_APB1PeriphReset(RCC_APB1ENR_I2C1);
|
||||
break;
|
||||
case (u32)I2C2: // I2C2_BASE:
|
||||
exRCC_APB1PeriphReset(RCC_APB1ENR_I2C2);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Initializes the i2c peripheral according to the specified
|
||||
/// parameters in the init_struct.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param init_struct: pointer to a I2C_InitTypeDef structure that
|
||||
/// contains the configuration information for the specified
|
||||
/// I2C peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_Init(I2C_TypeDef* i2c, I2C_InitTypeDef* init_struct)
|
||||
{
|
||||
u32 pclk1 = HSI_VALUE;
|
||||
u32 minSclLowTime = 0;
|
||||
u32 i2cPeriod = 0;
|
||||
u32 pclk1Period = 0;
|
||||
|
||||
|
||||
i2c->IC_ENABLE &= ~I2C_ENR_ENABLE;
|
||||
|
||||
|
||||
pclk1 = RCC_GetPCLK1Freq();
|
||||
pclk1Period = 1000000000 / pclk1;
|
||||
i2cPeriod = 1000000000 / init_struct->I2C_ClockSpeed;
|
||||
|
||||
minSclLowTime = pclk1 / init_struct->I2C_ClockSpeed ;
|
||||
i2cPeriod = 82 / pclk1Period;
|
||||
|
||||
if (init_struct->I2C_ClockSpeed <= 100000) {
|
||||
i2c->IC_SS_SCL_LCNT = (minSclLowTime - 13 - i2cPeriod) / 2;
|
||||
i2c->IC_SS_SCL_HCNT = (minSclLowTime - 13 - i2cPeriod - i2c->IC_SS_SCL_LCNT);
|
||||
}
|
||||
else {
|
||||
i2c->IC_FS_SCL_LCNT = (minSclLowTime - 13 - i2cPeriod ) / 2 + 4;
|
||||
i2c->IC_FS_SCL_HCNT = (minSclLowTime - 13 - i2c->IC_FS_SCL_LCNT - i2cPeriod);
|
||||
}
|
||||
|
||||
i2c->IC_CON &= ~(I2C_CR_EMPINT | \
|
||||
I2C_CR_SLAVEDIS | \
|
||||
I2C_CR_REPEN | \
|
||||
I2C_CR_MASTER10 | \
|
||||
I2C_CR_SLAVE10 | \
|
||||
I2C_CR_FAST | \
|
||||
I2C_CR_MASTER);
|
||||
|
||||
i2c->IC_CON = I2C_CR_EMPINT | \
|
||||
I2C_CR_REPEN | \
|
||||
((init_struct->I2C_Speed == I2C_CR_FAST) ? I2C_CR_FAST : I2C_CR_STD) | \
|
||||
((init_struct->I2C_Mode) ? I2C_CR_MASTER : 0x00);
|
||||
i2c->IC_INTR_MASK &= INTR_MASK;
|
||||
|
||||
i2c->IC_RX_TL = 0x00;
|
||||
i2c->IC_TX_TL = 0x00;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Fills each init_struct member with its default value.
|
||||
/// @param init_struct: pointer to an I2C_InitTypeDef structure
|
||||
/// which will be initialized.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_StructInit(I2C_InitTypeDef* init_struct)
|
||||
{
|
||||
init_struct->I2C_Mode = I2C_CR_MASTER;
|
||||
init_struct->I2C_OwnAddress = I2C_OWN_ADDRESS;
|
||||
init_struct->I2C_Speed = I2C_CR_STD;
|
||||
init_struct->I2C_ClockSpeed = 100000;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified I2C peripheral.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param state: new state of the i2c peripheral. This parameter
|
||||
/// can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_Cmd(I2C_TypeDef* i2c, FunctionalState state)
|
||||
{
|
||||
(state) ? (i2c->IC_ENABLE |= I2C_ENR_ENABLE) : (i2c->IC_ENABLE &= ~I2C_ENR_ENABLE);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified I2C DMA requests.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param state: new state of the I2C DMA transfer.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_DMACmd(I2C_TypeDef* i2c, FunctionalState state)
|
||||
{
|
||||
if (state) {
|
||||
if (I2C_DMA_DIR == TDMAE_SET)
|
||||
i2c->IC_DMA_CR |= TDMAE_SET;
|
||||
|
||||
else
|
||||
i2c->IC_DMA_CR |= RDMAE_SET;
|
||||
}
|
||||
else
|
||||
i2c->IC_DMA_CR &= ~(I2C_DMA_RXEN | I2C_DMA_TXEN);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Generates i2c communication START condition.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param state: new state of the I2C START condition generation.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_GenerateSTART(I2C_TypeDef* i2c, FunctionalState state)
|
||||
{
|
||||
(state) ? (i2c->IC_CON |= I2C_CR_REPEN) : (i2c->IC_CON &= ~I2C_CR_REPEN);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Generates i2c communication STOP condition.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param state: new state of the I2C STOP condition generation.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_GenerateSTOP(I2C_TypeDef* i2c, FunctionalState state)
|
||||
{
|
||||
u16 overTime = 3000;
|
||||
|
||||
i2c->IC_ENABLE |= I2C_ENR_ABORT;
|
||||
|
||||
while (i2c->IC_ENABLE & I2C_ENR_ABORT) {
|
||||
if (overTime-- == 0)
|
||||
break;
|
||||
}
|
||||
i2c->IC_CLR_TX_ABRT;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the specified I2C own address2.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param addr: specifies the 7bit I2C own address2.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_OwnAddress2Config(I2C_TypeDef* i2c, u8 addr)
|
||||
{
|
||||
MODIFY_REG(i2c->IC_TAR, (u16)I2C_TAR_ADDR, (u16)(addr >> 1));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified I2C dual addressing mode.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param state: new state of the I2C dual addressing mode.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_DualAddressCmd(I2C_TypeDef* i2c, FunctionalState state)
|
||||
{
|
||||
(state) ? (i2c->IC_TAR |= IC_TAR_ENDUAL_Set) : (i2c->IC_TAR &= IC_TAR_ENDUAL_Reset);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified I2C general call feature.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param state: new state of the I2C General call.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_GeneralCallCmd(I2C_TypeDef* i2c, FunctionalState state)
|
||||
{
|
||||
(state) ? (i2c->IC_TAR |= I2C_TAR_SPECIAL) : (i2c->IC_TAR &= ~I2C_TAR_SPECIAL);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified I2C interrupts.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param it: specifies the I2C interrupts sources to be enabled
|
||||
/// or disabled.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @arg I2C_IT_RX_UNDER : Rx Buffer is empty interrupt mask
|
||||
/// @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt mask
|
||||
/// @arg I2C_IT_RX_FULL : Rx buffer full interrupt mask
|
||||
/// @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt mask
|
||||
/// @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt mask
|
||||
/// @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt mask
|
||||
/// @arg I2C_IT_TX_ABRT : TX error interrupt mask(Master mode)
|
||||
/// @arg I2C_IT_RX_DONE : Master not ack interrupt mask(slave mode)
|
||||
/// @arg I2C_IT_ACTIVITY : I2C activity interrupt mask
|
||||
/// @arg I2C_IT_STOP_DET : stop condition interrupt mask
|
||||
/// @arg I2C_IT_START_DET : start condition interrupt mask
|
||||
/// @arg I2C_IT_GEN_CALL : a general call address and ack interrupt mask
|
||||
/// @param state: new state of the specified I2C interrupts.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_ITConfig(I2C_TypeDef* i2c, u16 it, FunctionalState state)
|
||||
{
|
||||
if (it == I2C_IT_RX_FULL)
|
||||
I2C_ReadCmd(i2c);
|
||||
(state) ? SET_BIT(i2c->IC_INTR_MASK, it) : CLEAR_BIT(i2c->IC_INTR_MASK, (u16)it);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Sends a data byte through the i2c peripheral.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param dat: Byte to be transmitted..
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_SendData(I2C_TypeDef* i2c, u8 dat)
|
||||
{
|
||||
i2c->IC_DATA_CMD = dat;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the most recent received data by the i2c peripheral.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @retval The value of the received data.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_ReadCmd(I2C_TypeDef* i2c)
|
||||
{
|
||||
i2c->IC_DATA_CMD = I2C_DR_CMD;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the most recent received data by the i2c peripheral.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @retval The value of the received data.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u8 I2C_ReceiveData(I2C_TypeDef* i2c)
|
||||
{
|
||||
I2C_CMD_DIR = 0;
|
||||
return (u8)i2c->IC_DATA_CMD;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Transmits the address byte to select the slave device.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param addr: specifies the slave address which will be transmitted
|
||||
/// @param dir: specifies whether the I2C device will be a
|
||||
/// Transmitter or a Receiver.
|
||||
/// This parameter can be one of the following values
|
||||
/// @arg I2C_Direction_Transmitter: Transmitter mode
|
||||
/// @arg I2C_Direction_Receiver: Receiver mode
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_Send7bitAddress(I2C_TypeDef* i2c, u8 addr, u8 dir)
|
||||
{
|
||||
i2c->IC_TAR = addr >> 1;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Reads the specified I2C register and returns its value.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param reg: specifies the register to read.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @retval The value of the read register.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u16 I2C_ReadRegister(I2C_TypeDef* i2c, u8 reg)
|
||||
{
|
||||
return (*(vu16*)(*((u32*)&i2c) + reg));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the last i2c Event.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @retval The last event
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 I2C_GetLastEvent(I2C_TypeDef* i2c)
|
||||
{
|
||||
return (u32)i2c->IC_RAW_INTR_STAT & FLAG_Mask;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the last i2c Event is equal to the one passed
|
||||
/// as parameter.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param event: specifies the event to be checked.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg I2C_EVENT_RX_UNDER : Rx Buffer is empty event
|
||||
/// @arg I2C_EVENT_RX_OVER : RX Buffer Overrun event
|
||||
/// @arg I2C_EVENTT_RX_FULL : Rx buffer full event
|
||||
/// @arg I2C_EVENT_TX_OVER : TX Buffer Overrun event
|
||||
/// @arg I2C_EVENT_TX_EMPTY : TX_FIFO empty event
|
||||
/// @arg I2C_EVENT_RD_REQ : I2C work as slave or master event
|
||||
/// @arg I2C_EVENT_TX_ABRT : TX error event(Master mode)
|
||||
/// @arg I2C_EVENT_RX_DONE : Master not ack event(slave mode)
|
||||
/// @arg I2C_EVENT_ACTIVITY : I2C activity event
|
||||
/// @arg I2C_EVENT_STOP_DET : stop condition event
|
||||
/// @arg I2C_EVENT_START_DET: start condition event
|
||||
/// @arg I2C_EVENT_GEN_CALL : a general call address and ack event
|
||||
/// - SUCCESS: Last event is equal to the I2C_EVENT
|
||||
/// - ERROR: Last event is different from the I2C_EVENT
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
ErrorStatus I2C_CheckEvent(I2C_TypeDef* i2c, u32 event)
|
||||
{
|
||||
if ((event == I2C_EVENT_RX_FULL) && (I2C_CMD_DIR == 0)) {
|
||||
i2c->IC_DATA_CMD = I2C_DR_CMD;
|
||||
I2C_CMD_DIR = 1;
|
||||
}
|
||||
|
||||
return (ErrorStatus)((i2c->IC_RAW_INTR_STAT & event) == event);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified I2C flag is set or not.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param flag: specifies the flag to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg I2C_FLAG_RX_UNDER : Rx Buffer is empty flag
|
||||
/// @arg I2C_FLAG_RX_OVER : RX Buffer Overrun flag
|
||||
/// @arg I2C_FLAG_RX_FULL : Rx buffer full flag
|
||||
/// @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag
|
||||
/// @arg I2C_FLAG_TX_EMPTY : TX_FIFO empty flag
|
||||
/// @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag
|
||||
/// @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode)
|
||||
/// @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode)
|
||||
/// @arg I2C_FLAG_ACTIVITY : I2C activity flag
|
||||
/// @arg I2C_FLAG_STOP_DET : stop condition flag
|
||||
/// @arg I2C_FLAG_START_DET: start condition flag
|
||||
/// @arg I2C_FLAG_GEN_CALL : a general call address and ack flag
|
||||
/// @retval The new state of I2C_FLAG (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* i2c, u32 flag)
|
||||
{
|
||||
if (flag & 0x8000)
|
||||
return ((i2c->IC_STATUS & flag) ? SET : RESET);
|
||||
|
||||
if ((flag == I2C_FLAG_RX_FULL) && (I2C_CMD_DIR == 0)) {
|
||||
i2c->IC_DATA_CMD = I2C_DR_CMD;
|
||||
I2C_CMD_DIR = 1;
|
||||
}
|
||||
return (((i2c->IC_RAW_INTR_STAT & flag)) ? SET : RESET);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the i2c's pending flags.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param flag: specifies the flag to clear.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @arg I2C_FLAG_RX_UNDER : Rx Buffer is empty flag
|
||||
/// @arg I2C_FLAG_RX_OVER : RX Buffer Overrun flag
|
||||
/// @arg I2C_FLAG_RX_FULL : Rx buffer full flag
|
||||
/// @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag
|
||||
/// @arg I2C_FLAG_TX_EMPTY : TX_FIFO empty flag
|
||||
/// @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag
|
||||
/// @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode)
|
||||
/// @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode)
|
||||
/// @arg I2C_FLAG_ACTIVITY : I2C activity flag
|
||||
/// @arg I2C_FLAG_STOP_DET : stop condition flag
|
||||
/// @arg I2C_FLAG_START_DET: start condition flag
|
||||
/// @arg I2C_FLAG_GEN_CALL : a general call address and ack flag
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_ClearFlag(I2C_TypeDef* i2c, u32 flag)
|
||||
{
|
||||
if ((flag & I2C_FLAG_RX_UNDER) == I2C_FLAG_RX_UNDER)
|
||||
i2c->IC_CLR_RX_UNDER;
|
||||
if ((flag & I2C_FLAG_RX_OVER) == I2C_FLAG_RX_OVER)
|
||||
i2c->IC_CLR_RX_OVER;
|
||||
if ((flag & I2C_FLAG_TX_OVER) == I2C_FLAG_TX_OVER)
|
||||
i2c->IC_CLR_TX_OVER;
|
||||
if ((flag & I2C_FLAG_RD_REQ) == I2C_FLAG_RD_REQ)
|
||||
i2c->IC_CLR_RD_REQ;
|
||||
if ((flag & I2C_FLAG_TX_ABRT) == I2C_FLAG_TX_ABRT)
|
||||
i2c->IC_CLR_TX_ABRT;
|
||||
if ((flag & I2C_FLAG_RX_DONE) == I2C_FLAG_RX_DONE)
|
||||
i2c->IC_CLR_RX_DONE;
|
||||
if ((flag & I2C_FLAG_ACTIVITY) == I2C_FLAG_ACTIVITY)
|
||||
i2c->IC_CLR_ACTIVITY;
|
||||
if ((flag & I2C_FLAG_STOP_DET) == I2C_FLAG_STOP_DET)
|
||||
i2c->IC_CLR_STOP_DET;
|
||||
if ((flag & I2C_FLAG_START_DET) == I2C_FLAG_START_DET)
|
||||
i2c->IC_CLR_START_DET;
|
||||
if ((flag & I2C_FLAG_GEN_CALL) == I2C_FLAG_GEN_CALL)
|
||||
i2c->IC_CLR_GEN_CALL;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified I2C interrupt has occurred or not.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param it: specifies the interrupt source to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg I2C_IT_RX_UNDER : Rx Buffer is empty interrupt
|
||||
/// @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt
|
||||
/// @arg I2C_IT_RX_FULL : Rx buffer full interrupt
|
||||
/// @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt
|
||||
/// @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
|
||||
/// @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt
|
||||
/// @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode)
|
||||
/// @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode)
|
||||
/// @arg I2C_IT_ACTIVITY : I2C activity interrupt
|
||||
/// @arg I2C_IT_STOP_DET : stop condition interrupt
|
||||
/// @arg I2C_IT_START_DET: start condition interrupt
|
||||
/// @arg I2C_IT_GEN_CALL : a general call address and ack interrupt
|
||||
/// @retval The new state of I2C_IT (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
ITStatus I2C_GetITStatus(I2C_TypeDef* i2c, u32 it)
|
||||
{
|
||||
return ((i2c->IC_RAW_INTR_STAT & it) ? SET : RESET);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the i2c interrupt pending bits.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param it: specifies the interrupt pending bit to clear.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @arg I2C_IT_RX_UNDER : Rx Buffer is empty interrupt
|
||||
/// @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt
|
||||
/// @arg I2C_IT_RX_FULL : Rx buffer full interrupt
|
||||
/// @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt
|
||||
/// @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
|
||||
/// @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt
|
||||
/// @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode)
|
||||
/// @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode)
|
||||
/// @arg I2C_IT_ACTIVITY : I2C activity interrupt
|
||||
/// @arg I2C_IT_STOP_DET : stop condition interrupt
|
||||
/// @arg I2C_IT_START_DET: start condition interrupt
|
||||
/// @arg I2C_IT_GEN_CALL : a general call address and ack interrupt
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_ClearITPendingBit(I2C_TypeDef* i2c, u32 it)
|
||||
{
|
||||
if ((it & I2C_IT_RX_UNDER) == I2C_FLAG_RX_UNDER)
|
||||
i2c->IC_CLR_RX_UNDER;
|
||||
if ((it & I2C_IT_RX_OVER) == I2C_FLAG_RX_OVER)
|
||||
i2c->IC_CLR_RX_OVER;
|
||||
if ((it & I2C_IT_TX_OVER) == I2C_FLAG_TX_OVER)
|
||||
i2c->IC_CLR_TX_OVER;
|
||||
if ((it & I2C_IT_RD_REQ) == I2C_FLAG_RD_REQ)
|
||||
i2c->IC_CLR_RD_REQ;
|
||||
if ((it & I2C_IT_TX_ABRT) == I2C_FLAG_TX_ABRT)
|
||||
i2c->IC_CLR_TX_ABRT;
|
||||
if ((it & I2C_IT_RX_DONE) == I2C_FLAG_RX_DONE)
|
||||
i2c->IC_CLR_RX_DONE;
|
||||
if ((it & I2C_IT_ACTIVITY) == I2C_FLAG_ACTIVITY)
|
||||
i2c->IC_CLR_ACTIVITY;
|
||||
if ((it & I2C_IT_STOP_DET) == I2C_FLAG_STOP_DET)
|
||||
i2c->IC_CLR_STOP_DET;
|
||||
if ((it & I2C_IT_START_DET) == I2C_FLAG_START_DET)
|
||||
i2c->IC_CLR_START_DET;
|
||||
if ((it & I2C_IT_GEN_CALL) == I2C_FLAG_GEN_CALL)
|
||||
i2c->IC_CLR_GEN_CALL;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// New Function Interface
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures slave address.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param addr: specifies the slave address which will be transmitted
|
||||
/// This parameter can be one of the following values
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_SendSlaveAddress(I2C_TypeDef* i2c, u8 addr)
|
||||
{
|
||||
WRITE_REG(i2c->IC_SAR, addr >> 1);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the I2C slave mode.
|
||||
/// @param i2c: select the I2C peripheral.
|
||||
/// @param state: new state of the specified I2C interrupts.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_SlaveConfigure(I2C_TypeDef* i2c, FunctionalState state)
|
||||
{
|
||||
(state) ? CLEAR_BIT(i2c->IC_CON, I2C_CR_SLAVEDIS) : SET_BIT(i2c->IC_CON, I2C_CR_SLAVEDIS);
|
||||
}
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
@@ -0,0 +1,208 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_iwdg.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE IWDG FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_IWDG_C_
|
||||
|
||||
// Files includes
|
||||
#include "hal_iwdg.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup IWDG_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup IWDG_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables write access to IWDG_PR and IWDG_RLR
|
||||
/// registers.
|
||||
/// @param write_access: new state of write access to IWDG_PR and
|
||||
/// IWDG_RLR registers.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg IWDG_WriteAccess_Enable: Enable write access to
|
||||
/// IWDG_PR and IWDG_RLR registers
|
||||
/// @arg IWDG_WriteAccess_Disable: Disable write access to
|
||||
/// IWDG_PR and IWDG_RLR registers
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void IWDG_WriteAccessCmd(u16 write_access)
|
||||
{
|
||||
IWDG->KR = write_access;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Sets IWDG Prescaler value.
|
||||
/// @param prescaler: specifies the IWDG Prescaler value.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg IWDG_Prescaler_4: IWDG prescaler set to 4
|
||||
/// @arg IWDG_Prescaler_8: IWDG prescaler set to 8
|
||||
/// @arg IWDG_Prescaler_16: IWDG prescaler set to 16
|
||||
/// @arg IWDG_Prescaler_32: IWDG prescaler set to 32
|
||||
/// @arg IWDG_Prescaler_64: IWDG prescaler set to 64
|
||||
/// @arg IWDG_Prescaler_128: IWDG prescaler set to 128
|
||||
/// @arg IWDG_Prescaler_256: IWDG prescaler set to 256
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void IWDG_SetPrescaler(u8 prescaler)
|
||||
{
|
||||
IWDG->PR = prescaler;
|
||||
PVU_CheckStatus();
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Set IWDG reload value.
|
||||
/// @param reload: specifies the IWDG reload value.
|
||||
/// This parameter must be a number between 0 and 0x0FFF.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void IWDG_SetReload(u16 reload)
|
||||
{
|
||||
IWDG->RLR = reload;
|
||||
RVU_CheckStatus();
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Get IWDG reload value.
|
||||
/// @param None.
|
||||
/// @retval reload: specifies the IWDG reload value.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 IWDG_GetReload(void)
|
||||
{
|
||||
return IWDG->RLR;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Reloads IWDG counter with value defined in the reload register
|
||||
/// (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void IWDG_ReloadCounter(void)
|
||||
{
|
||||
IWDG->KR = KR_KEY_Reload;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers
|
||||
/// disabled).
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void IWDG_Enable(void)
|
||||
{
|
||||
IWDG->KR = KR_KEY_Enable;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified IWDG flag is set or not.
|
||||
/// @param flag: specifies the flag to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg IWDG_FLAG_PVU: Prescaler Value Update on going
|
||||
/// @arg IWDG_FLAG_RVU: reload Value Update on going
|
||||
/// @retval The new state of flag (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus IWDG_GetFlagStatus(u16 flag)
|
||||
{
|
||||
return ((IWDG->SR & flag) != (u32)RESET) ? SET : RESET;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks prescaler value has been updated.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void PVU_CheckStatus(void)
|
||||
{
|
||||
while (IWDG_GetFlagStatus(IWDG_FLAG_PVU) == SET);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks count relead value has been updated.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RVU_CheckStatus(void)
|
||||
{
|
||||
while (IWDG_GetFlagStatus(IWDG_FLAG_RVU) == SET);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief IWDG overflow configuration.
|
||||
/// @param overflow_config
|
||||
/// @arg IWDG_Overflow_Interrupt: Interrupt after overflow.
|
||||
/// @arg IWDG_Overflow_Reset: Reset after overflow.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void IWDG_OverflowConfig(IWDGOverflowConfig_TypeDef overflow_config)
|
||||
{
|
||||
IWDG->CR &= ~IWDG_CR_IRQSEL;
|
||||
IWDG->CR |= overflow_config;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clear interrupt flag
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void IWDG_ClearITPendingBit(void)
|
||||
{
|
||||
IWDG->CR |= IWDG_CR_IRQCLR;//write 1 clear interrupt Flag
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clear interrupt flag
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void IWDG_ClearIT(void)
|
||||
{
|
||||
IWDG->CR |= IWDG_CR_IRQCLR;//write 1 clear interrupt Flag
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enable IWDG interrupt function
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void IWDG_EnableIT(void)
|
||||
{
|
||||
IWDG->CR |= IWDG_CR_IRQSEL;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Disable IWDG interrupt function
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void IWDG_Reset(void)
|
||||
{
|
||||
IWDG->CR &= ~IWDG_CR_IRQSEL;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
@@ -0,0 +1,147 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_misc.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE MSIC FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_MISC_C_
|
||||
|
||||
// Files includes
|
||||
#include "hal_misc.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MSIC_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MISC_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Set the NVIC interrupt vector table.
|
||||
/// @param vect_tab
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @arg NVIC_VectTab_RAM
|
||||
/// @arg NVIC_VectTab_FLASH
|
||||
/// @param offset
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void NVIC_SetVectorTable(u32 vect_tab, u32 offset)
|
||||
{
|
||||
SCB->VTOR = vect_tab | (offset & (u32)0x1FFFFF80);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Set the NVIC interrupt priority group.
|
||||
/// @param priority_group
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @arg NVIC_PriorityGroup_0
|
||||
/// @arg NVIC_PriorityGroup_1
|
||||
/// @arg NVIC_PriorityGroup_2
|
||||
/// @arg NVIC_PriorityGroup_3
|
||||
/// @arg NVIC_PriorityGroup_4
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void NVIC_PriorityGroupConfig(u32 priority_group)
|
||||
{
|
||||
SCB->AIRCR = AIRCR_VECTKEY_MASK | priority_group;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief NVIC initialization.
|
||||
/// @param init_struct
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void NVIC_Init(NVIC_InitTypeDef* init_struct)
|
||||
{
|
||||
if (init_struct->NVIC_IRQChannelCmd != DISABLE) {
|
||||
u32 pri = (SCB_AIRCR_PRIGROUP & ~(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk)) >> SCB_AIRCR_PRIGROUP_Pos;
|
||||
|
||||
pri = (((u32)init_struct->NVIC_IRQChannelPreemptionPriority << (0x4 - pri)) |
|
||||
(init_struct->NVIC_IRQChannelSubPriority & (0x0F >> pri)))
|
||||
<< 0x04;
|
||||
|
||||
NVIC->IP[init_struct->NVIC_IRQChannel] = pri;
|
||||
NVIC->ISER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
|
||||
}
|
||||
else {
|
||||
NVIC->ICER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief NVIC initialized extension function.
|
||||
/// @param init_struct
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exNVIC_Init(exNVIC_Init_TypeDef* init_struct)
|
||||
{
|
||||
u32 pri;
|
||||
|
||||
if (init_struct->NVIC_IRQChannelCmd != DISABLE) {
|
||||
pri = (SCB_AIRCR_PRIGROUP & ~(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk)) >> SCB_AIRCR_PRIGROUP_Pos;
|
||||
|
||||
pri = (((u32)init_struct->NVIC_IRQChannelPreemptionPriority << (0x4 - pri)) |
|
||||
(init_struct->NVIC_IRQChannelSubPriority & (0x0F >> pri))) << 0x04;
|
||||
|
||||
NVIC->IP[init_struct->NVIC_IRQChannel] = pri;
|
||||
NVIC->ISER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
|
||||
}
|
||||
else {
|
||||
NVIC->ICER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief System low power mode configuration.
|
||||
/// @param low_power_mode
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @arg NVIC_LP_SEVONPEND
|
||||
/// @arg NVIC_LP_SLEEPDEEP
|
||||
/// @arg NVIC_LP_SLEEPONEXIT
|
||||
/// @param state: new state of the low power mode.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void NVIC_SystemLPConfig(u8 low_power_mode, FunctionalState state)
|
||||
{
|
||||
(state) ? (SCB->SCR |= low_power_mode) : (SCB->SCR &= ~(u32)low_power_mode);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SysTick clock source configuration.
|
||||
/// @param systick_clk_source
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @arg SysTick_CLKSource_EXTCLK
|
||||
/// @arg SysTick_CLKSource_HCLK
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SysTick_CLKSourceConfig(u32 systick_clk_source)
|
||||
{
|
||||
(systick_clk_source == SysTick_CLKSource_HCLK) ? (SysTick->CTRL |= SysTick_CLKSource_HCLK) \
|
||||
: (SysTick->CTRL &= ~SysTick_CLKSource_HCLK);
|
||||
}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
@@ -0,0 +1,215 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_pwr.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE PWR FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define __HAL_PWR_C_
|
||||
|
||||
// Files includes
|
||||
#include "hal_pwr.h"
|
||||
#include "hal_rcc.h"
|
||||
#include "hal_syscfg.h"
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup PWR_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup PWR_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Deinitializes the PWR peripheral registers to their default reset
|
||||
/// values.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void PWR_DeInit(void)
|
||||
{
|
||||
exRCC_APB1PeriphReset(RCC_APB1ENR_PWR);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables access to the RTC and backup registers.
|
||||
/// @param state: new state of the access to the RTC and backup
|
||||
/// registers. This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void PWR_BackupAccessCmd(FunctionalState state)
|
||||
{
|
||||
(state) ? (RCC->BDCR |= RCC_BDCR_DBP) : (RCC->BDCR &= ~RCC_BDCR_DBP);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the Power Voltage Detector(PVD).
|
||||
/// @param state: new state of the PVD.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void PWR_PVDCmd(FunctionalState state)
|
||||
{
|
||||
(state) ? (SYSCFG->PDETCSR |= SYSCFG_PDETCSR_PVDE) : (SYSCFG->PDETCSR &= ~SYSCFG_PDETCSR_PVDE);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the voltage threshold detected by the Power Voltage
|
||||
/// Detector(PVD).
|
||||
/// @param pvd_level: specifies the PVD detection level
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg emPVD_LEVEL0 : PVD detection level set to 1.7V
|
||||
/// @arg emPVD_LEVEL1 : PVD detection level set to 2.0V
|
||||
/// @arg emPVD_LEVEL2 : PVD detection level set to 2.3V
|
||||
/// @arg emPVD_LEVEL3 : PVD detection level set to 2.6V
|
||||
/// @arg emPVD_LEVEL4 : PVD detection level set to 2.9V
|
||||
/// @arg emPVD_LEVEL5 : PVD detection level set to 3.2V
|
||||
/// @arg emPVD_LEVEL6 : PVD detection level set to 3.5V
|
||||
/// @arg emPVD_LEVEL7 : PVD detection level set to 3.8V
|
||||
/// @arg emPVD_LEVEL8 : PVD detection level set to 4.1V
|
||||
/// @arg emPVD_LEVEL9 : PVD detection level set to 4.4V
|
||||
/// @arg emPVD_LEVEL10: PVD detection level set to 4.7V
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void PWR_PVDLevelConfig(emPVD_Level_Typedef pvd_level)
|
||||
{
|
||||
SYSCFG->PDETCSR = (SYSCFG->PDETCSR & (~SYSCFG_PDETCSR_PLS)) | pvd_level;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the WakeUp Pin functionality.
|
||||
/// @param state: new state of the WakeUp Pin functionality.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void PWR_WakeUpPinCmd(FunctionalState state)
|
||||
{
|
||||
(state != DISABLE) ? (PWR->CR2 |= PWR_CR2_EWUP1) : (PWR->CSR &= ~PWR_CR2_EWUP1);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the WakeUp Pin functionality.
|
||||
/// @param state: new state of the WakeUp Pin functionality.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void PWR_WakeUpPinXCmd(emWUP_Pin_Typedef pin, FunctionalState state)
|
||||
{
|
||||
(state != DISABLE) ? (PWR->CR2 |= (PWR_CR2_EWUP1 << pin)) : (PWR->CSR &= ~(PWR_CR2_EWUP1 << pin));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enters STOP mode.
|
||||
/// @param regulator: specifies the regulator state in STOP mode.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg PWR_Regulator_ON: STOP mode with regulator ON
|
||||
/// @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode.
|
||||
/// @param stop_entry: specifies if STOP mode in entered with WFI or WFE
|
||||
/// instruction.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
|
||||
/// @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void PWR_EnterSTOPMode(emPWR_Reg_Stop_mode_Typedef regulator, emPWR_STOP_ModeEn_Typedef stop_entry)
|
||||
{
|
||||
|
||||
MODIFY_REG(PWR->CR, PWR_CR_LDPS, regulator);
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
if(stop_entry == PWR_STOPEntry_WFI) {
|
||||
__WFI();
|
||||
}
|
||||
else {
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enters STANDBY mode.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
PWR->CR |= PWR_CR_PDDS;
|
||||
PWR->SCR |= PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 | PWR_SCR_CWUF4 | PWR_SCR_CWUF5 | PWR_SCR_CWUF6;
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
#if defined(__CC_ARM)
|
||||
__force_stores();
|
||||
#endif
|
||||
__WFI();
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified PWR flag is set or not.
|
||||
/// @param flag: specifies the flag to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg PWR_FLAG_WU: Wake Up flag
|
||||
/// @arg PWR_FLAG_SB: StandBy flag
|
||||
/// @arg PWR_FLAG_PVDO: PVD Output
|
||||
/// @retval The new state of PWR_FLAG (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus PWR_GetPVDOFlagStatus(u32 flag)
|
||||
{
|
||||
return (FlagStatus)(SYSCFG->PDETCSR & flag);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the PWR's pending flags.
|
||||
/// @param flag: specifies the flag to clear.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg PWR_FLAG_WU: Wake Up flag
|
||||
/// @arg PWR_FLAG_SB: StandBy flag
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void PWR_ClearPVDOFlag(u32 flag)
|
||||
{
|
||||
PWR->CR |= flag << 2;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified PWR flag is set or not.
|
||||
/// @param flag: specifies the flag to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg PWR_FLAG_WU: Wake Up flag
|
||||
/// @arg PWR_FLAG_SB: StandBy flag
|
||||
/// @arg PWR_FLAG_PVDO: PVD Output
|
||||
/// @retval The new state of PWR_FLAG (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus PWR_GetFlagStatus(u32 flag)
|
||||
{
|
||||
return (FlagStatus)(PWR->CSR & flag);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the PWR's pending flags.
|
||||
/// @param flag: specifies the flag to clear.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg PWR_FLAG_WU: Wake Up flag
|
||||
/// @arg PWR_FLAG_SB: StandBy flag
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void PWR_ClearFlag(u32 flag)
|
||||
{
|
||||
PWR->CR |= flag << 2;
|
||||
}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
@@ -0,0 +1,995 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_rcc.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE RCC FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_RCC_C_
|
||||
|
||||
// Files includes
|
||||
#include "mm32_reg.h"
|
||||
#include "hal_rcc.h"
|
||||
|
||||
|
||||
|
||||
u8 tbPresc[] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup RCC_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup RCC_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Resets the RCC clock configuration to default state.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_DeInit()
|
||||
{
|
||||
SET_BIT(RCC->CR, RCC_CR_HSION);
|
||||
CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
|
||||
CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON );
|
||||
CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL_DN | RCC_PLLCFGR_PLL_DP);
|
||||
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
|
||||
CLEAR_REG(RCC->CFGR);
|
||||
CLEAR_REG(RCC->CIR);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the External High Speed oscillator (HSE).
|
||||
/// @param state: specifies the new state of HSE.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg RCC_HSE_OFF: HSE oscillator OFF
|
||||
/// @arg RCC_HSE_ON: HSE oscillator ON
|
||||
/// @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_HSEConfig(RCCHSE_TypeDef state)
|
||||
{
|
||||
RCC->CR &= ~(RCC_CR_HSEBYP | RCC_CR_HSEON);
|
||||
switch (state) {
|
||||
case RCC_HSE_Bypass:
|
||||
RCC->CR |= RCC_CR_HSEBYP;
|
||||
RCC->CR |= RCC_CR_HSEON;
|
||||
break;
|
||||
case RCC_HSE_ON:
|
||||
RCC->CR |= RCC_CR_HSEON;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified RCC flag is set or not.
|
||||
/// @param flag: specifies the flag to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
|
||||
/// @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
|
||||
/// @arg RCC_FLAG_PLLRDY: PLL clock ready
|
||||
/// @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
|
||||
/// @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
|
||||
/// @arg RCC_FLAG_PINRST: Pin reset
|
||||
/// @arg RCC_FLAG_PORRST: POR/PDR reset
|
||||
/// @arg RCC_FLAG_SFTRST: Software reset
|
||||
/// @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
|
||||
/// @arg RCC_FLAG_WWDGRST: Window Watchdog reset
|
||||
/// @arg RCC_FLAG_LPWRRST: Low Power reset
|
||||
/// @retval The new state of flag (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus RCC_GetFlagStatus(RCC_FLAG_TypeDef flag)
|
||||
{
|
||||
return ((((flag >> 5) == CR_REG_INDEX) ? RCC->CR : (((flag >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : RCC->CSR)) &
|
||||
(1 << (flag & 0x1F)))
|
||||
? SET : RESET;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Waits for HSE start-up.
|
||||
/// @param None.
|
||||
/// @retval An ErrorStatus enumuration value:
|
||||
/// - SUCCESS: HSE oscillator is stable and ready to use
|
||||
/// - ERROR: HSE oscillator not yet ready
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
ErrorStatus RCC_WaitForHSEStartUp(void)
|
||||
{
|
||||
u32 StartUpCounter = 0;
|
||||
|
||||
FlagStatus HSEStatus;
|
||||
|
||||
do {
|
||||
HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
|
||||
StartUpCounter++;
|
||||
} while ((HSEStatus == RESET) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
return (ErrorStatus)(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) ? SUCCESS : ERROR;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Waits for flag start-up.
|
||||
/// @param flag: specifies the flag to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
|
||||
/// @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
|
||||
/// @arg RCC_FLAG_PLLRDY: PLL clock ready
|
||||
/// @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
|
||||
/// @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
|
||||
/// @arg RCC_FLAG_PINRST: Pin reset
|
||||
/// @arg RCC_FLAG_PORRST: POR/PDR reset
|
||||
/// @arg RCC_FLAG_SFTRST: Software reset
|
||||
/// @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
|
||||
/// @arg RCC_FLAG_WWDGRST: Window Watchdog reset
|
||||
/// @retval An ErrorStatus enumuration value:
|
||||
/// - SUCCESS: HSE oscillator is stable and ready to use
|
||||
/// - ERROR: HSE oscillator not yet ready
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
ErrorStatus RCC_WaitForFlagStartUp(RCC_FLAG_TypeDef flag)
|
||||
{
|
||||
u32 StartUpCounter = 0;
|
||||
|
||||
while (RCC_GetFlagStatus(flag) == RESET) {
|
||||
if (StartUpCounter++ > HSE_STARTUP_TIMEOUT) {
|
||||
return ERROR;
|
||||
}
|
||||
}
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the Internal High Speed oscillator (HSI).
|
||||
/// @param state: new state of the HSI.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_HSICmd(FunctionalState state)
|
||||
{
|
||||
MODIFY_REG(RCC->CR, RCC_CR_HSION, (state << RCC_CR_HSION_Pos));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the system clock (SYSCLK).
|
||||
/// @param sys_clk_source: specifies the clock source used as system
|
||||
/// clock. This parameter can be one of the following values:
|
||||
/// @arg RCC_HSI: specifies HSI as system clock
|
||||
/// @arg RCC_HSE: specifies HSE as system clock
|
||||
/// @arg RCC_PLL: specifies PLL as system clock
|
||||
/// @arg RCC_LSI: specifies LSI as system clock
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_SYSCLKConfig(SYSCLK_TypeDef sys_clk_source)
|
||||
{
|
||||
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (sys_clk_source << RCC_CFGR_SW_Pos));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the PLL clock source and DM DN factor.
|
||||
/// This function must be used only when the PLL is disabled.
|
||||
/// @param plldn: specifies the PLL multiplication factor.
|
||||
/// This parameter can be RCC_PLLMul_x where x:[31:26]
|
||||
/// @param plldm: specifies the PLL Divsior factor.
|
||||
/// This parameter can be RCC_Divsior_x where x:[22:20]
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_PLLDMDNConfig(u32 plldn, u32 plldm)
|
||||
{
|
||||
MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLL_DN | RCC_PLLCFGR_PLL_DP), ((plldn << RCC_PLLCFGR_PLL_DN_Pos) | (plldm << RCC_PLLCFGR_PLL_DP_Pos)));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the PLL.
|
||||
/// The PLL can not be disabled if it is used as system clock.
|
||||
/// @param state: new state of the PLL.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_PLLCmd(FunctionalState state)
|
||||
{
|
||||
MODIFY_REG(RCC->CR, RCC_CR_PLLON, (state << RCC_CR_PLLON_Pos));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the PLL clock source and multiplication factor.
|
||||
/// This function must be used only when the PLL is disabled.
|
||||
/// @param pll_src: specifies the PLL entry clock source.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg RCC_HSI_Div4: HSI oscillator clock divided
|
||||
/// by 4 selected as PLL clock entry
|
||||
/// @arg RCC_HSE_Div1: HSE oscillator clock selected
|
||||
/// as PLL clock entry
|
||||
/// @arg RCC_HSE_Div2: HSE oscillator clock divided
|
||||
/// by 2 selected as PLL clock entry
|
||||
/// @param pll_mul: specifies the PLL multiplication factor.
|
||||
/// This parameter can be RCC_PLLMul_x where x:[31:26][22:20]
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_PLLConfig(RCC_PLLSource_TypeDef pll_src, RCC_PLLMul_TypeDef pll_mul)
|
||||
{
|
||||
const u8 DNDM_Item[] = {0x07, 0x03, 0x05, 0x01, 0x07, 0x01, 0x09, 0x01, // Frclk*8/4 ; Frclk*6/2 ; Frclk*8/2 ; Frclk*10/2;
|
||||
0x0B, 0x01, 0x0D, 0x01, 0x0F, 0x01, 0x11, 0x01, // Frclk*12/2; Frclk*14/2; Frclk*16/2; Frclk*18/2;
|
||||
0x13, 0x01, 0x15, 0x01, 0x17, 0x01, 0x19, 0x01, // Frclk*20/2; Frclk*22/2; Frclk*24/2; Frclk*26/2;
|
||||
0x1B, 0x01, 0x1D, 0x01, 0x1F, 0x01
|
||||
}; // Frclk*28/2; Frclk*30/2; // Frclk*32/2;
|
||||
MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLLXTPRE | RCC_PLLCFGR_PLLSRC), pll_src);
|
||||
RCC_PLLDMDNConfig((u32)DNDM_Item[pll_mul >> 17], (u32)DNDM_Item[(pll_mul >> 17) + 1]);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the USB clock (USBCLK).
|
||||
/// @param usb_clk_src: specifies the USB clock source.
|
||||
/// This clock is derived from the PLL output.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
|
||||
/// @arg RCC_USBCLKSource_PLLCLK_Div2: PLL clock divided by 2 selected as USB
|
||||
/// clock source
|
||||
/// @arg RCC_USBCLKSource_PLLCLK_Div3: PLL clock divided by 3 selected as USB
|
||||
/// clock source
|
||||
/// @arg RCC_USBCLKSource_PLLCLK_Div4: PLL clock divided by 4 selected as USB
|
||||
/// clock source
|
||||
/// @arg RCC_USBCLKSource_PLLCLK_Div5: PLL clock divided by 5 selected as USB
|
||||
/// clock source
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_USBCLKConfig(RCC_USBCLKSOURCE_TypeDef usb_clk_src)
|
||||
{
|
||||
MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (usb_clk_src << RCC_CFGR_USBPRE_Pos));
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the clock source used as system clock.
|
||||
/// @param None.
|
||||
/// @retval The clock source used as system clock. The returned value can
|
||||
/// be one of the following:
|
||||
/// - 0x00: HSI/6 used as system clock
|
||||
/// - 0x04: HSE used as system clock
|
||||
/// - 0x08: PLL used as system clock
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u8 RCC_GetSYSCLKSource(void)
|
||||
{
|
||||
return ((u8)READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the AHB clock (hclk).
|
||||
/// @param sys_clk: defines the AHB clock divider. This clock is derived
|
||||
/// from the system clock (SYSCLK).
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
|
||||
/// @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
|
||||
/// @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
|
||||
/// @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
|
||||
/// @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
|
||||
/// @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
|
||||
/// @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
|
||||
/// @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
|
||||
/// @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_HCLKConfig(RCC_AHB_CLK_TypeDef sys_clk)
|
||||
{
|
||||
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, sys_clk);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the Low Speed APB clock (pclk1).
|
||||
/// @param hclk: defines the APB1 clock divider. This clock is derived from
|
||||
/// the AHB clock (hclk).
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg RCC_HCLK_Div1: APB1 clock = hclk
|
||||
/// @arg RCC_HCLK_Div2: APB1 clock = hclk/2
|
||||
/// @arg RCC_HCLK_Div4: APB1 clock = hclk/4
|
||||
/// @arg RCC_HCLK_Div8: APB1 clock = hclk/8
|
||||
/// @arg RCC_HCLK_Div16: APB1 clock = hclk/16
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_PCLK1Config(RCC_APB1_APB2_CLK_TypeDef hclk)
|
||||
{
|
||||
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, hclk);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the High Speed APB clock (pclk2).
|
||||
/// @param hclk: defines the APB2 clock divider. This clock is derived from
|
||||
/// the AHB clock (hclk).
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg RCC_HCLK_Div1: APB2 clock = hclk
|
||||
/// @arg RCC_HCLK_Div2: APB2 clock = hclk/2
|
||||
/// @arg RCC_HCLK_Div4: APB2 clock = hclk/4
|
||||
/// @arg RCC_HCLK_Div8: APB2 clock = hclk/8
|
||||
/// @arg RCC_HCLK_Div16: APB2 clock = hclk/16
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_PCLK2Config(RCC_APB1_APB2_CLK_TypeDef hclk)
|
||||
{
|
||||
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (hclk << 3));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the ADC clock (ADCCLK).
|
||||
/// @param pclk2: defines the ADC clock divider. This clock is derived from
|
||||
/// the APB2 clock (pclk2).
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg RCC_PCLK2_Div2: ADC clock = pclk2/2
|
||||
/// @arg RCC_PCLK2_Div4: ADC clock = pclk2/4
|
||||
/// @arg RCC_PCLK2_Div6: ADC clock = pclk2/6
|
||||
/// @arg RCC_PCLK2_Div8: ADC clock = pclk2/8
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_ADCCLKConfig(RCC_ADCCLKSOURCE_TypeDef pclk2)
|
||||
{
|
||||
MODIFY_REG(RCC->CFGR, ADC_CFGR_PRE, pclk2);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the External Low Speed oscillator (LSE).
|
||||
/// @param state: specifies the new state of the LSE.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg RCC_LSE_OFF: LSE oscillator OFF
|
||||
/// @arg RCC_LSE_ON: LSE oscillator ON
|
||||
/// @arg RCC_LSE_Bypass: LSE oscillator bypassed with external
|
||||
/// clock
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_LSEConfig(RCC_LSE_TypeDef state)
|
||||
{
|
||||
RCC->BDCR &= ~(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON);
|
||||
|
||||
switch (state) {
|
||||
case RCC_LSE_Bypass:
|
||||
RCC->BDCR |= RCC_BDCR_LSEBYP;
|
||||
RCC->BDCR |= RCC_BDCR_LSEON;
|
||||
break;
|
||||
case RCC_LSE_ON:
|
||||
RCC->BDCR |= RCC_BDCR_LSEON;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the RTC clock (RTCCLK).
|
||||
/// Once the RTC clock is selected it can be changed unless the
|
||||
/// Backup domain is reset.
|
||||
/// @param rtc_clk_src: specifies the RTC clock source.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
|
||||
/// @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
|
||||
/// @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128
|
||||
/// selected as RTC clock
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_RTCCLKConfig(RCC_RTCCLKSOURCE_TypeDef rtc_clk_src)
|
||||
{
|
||||
MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, rtc_clk_src);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the RTC clock.
|
||||
/// This function must be used only after the RTC clock was
|
||||
/// selected using the RCC_RTCCLKConfig function.
|
||||
/// @param state: new state of the RTC clock.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_RTCCLKCmd(FunctionalState state)
|
||||
{
|
||||
MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCEN, (state << RCC_BDCR_RTCEN_Pos));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the Internal Low Speed oscillator (LSI).
|
||||
/// LSI can not be disabled if the IWDG is running.
|
||||
/// @param state: new state of the LSI.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_LSICmd(FunctionalState state)
|
||||
{
|
||||
// u32 j;
|
||||
MODIFY_REG(RCC->CSR, RCC_CSR_LSION | RCC_CSR_LSIOENLV, RCC_CSR_LSIOENLV | (state << RCC_CSR_LSION_Pos));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the clock frequency of different on chip clocks.
|
||||
/// @param None.
|
||||
/// @retval sys_clk : System clock frequency
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 RCC_GetSysClockFreq(void)
|
||||
{
|
||||
u32 result;
|
||||
u32 clock, mul, div;
|
||||
switch (RCC->CFGR & RCC_CFGR_SWS) {
|
||||
case RCC_CFGR_SWS_LSI:
|
||||
result = LSI_VALUE;
|
||||
break;
|
||||
|
||||
case RCC_CFGR_SWS_HSE:
|
||||
result = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case RCC_CFGR_SWS_PLL:
|
||||
clock = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) ? (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLXTPRE) ? (HSE_VALUE >> 1) : HSE_VALUE)
|
||||
: HSI_VALUE_PLL_ON;
|
||||
mul = ((RCC->PLLCFGR & (u32)RCC_PLLCFGR_PLL_DN) >> RCC_PLLCFGR_PLL_DN_Pos) + 1;
|
||||
div = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL_DP) >> RCC_PLLCFGR_PLL_DP_Pos) + 1;
|
||||
|
||||
result = clock * mul / div;
|
||||
break;
|
||||
default:
|
||||
result = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the hclk frequency of different on chip clocks.
|
||||
/// @param None.
|
||||
/// @retval hclk frequency
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 RCC_GetHCLKFreq(void)
|
||||
{
|
||||
return (RCC_GetSysClockFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the pclk1 frequency of different on chip clocks.
|
||||
/// @param None.
|
||||
/// @retval pclk1 frequency
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 RCC_GetPCLK1Freq(void)
|
||||
{
|
||||
return (RCC_GetHCLKFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the pclk2 frequency of different on chip clocks.
|
||||
/// @param None.
|
||||
/// @retval pclk2 frequency
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 RCC_GetPCLK2Freq(void)
|
||||
{
|
||||
return (RCC_GetHCLKFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the frequency of different on chip clocks.
|
||||
/// @param clk: pointer to a RCC_ClocksTypeDef structure which
|
||||
/// will hold the clocks frequency.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef* clk)
|
||||
{
|
||||
u8 tbADCPresc[] = {2, 4, 6, 8};
|
||||
|
||||
clk->SYSCLK_Frequency = RCC_GetSysClockFreq();
|
||||
clk->HCLK_Frequency = RCC_GetHCLKFreq();
|
||||
clk->PCLK1_Frequency = RCC_GetPCLK1Freq();
|
||||
clk->PCLK2_Frequency = RCC_GetPCLK2Freq();
|
||||
|
||||
clk->ADCCLK_Frequency = clk->PCLK2_Frequency / tbADCPresc[(RCC->CFGR & ADC_CFGR_PRE) >> ADC_CFGR_PRE_Pos];
|
||||
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the AHB peripheral clock.
|
||||
/// @param ahb_periph: specifies the AHB peripheral to gates its clock.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @param state: new state of the specified peripheral clock.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_AHBPeriphClockCmd(u32 ahb_periph, FunctionalState state)
|
||||
{
|
||||
(state) ? (RCC->AHBENR |= ahb_periph) : (RCC->AHBENR &= ~ahb_periph);
|
||||
}
|
||||
/// @param state: new state of the specified peripheral clock.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_AHB2PeriphClockCmd(u32 ahb_periph, FunctionalState state)
|
||||
{
|
||||
(state) ? (RCC->AHB2ENR |= ahb_periph) : (RCC->AHB2ENR &= ~ahb_periph);
|
||||
}
|
||||
/// @param state: new state of the specified peripheral clock.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_AHB3PeriphClockCmd(u32 ahb_periph, FunctionalState state)
|
||||
{
|
||||
(state) ? (RCC->AHB3ENR |= ahb_periph) : (RCC->AHB3ENR &= ~ahb_periph);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the High Speed APB (APB2) peripheral clock.
|
||||
/// @param apb2_periph: specifies the APB2 peripheral to gates its
|
||||
/// clock.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @param state: new state of the specified peripheral clock.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_APB2PeriphClockCmd(u32 apb2_periph, FunctionalState state)
|
||||
{
|
||||
(state) ? (RCC->APB2ENR |= apb2_periph) : (RCC->APB2ENR &= ~apb2_periph);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
|
||||
/// @param apb1_periph: specifies the APB1 peripheral to gates its
|
||||
/// clock.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @param state: new state of the specified peripheral clock.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_APB1PeriphClockCmd(u32 apb1_periph, FunctionalState state)
|
||||
{
|
||||
(state) ? (RCC->APB1ENR |= apb1_periph) : (RCC->APB1ENR &= ~apb1_periph);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Forces or releases High Speed APB (APB2) peripheral reset.
|
||||
/// @param apb2_periph: specifies the APB2 peripheral to reset.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @param state: new state of the specified peripheral reset.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_APB2PeriphResetCmd(u32 apb2_periph, FunctionalState state)
|
||||
{
|
||||
(state) ? (RCC->APB2RSTR |= apb2_periph) : (RCC->APB2RSTR &= ~apb2_periph);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Forces or releases Low Speed APB (APB1) peripheral reset.
|
||||
/// @param apb1_periph: specifies the APB1 peripheral to reset.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @param state: new state of the specified peripheral clock.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_APB1PeriphResetCmd(u32 apb1_periph, FunctionalState state)
|
||||
{
|
||||
(state) ? (RCC->APB1RSTR |= apb1_periph) : (RCC->APB1RSTR &= ~apb1_periph);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Forces or releases Low Speed AHB peripheral reset.
|
||||
/// @param ahb_periph: specifies the AHB peripheral to reset.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @param state: new state of the specified peripheral clock.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_AHBPeriphResetCmd(u32 ahb_periph, FunctionalState state)
|
||||
{
|
||||
(state) ? (RCC->AHBRSTR |= ahb_periph) : (RCC->AHBRSTR &= ~ahb_periph);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Forces or releases Low Speed AHB2 peripheral reset.
|
||||
/// @param ahb_periph: specifies the AHB peripheral to reset.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @param state: new state of the specified peripheral clock.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_AHB2PeriphResetCmd(u32 ahb_periph, FunctionalState state)
|
||||
{
|
||||
(state) ? (RCC->AHB2RSTR |= ahb_periph) : (RCC->AHB2RSTR &= ~ahb_periph);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Forces or releases Low Speed AHB2 peripheral reset.
|
||||
/// @param ahb_periph: specifies the AHB peripheral to reset.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @param state: new state of the specified peripheral clock.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_AHB3PeriphResetCmd(u32 ahb_periph, FunctionalState state)
|
||||
{
|
||||
(state) ? (RCC->AHB3RSTR |= ahb_periph) : (RCC->AHB3RSTR &= ~ahb_periph);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Forces or releases the Backup domain reset.
|
||||
/// @param state: new state of the Backup domain reset.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_BackupResetCmd(FunctionalState state)
|
||||
{
|
||||
MODIFY_REG(RCC->BDCR, RCC_BDCR_BDRST, (state << RCC_BDCR_BDRST_Pos));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the Clock Security System.
|
||||
/// @param state: new state of the Clock Security System..
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_ClockSecuritySystemCmd(FunctionalState state)
|
||||
{
|
||||
MODIFY_REG(RCC->CR, RCC_CR_CSSON, (state << RCC_CR_CSSON_Pos));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Selects the clock source to output on MCO pin.
|
||||
/// @param mco_src: specifies the clock source to output.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg RCC_MCO_NoClock: No clock selected
|
||||
/// @arg RCC_MCO_LSI: LSI oscillator clock selected
|
||||
/// @arg RCC_MCO_LSE: LSE oscillator clock selected
|
||||
/// @arg RCC_MCO_SYSCLK: System clock selected
|
||||
/// @arg RCC_MCO_HSI: HSI oscillator clock selected
|
||||
/// @arg RCC_MCO_HSE: HSE oscillator clock selected
|
||||
/// @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_MCOConfig(RCC_MCO_TypeDef mco_src)
|
||||
{
|
||||
MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, mco_src);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the RCC reset flags.
|
||||
/// The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
|
||||
/// RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
|
||||
/// RCC_FLAG_LPWRRST
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_ClearFlag(void)
|
||||
{
|
||||
SET_BIT(RCC->CSR, RCC_CSR_RMVF);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified RCC interrupts.
|
||||
/// @param it: specifies the RCC interrupt sources to be enabled or
|
||||
/// disabled.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @arg RCC_IT_LSIRDY: LSI ready interrupt
|
||||
/// @arg RCC_IT_LSERDY: LSE ready interrupt
|
||||
/// @arg RCC_IT_HSIRDY: HSI ready interrupt
|
||||
/// @arg RCC_IT_HSERDY: HSE ready interrupt
|
||||
/// @arg RCC_IT_PLLRDY: PLL ready interrupt
|
||||
/// @param state: new state of the specified RCC interrupts.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_ITConfig(RCC_IT_TypeDef it, FunctionalState state)
|
||||
{
|
||||
(state) ? SET_BIT(RCC->CIR, it << RCC_CIR_LSIRDYIE_Pos) : CLEAR_BIT(RCC->CIR, it << RCC_CIR_LSIRDYIE_Pos);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified RCC interrupt has occurred or not.
|
||||
/// @param it: specifies the RCC interrupt source to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg RCC_IT_LSIRDY: LSI ready interrupt
|
||||
/// @arg RCC_IT_LSERDY: LSE ready interrupt
|
||||
/// @arg RCC_IT_HSIRDY: HSI ready interrupt
|
||||
/// @arg RCC_IT_HSERDY: HSE ready interrupt
|
||||
/// @arg RCC_IT_PLLRDY: PLL ready interrupt
|
||||
/// @arg RCC_IT_CSS: Clock Security System interrupt
|
||||
/// @retval The new state of it (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
ITStatus RCC_GetITStatus(RCC_IT_TypeDef it)
|
||||
{
|
||||
return (ITStatus)READ_BIT(RCC->CIR, (it << RCC_CIR_LSIRDYF_Pos));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the RCC�?interrupt pending bits.
|
||||
/// @param it: specifies the interrupt pending bit to clear.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @arg RCC_IT_LSIRDY: LSI ready interrupt
|
||||
/// @arg RCC_IT_LSERDY: LSE ready interrupt
|
||||
/// @arg RCC_IT_HSIRDY: HSI ready interrupt
|
||||
/// @arg RCC_IT_HSERDY: HSE ready interrupt
|
||||
/// @arg RCC_IT_PLLRDY: PLL ready interrupt
|
||||
/// @arg RCC_IT_CSS: Clock Security System interrupt
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_ClearITPendingBit(u8 it)
|
||||
{
|
||||
SET_BIT(RCC->CIR, (it << RCC_CIR_LSIRDYC_Pos));
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Forces or releases Low Speed APB (APB1) peripheral reset.
|
||||
/// @param apb1_periph: specifies the APB1 peripheral to reset.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_APB1PeriphReset(u32 apb1_periph)
|
||||
{
|
||||
RCC->APB1RSTR |= apb1_periph;
|
||||
RCC->APB1RSTR &= ~apb1_periph;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Forces or releases Low Speed APB (APB2) peripheral reset.
|
||||
/// @param apb2_periph: specifies the APB2 peripheral to reset.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_APB2PeriphReset(u32 apb2_periph)
|
||||
{
|
||||
RCC->APB2RSTR |= apb2_periph;
|
||||
RCC->APB2RSTR &= ~apb2_periph;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Forces or releases High Speed AHB (AHB1) peripheral reset.
|
||||
/// @param ahb1_periph: specifies the AHB1 peripheral to reset.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_AHBPeriphReset(u32 ahb1_periph)
|
||||
{
|
||||
RCC->AHBRSTR |= ahb1_periph;
|
||||
RCC->AHBRSTR &= ~ahb1_periph;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// New Function Interface
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Forces or releases Low Speed APB (APB1) peripheral reset.
|
||||
/// @param apb1_periph: specifies the APB1 peripheral to reset.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exRCC_APB1PeriphReset(u32 apb1_periph)
|
||||
{
|
||||
RCC->APB1RSTR |= apb1_periph;
|
||||
RCC->APB1RSTR &= ~apb1_periph;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief
|
||||
/// @param
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exRCC_BackupReset()
|
||||
{
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Forces or releases High Speed APB (APB2) peripheral reset.
|
||||
/// @param apb2_periph: specifies the APB2 peripheral to reset.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exRCC_APB2PeriphReset(u32 apb2_periph)
|
||||
{
|
||||
RCC->APB2RSTR |= apb2_periph;
|
||||
RCC->APB2RSTR &= ~apb2_periph;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Forces or releases High Speed AHB (AHB1) peripheral reset.
|
||||
/// @param ahb1_periph: specifies the AHB1 peripheral to reset.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exRCC_AHBPeriphReset(u32 ahb1_periph)
|
||||
{
|
||||
RCC->AHBRSTR |= ahb1_periph;
|
||||
RCC->AHBRSTR &= ~ahb1_periph;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Disable systick
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exRCC_SystickDisable()
|
||||
{
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enable systick
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exRCC_SystickEnable(u32 sys_tick_period)
|
||||
{
|
||||
SysTick_Config(RCC_GetHCLKFreq() / 1000000 * sys_tick_period);
|
||||
}
|
||||
|
||||
/*
|
||||
(state) ? (RCC->AHBENR |= ahb_periph) : (RCC->AHBENR &= ~ahb_periph);
|
||||
(state) ? (RCC->APB1ENR |= apb1_periph) : (RCC->APB1ENR &= ~apb1_periph);
|
||||
(state) ? (RCC->APB2ENR |= apb2_periph) : (RCC->APB2ENR &= ~apb2_periph);
|
||||
*/
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified ADC peripheral Clock.
|
||||
/// @param peripheral:select the ADC peripheral.
|
||||
/// @param state: new state of the ADC peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_ADC_ClockCmd(ADC_TypeDef* peripheral, FunctionalState state)
|
||||
{
|
||||
switch (*(vu32*)&peripheral) {
|
||||
|
||||
case ADC1_BASE:
|
||||
(state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC1) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC1);
|
||||
break;
|
||||
case ADC2_BASE:
|
||||
(state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC2) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC2);
|
||||
break;
|
||||
case ADC3_BASE:
|
||||
(state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC3) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC3);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified BKP peripheral Clock.
|
||||
/// @param peripheral:select the BKP peripheral.
|
||||
/// @param state: new state of the BKP peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_BKP_ClockCmd(BKP_TypeDef* peripheral, FunctionalState state)
|
||||
{
|
||||
if(BKP == peripheral) {
|
||||
(state) ? (RCC->APB1ENR |= RCC_APB1ENR_BKP) : (RCC->APB1ENR &= ~RCC_APB1ENR_BKP);
|
||||
(state) ? (RCC->APB1ENR |= RCC_APB1ENR_PWR) : (RCC->APB1ENR &= ~RCC_APB1ENR_PWR);
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified CAN peripheral Clock.
|
||||
/// @param peripheral:select the CAN peripheral.
|
||||
/// @param state: new state of the CAN peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_CAN_ClockCmd(CAN_TypeDef* peripheral, FunctionalState state)
|
||||
{
|
||||
if(CAN1 == peripheral) {
|
||||
(state) ? (RCC->APB1ENR |= RCC_APB1ENR_CAN) : (RCC->APB1ENR &= ~RCC_APB1ENR_CAN);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified COMP peripheral Clock.
|
||||
/// @param peripheral:select the COMP peripheral.
|
||||
/// @param state: new state of the COMP peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_COMP_ClockCmd(COMP_TypeDef* peripheral, FunctionalState state)
|
||||
{
|
||||
if(COMP == peripheral) {
|
||||
(state) ? (RCC->APB2ENR |= RCC_APB2ENR_COMP) : (RCC->APB2ENR &= ~RCC_APB2ENR_COMP);
|
||||
}
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified CRC peripheral Clock.
|
||||
/// @param peripheral:select the CRC peripheral.
|
||||
/// @param state: new state of the CRC peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_CRC_ClockCmd(CRC_TypeDef* peripheral, FunctionalState state)
|
||||
{
|
||||
if(CRC == peripheral) {
|
||||
(state) ? (RCC->AHBENR |= RCC_AHBENR_CRC) : (RCC->AHBENR &= ~RCC_AHBENR_CRC);
|
||||
}
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified DAC peripheral Clock.
|
||||
/// @param peripheral:select the DAC peripheral.
|
||||
/// @param state: new state of the DAC peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_DAC_ClockCmd(DAC_TypeDef* peripheral, FunctionalState state)
|
||||
{
|
||||
if(DAC == peripheral) {
|
||||
(state) ? (RCC->APB1ENR |= RCC_APB1ENR_DAC) : (RCC->APB1ENR &= ~RCC_APB1ENR_DAC);
|
||||
}
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified DMA peripheral Clock.
|
||||
/// @param peripheral:select the DMA peripheral.
|
||||
/// @param state: new state of the DMA peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_DMA_ClockCmd(DMA_TypeDef* peripheral, FunctionalState state)
|
||||
{
|
||||
if(DMA1 == peripheral) {
|
||||
(state) ? (RCC->AHBENR |= RCC_AHBENR_DMA1) : (RCC->AHBENR &= ~RCC_AHBENR_DMA1);
|
||||
}
|
||||
if(DMA2 == peripheral) {
|
||||
(state) ? (RCC->AHBENR |= RCC_AHBENR_DMA2) : (RCC->AHBENR &= ~RCC_AHBENR_DMA2);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified GPIO peripheral Clock.
|
||||
/// @param peripheral:select the GPIO peripheral.
|
||||
/// @param state: new state of the GPIO peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_GPIO_ClockCmd(GPIO_TypeDef* peripheral, FunctionalState state)
|
||||
{
|
||||
switch (*(vu32*)&peripheral) {
|
||||
case (u32)GPIOA:
|
||||
(state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOA) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOA);
|
||||
break;
|
||||
case (u32)GPIOB:
|
||||
(state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOB) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOB);
|
||||
break;
|
||||
case (u32)GPIOC:
|
||||
(state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOC) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOC);
|
||||
break;
|
||||
case (u32)GPIOD:
|
||||
(state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOD) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOD);
|
||||
break;
|
||||
case (u32)GPIOE:
|
||||
(state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOE) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOE);
|
||||
break;
|
||||
case (u32)GPIOF:
|
||||
(state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOF) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOF);
|
||||
break;
|
||||
case (u32)GPIOG:
|
||||
(state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOG) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOG);
|
||||
break;
|
||||
case (u32)GPIOH:
|
||||
(state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOH) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOH);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Deinitializes the uart peripheral registers to their
|
||||
/// default reset values.
|
||||
/// @param peripheral: Select the UART or the UART peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RCC_UART_ClockCmd(UART_TypeDef* peripheral, FunctionalState state)
|
||||
{
|
||||
if(UART2 == peripheral) {
|
||||
(state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART2) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART2);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART2);
|
||||
}
|
||||
if(UART1 == peripheral) {
|
||||
(state) ? (RCC->APB2ENR |= RCC_APB2ENR_UART1) : (RCC->APB2ENR &= ~RCC_APB2ENR_UART1);//exRCC_APB2PeriphReset(RCC_APB2ENR_UART1);
|
||||
}
|
||||
if(UART3 == peripheral) {
|
||||
(state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART3) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART3);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART3);
|
||||
}
|
||||
if(UART4 == peripheral) {
|
||||
(state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART4) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART4);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART4);
|
||||
}
|
||||
if(UART5 == peripheral) {
|
||||
(state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART5) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART5);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART5);
|
||||
}
|
||||
if(UART6 == peripheral) {
|
||||
(state) ? (RCC->APB2ENR |= RCC_APB2ENR_UART6) : (RCC->APB2ENR &= ~RCC_APB2ENR_UART6);//exRCC_APB2PeriphReset(RCC_APB2ENR_UART6);
|
||||
}
|
||||
if(UART7 == peripheral) {
|
||||
(state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART7) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART7);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART7);
|
||||
}
|
||||
if(UART8 == peripheral) {
|
||||
(state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART8) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART8);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART8);
|
||||
}
|
||||
}
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
@@ -0,0 +1,234 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_rtc.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE RTC FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_RTC_C_
|
||||
|
||||
// Files includes
|
||||
#include "hal_rtc.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup RTC_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup RTC_Exported_Functions
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified RTC interrupts.
|
||||
/// @param it: specifies the RTC interrupts sources to be enabled or
|
||||
/// disabled.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @arg RTC_IT_OW: Overflow interrupt
|
||||
/// @arg RTC_IT_ALR: Alarm interrupt
|
||||
/// @arg RTC_IT_SEC: Second interrupt
|
||||
/// @param state: new state of the specified RTC interrupts.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RTC_ITConfig(RTC_IT_TypeDef it, FunctionalState state)
|
||||
{
|
||||
(state == ENABLE) ? (RTC->CR |= it) : (RTC->CR &= (u16)~it);
|
||||
// RTC_WaitForLastTask();
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enters the RTC configuration mode.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RTC_EnterConfigMode(void)
|
||||
{
|
||||
// PWR->CR |= PWR_CR_DBP;
|
||||
RTC->CSR |= RTC_CSR_CNF;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Exits from the RTC configuration mode.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RTC_ExitConfigMode(void)
|
||||
{
|
||||
RTC->CSR &= ~RTC_CSR_CNF;
|
||||
while (!(RTC->CSR & RTC_CSR_RTOFF));
|
||||
// PWR->CR &= ~PWR_CR_DBP;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Gets the RTC counter value.
|
||||
/// @param None.
|
||||
/// @retval RTC counter value.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 RTC_GetCounter(void)
|
||||
{
|
||||
u32 dat = RTC->CNTH << 16;
|
||||
return (RTC->CNTL | dat);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Sets the RTC counter value.
|
||||
/// @param count: RTC counter new value.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RTC_SetCounter(u32 count)
|
||||
{
|
||||
RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
|
||||
RTC->CNTH = count >> 16;
|
||||
RTC->CNTL = count;
|
||||
RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
|
||||
// while (!(RTC->CSR & RTC_CSR_RTOFF));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Sets the RTC prescaler value.
|
||||
/// @param prescaler: RTC prescaler new value.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RTC_SetPrescaler(u32 prescaler)
|
||||
{
|
||||
RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
|
||||
RTC->PRLH = prescaler >> 16;
|
||||
RTC->PRLL = prescaler;
|
||||
RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
|
||||
// while (!(RTC->CSR & RTC_CSR_RTOFF));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Sets the RTC alarm value.
|
||||
/// @param alarm: RTC alarm new value.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RTC_SetAlarm(u32 alarm)
|
||||
{
|
||||
RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
|
||||
RTC->ALRH = alarm >> 16;
|
||||
RTC->ALRL = alarm;
|
||||
RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
|
||||
// while (!(RTC->CSR & RTC_CSR_RTOFF));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Gets the RTC divider value.
|
||||
/// @param None.
|
||||
/// @retval RTC Divider value.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 RTC_GetDivider(void)
|
||||
{
|
||||
u32 dat = ((u32)(RTC->DIVH & RTC_DIVH_DIV) << 16);
|
||||
return (RTC->DIVL | dat);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Waits until last write operation on RTC registers has finished.
|
||||
/// @note This function must be called before any write to RTC registers.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RTC_WaitForLastTask(void)
|
||||
{
|
||||
while (!(RTC->CSR & RTC_CSR_RTOFF));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
|
||||
/// are synchronized with RTC APB clock.
|
||||
/// @note This function must be called before any read operation after an APB
|
||||
/// reset or an APB clock stop.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RTC_WaitForSynchro(void)
|
||||
{
|
||||
RTC->CSR &= ~RTC_CSR_RSF;
|
||||
while (!(RTC->CSR & RTC_CSR_RSF));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified RTC flag is set or not.
|
||||
/// @param flag: specifies the flag to check.
|
||||
/// This parameter can be one the following values:
|
||||
/// @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
|
||||
/// @arg RTC_FLAG_RSF: Registers Synchronized flag
|
||||
/// @arg RTC_FLAG_OW: Overflow flag
|
||||
/// @arg RTC_FLAG_ALR: Alarm flag
|
||||
/// @arg RTC_FLAG_SEC: Second flag
|
||||
/// @retval The state of RTC_FLAG (SET or RESET).
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus RTC_GetFlagStatus(RTC_FLAG_TypeDef flag)
|
||||
{
|
||||
return (FlagStatus)(RTC->CSR & flag);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the RTC's pending flags.
|
||||
/// @param flag: specifies the flag to clear.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only
|
||||
/// after an APB reset or an APB Clock stop.
|
||||
/// @arg RTC_FLAG_OW: Overflow flag
|
||||
/// @arg RTC_FLAG_ALR: Alarm flag
|
||||
/// @arg RTC_FLAG_SEC: Second flag
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RTC_ClearFlag(RTC_FLAG_TypeDef flag)
|
||||
{
|
||||
RTC->CSR &= ~flag;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified RTC interrupt has occurred or not.
|
||||
/// @param it: specifies the RTC interrupts sources to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg RTC_IT_OW: Overflow interrupt
|
||||
/// @arg RTC_IT_ALR: Alarm interrupt
|
||||
/// @arg RTC_IT_SEC: Second interrupt
|
||||
/// @retval The state of the RTC_IT (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
ITStatus RTC_GetITStatus(RTC_IT_TypeDef it)
|
||||
{
|
||||
return (ITStatus)(RTC->CSR & it);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the RTC's interrupt pending bits.
|
||||
/// @param it: specifies the interrupt pending bit to clear.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @arg RTC_IT_OW: Overflow interrupt
|
||||
/// @arg RTC_IT_ALR: Alarm interrupt
|
||||
/// @arg RTC_IT_SEC: Second interrupt
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void RTC_ClearITPendingBit(RTC_IT_TypeDef it)
|
||||
{
|
||||
// RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
|
||||
RTC->CSR &= ~it;
|
||||
// RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
|
||||
}
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
@@ -0,0 +1,527 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_sdio.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE SDIO FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_SDIO_C_
|
||||
#include "reg_sdio.h"
|
||||
#include "hal_sdio.h"
|
||||
#include "hal_rcc.h"
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup SDIO_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup SDIO_Exported_Functions
|
||||
/// @{
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Deinitializes the SDIO peripheral registers to their default reset
|
||||
/// values.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SDIO_DeInit(void)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBRSTR_SDIO, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBRSTR_SDIO, DISABLE);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Fills each SDIO_InitStruct member with its default value.
|
||||
/// @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
|
||||
/// will be initialized.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
|
||||
{
|
||||
// SDIO_InitStruct members default value
|
||||
SDIO_InitStruct->SDIO_MDEN = 0;
|
||||
SDIO_InitStruct->SDIO_DATWT = 0;
|
||||
SDIO_InitStruct->SDIO_SelPTSM = 0;
|
||||
SDIO_InitStruct->SDIO_CLKSP = 0;
|
||||
SDIO_InitStruct->SDIO_OUTM = 0;
|
||||
SDIO_InitStruct->SDIO_SelSM = 0;
|
||||
SDIO_InitStruct->SDIO_OPMSel = 0;
|
||||
}
|
||||
|
||||
|
||||
///
|
||||
/// @brief Fills each SDIO_DataInitStruct member with its default value.
|
||||
/// @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
|
||||
/// will be initialized.
|
||||
/// @retval None
|
||||
///
|
||||
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
|
||||
{
|
||||
/* SDIO_DataInitStruct members default value */
|
||||
SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
|
||||
SDIO_DataInitStruct->SDIO_DataLength = 0x00;
|
||||
SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
|
||||
SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
|
||||
// SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
|
||||
// SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
|
||||
}
|
||||
|
||||
///
|
||||
/// @brief Initializes the SDIO data path according to the specified
|
||||
/// parameters in the SDIO_DataInitStruct.
|
||||
/// @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
|
||||
/// contains the configuration information for the SDIO command.
|
||||
/// @retval None
|
||||
///
|
||||
//void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
|
||||
//{
|
||||
// u32 tmpreg = 0;
|
||||
|
||||
// /*---------------------------- SDIO DTIMER Configuration ---------------------*/
|
||||
// /* Set the SDIO Data TimeOut value */
|
||||
// SDIO->MMC_TIMEOUTCNT = SDIO_DataInitStruct->SDIO_DataTimeOut;
|
||||
|
||||
// /*---------------------------- SDIO DLEN Configuration -----------------------*/
|
||||
// /* Set the SDIO DataLength value */
|
||||
// SDIO->MMC_BYTECNTL = SDIO_DataInitStruct->SDIO_DataLength;
|
||||
|
||||
// /*---------------------------- SDIO DCTRL Configuration ----------------------*/
|
||||
// /* Get the SDIO DCTRL value */
|
||||
// tmpreg = SDIO->DCTRL;
|
||||
// /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
|
||||
// tmpreg &= DCTRL_CLEAR_MASK;
|
||||
// /* Set DEN bit according to SDIO_DPSM value */
|
||||
// /* Set DTMODE bit according to SDIO_TransferMode value */
|
||||
// /* Set DTDIR bit according to SDIO_TransferDir value */
|
||||
// /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
|
||||
// tmpreg |= (u32)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir;//
|
||||
// //| SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
|
||||
|
||||
// /* Write to SDIO DCTRL */
|
||||
// SDIO->DCTRL = tmpreg;
|
||||
//}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief The frequency division factor is configured to generate the SDIO clock.
|
||||
/// @param value : 1MHz = Fhclk/((mmc_cardsel[5 : 0] + 1) × 2)
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SDIO_ClockSet(u32 value)
|
||||
{
|
||||
// SDIO->MMC_CARDSEL &= ~SDIO_MMC_CARDSEL_MASK;
|
||||
SDIO->MMC_CARDSEL = (SDIO_MMC_CARDSEL_CTREN | SDIO_MMC_CARDSEL_ENPCLK | (value & 0x3F));
|
||||
// SDIO->MMC_CARDSEL = 0xC0+0x2F;//0xdf;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Initializes the SDIO peripheral according to the specified
|
||||
/// parameters in the SDIO_InitStruct.
|
||||
/// @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
|
||||
/// that contains the configuration information for the SDIO peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
|
||||
{
|
||||
SDIO->MMC_CTRL &= 0x700;
|
||||
SDIO->MMC_CTRL |= (SDIO_InitStruct->SDIO_OPMSel | SDIO_InitStruct->SDIO_SelSM |
|
||||
SDIO_InitStruct->SDIO_OUTM | SDIO_InitStruct->SDIO_CLKSP |
|
||||
SDIO_InitStruct->SDIO_SelPTSM | SDIO_InitStruct->SDIO_DATWT |
|
||||
SDIO_InitStruct->SDIO_MDEN);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the SDIO interrupts.
|
||||
/// @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
|
||||
/// state : new state of the specified SDIO interrupts.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SDIO_ITConfig(u32 SDIO_IT, FunctionalState state)
|
||||
{
|
||||
(state) ? (SDIO->MMC_INT_MASK |= SDIO_IT) : (SDIO->MMC_INT_MASK &= ~SDIO_IT);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the SDIO CRC.
|
||||
/// @param SDIO_CRC: specifies the SDIO CRC sources to be enabled or disabled.
|
||||
/// state : new state of the specified SDIO CRC.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SDIO_CRCConfig(u32 SDIO_CRC, FunctionalState state)
|
||||
{
|
||||
(state) ? (SDIO->MMC_CRCCTL |= SDIO_CRC) : (SDIO->MMC_CRCCTL &= ~SDIO_CRC);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Port transfer speed mode.
|
||||
/// @param clkdiv : High/low speed.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SDIO_Clock_Set(u8 clkdiv)
|
||||
{
|
||||
SDIO->MMC_CTRL &= ~SDIO_MMC_CTRL_SelPTSM;
|
||||
(clkdiv) ? (SDIO->MMC_CTRL |= SDIO_MMC_CTRL_SelPTSM) : (SDIO->MMC_CTRL &= ~SDIO_MMC_CTRL_SelPTSM);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Turn off the SDIO switch.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
SD_Error SD_PowerOFF(void)
|
||||
{
|
||||
SDIO->MMC_CARDSEL &= ~(SDIO_MMC_CARDSEL_ENPCLK | SDIO_MMC_CARDSEL_CTREN);
|
||||
return SD_OK;
|
||||
}
|
||||
///
|
||||
/// @brief Fills each SDIO_CmdInitStruct member with its default value.
|
||||
/// @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
|
||||
/// structure which will be initialized.
|
||||
/// @retval None
|
||||
///
|
||||
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
|
||||
{
|
||||
/* SDIO_CmdInitStruct members default value */
|
||||
SDIO_CmdInitStruct->SDIO_Argument = 0x00;
|
||||
SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
|
||||
SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
|
||||
SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
|
||||
// SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SDIO sends command functions.
|
||||
/// @param cmdindex : Type the command.
|
||||
/// waitrsp : Expected correspondence.
|
||||
/// arg : parameter.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SDIO_Send_Cmd(u8 cmdindex, u8 waitrsp, u32 arg)
|
||||
{
|
||||
SDIO->CMD_BUF0 = (arg >> 0) & 0xFF;
|
||||
SDIO->CMD_BUF1 = (arg >> 8) & 0xFF;
|
||||
SDIO->CMD_BUF2 = (arg >> 16) & 0xFF;
|
||||
SDIO->CMD_BUF3 = (arg >> 24) & 0xFF;
|
||||
SDIO->CMD_BUF4 = 0x40 | cmdindex;
|
||||
SDIO->CLR_MMC_INT |= 0;
|
||||
SDIO->MMC_IO = SDIO_MMC_IO_AUTOTR;
|
||||
while(1) {
|
||||
if(SDIO->CLR_MMC_INT & SDIO_CLR_MMC_INT_CMDDMC) {
|
||||
SDIO->CLR_MMC_INT |= SDIO_CLR_MMC_INT_CMDDMC;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(waitrsp == SDIO_Response_Short) {
|
||||
SDIO->MMC_IO = SDIO_MMC_IO_AUTOCLKG | \
|
||||
SDIO_MMC_IO_AUTOTR | \
|
||||
SDIO_MMC_IO_RESPCMDSEL;
|
||||
}
|
||||
else if(waitrsp == SDIO_Response_Long) {
|
||||
SDIO->MMC_IO = SDIO_MMC_IO_AUTOCLKG | \
|
||||
SDIO_MMC_IO_AUTOTR | \
|
||||
SDIO_MMC_IO_RESPCMDSEL | \
|
||||
SDIO_MMC_IO_CID_CSDRD;
|
||||
}
|
||||
else {
|
||||
}
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Check the execution status of CMD0.
|
||||
/// @param None.
|
||||
/// @retval card error code.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
SD_Error CmdError(void)
|
||||
{
|
||||
SD_Error errorstatus = SD_OK;
|
||||
u32 timeout = SDIO_CMD0TIMEOUT;
|
||||
while (timeout--) {
|
||||
if(((SDIO->MMC_IO & SDIO_MMC_IO_RESPCMDSEL) == 0) && ((SDIO->MMC_IO & SDIO_MMC_IO_AUTOTR) == 0))
|
||||
break;
|
||||
}
|
||||
if (timeout == 0)
|
||||
return SD_CMD_RSP_TIMEOUT;
|
||||
SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
|
||||
return errorstatus;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Check the error status of the R1 response.
|
||||
/// @param cmd : Current command.
|
||||
/// @retval card error code.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
SD_Error CmdResp1Error(u8 cmd)
|
||||
{
|
||||
u32 status;
|
||||
u32 response;
|
||||
while(1) {
|
||||
status = SDIO->CLR_MMC_INT ;
|
||||
if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
|
||||
break;
|
||||
}
|
||||
if(status & SDIO_CLR_MMC_INT_CRNTMC) {
|
||||
SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
|
||||
return SD_CMD_RSP_TIMEOUT;
|
||||
}
|
||||
if(status & (SDIO_CLR_MMC_INT_CRCEMC)) {
|
||||
SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC;
|
||||
return SD_CMD_CRC_FAIL;
|
||||
}
|
||||
SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
|
||||
|
||||
if((SDIO->CMD_BUF4 & 0x3F) != cmd) {
|
||||
return SD_ILLEGAL_CMD;
|
||||
}
|
||||
response = SDIO->CMD_BUF3 << 24 | SDIO->CMD_BUF2 << 16 | SDIO->CMD_BUF1 << 8 | SDIO->CMD_BUF0;
|
||||
return (SD_Error)(response & SD_OCR_ERRORBITS);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Check the execution status of CMD2.
|
||||
/// @param None.
|
||||
/// @retval card error code.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
SD_Error CmdResp2Error(void)
|
||||
{
|
||||
SD_Error errorstatus = SD_OK;
|
||||
u32 status;
|
||||
u32 timeout = SDIO_CMD0TIMEOUT;
|
||||
while(timeout--) {
|
||||
status = SDIO->CLR_MMC_INT ;
|
||||
if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
|
||||
break;
|
||||
}
|
||||
if((timeout == 0) || (status & SDIO_CLR_MMC_INT_CRNTMC)) {
|
||||
errorstatus = SD_CMD_RSP_TIMEOUT;
|
||||
SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
|
||||
return errorstatus;
|
||||
}
|
||||
if(status & SDIO_CLR_MMC_INT_CRCEMC) {
|
||||
errorstatus = SD_CMD_CRC_FAIL;
|
||||
SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC;
|
||||
}
|
||||
SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
|
||||
return errorstatus;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Check the execution status of CMD3.
|
||||
/// @param None.
|
||||
/// @retval card error code.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
SD_Error CmdResp3Error(void)
|
||||
{
|
||||
u32 status;
|
||||
while(1) {
|
||||
status = SDIO->CLR_MMC_INT ;
|
||||
if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
|
||||
break;
|
||||
}
|
||||
if(status & SDIO_CLR_MMC_INT_CRNTMC) {
|
||||
SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
|
||||
return SD_CMD_RSP_TIMEOUT;
|
||||
}
|
||||
SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
|
||||
return SD_OK;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Check the execution status of CMD6.
|
||||
/// @param None.
|
||||
/// @retval card error code.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
SD_Error CmdResp6Error(u8 cmd, u16* prca)
|
||||
{
|
||||
SD_Error errorstatus = SD_OK;
|
||||
u32 status;
|
||||
u32 rspr1;
|
||||
while(1) {
|
||||
status = SDIO->CLR_MMC_INT ;
|
||||
if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
|
||||
break;
|
||||
}
|
||||
if(status & SDIO_CLR_MMC_INT_CRNTMC) {
|
||||
SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
|
||||
return SD_CMD_RSP_TIMEOUT;
|
||||
}
|
||||
if(status & SDIO_CLR_MMC_INT_CRCEMC) {
|
||||
SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC;
|
||||
return SD_CMD_CRC_FAIL;
|
||||
}
|
||||
if((SDIO->CMD_BUF4 & 0x3F) != cmd) {
|
||||
return SD_ILLEGAL_CMD;
|
||||
}
|
||||
SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
|
||||
rspr1 = SDIO->CMD_BUF3 << 24 | SDIO->CMD_BUF2 << 16 | SDIO->CMD_BUF1 << 8 | SDIO->CMD_BUF0;
|
||||
if(SD_ALLZERO == (rspr1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED))) {
|
||||
*prca = (u16)(rspr1 >> 16);
|
||||
return errorstatus;
|
||||
}
|
||||
if(rspr1 & SD_R6_GENERAL_UNKNOWN_ERROR) {
|
||||
return SD_GENERAL_UNKNOWN_ERROR;
|
||||
}
|
||||
if(rspr1 & SD_R6_ILLEGAL_CMD) {
|
||||
return SD_ILLEGAL_CMD;
|
||||
}
|
||||
if(rspr1 & SD_R6_COM_CRC_FAILED) {
|
||||
return SD_COM_CRC_FAILED;
|
||||
}
|
||||
return errorstatus;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Check the execution status of CMD7.
|
||||
/// @param None.
|
||||
/// @retval card error code.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
SD_Error CmdResp7Error(void)
|
||||
{
|
||||
SD_Error errorstatus = SD_OK;
|
||||
u32 status;
|
||||
u32 timeout = SDIO_CMD0TIMEOUT;
|
||||
while(timeout--) {
|
||||
status = SDIO->CLR_MMC_INT ;
|
||||
if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
|
||||
break;
|
||||
}
|
||||
if((timeout == 0) || (status & SDIO_CLR_MMC_INT_CRNTMC)) { //timeout
|
||||
errorstatus = SD_CMD_RSP_TIMEOUT;
|
||||
SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
|
||||
return errorstatus;
|
||||
}
|
||||
if(status & SDIO_CLR_MMC_INT_CMDDMC) {
|
||||
errorstatus = SD_OK;
|
||||
SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CMDDMC;
|
||||
}
|
||||
return errorstatus;
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Write data direction block size configuration.
|
||||
/// @param datatimeout : maximum latency.
|
||||
/// datalen : data len
|
||||
/// blksize : block count.
|
||||
/// dir : direction
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SDIO_Send_Data_Cfg(u32 datatimeout, u32 datalen, u8 blksize, u8 dir)
|
||||
{
|
||||
u32 tmpreg, tmpreg1, tmpreg2 = 0;
|
||||
tmpreg = SDIO->MMC_IO_MBCTL;
|
||||
tmpreg1 = SDIO->MMC_IO;
|
||||
tmpreg &= ~(SDIO_MMC_IO_MBCTL_BTSSel | SDIO_MMC_IO_MBCTL_SPMBDTR | SDIO_MMC_IO_MBCTL_SMBDTD);
|
||||
if (datatimeout < 100) {
|
||||
SDIO->MMC_TIMEOUTCNT = datatimeout;
|
||||
}
|
||||
else if (datatimeout < 10000) {
|
||||
SDIO->MMC_TIMEOUTCNT = datatimeout / 100;
|
||||
tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel;
|
||||
}
|
||||
else if (datatimeout < 1000000) {
|
||||
SDIO->MMC_TIMEOUTCNT = datatimeout / 10000;
|
||||
tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel_2;
|
||||
}
|
||||
else {
|
||||
SDIO->MMC_TIMEOUTCNT = datatimeout / 1000000;
|
||||
tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel;
|
||||
}
|
||||
SDIO->MMC_BYTECNTL = datalen & 0x1FFFFFF; ;
|
||||
SDIO->MMC_BLOCKCNT = blksize;
|
||||
if (dir == 0) {
|
||||
tmpreg |= SDIO_MMC_IO_MBCTL_SMBDTD;
|
||||
tmpreg1 |= SDIO_MMC_IO_TRANSFDIR;
|
||||
tmpreg2 |= SDIO_BUF_CTLL_SBAD;
|
||||
}
|
||||
else {
|
||||
tmpreg &= ~(SDIO_MMC_IO_MBCTL_SMBDTD);
|
||||
tmpreg1 &= ~(SDIO_MMC_IO_TRANSFDIR);
|
||||
tmpreg2 &= ~(SDIO_BUF_CTLL_SBAD);
|
||||
}
|
||||
SDIO->MMC_IO_MBCTL = tmpreg;
|
||||
SDIO->MMC_IO = tmpreg1;
|
||||
SDIO->BUF_CTL = tmpreg2;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the SDIO's Flag pending bits.
|
||||
/// @param SDIO_IT: specifies the flag pending bit to clear.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SDIO_ClearFlag(u32 SDIO_FLAG)
|
||||
{
|
||||
SDIO->CLR_MMC_INT |= SDIO_FLAG;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the SDIO's interrupt pending bits.
|
||||
/// @param SDIO_IT: specifies the interrupt pending bit to clear.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SDIO_ClearITPendingBit(u32 SDIO_IT)
|
||||
{
|
||||
SDIO->CLR_MMC_INT |= SDIO_IT;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified SDIO flag is set or not.
|
||||
/// @param SDIO_FLAG: specifies the flag to check.
|
||||
/// @retval The new state of SDIO_FLAG (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG)
|
||||
{
|
||||
return ((SDIO->CLR_MMC_INT & SDIO_FLAG) ? SET : RESET);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Reads the value of the data transfer timeout count
|
||||
/// @param None.
|
||||
/// @retval timeout count.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 SDIO_GetTimeOutCounter(void)
|
||||
{
|
||||
return (SDIO->MMC_TIMEOUTCNT & 0xFF);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Read one data word from FIFO.
|
||||
/// @param None.
|
||||
/// @retval Data received.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 SDIO_ReadData(void)
|
||||
{
|
||||
return SDIO->FIFO;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Write one data word to FIFO.
|
||||
/// @param tempbuff : Write data.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SDIO_WriteData(u32 tempbuff)
|
||||
{
|
||||
SDIO->FIFO = tempbuff;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns number of remaining data bytes to be transferred.
|
||||
/// @param None
|
||||
/// @retval Number of remaining data bytes to be transferred
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 SDIO_GetDataCounter(void)
|
||||
{
|
||||
return SDIO->MMC_BYTECNTL;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enable or Dsiable DMA .
|
||||
/// @param tempbuff : Write data.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SDIO_DMACmd(FunctionalState state)
|
||||
{
|
||||
(state) ? ((SDIO->BUF_CTL |= SDIO_BUF_CTLL_DMAHEN), SDIO->BUF_CTL &= (~(SDIO_BUF_CTLL_DRM))) : (SDIO->BUF_CTL &= ~SDIO_BUF_CTLL_DMAHEN);
|
||||
}
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
@@ -0,0 +1,648 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_spi.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE SPI FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_SPI_C_
|
||||
#include <math.h>
|
||||
// Files includes
|
||||
#include "hal_spi.h"
|
||||
#include "hal_rcc.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup SPI_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///@addtogroup SPI_Exported_Functions
|
||||
///@{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Deinitializes the spi peripheral registers to their
|
||||
/// default reset values.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SPI_DeInit(SPI_TypeDef* spi)
|
||||
{
|
||||
switch (*(vu32*)&spi) {
|
||||
case (u32)SPI2: // SPI2_BASE:
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI2, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI2, DISABLE);
|
||||
break;
|
||||
case (u32)SPI3: // SPI3_BASE:
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI3, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI3, DISABLE);
|
||||
break;
|
||||
case (u32)SPI1: // SPI1_BASE:
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2ENR_SPI1, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2ENR_SPI1, DISABLE);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Initializes the spi peripheral according to the specified
|
||||
/// parameters in the init_struct .
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param init_struct: pointer to a SPI_InitTypeDef structure
|
||||
/// that contains the configuration information for the
|
||||
/// specified SPI peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SPI_Init(SPI_TypeDef* spi, SPI_InitTypeDef* init_struct)
|
||||
{
|
||||
if (init_struct->SPI_DataSize == SPI_DataSize_32b) {
|
||||
SET_BIT(spi->GCR, SPI_GCR_DWSEL);
|
||||
}
|
||||
else {
|
||||
CLEAR_BIT(spi->GCR, SPI_GCR_DWSEL);
|
||||
}
|
||||
MODIFY_REG(spi->GCR, SPI_GCR_NSS, init_struct->SPI_NSS);
|
||||
MODIFY_REG(spi->GCR, SPI_GCR_MODE, init_struct->SPI_Mode);
|
||||
MODIFY_REG(spi->CCR, SPI_CCR_LSBFE, init_struct->SPI_FirstBit);
|
||||
MODIFY_REG(spi->CCR, SPI_CCR_CPOL, init_struct->SPI_CPOL);
|
||||
MODIFY_REG(spi->CCR, SPI_CCR_CPHA, init_struct->SPI_CPHA);
|
||||
|
||||
SET_BIT(spi->CCR, SPI_CCR_SPILEN);
|
||||
|
||||
MODIFY_REG(spi->BRR, BRR_Mask, init_struct->SPI_BaudRatePrescaler);
|
||||
|
||||
if (init_struct->SPI_DataWidth >= 32) {
|
||||
MODIFY_REG(spi->ECR, ECR_Mask, 0);
|
||||
}
|
||||
else {
|
||||
MODIFY_REG(spi->ECR, ECR_Mask, init_struct->SPI_DataWidth);
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Fills each init_struct member with its default value.
|
||||
/// @param init_struct: pointer to a SPI_InitTypeDef structure
|
||||
/// which will be initialized.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SPI_StructInit(SPI_InitTypeDef* init_struct)
|
||||
{
|
||||
init_struct->SPI_Mode = SPI_Mode_Slave;
|
||||
init_struct->SPI_DataSize = SPI_DataSize_8b;
|
||||
init_struct->SPI_DataWidth = 8;
|
||||
init_struct->SPI_CPOL = SPI_CPOL_Low;
|
||||
init_struct->SPI_CPHA = SPI_CPHA_1Edge;
|
||||
init_struct->SPI_NSS = SPI_NSS_Soft;
|
||||
init_struct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
|
||||
init_struct->SPI_FirstBit = SPI_FirstBit_MSB;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified SPI peripheral.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param state: new state of the spi peripheral.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SPI_Cmd(SPI_TypeDef* spi, FunctionalState state)
|
||||
{
|
||||
(state) ? SET_BIT(spi->GCR, SPI_GCR_SPIEN) : CLEAR_BIT(spi->GCR, SPI_GCR_SPIEN);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified SPI interrupts.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:SPI1, SPI2.
|
||||
/// @param interrupt: specifies the SPI interrupt sources to be
|
||||
/// enabled or disabled.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg SPI_IT_TXEPT: Transmitter empty interrupt
|
||||
/// @arg SPI_IT_RXFULL: RX FIFO full interrupt
|
||||
/// @arg SPI_IT_RXMATCH: Receive data match the RXDNR number interrupt
|
||||
/// @arg SPI_IT_RXOERR: Receive overrun error interrupt
|
||||
/// @arg SPI_IT_UNDERRUN: underrun interrupt
|
||||
/// @arg SPI_IT_RX: Receive data available interrupt
|
||||
/// @arg SPI_IT_TX: Transmit FIFO available interrupt
|
||||
/// @param state: new state of the specified spi interrupts.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SPI_ITConfig(SPI_TypeDef* spi, u8 interrupt, FunctionalState state)
|
||||
{
|
||||
if (state) {
|
||||
SET_BIT(spi->GCR, (u32)SPI_GCR_IEN);
|
||||
SET_BIT(spi->IER, (u32)interrupt);
|
||||
}
|
||||
else {
|
||||
CLEAR_BIT(spi->IER, interrupt);
|
||||
CLEAR_BIT(spi->GCR, SPI_GCR_IEN);
|
||||
}
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the SPI DMA interface.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param state: new state of the DMA Request sources.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SPI_DMACmd(SPI_TypeDef* spi, FunctionalState state)
|
||||
{
|
||||
(state) ? SET_BIT(spi->GCR, SPI_GCR_DMAEN) : CLEAR_BIT(spi->GCR, SPI_GCR_DMAEN);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief configure tn Fifo trigger level bit.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param fifo_trigger_value: specifies the Fifo trigger level
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// SPI_TXTLF : SPI TX FIFO Trigger value set
|
||||
/// SPI_RXTLF : SPI RX FIFO Trigger value set
|
||||
/// @param state: new state of the selected SPI transfer request.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SPI_FifoTrigger(SPI_TypeDef* spi, SPI_TLF_TypeDef fifo_trigger_value, FunctionalState state)
|
||||
{
|
||||
(state) ? SET_BIT(spi->GCR, (u32)fifo_trigger_value) : CLEAR_BIT(spi->GCR, (u32)fifo_trigger_value);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Transmits a Data through the spi peripheral.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param data : Data to be transmitted.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SPI_SendData(SPI_TypeDef* spi, u32 data)
|
||||
{
|
||||
u16 templen;
|
||||
__asm volatile("cpsid i");
|
||||
|
||||
WRITE_REG(spi->TDR, data);
|
||||
|
||||
templen = READ_REG(spi->ECR);
|
||||
if(templen == 0)
|
||||
templen = 32;
|
||||
if (templen > 8)
|
||||
WRITE_REG(spi->TDR, data >> 8);
|
||||
if (templen > 16)
|
||||
WRITE_REG(spi->TDR, data >> 16);
|
||||
if (templen > 24)
|
||||
WRITE_REG(spi->TDR, data >> 24);
|
||||
__asm volatile("cpsie i");
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the most recent received data by the spi peripheral.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @retval The value of the received data.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 SPI_ReceiveData(SPI_TypeDef* spi)
|
||||
{
|
||||
u32 temp;
|
||||
u8 templen;
|
||||
__asm volatile("cpsid i");
|
||||
|
||||
temp = READ_REG(spi->RDR);
|
||||
|
||||
templen = READ_REG(spi->ECR);
|
||||
if(templen == 0)
|
||||
templen = 32;
|
||||
if (templen > 8)
|
||||
temp |= (u32)(READ_REG(spi->RDR) << 8);
|
||||
if (templen > 16)
|
||||
temp |= (u32)(READ_REG(spi->RDR) << 16);
|
||||
if (templen > 24)
|
||||
temp |= (u32)(READ_REG(spi->RDR) << 24);
|
||||
|
||||
__asm volatile("cpsie i");
|
||||
|
||||
return temp;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Slave chip csn single by selected
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param state: new state of the selected SPI CS pin
|
||||
/// request.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state)
|
||||
{
|
||||
(state) ? CLEAR_BIT(spi->NSSR, SPI_NSSR_NSS) : SET_BIT(spi->NSSR, SPI_NSSR_NSS); // illogical
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the NSS pin control mode for the selected SPI.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param nss: specifies the SPI NSS internal state.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg SPI_NSS_Soft: NSS pin control by software
|
||||
/// @arg SPI_NSS_Hard: NSS pin control by hardware
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* spi, SPI_NSS_TypeDef nss)
|
||||
{
|
||||
(nss != SPI_NSS_Soft) ? SET_BIT(spi->GCR, SPI_NSS_Hard) : CLEAR_BIT(spi->GCR, SPI_NSS_Hard);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configures the data size for the selected SPI.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param data_size: specifies the SPI data size.
|
||||
/// This parameter can be one of the following values:
|
||||
/// 0 to 31, 0 = 32b, 1 = 1b, 2 = 2b
|
||||
/// @arg DataSize : 0 to 31
|
||||
/// @retval None.
|
||||
/// @retval None.
|
||||
bool SPI_DataSizeConfig(SPI_TypeDef* spi, u8 data_size)
|
||||
{
|
||||
if (data_size > 32)
|
||||
return false;
|
||||
data_size &= 0x1F;
|
||||
WRITE_REG(spi->ECR, data_size);
|
||||
return true;
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
void SPI_DataSizeTypeConfig(SPI_TypeDef* spi, SPI_DataSize_TypeDef SPI_DataSize)
|
||||
{
|
||||
CLEAR_BIT(spi->GCR, (u32)SPI_DataSize_32b);
|
||||
SET_BIT(spi->GCR, (u32)SPI_DataSize);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Selects the data transfer direction in bi-directional mode
|
||||
/// for the specified SPI.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param direction: specifies the data transfer direction in
|
||||
/// bi-directional mode.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg SPI_Direction_Tx: Selects Tx transmission direction
|
||||
/// @arg SPI_Direction_Rx: Selects Rx receive direction
|
||||
/// @arg SPI_Disable_Tx: Selects Rx receive direction
|
||||
/// @arg SPI_Disable_Rx: Selects Rx receive direction
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef* spi, SPI_Direction_TypeDef direction)
|
||||
{
|
||||
switch (direction) {
|
||||
case SPI_Direction_Rx:
|
||||
SET_BIT(spi->GCR, SPI_GCR_RXEN);
|
||||
break;
|
||||
case SPI_Direction_Tx:
|
||||
SET_BIT(spi->GCR, SPI_GCR_TXEN);
|
||||
break;
|
||||
case SPI_Disable_Rx:
|
||||
CLEAR_BIT(spi->GCR, SPI_GCR_RXEN);
|
||||
break;
|
||||
case SPI_Disable_Tx:
|
||||
CLEAR_BIT(spi->GCR, SPI_GCR_TXEN);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified SPI flag is set or not.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param flag: specifies the SPI flag to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg SPI_FLAG_RXAVL: Rx buffer has bytes flag
|
||||
/// @arg SPI_FLAG_TXEPT: Tx buffer and tx shifter empty flag
|
||||
/// @arg SPI_FLAG_TXFULL: Tx buffer full flag
|
||||
/// @arg SPI_FLAG_RXAVL_4BYTE: Receive available 4 byte data message flag.
|
||||
/// @retval The new state of SPI_FLAG (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus SPI_GetFlagStatus(SPI_TypeDef* spi, SPI_FLAG_TypeDef flag)
|
||||
{
|
||||
// u8 number;
|
||||
return (spi->SR & flag) ? SET : RESET;
|
||||
// if (spi->ECR == 8 || spi->ECR == 0)
|
||||
// return (spi->SR & SPI_FLAG) ? SET : RESET;
|
||||
// else {
|
||||
// if ((spi->ECR > 0) && (spi->ECR <= 8))
|
||||
// number = 1;
|
||||
// else if ((spi->ECR) <= 16)
|
||||
// number = 2;
|
||||
// else if ((spi->ECR) <= 24)
|
||||
// number = 3;
|
||||
// else if (((spi->ECR) <= 31) || (spi->ECR == 0))
|
||||
// number = 4;
|
||||
// return (((spi->SR & 0xf00) >> 8) >= number) ? SET : RESET;
|
||||
// }
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified SPI interrupt has occurred or not.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param interrupt: specifies the SPI interrupt source to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg SPI_IT_TX: Tx buffer empty interrupt
|
||||
/// @arg SPI_IT_RX: Rx buffer interrupt
|
||||
/// @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode
|
||||
/// @arg SPI_IT_RXOVER: RX OVER Error interrupt
|
||||
/// @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt
|
||||
/// @arg SPI_IT_RXFULL: Rx buffer full interrupt
|
||||
/// @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt
|
||||
/// @retval The new state of SPI_IT (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
ITStatus SPI_GetITStatus(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt)
|
||||
{
|
||||
return (spi->ISR & interrupt) ? SET : RESET;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the spi interrupt pending bit.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param interrupt: specifies the SPI interrupt pending bit to clear.
|
||||
/// @arg SPI_IT_TX: Tx buffer empty interrupt
|
||||
/// @arg SPI_IT_RX: Rx buffer interrupt
|
||||
/// @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode
|
||||
/// @arg SPI_IT_RXOVER: RX OVER Error interrupt
|
||||
/// @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt
|
||||
/// @arg SPI_IT_RXFULL: Rx buffer full interrupt
|
||||
/// @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt
|
||||
/// This function clears only ERR intetrrupt pending bit.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SPI_ClearITPendingBit(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt)
|
||||
{
|
||||
SET_BIT(spi->ICR, interrupt);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI Hole a count Received bytes in next receive process.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param number: specifies the SPI receive Number.
|
||||
/// This parament can be 1-65535.
|
||||
/// This function can use only in SPI master single receive mode.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SPI_RxBytes(SPI_TypeDef* spi, u16 number)
|
||||
{
|
||||
WRITE_REG(spi->RDNR, number);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief slave mode tx data transmit phase adjust set.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param adjust_value: slave mode tx data transmit phase adjust enum.
|
||||
/// This parament can be :
|
||||
/// SPI_SlaveAdjust_FAST: fast speed use
|
||||
/// SPI_SlaveAdjust_LOW: low speed use
|
||||
/// This function can use only in SPI master single receive mode.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void SPI_SlaveAdjust(SPI_TypeDef* spi, SPI_SlaveAdjust_TypeDef adjust_value)
|
||||
{
|
||||
(adjust_value) ? SET_BIT(spi->CCR, SPI_CCR_RXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_RXEDGE);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables all SPI interrupts.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param state: new state of all spi interrupts.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exSPI_ITCmd(SPI_TypeDef* spi, FunctionalState state)
|
||||
{
|
||||
(state) ? SET_BIT(spi->IER, (u32)SPI_GCR_IEN) : CLEAR_BIT(spi->IER, (u32)SPI_GCR_IEN);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified SPI interrupts.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param interrupt: specifies the SPI interrupt sources to be enabled or disabled.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg SPI_IT_TXEPT: Transmitter empty interrupt
|
||||
/// @arg SPI_IT_RXFULL: RX FIFO full interrupt
|
||||
/// @arg SPI_IT_RXMATCH: Receive data match the RXDNR number interrupt
|
||||
/// @arg SPI_IT_RXOERR: Receive overrun error interrupt
|
||||
/// @arg SPI_IT_UNDERRUN: underrun interrupt
|
||||
/// @arg SPI_IT_RX: Receive data available interrupt
|
||||
/// @arg SPI_IT_TX: Transmit FIFO available interrupt
|
||||
/// @param state: new state of the specified spi interrupts.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exSPI_ITConfig(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt, FunctionalState state)
|
||||
{
|
||||
(state) ? SET_BIT(spi->IER, (u32)interrupt) : CLEAR_BIT(spi->IER, (u32)interrupt);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the SPI DMA request.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param state: new state of the DMA Request.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exSPI_DMACmd(SPI_TypeDef* spi, FunctionalState state)
|
||||
{
|
||||
(state) ? SET_BIT(spi->GCR, SPI_GCR_DMAEN) : CLEAR_BIT(spi->GCR, SPI_GCR_DMAEN);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Set or reset Slave chip csn signal output
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param state: new state of Slave chip csn signal output.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exSPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state)
|
||||
{
|
||||
(state) ? CLEAR_BIT(spi->NSSR, SPI_NSSR_NSS) : SET_BIT(spi->NSSR, SPI_NSSR_NSS); // illogical
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief tx data and rx data phase adjust.
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2.
|
||||
/// @param adjust_value: choose adjust mode.
|
||||
/// This parament can be :
|
||||
/// SPI_DataEdgeAdjust_LOW,
|
||||
/// SPI_DataEdgeAdjust_FAST
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exSPI_DataEdgeAdjust(SPI_TypeDef* spi, SPI_DataEdgeAdjust_TypeDef adjust_value)
|
||||
{
|
||||
// master mode
|
||||
if (spi->GCR & SPI_GCR_MODE) {
|
||||
adjust_value ? SET_BIT(spi->CCR, SPI_CCR_RXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_RXEDGE);
|
||||
}
|
||||
// slave mode
|
||||
else {
|
||||
adjust_value ? SET_BIT(spi->CCR, SPI_CCR_TXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_TXEDGE);
|
||||
}
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Set or reset i2s
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2, SPI3.
|
||||
/// @param state: new state of Slave chip csn signal output.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2S_Cmd(SPI_TypeDef* spi, FunctionalState state)
|
||||
{
|
||||
(state) ? SET_BIT(spi->CFGR, I2S_CFGR_SPI_I2S) : CLEAR_BIT(spi->CFGR, I2S_CFGR_SPI_I2S);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief i2s Config
|
||||
/// @param spi: Select the SPI peripheral.
|
||||
/// This parameter can be one of the following values:
|
||||
/// SPI1, SPI2, SPI3.
|
||||
/// @param state: new state of Slave chip csn signal output.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2S_Init(SPI_TypeDef* spi, I2S_InitTypeDef* I2S_InitStruct)
|
||||
{
|
||||
u32 i2sdiv = 2;
|
||||
u32 tmpreg = 0;
|
||||
u32 packetlength = 1;
|
||||
u32 result = 0, yushu = 0;
|
||||
u32 sourceclock = 0;
|
||||
RCC_ClocksTypeDef RCC_Clocks;
|
||||
|
||||
if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) {
|
||||
i2sdiv = 2;
|
||||
}
|
||||
else {
|
||||
if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) {
|
||||
packetlength = 1;
|
||||
}
|
||||
else {
|
||||
packetlength = 2;
|
||||
}
|
||||
RCC_GetClocksFreq(&RCC_Clocks);
|
||||
|
||||
if((SPI2 == spi) || (SPI3 == spi)) {
|
||||
sourceclock = RCC_Clocks.PCLK1_Frequency;
|
||||
}
|
||||
else {
|
||||
sourceclock = RCC_Clocks.PCLK2_Frequency;
|
||||
}
|
||||
if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) {
|
||||
result = (sourceclock) / (256 * (I2S_InitStruct->I2S_AudioFreq));
|
||||
yushu = (sourceclock) % (256 * (I2S_InitStruct->I2S_AudioFreq));
|
||||
if(yushu > (128 * (I2S_InitStruct->I2S_AudioFreq))) {
|
||||
result = result + 1;
|
||||
}
|
||||
i2sdiv = result;
|
||||
if ((i2sdiv < 2) || (i2sdiv > 0x1FF)) {
|
||||
i2sdiv = 2;
|
||||
}
|
||||
}
|
||||
else {
|
||||
result = (sourceclock) / (16 * 2 * packetlength * (I2S_InitStruct->I2S_AudioFreq));
|
||||
yushu = (sourceclock) % (16 * 2 * packetlength * (I2S_InitStruct->I2S_AudioFreq));
|
||||
if(yushu > ((16 * packetlength * (I2S_InitStruct->I2S_AudioFreq)))) {
|
||||
result = result + 1;
|
||||
}
|
||||
if ((i2sdiv < 1) || (i2sdiv > 0x1FF)) {
|
||||
i2sdiv = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
if(I2S_CPOL_High == I2S_InitStruct->I2S_CPOL) {
|
||||
spi->CCTL |= SPI_CCR_CPOL;
|
||||
}
|
||||
else {
|
||||
spi->CCTL &= ~SPI_CCR_CPOL;
|
||||
}
|
||||
|
||||
spi->CFGR = 0x2 << I2S_CFGR_I2SDIV_Pos;
|
||||
|
||||
if((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx)) {
|
||||
spi->GCTL |= SPI_GCR_MODE;
|
||||
}
|
||||
else {
|
||||
spi->GCTL &= ~SPI_GCR_MODE;
|
||||
}
|
||||
if((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx)) {
|
||||
spi->GCTL |= SPI_GCR_TXEN;
|
||||
spi->GCTL &= ~SPI_GCR_RXEN;
|
||||
}
|
||||
else {
|
||||
spi->GCTL &= ~SPI_GCR_TXEN;
|
||||
spi->GCTL |= SPI_GCR_RXEN;
|
||||
}
|
||||
// tmpreg = spi->GCTL;
|
||||
// tmpreg &= ~(1 << 2);
|
||||
// tmpreg |= (u16)(I2S_InitStruct->I2S_Mode);
|
||||
// spi->GCTL = tmpreg;
|
||||
//
|
||||
tmpreg = 0;
|
||||
tmpreg |= (i2sdiv << I2S_CFGR_I2SDIV_Pos) | \
|
||||
(I2S_InitStruct->I2S_MCLKOutput) | \
|
||||
(I2S_CFGR_SPI_I2S) | \
|
||||
(I2S_InitStruct->I2S_Standard) | \
|
||||
(I2S_InitStruct->I2S_DataFormat);
|
||||
spi->CFGR &= ~I2S_CFGR_I2SDIV;
|
||||
spi->CFGR |= tmpreg;
|
||||
|
||||
}
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,502 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_uart.c
|
||||
/// @file hal_uart.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE UART FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_UART_C_
|
||||
|
||||
// Files includes
|
||||
#include "hal_rcc.h"
|
||||
#include "hal_uart.h"
|
||||
#include "hal_gpio.h"
|
||||
#include "hal_dma.h"
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///@addtogroup UART_HAL
|
||||
///@{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup UART_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Deinitializes the uart peripheral registers to their
|
||||
/// default reset values.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_DeInit(UART_TypeDef* uart)
|
||||
{
|
||||
|
||||
|
||||
if(UART2 == uart) {
|
||||
exRCC_APB1PeriphReset(RCC_APB1ENR_UART2);
|
||||
}
|
||||
if(UART1 == uart) {
|
||||
exRCC_APB2PeriphReset(RCC_APB2ENR_UART1);
|
||||
}
|
||||
if(UART3 == uart) {
|
||||
exRCC_APB1PeriphReset(RCC_APB1ENR_UART3);
|
||||
}
|
||||
if(UART4 == uart) {
|
||||
exRCC_APB1PeriphReset(RCC_APB1ENR_UART4);
|
||||
}
|
||||
if(UART5 == uart) {
|
||||
exRCC_APB1PeriphReset(RCC_APB1ENR_UART5);
|
||||
}
|
||||
if(UART6 == uart) {
|
||||
exRCC_APB2PeriphReset(RCC_APB2ENR_UART6);
|
||||
}
|
||||
if(UART7 == uart) {
|
||||
exRCC_APB1PeriphReset(RCC_APB1ENR_UART7);
|
||||
}
|
||||
if(UART8 == uart) {
|
||||
exRCC_APB1PeriphReset(RCC_APB1ENR_UART8);
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Initializes the uart peripheral according to the specified
|
||||
/// parameters in the UART_InitStruct .
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param init_struct: pointer to a UART_InitTypeDef structure
|
||||
/// that contains the configuration information for the
|
||||
/// specified UART peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_Init(UART_TypeDef* uart, UART_InitTypeDef* init_struct)
|
||||
{
|
||||
u32 apbclock = 0x00;
|
||||
// UART CCR Configuration
|
||||
MODIFY_REG(uart->CCR, UART_CCR_CHAR, init_struct->WordLength);
|
||||
|
||||
|
||||
MODIFY_REG(uart->CCR, (UART_CCR_SPB0 | UART_CCR_SPB1), init_struct->StopBits);
|
||||
|
||||
MODIFY_REG(uart->CCR, (UART_CCR_PEN | UART_CCR_PSEL), init_struct->Parity);
|
||||
|
||||
// UART GCR Configuration
|
||||
MODIFY_REG(uart->GCR, (UART_GCR_TX | UART_GCR_RX), init_struct->Mode);
|
||||
MODIFY_REG(uart->GCR, UART_GCR_AUTOFLOW, init_struct->HWFlowControl);
|
||||
|
||||
//UART BRR Configuration
|
||||
//Configure the UART Baud Rate
|
||||
if (uart == UART1) {
|
||||
|
||||
apbclock = RCC_GetPCLK2Freq();
|
||||
}
|
||||
else {
|
||||
apbclock = RCC_GetPCLK1Freq();
|
||||
}
|
||||
// Determine the UART_baud
|
||||
uart->BRR = (apbclock / init_struct->BaudRate) / 16;
|
||||
uart->FRA = (apbclock / init_struct->BaudRate) % 16;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Fills each UART_InitStruct member with its default value.
|
||||
/// @param init_struct: pointer to a UART_InitTypeDef structure
|
||||
/// which will be initialized.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_StructInit(UART_InitTypeDef* init_struct)
|
||||
{
|
||||
// UART_InitStruct members default value
|
||||
init_struct->BaudRate = 9600;
|
||||
init_struct->WordLength = UART_WordLength_8b;
|
||||
init_struct->StopBits = UART_StopBits_1;
|
||||
init_struct->Parity = UART_Parity_No;
|
||||
init_struct->Mode = UART_GCR_RX | UART_GCR_TX;
|
||||
init_struct->HWFlowControl = UART_HWFlowControl_None;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified UART peripheral.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param state: new state of the uart peripheral.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_Cmd(UART_TypeDef* uart, FunctionalState state)
|
||||
{
|
||||
MODIFY_REG(uart->GCR, UART_GCR_UART, state << UART_GCR_UART_Pos);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the specified UART interrupts.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param it: specifies the UART interrupt sources to be
|
||||
/// enabled or disabled.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg UART_IT_ERR: Error interrupt(Frame error,)
|
||||
/// @arg UART_IT_PE: Parity Error interrupt
|
||||
/// @arg UART_OVER_ERR: overrun Error interrupt
|
||||
/// @arg UART_IT_RXIEN: Receive Data register interrupt
|
||||
/// @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt
|
||||
///
|
||||
/// @param state: new state of the specified uart interrupts.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_ITConfig(UART_TypeDef* uart, u16 it, FunctionalState state)
|
||||
{
|
||||
(state) ? (uart->IER |= it) : (uart->IER &= ~it);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the UART DMA interface.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param dma_request: specifies the DMA request.
|
||||
/// This parameter can be any combination of the following values:
|
||||
/// @arg UART_DMAReq_EN: UART DMA transmit request
|
||||
///
|
||||
/// @param state: new state of the DMA Request sources.
|
||||
/// This parameter can be: ENABLE or DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_DMACmd(UART_TypeDef* uart, u16 dma_request, FunctionalState state)
|
||||
{
|
||||
MODIFY_REG(uart->GCR, UART_GCR_DMA, state << UART_GCR_DMA_Pos);
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Transmits single data through the uart peripheral.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param Data: the data to transmit.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_SendData(UART_TypeDef* uart, u16 value)
|
||||
{
|
||||
// Transmit Data
|
||||
WRITE_REG(uart->TDR, (value & 0xFFU));
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the most recent received data by the uart peripheral.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @retval The received data.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u16 UART_ReceiveData(UART_TypeDef* uart)
|
||||
{
|
||||
// Receive Data
|
||||
return (u16)(uart->RDR & 0xFFU);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified UART flag is set or not.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param flag: specifies the flag to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg UART_FLAG_TXEMPTY: Transmit data register empty flag
|
||||
/// @arg UART_FLAG_TXFULL: Transmit data buffer full
|
||||
/// @arg UART_FLAG_RXAVL: RX Buffer has a byte flag
|
||||
/// @arg UART_FLAG_TXEPT: tx and shifter are emptys flag
|
||||
/// @retval The new state of UART_FLAG (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus UART_GetFlagStatus(UART_TypeDef* uart, u16 flag)
|
||||
{
|
||||
return (uart->CSR & flag) ? SET : RESET;
|
||||
}
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the specified UART interrupt has occurred or not.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param it: specifies the UART interrupt source to check.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg UART_IT_ERR: Error interrupt(Frame error,)
|
||||
/// @arg UART_IT_PE: Parity Error interrupt
|
||||
/// @arg UART_OVER_ERR: overrun Error interrupt
|
||||
/// @arg UART_IT_RXIEN: Receive Data register interrupt
|
||||
/// @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt
|
||||
/// @retval The new state of UART_IT (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
ITStatus UART_GetITStatus(UART_TypeDef* uart, u16 it)
|
||||
{
|
||||
return (uart->ISR & it) ? SET : RESET;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears the uart interrupt pending bits.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param it: specifies the interrupt pending bit to clear.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg UART_IT_ERR: Error interrupt(Frame error,)
|
||||
/// @arg UART_IT_PE: Parity Error interrupt
|
||||
/// @arg UART_OVER_ERR: overrun Error interrupt
|
||||
/// @arg UART_IT_RXIEN: Receive Data register interrupt
|
||||
/// @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_ClearITPendingBit(UART_TypeDef* uart, u16 it)
|
||||
{
|
||||
//clear UART_IT pendings bit
|
||||
uart->ICR = it;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Selects the UART WakeUp method.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param mode: specifies the UART wakeup method.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_WakeUpConfig(UART_TypeDef* uart, UART_WakeUp_TypeDef mode)
|
||||
{
|
||||
MODIFY_REG(uart->CCR, UART_CCR_WAKE, mode);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Determines if the UART is in mute mode or not.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param state: new state of the UART mute mode.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_ReceiverWakeUpCmd(UART_TypeDef* uart, FunctionalState state)
|
||||
{
|
||||
MODIFY_REG(uart->CCR, UART_CCR_RWU, state << UART_CCR_RWU_Pos);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Sets the address of the UART Rx Address.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param address: Indicates the address of the UART Rx Address.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_SetRXAddress(UART_TypeDef* uart, u8 address)
|
||||
{
|
||||
MODIFY_REG(uart->RXAR, UART_RXAR_ADDR, address);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Sets the address of the UART Rx MASK.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param address: Indicates the address of the UART Rx MASK.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_SetRXMASK(UART_TypeDef* uart, u8 address)
|
||||
{
|
||||
MODIFY_REG(uart->RXMR, UART_RXMR_MASK, address);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief ENBALE or DISABLE the UART's 9bit.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param state: new state of the UART 9 bit.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_Enable9bit(UART_TypeDef* uart, FunctionalState state)
|
||||
{
|
||||
MODIFY_REG(uart->CCR, UART_CCR_B8EN, state << UART_CCR_B8EN_Pos);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Set the UART's 9bit Level.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param state: new state of the UART 9 bit.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_Set9bitLevel(UART_TypeDef* uart, FunctionalState state)
|
||||
{
|
||||
MODIFY_REG(uart->CCR, UART_CCR_B8TXD, state << UART_CCR_B8TXD_Pos);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Set the UART's 9bit Polarity.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param polarity: new state of the UART 9 bit Polarity.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_Set9bitPolarity(UART_TypeDef* uart, UART_9bit_Polarity_TypeDef polarity)
|
||||
{
|
||||
MODIFY_REG(uart->CCR, UART_CCR_B8POL, polarity);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Set the UART's 9bit Automatic Toggle.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param state: new state of the UART 9 bit Automatic Toggle.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_Set9bitAutomaticToggle(UART_TypeDef* uart, FunctionalState state)
|
||||
{
|
||||
MODIFY_REG(uart->CCR, UART_CCR_B8TOG, state << UART_CCR_B8TOG_Pos);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the UART Half Duplex communication.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param state: new state of the UART Communication.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_HalfDuplexCmd(UART_TypeDef* uart, FunctionalState state)
|
||||
{
|
||||
MODIFY_REG(uart->SCR, UART_SCR_HDSEL, state << UART_SCR_HDSEL_Pos);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Sets the specified UART guard time.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param guard_time: specifies the guard time.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_SetGuardTime(UART_TypeDef* uart, u8 guard_time)
|
||||
{
|
||||
MODIFY_REG(uart->SCR, UART_SCR_SCFCNT, guard_time << UART_SCR_SCFCNT_Pos);
|
||||
// Clear the UART Guard time
|
||||
// uart->SCR &= SCR_SCFCNT_Mask;
|
||||
// Set the UART guard time
|
||||
// uart->SCR |= (u16)((u16)guard_time << 0x04);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables the UART's Smart Card mode.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param state: new state of the Smart Card mode.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_SmartCardCmd(UART_TypeDef* uart, FunctionalState state)
|
||||
{
|
||||
MODIFY_REG(uart->SCR, UART_SCR_SCEN, state << UART_SCR_SCEN_Pos);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables or disables NACK transmission.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param state: new state of the NACK transmission.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_SmartCardNACKCmd(UART_TypeDef* uart, FunctionalState state)
|
||||
{
|
||||
MODIFY_REG(uart->SCR, UART_SCR_SCARB, state << UART_SCR_SCARB_Pos);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Transmits break characters.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_SendBreak(UART_TypeDef* uart)
|
||||
{
|
||||
SET_BIT(uart->CCR, UART_CCR_BRK);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enable or Disable Auto Baud-Rate Detection
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// @param state: new state of the UART AutoBaudRate Detection.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_AutoBaudRateCmd(UART_TypeDef* uart, FunctionalState state)
|
||||
{
|
||||
state ? SET_BIT(uart->ABRCR, UART_ABRCR_ABREN) : CLEAR_BIT(uart->ABRCR, UART_ABRCR_ABREN) ;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief AutoBaudRate.
|
||||
/// @param uart: Select the UART or the UART peripheral.
|
||||
/// value: special character.
|
||||
/// state: ENABLE/DISABLE.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void UART_AutoBaudRateSet(UART_TypeDef* uart, UART_AutoBaud_TypeDef value, FunctionalState state)
|
||||
{
|
||||
CLEAR_BIT(uart->ABRCR, UART_ABRCR_ABREN);
|
||||
//This bit field can only be written when ABREN = 0 or the UART is disabled (UARTEN=0).
|
||||
|
||||
if ((value == ABRMODE_FALLING_TO_RISINGEDGE1BIT) || (value == ABRMODE_STARTBIT) || (value == ABRMODE_VALUE0XFF)) {
|
||||
//UART measures the duration of the start bit (falling edge) to first rising edge
|
||||
//FORMER edge = 0 LATTER edge= 1, from fist falling edge to rising edge = one bit
|
||||
//___ _ _______
|
||||
// |_|1 x x x x x x x| = Bxxxx xxx1 F to U = 1 start bit
|
||||
//
|
||||
MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
|
||||
UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE0 );
|
||||
}
|
||||
else if((value == ABRMODE_FALLING_TO_RISINGEDGE2BIT) || (value == Data_FE)) {
|
||||
//UART measures the duration of the start bit (falling edge) to first rising edge
|
||||
//FORMER edge = 0 LATTER edge= 1, from fist falling edge to rising edge = two bit
|
||||
//___ _ _______
|
||||
// |_ _|1 x x x x x x| = Bxxxx xx10 F to U = 2
|
||||
//
|
||||
MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
|
||||
UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE1);
|
||||
}
|
||||
else if((value == ABRMODE_FALLING_TO_RISINGEDGE4BIT) || (value == Data_F8)) {
|
||||
//UART measures the duration of the start bit (falling edge) to first rising edge
|
||||
//FORMER edge = 0 LATTER edge= 1, from fist falling edge to rising edge = four bit
|
||||
//___ _ _______
|
||||
// |_ _ _ _|1 x x x x| = Bxxxx 1000 F to U = 4
|
||||
//
|
||||
MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
|
||||
UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE2);
|
||||
}
|
||||
else if((value == ABRMODE_FALLING_TO_RISINGEDGE8BIT) || (value == ABRMODE_VALUE0X80)) {
|
||||
//UART measures the duration of the start bit (falling edge) to first rising edge
|
||||
//FORMER edge = 0 LATTER edge= 1, from fist falling edge to rising edge = eight bit
|
||||
//___ _ ______
|
||||
// |_ _ _ _ _ _ _ _|1 = B1000 0000 F to U = 8
|
||||
//
|
||||
MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
|
||||
UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE3);
|
||||
}
|
||||
else if((value == ABRMODE_FALLING_TO_FALLINGEDGE2BIT) || (value == ABRMODE_VALUE0X55)) {
|
||||
//UART measures the duration of the start bit (falling edge) to next falling edge
|
||||
//FORMER edge = 0 LATTER edge= 0, from fist falling edge to next falling edge = two bit
|
||||
//___ _ ______
|
||||
// |_|1|_|x x x x x x| = Bxxxx xx01 F to F = 2 0x55 and Falling to Falling
|
||||
//
|
||||
MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
|
||||
UART_ABRCR_BITCNT_MODE1);
|
||||
}
|
||||
else if((value == ABRMODE_FALLING_TO_FALLINGEDGE4BIT) || (value == ABRMODE_VALUE0XF7)) {
|
||||
//UART measures the duration of the start bit (falling edge) to next falling edge
|
||||
//FORMER edge = 0 LATTER edge= 0, from fist falling edge to next falling edge = four bit
|
||||
//___ _ _ _ ______
|
||||
// |_|1 1 1|_|x x x x| = Bxxxx 0111 F to F = 4
|
||||
//
|
||||
MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
|
||||
UART_ABRCR_BITCNT_MODE2);
|
||||
}
|
||||
else if((value == ABRMODE_FALLING_TO_FALLINGEDGE8BIT) || (value == ABRMODE_VALUE0x7F)) {
|
||||
//UART measures the duration of the start bit (falling edge) to next falling edge
|
||||
//FORMER edge = 0 LATTER edge= 0, from fist falling edge to next falling edge = eight bit
|
||||
//___ _ _ _ _ _ _ _ ______
|
||||
// |_|1 1 1 1 1 1 1|_| = B0111 1111 F to F = 8 0x7F
|
||||
//
|
||||
MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
|
||||
UART_ABRCR_BITCNT_MODE3);
|
||||
}
|
||||
|
||||
else {
|
||||
//UART measures the duration of the start bit (falling edge) to next falling edge
|
||||
//FORMER edge = 0 LATTER edge= 0, from fist falling edge to next falling edge = eight bit
|
||||
//___ _ _ _ _ _ _ _ ______
|
||||
// |_|1 1 1 1 1 1 1|_| = B0111 1111 F to F = 8 0x7F
|
||||
//
|
||||
MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
|
||||
UART_ABRCR_BITCNT_MODE3);
|
||||
}
|
||||
if(state == ENABLE) {
|
||||
SET_BIT(uart->ABRCR, UART_ABRCR_ABREN);
|
||||
}
|
||||
}
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
@@ -0,0 +1,55 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_uid.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE UID FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_UID_C_
|
||||
|
||||
// Files includes
|
||||
#include "hal_uid.h"
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///@addtogroup UID_HAL
|
||||
///@{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup UID_Exported_Functions
|
||||
/// @{
|
||||
|
||||
u8 device_id_data[12] = {0};
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Get device ID.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void GetChipUID(void)
|
||||
{
|
||||
u8 i;
|
||||
|
||||
for (i = 0; i < 12; i++) {
|
||||
device_id_data[i] = *((vu8*)(UID_BASE + i));
|
||||
}
|
||||
}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
@@ -0,0 +1,131 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_ver.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE LIB AND THE CHIPSET INFORMATION.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_VER_C_
|
||||
|
||||
// Files includes
|
||||
#include "hal_ver.h"
|
||||
|
||||
|
||||
// MM32 Library version is 0.90
|
||||
|
||||
#define __MM32_LIB_VERSION_MAIN (0x0U) //!< [31:24] main version
|
||||
#define __MM32_LIB_VERSION_SUB1 (0x9U) //!< [23:16] sub1 version
|
||||
#define __MM32_LIB_VERSION_SUB2 (0x0U) //!< [15:8] sub2 version
|
||||
#define __MM32_LIB_VERSION_RC (0x00U) //!< [7:0] release candidate
|
||||
#define __MM32_LIB_VERSION ((__MM32_LIB_VERSION_MAIN << 24U)\
|
||||
|(__MM32_LIB_VERSION_SUB1 << 16U)\
|
||||
|(__MM32_LIB_VERSION_SUB2 << 8U )\
|
||||
|(__MM32_LIB_VERSION_RC))
|
||||
|
||||
// MM32 Library release date is 2021-05-10 (YYYY-MM-DD)
|
||||
#define __MM32_LIB_RELESE_YEARH (0x20U) //!< [31:24] release year high
|
||||
#define __MM32_LIB_RELESE_YEARL (0x21U) //!< [23:16] release year low
|
||||
#define __MM32_LIB_RELESE_MONTH (0x05U) //!< [15:8] release month
|
||||
#define __MM32_LIB_RELESE_DAY (0x10U) //!< [7:0] release day
|
||||
#define __MM32_LIB_RELESE_DATE ((__MM32_LIB_RELESE_YEARH << 24U)\
|
||||
|(__MM32_LIB_RELESE_YEARL << 16U)\
|
||||
|(__MM32_LIB_RELESE_MONTH << 8U )\
|
||||
|(__MM32_LIB_RELESE_DAY))
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///@addtogroup VER_HAL
|
||||
///@{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup Lib and chipset_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief This method returns the Lib revision.
|
||||
/// @param None.
|
||||
/// @retval return the Lib version.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 Get_MM32LibVersion(void)
|
||||
{
|
||||
return __MM32_LIB_VERSION;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief This method returns the Lib release date.
|
||||
/// @param None.
|
||||
/// @retval return the Lib release date.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 Get_MM32LibReleaseDate(void)
|
||||
{
|
||||
return __MM32_LIB_RELESE_DATE;
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the device revision identifier.
|
||||
/// @param None.
|
||||
/// @retval return the device revision identifier.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 Get_ChipsetREVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) & 0xF );
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns the device identifier..
|
||||
/// @param None.
|
||||
/// @retval return the device Device identifier.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 Get_ChipsetDEVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) );
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns first word of the unique device identifier (UID based on 96 bits)
|
||||
/// @param None.
|
||||
/// @retval Device identifier
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 Get_ChipsetUIDw0(void)
|
||||
{
|
||||
return(READ_REG(*((vu32*)UID_BASE)));
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns second word of the unique device identifier (UID based on 96 bits)
|
||||
/// @param None.
|
||||
/// @retval Device identifier
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 Get_ChipsetUIDw1(void)
|
||||
{
|
||||
return(READ_REG(*((vu32*)(UID_BASE + 4U))));
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Returns third word of the unique device identifier (UID based on 96 bits)
|
||||
/// @param None.
|
||||
/// @retval Device identifier
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 Get_ChipsetUIDw2(void)
|
||||
{
|
||||
return(READ_REG(*((vu32*)(UID_BASE + 8U))));
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
@@ -0,0 +1,147 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_wwdg.c
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE WWDG FIRMWARE FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _HAL_WWDG_C_
|
||||
|
||||
// Files includes
|
||||
#include "hal_wwdg.h"
|
||||
#include "hal_rcc.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup WWDG_HAL
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup WWDG_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Deinitializes the WWDG peripheral registers to their default reset
|
||||
/// values.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void WWDG_DeInit()
|
||||
{
|
||||
exRCC_APB1PeriphReset(RCC_APB1RSTR_WWDG);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Sets the WWDG Prescaler.
|
||||
/// @param WWDG_Prescaler: specifies the WWDG Prescaler.
|
||||
/// This parameter can be one of the following values:
|
||||
/// @arg WWDG_Prescaler_1: WWDG counter clock = APB1CLK / 4096 / 1
|
||||
/// @arg WWDG_Prescaler_2: WWDG counter clock = APB1CLK / 4096 / 2
|
||||
/// @arg WWDG_Prescaler_4: WWDG counter clock = APB1CLK / 4096 / 4
|
||||
/// @arg WWDG_Prescaler_8: WWDG counter clock = APB1CLK / 4096 / 8
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void WWDG_SetPrescaler(u32 prescaler)
|
||||
{
|
||||
WWDG->CFGR = (WWDG->CFGR & ~WWDG_CFGR_WDGTB) | prescaler;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Sets the WWDG window value.
|
||||
/// @param WindowValue: specifies the window value to be compared to the
|
||||
/// downcounter.
|
||||
/// This parameter value must be lower than 0x80.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void WWDG_SetWindowValue(u8 window_value)
|
||||
{
|
||||
WWDG->CFGR = (WWDG->CFGR & ~WWDG_CFGR_WINDOW) | (window_value & WWDG_CFGR_WINDOW);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables the WWDG Early Wakeup interrupt(EWI).
|
||||
/// @note Once enabled this interrupt cannot be disabled except by a system
|
||||
/// reset.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void WWDG_EnableIT()
|
||||
{
|
||||
WWDG->CFGR |= WWDG_CFGR_EWI;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Sets the WWDG counter value.
|
||||
/// @param Counter: specifies the watchdog counter value.
|
||||
/// This parameter must be a number between 0x40 and 0x7F (to prevent
|
||||
/// generating an immediate reset).
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void WWDG_SetCounter(u8 count)
|
||||
{
|
||||
WWDG->CR = count & WWDG_CFGR_WINDOW;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables WWDG and load the counter value.
|
||||
/// @param Counter: specifies the watchdog counter value.
|
||||
/// This parameter must be a number between 0x40 and 0x7F (to prevent
|
||||
/// generating an immediate reset).
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
u32 WWDG_GetCounter()
|
||||
{
|
||||
return WWDG->CR & WWDG_CR_CNT;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Enables WWDG and load the counter value.
|
||||
/// @param Counter: specifies the watchdog counter value.
|
||||
/// This parameter must be a number between 0x40 and 0x7F (to prevent
|
||||
/// generating an immediate reset).
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void WWDG_Enable(u8 count)
|
||||
{
|
||||
WWDG->CR = WWDG_CR_WDGA | count;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Checks whether the Early Wakeup interrupt flag is set or not.
|
||||
/// @param None.
|
||||
/// @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
FlagStatus WWDG_GetFlagStatus()
|
||||
{
|
||||
return WWDG->SR ? SET : RESET;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clears Early Wakeup interrupt flag.
|
||||
/// @param None.
|
||||
/// @retval None.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void WWDG_ClearFlag()
|
||||
{
|
||||
WWDG->SR &= ~WWDG_SR_EWIF;
|
||||
}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
Reference in New Issue
Block a user