Add MM32 SDK and USB driver
Signed-off-by: zhangslice <1304224508@qq.com>
This commit is contained in:
zhangslice
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////////////////////////////////////////////////////////////////////////////////
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/// @file: dtype.h
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/// @author AE TEAM
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/// @brief Define the data types to be used in the project, including the function
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/// library and application code. Use the data types defined in this file.
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////////////////////////////////////////////////////////////////////////////////
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#ifndef __DTYPE_H
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#define __DTYPE_H //This is done to avoid including the header file repeatedly in the same file
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//Defines the read and write characteristics of data, which is often used for storage limits of peripheral registers
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#ifndef __I
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#define __I volatile const //only read
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#endif
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#ifndef __O
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#define __O volatile //only write
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#endif
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#ifndef __IO
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#define __IO volatile //read write
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#endif
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//Common data type definitions
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typedef unsigned char int8u; //haven't symbol8 bit integer variable
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typedef signed char int8s; //have symbol8 bit integer variable
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typedef unsigned short int16u; //haven't symbol16 bit integer variable
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typedef signed short int16s; //have symbol16 bit integer variable
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typedef unsigned int int32u; //haven't symbol32 bit integer variable
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typedef signed int int32s; //have symbol32 bit integer variable
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typedef float fp32; //Single-precision floating-point number (32-bit length)
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typedef double fp64; //Double-precision floating-point number (64-bit length)
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#endif //__DTYPE_H
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@@ -0,0 +1,341 @@
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////////////////////////////////////////////////////////////////////////////////
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/// @file hal_adc.h
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/// @author AE TEAM
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/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE ADC
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/// FIRMWARE LIBRARY.
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////////////////////////////////////////////////////////////////////////////////
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/// @attention
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///
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/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
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/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
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/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
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/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
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/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
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/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
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///
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/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
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////////////////////////////////////////////////////////////////////////////////
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// Define to prevent recursive inclusion
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#ifndef __HAL_ADC_H
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#define __HAL_ADC_H
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// Files includes
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#include "types.h"
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#include "reg_adc.h"
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////////////////////////////////////////////////////////////////////////////////
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/// @addtogroup MM32_Hardware_Abstract_Layer
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup ADC_HAL
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/// @brief ADC HAL modules
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup ADC_Exported_Types
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Channels
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_Channel_0 = 0x00, ///< ADC Channel 0
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ADC_Channel_1 = 0x01, ///< ADC Channel 1
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ADC_Channel_2 = 0x02, ///< ADC Channel 2
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ADC_Channel_3 = 0x03, ///< ADC Channel 3
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ADC_Channel_4 = 0x04, ///< ADC Channel 4
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ADC_Channel_5 = 0x05, ///< ADC Channel 5
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ADC_Channel_6 = 0x06, ///< ADC Channel 6
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ADC_Channel_7 = 0x07, ///< ADC Channel 7
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ADC_Channel_8 = 0x08, ///< ADC Channel 8
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ADC_Channel_9 = 0x09, ///< ADC Channel 9
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ADC_Channel_10 = 0x0A, ///< ADC Channel 10
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ADC_Channel_11 = 0x0B, ///< ADC Channel 11
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ADC_Channel_12 = 0x0C, ///< ADC Channel 12
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ADC_Channel_13 = 0x0D, ///< ADC Channel 13
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ADC_Channel_14 = 0x0E, ///< ADC Channel 14
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ADC_Channel_15 = 0x0F, ///< ADC Channel 15
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ADC_Channel_TempSensor = 0x0E, ///< Temperature sensor channel(ADC1)
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ADC_Channel_VoltReference = 0x0F, ///< Internal reference voltage channel(ADC1)
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ADC_Channel_Vrefint = 0x0F, ///< Internal reference voltage channel(ADC1)
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} ADCCHANNEL_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Sampling_Times
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_Samctl_1_5 = ADC_SMPR1_SAMCTL0_2_5, ///< ADC sample time select 1.5t
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ADC_Samctl_2_5 = ADC_SMPR1_SAMCTL0_2_5, ///< ADC sample time select 2.5t
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ADC_Samctl_3_5 = ADC_SMPR1_SAMCTL0_3_5, ///< ADC sample time select 3.5t
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ADC_Samctl_4_5 = ADC_SMPR1_SAMCTL0_4_5, ///< ADC sample time select 4.5t
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ADC_Samctl_5_5 = ADC_SMPR1_SAMCTL0_5_5, ///< ADC sample time select 5.5t
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ADC_Samctl_6_5 = ADC_SMPR1_SAMCTL0_6_5, ///< ADC sample time select 6.5t
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ADC_Samctl_7_5 = ADC_SMPR1_SAMCTL0_7_5, ///< ADC sample time select 7.5t
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ADC_Samctl_8_5 = ADC_SMPR1_SAMCTL0_8_5, ///< ADC sample time select 7.5t
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ADC_Samctl_13_5 = ADC_SMPR1_SAMCTL0_14_5, ///< ADC sample time select 13.5t
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ADC_Samctl_14_5 = ADC_SMPR1_SAMCTL0_14_5, ///< ADC sample time select 14.5t
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ADC_Samctl_28_5 = ADC_SMPR1_SAMCTL0_29_5, ///< ADC sample time select 28.5t
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ADC_Samctl_29_5 = ADC_SMPR1_SAMCTL0_29_5, ///< ADC sample time select 29.5t
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ADC_Samctl_41_5 = ADC_SMPR1_SAMCTL0_42_5, ///< ADC sample time select 41.5t
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ADC_Samctl_42_5 = ADC_SMPR1_SAMCTL0_42_5, ///< ADC sample time select 42.5t
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ADC_Samctl_55_5 = ADC_SMPR1_SAMCTL0_56_5, ///< ADC sample time select 55.5t
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ADC_Samctl_56_5 = ADC_SMPR1_SAMCTL0_56_5, ///< ADC sample time select 56.5t
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ADC_Samctl_71_5 = ADC_SMPR1_SAMCTL0_72_5, ///< ADC sample time select 71.5t
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ADC_Samctl_72_5 = ADC_SMPR1_SAMCTL0_72_5, ///< ADC sample time select 72.5t
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ADC_Samctl_239_5 = ADC_SMPR1_SAMCTL0_240_5, ///< ADC sample time select 239.5t
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ADC_Samctl_240_5 = ADC_SMPR1_SAMCTL0_240_5 ///< ADC sample time select 240.5t
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} ADCSAM_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Resolution
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_Resolution_12b = ADC_CFGR_RSLTCTL_12, ///< ADC resolution select 12bit
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ADC_Resolution_11b = ADC_CFGR_RSLTCTL_11, ///< ADC resolution select 11bit
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ADC_Resolution_10b = ADC_CFGR_RSLTCTL_10, ///< ADC resolution select 10bit
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ADC_Resolution_9b = ADC_CFGR_RSLTCTL_9, ///< ADC resolution select 9bit
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ADC_Resolution_8b = ADC_CFGR_RSLTCTL_8 ///< ADC resolution select 8bit
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} ADCRSL_TypeDef;
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/// @brief ADC_Prescare
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_PCLK2_PRESCARE_3 = ADC_CFGR_PRE_3, ///< ADC preclk 3
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ADC_PCLK2_PRESCARE_5 = ADC_CFGR_PRE_5, ///< ADC preclk 5
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ADC_PCLK2_PRESCARE_7 = ADC_CFGR_PRE_7, ///< ADC preclk 7
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ADC_PCLK2_PRESCARE_9 = ADC_CFGR_PRE_9, ///< ADC preclk 9
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ADC_PCLK2_PRESCARE_11 = ADC_CFGR_PRE_11, ///< ADC preclk 11
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ADC_PCLK2_PRESCARE_13 = ADC_CFGR_PRE_13, ///< ADC preclk 13
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ADC_PCLK2_PRESCARE_15 = ADC_CFGR_PRE_15, ///< ADC preclk 15
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ADC_PCLK2_PRESCARE_17 = ADC_CFGR_PRE_17, ///< ADC preclk 17
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ADC_PCLK2_PRESCARE_2 = ADC_CFGR_PRE_2, ///< ADC preclk 2
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ADC_PCLK2_PRESCARE_4 = ADC_CFGR_PRE_4, ///< ADC preclk 4
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ADC_PCLK2_PRESCARE_6 = ADC_CFGR_PRE_6, ///< ADC preclk 6
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ADC_PCLK2_PRESCARE_8 = ADC_CFGR_PRE_8, ///< ADC preclk 8
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ADC_PCLK2_PRESCARE_10 = ADC_CFGR_PRE_10, ///< ADC preclk 10
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ADC_PCLK2_PRESCARE_12 = ADC_CFGR_PRE_12, ///< ADC preclk 12
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ADC_PCLK2_PRESCARE_14 = ADC_CFGR_PRE_14, ///< ADC preclk 14
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ADC_PCLK2_PRESCARE_16 = ADC_CFGR_PRE_16 ///< ADC preclk 16
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} ADCPRE_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Conversion_Mode
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_Mode_Imm = ADC_CR_IMM, ///< ADC single convert mode
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ADC_Mode_Scan = ADC_CR_SCAN, ///< ADC single period convert mode
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ADC_Mode_Continue = ADC_CR_CONTINUE ///< ADC continue scan convert mode
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} ADCMODE_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Extrenal_Trigger_Sources_For_Regular_Channels_Conversion
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC1_ExternalTrigConv_T1_CC1 = ADC_CR_T1_CC1,
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ADC1_ExternalTrigConv_T1_CC2 = ADC_CR_T1_CC2,
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ADC1_ExternalTrigConv_T1_CC3 = ADC_CR_T1_CC3,
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ADC1_ExternalTrigConv_T2_CC2 = ADC_CR_T2_CC2,
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ADC1_ExternalTrigConv_T3_TRIG = ADC_CR_T3_TRIG,
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ADC1_ExternalTrigConv_T3_CC1 = ADC_CR_T3_CC1,
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ADC1_ExternalTrigConv_EXTI_11 = ADC_CR_EXTI_11,
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ADC1_ExternalTrigConv_T1_CC4_CC5 = ADC_CR_T1_CC4_CC5,
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ADC1_ExternalTrigConv_T1_TRIG = ADC_CR_T1_TRIG,
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ADC1_ExternalTrigConv_T8_CC4 = ADC_CR_T8_CC4,
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ADC1_ExternalTrigConv_T8_CC4_CC5 = ADC_CR_T8_CC4_CC5,
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ADC1_ExternalTrigConv_T2_CC1 = ADC_CR_T2_CC1,
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ADC1_ExternalTrigConv_T3_CC4 = ADC_CR_T3_CC4,
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ADC1_ExternalTrigConv_T2_TRIG = ADC_CR_T2_TRIG,
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ADC1_ExternalTrigConv_T8_CC5 = ADC_CR_T8_CC5,
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ADC1_ExternalTrigConv_EXTI_15 = ADC_CR_EXTI_15,
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ADC1_ExternalTrigConv_T1_CC4 = ADC_CR_TIM1_CC4,
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ADC1_ExternalTrigConv_T1_CC5 = ADC_CR_TIM1_CC5
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} EXTERTRIG_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Data_Align
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_DataAlign_Right = ADC_CR_RIGHT, ///< ADC data left align
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ADC_DataAlign_Left = ADC_CR_LEFT ///< ADC data right align
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} ADCDATAALI_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Flags_Definition
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_IT_EOC = 1, ///< ADC conversion flag
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ADC_FLAG_EOC = 1,
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ADC_IT_AWD = 2, ///< ADC window comparator flag
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ADC_FLAG_AWD = 2
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} ADCFLAG_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Trig_Edge
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_ADC_Trig_Edge_Dual = ADC_CR_TRG_EDGE_DUAL, ///< ADC trig edge dual mode down and up
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ADC_ADC_Trig_Edge_Down = ADC_CR_TRG_EDGE_DOWN, ///< ADC trig edge single mode down
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ADC_ADC_Trig_Edge_Up = ADC_CR_TRG_EDGE_UP, ///< ADC trig edge single mode up
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ADC_ADC_Trig_Edge_Mask = ADC_CR_TRG_EDGE_MASK ///< ADC trig edge is mask, not allowed
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} ADCTRIGEDGE_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Scan_Direct
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_Scan_Direct_Up = ADC_CR_SCANDIR, ///< ADC scan from low channel to high channel
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ADC_Scan_Direct_Down = 0 ///< ADC scan from High channel to low channel
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} ADCSCANDIRECT_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Trig_Shift
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_ADC_Trig_Shift_0 = ADC_CR_TRGSHIFT_0, ///< ADC trig shift bit is 0
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ADC_ADC_Trig_Shift_4 = ADC_CR_TRGSHIFT_4, ///< ADC trig shift bit is 4
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ADC_ADC_Trig_Shift_16 = ADC_CR_TRGSHIFT_16, ///< ADC trig shift bit is 16
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ADC_ADC_Trig_Shift_32 = ADC_CR_TRGSHIFT_32, ///< ADC trig shift bit is 32
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ADC_ADC_Trig_Shift_64 = ADC_CR_TRGSHIFT_64, ///< ADC trig shift bit is 64
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ADC_ADC_Trig_Shift_128 = ADC_CR_TRGSHIFT_128, ///< ADC trig shift bit is 128
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ADC_ADC_Trig_Shift_256 = ADC_CR_TRGSHIFT_256, ///< ADC trig shift bit is 256
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ADC_ADC_Trig_Shift_512 = ADC_CR_TRGSHIFT_512, ///< ADC trig shift bit is 512
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} ADCTRIGSHIFT_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Inject_Sequence_Length the sequencer length for injected channels
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_Inject_Seqen_Len1 = 0, ///< ADC Injected Seqence length is 1
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ADC_Inject_Seqen_Len2 = 1, ///< ADC Injected Seqence length is 2
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ADC_Inject_Seqen_Len3 = 2, ///< ADC Injected Seqence length is 3
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ADC_Inject_Seqen_Len4 = 3, ///< ADC Injected Seqence length is 4
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} ADC_INJ_SEQ_LEN_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Inject_Sequence_Length the sequencer length for injected channels
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC_InjectedChannel_1 = 0x00,
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ADC_InjectedChannel_2 = 0x04,
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ADC_InjectedChannel_3 = 0x08,
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ADC_InjectedChannel_4 = 0x0c,
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} ADC_INJ_SEQ_Channel_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC_Extrenal_Trigger_Sources_For_Regular_Channels_Conversion
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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ADC1_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO
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ADC1_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4
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ADC1_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5
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ADC1_InjectExtTrigSrc_T2_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM2 CC1
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ADC1_InjectExtTrigSrc_T3_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM3 CC4
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ADC1_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4
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ADC1_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5
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ADC1_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12
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ADC2_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO
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ADC2_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4
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ADC2_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5
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ADC2_InjectExtTrigSrc_T2_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM2 CC1
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ADC2_InjectExtTrigSrc_T3_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM3 CC4
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ADC2_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4
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ADC2_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5
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ADC2_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12
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ADC3_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO
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ADC3_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4
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ADC3_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5
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ADC3_InjectExtTrigSrc_T4_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM4 CC1
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ADC3_InjectExtTrigSrc_T5_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM5 CC4
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ADC3_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4
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ADC3_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5
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ADC3_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12
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} EXTER_INJ_TRIG_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC Init Structure definition
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////////////////////////////////////////////////////////////////////////////////
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typedef struct {
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u32 ADC_Resolution; ///< Convert data resolution
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u32 ADC_PRESCARE; ///< Clock prescaler
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u32 ADC_Mode; ///< ADC conversion mode
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FunctionalState ADC_ContinuousConvMode; ///< Useless just for compatibility
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u32 ADC_ExternalTrigConv; ///< External trigger source selection
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u32 ADC_DataAlign; ///< Data alignmentn
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} ADC_InitTypeDef;
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup ADC_Exported_Variables
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/// @{
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#ifdef _HAL_ADC_C_
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#define GLOBAL
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#else
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#define GLOBAL extern
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#endif
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#undef GLOBAL
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup ADC_Exported_Functions
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/// @{
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void ADC_DeInit(ADC_TypeDef* adc);
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void ADC_Init(ADC_TypeDef* adc, ADC_InitTypeDef* init_struct);
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void ADC_StructInit(ADC_InitTypeDef* init_struct);
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void ADC_Cmd(ADC_TypeDef* adc, FunctionalState state);
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void ADC_DMACmd(ADC_TypeDef* adc, FunctionalState state);
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void ADC_ITConfig(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt, FunctionalState state);
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void ADC_SoftwareStartConvCmd(ADC_TypeDef* adc, FunctionalState state);
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void ADC_RegularChannelConfig(ADC_TypeDef* adc, u32 channel, u8 rank, u32 sample_time);//ADCSAM_TypeDef
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void ADC_ExternalTrigConvCmd(ADC_TypeDef* adc, FunctionalState state);
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void ADC_ExternalTrigConvConfig(ADC_TypeDef* adc, EXTERTRIG_TypeDef adc_external_trig_source);
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#define ADC_ExternalTrigInjectedConvConfig ADC_ExternalTrigConvConfig
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void ADC_AnalogWatchdogCmd(ADC_TypeDef* adc, FunctionalState state);
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void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* adc, u16 high_threshold, u16 low_threshold);
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void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel);
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void ADC_TempSensorVrefintCmd(FunctionalState state);
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void ADC_ClearITPendingBit(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt);
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void ADC_ClearFlag(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag);
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u16 ADC_GetConversionValue(ADC_TypeDef* adc);
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FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* adc);
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag);
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt);
|
||||
void ADC_TempSensorCmd(FunctionalState state);
|
||||
void ADC_VrefintCmd(FunctionalState state);
|
||||
void exADC_TempSensorVrefintCmd(u32 chs, FunctionalState state);
|
||||
void ADC_ANY_CH_Config(ADC_TypeDef* adc, u8 rank, ADCCHANNEL_TypeDef adc_channel);
|
||||
void ADC_ANY_NUM_Config(ADC_TypeDef* adc, u8 num);
|
||||
void ADC_ANY_Cmd(ADC_TypeDef* adc, FunctionalState state);
|
||||
void ADC_AutoInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state);
|
||||
void ADC_ExternalTrigInjectedConvertConfig(ADC_TypeDef* adc, EXTER_INJ_TRIG_TypeDef ADC_ExtInjTrigSource);
|
||||
void ADC_InjectedConvCmd(ADC_TypeDef* adc, FunctionalState state);
|
||||
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state);
|
||||
void ADC_InjectedSequencerConfig(ADC_TypeDef* adc, u32 event, u32 sample_time);
|
||||
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_LEN_TypeDef Length);
|
||||
void ADC_InjectedSequencerChannelConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, ADCCHANNEL_TypeDef channel);
|
||||
u16 ADC_GetInjectedConversionValue(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr);
|
||||
u16 ADC_GetInjectedCurrentConvertedValue(ADC_TypeDef* adc);
|
||||
void ADC_SetInjectedOffset(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, u16 value);
|
||||
u16 ADC_GetChannelConvertedValue(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel);
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
@@ -0,0 +1,130 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_bkp.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE BKP
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_BKP_H
|
||||
#define __HAL_BKP_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_bkp.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup BKP_HAL
|
||||
/// @brief BKP HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup BKP_Exported_Types
|
||||
/// @{
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Data_Backup_Register
|
||||
/// @anchor Data_Backup_Register
|
||||
|
||||
typedef enum {
|
||||
BKP_DR1 = 0x0010,
|
||||
BKP_DR2 = 0x0014,
|
||||
BKP_DR3 = 0x0018,
|
||||
BKP_DR4 = 0x001C,
|
||||
BKP_DR5 = 0x0020,
|
||||
BKP_DR6 = 0x0024,
|
||||
BKP_DR7 = 0x0028,
|
||||
BKP_DR8 = 0x002C,
|
||||
BKP_DR9 = 0x0030,
|
||||
BKP_DR10 = 0x0034,
|
||||
BKP_DR11 = 0x0038,
|
||||
BKP_DR12 = 0x003C,
|
||||
BKP_DR13 = 0x0040,
|
||||
BKP_DR14 = 0x0044,
|
||||
BKP_DR15 = 0x0048,
|
||||
BKP_DR16 = 0x004C,
|
||||
BKP_DR17 = 0x0050,
|
||||
BKP_DR18 = 0x0054,
|
||||
BKP_DR19 = 0x0058,
|
||||
BKP_DR20 = 0x005C
|
||||
} BKPDR_Typedef;
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Tamper_Pin_active_level
|
||||
/// @anchor Tamper_Pin_active_level
|
||||
typedef enum {
|
||||
BKP_TamperPinLevel_High, ///< Tamper pin active on high level
|
||||
BKP_TamperPinLevel_Low = BKP_CR_TPAL, ///< Tamper pin active on low level
|
||||
} BKPTPAL_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief RTC_output_source_to_output_on_the_Tamper_pin
|
||||
/// @anchor RTC_output_source_to_output_on_the_Tamper_pin
|
||||
typedef enum {
|
||||
BKP_RTCOutputSource_None = 0x0000, ///< No RTC output on the Tamper pin
|
||||
BKP_RTCOutputSource_CalibClock = 0x0080, ///< Output the RTC clock with frequency divided by 64 on the Tamper pin
|
||||
BKP_RTCOutputSource_Alarm = 0x0100, ///< Output the RTC Alarm pulse signal on the Tamper pin
|
||||
BKP_RTCOutputSource_Second = 0x0300 ///< Output the RTC Second pulse signal on the Tamper pin
|
||||
} BKPRTCOUTPUTSRC_Typedef;
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup BKP_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_BKP_C_
|
||||
#define GLOBAL
|
||||
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup BKP_Exported_Functions
|
||||
/// @{
|
||||
|
||||
void BKP_WriteBackupRegister(BKPDR_Typedef bkp_dr, u16 data);
|
||||
u16 BKP_ReadBackupRegister(BKPDR_Typedef bkp_dr);
|
||||
|
||||
void BKP_DeInit(void);
|
||||
void BKP_ClearFlag(void);
|
||||
void BKP_ClearITPendingBit(void);
|
||||
void BKP_TamperPinLevelConfig(BKPTPAL_Typedef tamper_pin_level);
|
||||
void BKP_TamperPinCmd(FunctionalState state);
|
||||
void BKP_ITConfig(FunctionalState state);
|
||||
void BKP_RTCOutputConfig(BKPRTCOUTPUTSRC_Typedef rtc_output_source);
|
||||
void BKP_SetRTCCalibrationValue(u8 calibration_value);
|
||||
|
||||
ITStatus BKP_GetITStatus(void);
|
||||
FlagStatus BKP_GetFlagStatus(void);
|
||||
void exBKP_Init(void);
|
||||
void exBKP_ImmWrite(BKPDR_Typedef bkp_dr, u16 data);
|
||||
u16 exBKP_ImmRead(BKPDR_Typedef bkp_dr);
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_BKP_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,340 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_can.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CAN
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_CAN_H
|
||||
#define __HAL_CAN_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_can.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CAN_HAL
|
||||
/// @brief CAN HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CAN_Exported_Types
|
||||
/// @{
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Initialization
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CANINITFAILED = 0x00000000, ///< CAN initialization failed
|
||||
CANINITOK = 0x00000001 ///< CAN initialization ok
|
||||
} emCAN_INIT_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_sleep_constants
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CANSLEEPFAILED = 0x00000000, ///< CAN did not enter the sleep mode
|
||||
CANSLEEPOK = 0x00000001 ///< CAN entered the sleep mode
|
||||
} emCAN_SLEEP_conts_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_wake_up_constants
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CANWAKEUPFAILED = 0x00000000, ///< CAN did not leave the sleep mode
|
||||
CANWAKEUPOK = 0x00000001 ///< CAN leaved the sleep mode
|
||||
} emCAN_WAKE_conts_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Mode
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CAN_BASICMode = 0x00000000,
|
||||
CAN_PELIMode = 0x00000080,
|
||||
CAN_WorkMode = 0x00000080,
|
||||
CAN_ResetMode = 0x00000001,
|
||||
CAN_ListenOnlyMode = 0x00000002,
|
||||
CAN_SeftTestMode = 0x00000004,
|
||||
CAN_FilterMode_Singal = 0x00000008,
|
||||
CAN_FilterMode_Double = 0x000000f7,
|
||||
CAN_SleepMode = 0x00000010
|
||||
} emCAN_CAN_Mode_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief BASIC_CAN_interrupt
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CAN_IT_RIE = CAN_CR_RIE, ///< Overflow interrupt enable
|
||||
CAN_IT_TIE = CAN_CR_TIE, ///< Transmit interrupt enable
|
||||
CAN_IT_EIE = CAN_CR_EIE, ///< Error interrupt enable
|
||||
CAN_IT_OIE = CAN_CR_OIE ///< Receive interrupt enable
|
||||
} emCAN_BASIC_IntEn_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief PELI_CAN_interrupt
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CAN_IT_RI = CAN_IR_RI, ///< Overflow interrupt enable
|
||||
CAN_IT_TI = CAN_IR_TI, ///< Transmit interrupt enable
|
||||
CAN_IT_EI = CAN_IR_EI, ///< Error interrupt enable
|
||||
CAN_IT_DOI = CAN_IR_DOI, ///< Receive interrupt enable
|
||||
CAN_IT_WUI = 0x00001010, ///< Receive interrupt enable
|
||||
CAN_IT_EPI = CAN_IR_EPI, ///< Receive interrupt enable
|
||||
CAN_IT_ALI = CAN_IR_ALI, ///< Receive interrupt enable
|
||||
CAN_IT_BEI = CAN_IR_BEI, ///< Receive interrupt enable
|
||||
CAN_IT_ALL = 0xFFFF ///< Receive interrupt enable
|
||||
|
||||
} emCAN_PELI_IntEn_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Status
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CAN_STATUS_RBS = CAN_SR_RBS,
|
||||
CAN_STATUS_DOS = CAN_SR_DOS,
|
||||
CAN_STATUS_TBS = CAN_SR_TBS,
|
||||
CAN_STATUS_TCS = CAN_SR_TCS,
|
||||
CAN_STATUS_RS = CAN_SR_RS,
|
||||
CAN_STATUS_TS = CAN_SR_TS,
|
||||
CAN_STATUS_ES = CAN_SR_ES,
|
||||
CAN_STATUS_BS = CAN_SR_BS
|
||||
} emCAN_Status_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Command_register
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CAN_TR = CAN_CMR_TR, ///< Transmission request
|
||||
CAN_AT = CAN_CMR_AT,
|
||||
CAN_RRB = CAN_CMR_RRB,
|
||||
CAN_CDO = CAN_CMR_CDO
|
||||
} emCAN_Command_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Peli transmit frame definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DataFrame = 0, ///< Data Frame
|
||||
RemoteFrame = !DataFrame
|
||||
} TransFrame;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Basic init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u8 SJW;
|
||||
u8 BRP;
|
||||
FlagStatus SAM;
|
||||
u8 TESG2;
|
||||
u8 TESG1;
|
||||
FunctionalState GTS;
|
||||
u8 CDCLK;
|
||||
u8 CLOSE_OPEN_CLK;
|
||||
u8 RXINTEN;
|
||||
u8 CBP;
|
||||
} CAN_Basic_InitTypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Peli init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u8 SJW;
|
||||
u8 BRP;
|
||||
FlagStatus SAM;
|
||||
u8 TESG2;
|
||||
u8 TESG1;
|
||||
FunctionalState LOM;
|
||||
FunctionalState STM;
|
||||
FunctionalState SM;
|
||||
FunctionalState SRR;
|
||||
u32 EWLR;
|
||||
} CAN_Peli_InitTypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Basic filter init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef struct {
|
||||
u8 CAN_FilterId; ///< Specifies the filter identification number. This parameter can be a value between 0x00 and 0xFF.
|
||||
u8 CAN_FilterMaskId; ///< Specifies the filter mask number or identification number, This parameter can be a value between
|
||||
///< 0x00 and 0xFF.
|
||||
} CAN_Basic_FilterInitTypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Peli filter init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef struct {
|
||||
u8 AFM;
|
||||
u8 CAN_FilterId0; ///< Specifies the filter identification number, This parameter can be a value between 0x00 and 0xFF
|
||||
u8 CAN_FilterId1;
|
||||
u8 CAN_FilterId2;
|
||||
u8 CAN_FilterId3;
|
||||
u8 CAN_FilterMaskId0; ///< Specifies the filter mask number or identification number, This parameter can be a value between
|
||||
///< 0x00 and 0xFF
|
||||
u8 CAN_FilterMaskId1;
|
||||
u8 CAN_FilterMaskId2;
|
||||
u8 CAN_FilterMaskId3;
|
||||
} CAN_Peli_FilterInitTypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Basic Tx message structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef struct {
|
||||
u8 IDH; ///< Specifies the standard high identifier. This parameter can be a value between 0 to 0xFF.
|
||||
u8 IDL; ///< Specifies the standard low identifier. This parameter can be a value between 0 to 0x7.
|
||||
u8 RTR; ///< Specifies the type of frame for the message that will be transmitted. This parameter can be @TransFrame.
|
||||
u8 DLC; ///< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8.
|
||||
u8 Data[8]; ///< Contains the data to be transmitted. It ranges from 0 to 0xFF.
|
||||
} CanBasicTxMsg;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Basic Rx message structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef struct {
|
||||
u16 ID; ///< Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF.
|
||||
u8 RTR; ///< Specifies the type of frame for the received message. This parameter can be a value of @ref TransFrame
|
||||
u8 DLC; ///< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8
|
||||
u8 Data[8]; ///< Contains the data to be received. It ranges from 0 to 0xFF.
|
||||
} CanBasicRxMsg;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN_Peli_Tx message structure definition
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef struct {
|
||||
u8 IDLL; ///< Specifies the extended identifier.
|
||||
///< This parameter can be a value between 0 to 0xFF.
|
||||
u8 IDLH;
|
||||
u8 IDHL;
|
||||
u8 IDHH;
|
||||
u8 FF; ///< Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of @ref
|
||||
///< CAN_identifier_type
|
||||
u8 RTR; ///< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref
|
||||
///< TransFrame.
|
||||
u8 DLC; ///< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8.
|
||||
u8 Data[8]; ///< Contains the data to be transmitted. It ranges from 0 to 0xFF.
|
||||
} CanPeliTxMsg;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief CAN Rx message structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u32 ID; ///< Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF.
|
||||
u8 FF; ///< Specifies the type of identifier for the message that will be received. This parameter can be a value of @ref
|
||||
///< CAN_identifier_type.
|
||||
u8 RTR; ///< Specifies the type of frame for the received message. This parameter can be a value of @ref TransFrame.
|
||||
u8 DLC; ///< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8.
|
||||
u8 Data[8]; ///< Contains the data to be received. It ranges from 0 to0xFF.
|
||||
} CanPeliRxMsg;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CAN_Exported_Constants
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup parasmeter_of_CAN_transmission_register
|
||||
/// @{
|
||||
#define CANTXFAILED (0x00U) ///< CAN transmission failed
|
||||
#define CANTXOK (0x01U) ///< CAN transmission succeeded
|
||||
#define CANTXPENDING (0x02U) ///< CAN transmission pending
|
||||
#define CAN_NO_MB (0x04U) ///< CAN cell did not provide an empty mailbox
|
||||
/// @}
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CAN_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_CAN_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CAN_Exported_Functions
|
||||
/// @{
|
||||
|
||||
// Basic and Peli Work all need function ---------------------------------------
|
||||
|
||||
void CAN_Mode_Cmd(CAN_TypeDef* can, u32 mode);
|
||||
void CAN_ResetMode_Cmd(CAN_TypeDef* can, FunctionalState state);
|
||||
void CAN_ClearDataOverflow(CAN_TypeDef* can);
|
||||
void CAN_ClearITPendingBit(CAN_TypeDef* can);
|
||||
|
||||
// Basic Work function ---------------------------------------------------------
|
||||
void CAN_DeInit(CAN_TypeDef* can);
|
||||
void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* basic_filter_init_struct);
|
||||
void CAN_StructInit(CAN_Basic_InitTypeDef* basic_init_struct);
|
||||
void CAN_ITConfig(CAN_TypeDef* can, u32 it, FunctionalState state);
|
||||
void CAN_CancelTransmit(CAN_TypeDef* can);
|
||||
void CAN_FIFORelease(CAN_TypeDef* can);
|
||||
void CAN_Receive(CAN_TypeDef* can, CanBasicRxMsg* basic_receive_message);
|
||||
|
||||
u8 CAN_Transmit(CAN_TypeDef* can, CanBasicTxMsg* basic_transmit_message);
|
||||
u8 CAN_Init(CAN_TypeDef* can, CAN_Basic_InitTypeDef* basic_init_struct);
|
||||
u8 CAN_Sleep(CAN_TypeDef* can);
|
||||
u8 CAN_WakeUp(CAN_TypeDef* can);
|
||||
|
||||
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* can, u32 flag);
|
||||
ITStatus CAN_GetITStatus(CAN_TypeDef* can, u32 it);
|
||||
|
||||
// Peli Work function ----------------------------------------------------------
|
||||
void CAN_Peli_SleepMode_Cmd(FunctionalState state);
|
||||
void CAN_Peli_Init(CAN_Peli_InitTypeDef* init_struct);
|
||||
void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* peli_init_struct);
|
||||
void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct);
|
||||
void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct);
|
||||
void CAN_Peli_Transmit(CanPeliTxMsg* peli_transmit_message);
|
||||
void CAN_Peli_TransmitRepeat(CanPeliTxMsg* peli_transmit_message);
|
||||
void CAN_Peli_Receive(CanPeliRxMsg* peli_receive_message);
|
||||
void CAN_Peli_ITConfig(u32 it, FunctionalState state);
|
||||
void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef* init_struct, u32 src_clk, u32 baud);
|
||||
|
||||
u32 CAN_Peli_GetRxFIFOInfo(void);
|
||||
u8 CAN_Peli_GetLastErrorCode(void);
|
||||
u8 CAN_Peli_GetReceiveErrorCounter(void);
|
||||
u8 CAN_Peli_GetLSBTransmitErrorCounter(void);
|
||||
|
||||
ITStatus CAN_Peli_GetITStatus(u32 it);
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
@@ -0,0 +1,228 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_comp.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE COMP
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_COMP_H
|
||||
#define __HAL_COMP_H
|
||||
|
||||
|
||||
// Files includes
|
||||
#include "reg_common.h"
|
||||
#include "reg_comp.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup COMP_HAL
|
||||
/// @brief COMP HAL modules
|
||||
/// @{
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup COMP_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP_InvertingInput
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
COMP_InvertingInput_IO0 = COMP_CSR_INM_0, ///< INM0 as COMP inverting input
|
||||
COMP_InvertingInput_IO1 = COMP_CSR_INM_1, ///< INM1 as COMP inverting input
|
||||
COMP_InvertingInput_IO2 = COMP_CSR_INM_2, ///< INM2 as COMP inverting input
|
||||
COMP_InvertingInput_CRV = COMP_CSR_INM_3, ///< INM3 as COMP inverting input
|
||||
COMP_InvertingInput_IO3 = COMP_CSR_INM_3, ///< INM3 as COMP inverting input
|
||||
} EM_COMP_InvertingInput;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP_NonInvertingInput
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
COMP_NonInvertingInput_IO0 = COMP_CSR_INP_INP0, ///< INP0 as COMP non-inverting input
|
||||
COMP_NonInvertingInput_IO1 = COMP_CSR_INP_INP1, ///< INP1 as COMP non-inverting input
|
||||
COMP_NonInvertingInput_IO2 = COMP_CSR_INP_INP2, ///< INP2 as COMP non-inverting input
|
||||
COMP_NonInvertingInput_IO3 = COMP_CSR_INP_INP3, ///< INP3 as COMP non-inverting input
|
||||
} EM_COMP_NonInvertingInput;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP_Output
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
COMP_Output_None = 0x00000000, ///< No output
|
||||
COMP_Output_TIM1BKIN = COMP_CSR_OUT_TIM1_BRAKE, ///< Timer1 brake input
|
||||
COMP_Output_TIM1OCREFCLR = COMP_CSR_OUT_TIM1_OCREFCLR, ///< Timer1 ocrefclear input
|
||||
COMP_Output_TIM1IC1 = COMP_CSR_OUT_TIM1_CAPTURE1, ///< Timer1 input capture 1
|
||||
COMP_Output_TIM2IC4 = COMP_CSR_OUT_TIM2_CAPTURE4, ///< Timer2 input capture 4
|
||||
COMP_Output_TIM2OCREFCLR = COMP_CSR_OUT_TIM2_OCREFCLR, ///< Timer2 ocrefclear input
|
||||
COMP_Output_TIM3IC1 = COMP_CSR_OUT_TIM3_CAPTURE1, ///< Timer3 input capture 1
|
||||
COMP_Output_TIM3OCREFCLR = COMP_CSR_OUT_TIM3_OCREFCLR ///< Timer3 ocrefclear input
|
||||
} EM_COMP_Output;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP_OutputPoloarity
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
COMP_NonInverted = 0x00000000, ///< COMP non-inverting output
|
||||
COMP_OutputPol_NonInverted = 0x00000000,
|
||||
COMP_Inverted = 0x00008000, ///< COMP inverting output
|
||||
COMP_OutputPol_Inverted = 0x00008000
|
||||
} EM_COMP_OutputPol;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP_Hysteresis
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
COMP_Hysteresis_No = COMP_CSR_HYST_0, ///< Hysteresis Voltage: 0mV
|
||||
COMP_Hysteresis_Low = COMP_CSR_HYST_15, ///< Hysteresis Voltage: 15mV
|
||||
COMP_Hysteresis_Medium = COMP_CSR_HYST_30, ///< Hysteresis Voltage: 30mV
|
||||
COMP_Hysteresis_High = COMP_CSR_HYST_90 ///< Hysteresis Voltage: 90mV
|
||||
} EM_COMP_Hysteresis;
|
||||
typedef enum {
|
||||
COMP_Filter_0_Period = COMP_CSR_OFLT_0, ///< filter is ((u32)0x00000000)
|
||||
COMP_Filter_2_Period = COMP_CSR_OFLT_1, ///< filter is ((u32)0x00040000)
|
||||
COMP_Filter_4_Period = COMP_CSR_OFLT_2, ///< filter is ((u32)0x00080000)
|
||||
COMP_Filter_8_Period = COMP_CSR_OFLT_3, ///< filter is ((u32)0x000C0000)
|
||||
COMP_Filter_16_Period = COMP_CSR_OFLT_4, ///< filter is ((u32)0x00100000)
|
||||
COMP_Filter_32_Period = COMP_CSR_OFLT_5, ///< filter is ((u32)0x00140000)
|
||||
COMP_Filter_64_Period = COMP_CSR_OFLT_6, ///< filter is ((u32)0x00180000)
|
||||
COMP_Filter_128_Period = COMP_CSR_OFLT_7, ///< filter is ((u32)0x001C0000)
|
||||
} EM_COMP_FILT;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP_Mode
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
COMP_Mode_HighSpeed = COMP_CSR_MODE_HIGHRATE, ///< Comparator high rate mode
|
||||
COMP_Mode_MediumSpeed = COMP_CSR_MODE_MEDIUMRATE, ///< Comparator medium rate mode
|
||||
COMP_Mode_LowPower = COMP_CSR_MODE_LOWPOWER, ///< Comparator low power mode
|
||||
COMP_Mode_UltraLowPower = COMP_CSR_MODE_LOWESTPOWER ///< Comparator lowest power mode
|
||||
} EM_COMP_Mode;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP_OutputLevel
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
COMP_OutputLevel_High = COMP_CSR_OUT, ///< High output
|
||||
COMP_OutputLevel_Low = 0x00000000 ///< Low output
|
||||
} EM_COMP_OutputLevel;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
union {
|
||||
u32 COMP_InvertingInput;
|
||||
u32 Invert; ///< Selects the inverting input of the comparator.
|
||||
};
|
||||
union {
|
||||
u32 COMP_NonInvertingInput;
|
||||
u32 NonInvert; ///< Selects the non inverting input of the comparator.
|
||||
};
|
||||
union {
|
||||
u32 COMP_Output;
|
||||
u32 Output; ///< Selects the output redirection of the comparator.
|
||||
u32 BlankingSrce; ///< Selects the output blanking source of the comparator.
|
||||
};
|
||||
union {
|
||||
u32 COMP_OutputPol;
|
||||
u32 OutputPol; ///< Selects the output polarity of the comparator.
|
||||
};
|
||||
union {
|
||||
u32 COMP_Hysteresis;
|
||||
u32 Hysteresis; ///< Selects the hysteresis voltage of the comparator.
|
||||
};
|
||||
union {
|
||||
u32 COMP_Mode;
|
||||
u32 Mode; ///< Selects the operating mode of the comparator and allows
|
||||
};
|
||||
union {
|
||||
u32 COMP_Filter;
|
||||
u32 OFLT; ///< to adjust the speed/consumption.
|
||||
};
|
||||
} COMP_InitTypeDef;
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
|
||||
FunctionalState COMP_Poll_En; ///< Selects the inverting input of the comparator.
|
||||
|
||||
u32 COMP_Poll_Ch; ///< Selects the non inverting input of the comparator.
|
||||
u32 COMP_Poll_Fixn; ///< Selects the output redirection of the comparator.
|
||||
u32 COMP_Poll_Period; ///< Selects the output polarity of the comparator.
|
||||
u32 COMP_Poll_Pout; ///< Selects the hysteresis voltage of the comparator.
|
||||
|
||||
} COMP_POLL_InitTypeDef;
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup COMP_Exported_Constants
|
||||
/// @{
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief COMP Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
COMP1 = (0x00000C), ///< Select comparator 1
|
||||
COMP2 = (0x000010), ///< Select comparator 2
|
||||
} COMP_Selection_TypeDef;
|
||||
|
||||
#define COMP_BlankingSrce_None ((u32)0x00000000)
|
||||
#define COMP_CSR_CLEAR_MASK ((u32)0x00000003)
|
||||
|
||||
#define COMP_CSR_COMPSW1 ((u32)0x00000002)
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///@defgroup COMP_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_COMP_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup COMP_Exported_Functions
|
||||
/// @{
|
||||
|
||||
|
||||
void COMP_DeInit(COMP_Selection_TypeDef selection);
|
||||
void COMP_Init(COMP_Selection_TypeDef selection, COMP_InitTypeDef* init_struct);
|
||||
void COMP_StructInit(COMP_InitTypeDef* init_struct);
|
||||
void COMP_Cmd(COMP_Selection_TypeDef selection, FunctionalState state);
|
||||
void COMP_SwitchCmd(COMP_Selection_TypeDef selection, FunctionalState state);
|
||||
void COMP_LockConfig(COMP_Selection_TypeDef selection);
|
||||
|
||||
u32 COMP_GetOutputLevel(COMP_Selection_TypeDef selection);
|
||||
|
||||
void COMP_SetCrv(u8 crv_select, u8 crv_level);
|
||||
#define SET_COMP_CRV COMP_SetCrv
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_COMP_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,62 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_conf.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GENERIC MICROCONTROLLER
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_CONF_H
|
||||
#define __HAL_CONF_H
|
||||
// Files includes
|
||||
#include "mm32_device.h"
|
||||
|
||||
#include "hal_adc.h"
|
||||
#include "hal_bkp.h"
|
||||
#include "hal_can.h"
|
||||
#include "hal_comp.h"
|
||||
#include "hal_crc.h"
|
||||
#include "hal_crs.h"
|
||||
#include "hal_dac.h"
|
||||
#include "hal_dbg.h"
|
||||
#include "hal_dma.h"
|
||||
#include "hal_exti.h"
|
||||
#include "hal_flash.h"
|
||||
#include "hal_gpio.h"
|
||||
#include "hal_i2c.h"
|
||||
#include "hal_iwdg.h"
|
||||
#include "hal_misc.h"
|
||||
#include "hal_pwr.h"
|
||||
#include "hal_rcc.h"
|
||||
#include "hal_rtc.h"
|
||||
#include "hal_spi.h"
|
||||
#include "hal_syscfg.h"
|
||||
#include "hal_tim.h"
|
||||
#include "hal_uart.h"
|
||||
#include "hal_uid.h"
|
||||
#include "hal_wwdg.h"
|
||||
#include "hal_redefine.h"
|
||||
#include "hal_eth.h"
|
||||
#include "hal_eth_conf.h"
|
||||
#include "hal_fsmc.h"
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_CONF_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,84 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_crc.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CRC
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_CRC_H
|
||||
#define __HAL_CRC_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
#include "reg_crc.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CRC_HAL
|
||||
/// @brief CRC HAL modules
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CRC_Exported_Types
|
||||
/// @{
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CRC_Exported_Constants
|
||||
/// @{
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CRC_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_CRC_C_
|
||||
#define GLOBAL
|
||||
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CRC_Exported_Functions
|
||||
/// @{
|
||||
void CRC_ResetDR(void);
|
||||
void CRC_SetIDRegister(u8 id_value);
|
||||
|
||||
u32 CRC_CalcCRC(u32 data);
|
||||
u32 CRC_CalcBlockCRC(u32* buffer, u32 length);
|
||||
u32 CRC_GetCRC(void);
|
||||
|
||||
u8 CRC_GetIDRegister(void);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_CRC_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,46 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_crs.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CRS
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_CRS_H
|
||||
#define __HAL_CRS_H
|
||||
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_crs.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup CRS_HAL
|
||||
/// @brief CRS HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup GPIO_Exported_Types
|
||||
/// @{
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
@@ -0,0 +1,166 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_dac.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DAC
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_DAC_H
|
||||
#define __HAL_DAC_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_dac.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DAC_HAL
|
||||
/// @brief DAC HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DAC_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DAC_Trigger_Selection
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DAC_Trigger_None = 0x00000000,
|
||||
DAC_Trigger_T1_TRIG = (DAC_CR_TSEL1_TIM1_TRIG | DAC_CR_TEN1),
|
||||
DAC_Trigger_T3_TRIG = (DAC_CR_TSEL1_TIM3_TRIG | DAC_CR_TEN1),
|
||||
DAC_Trigger_T2_TRIG = (DAC_CR_TSEL1_TIM2_TRIG | DAC_CR_TEN1),
|
||||
DAC_Trigger_T4_TRIG = (DAC_CR_TSEL1_TIM4_TRIG | DAC_CR_TEN1),
|
||||
DAC_Trigger_Ext_IT9 = (DAC_CR_TSEL1_EXTI9 | DAC_CR_TEN1),
|
||||
DAC_Trigger_Software = (DAC_CR_TSEL1_SOFTWARE)
|
||||
} emDACTRIG_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DAC_Wave_Generation
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DAC_WaveGeneration_None = DAC_CR_WAVE1_NONE,
|
||||
DAC_WaveGeneration_Noise = DAC_CR_WAVE1_NOISE,
|
||||
DAC_WaveGeneration_Triangle = DAC_CR_WAVE1_TRIANGLE
|
||||
} emDACWAVE_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DAC_Mask_Amplitude
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DAC_TriangleAmplitude_1 = DAC_CR_MAMP1_1,
|
||||
DAC_TriangleAmplitude_3 = DAC_CR_MAMP1_3,
|
||||
DAC_TriangleAmplitude_7 = DAC_CR_MAMP1_7,
|
||||
DAC_TriangleAmplitude_15 = DAC_CR_MAMP1_15,
|
||||
DAC_TriangleAmplitude_31 = DAC_CR_MAMP1_31,
|
||||
DAC_TriangleAmplitude_63 = DAC_CR_MAMP1_63,
|
||||
DAC_TriangleAmplitude_127 = DAC_CR_MAMP1_127,
|
||||
DAC_TriangleAmplitude_255 = DAC_CR_MAMP1_255,
|
||||
DAC_TriangleAmplitude_511 = DAC_CR_MAMP1_511,
|
||||
DAC_TriangleAmplitude_1023 = DAC_CR_MAMP1_1023,
|
||||
DAC_TriangleAmplitude_2047 = DAC_CR_MAMP1_2047,
|
||||
DAC_TriangleAmplitude_4095 = DAC_CR_MAMP1_4095
|
||||
} emDACAMP_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief channel
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DAC_Channel_1, ///< DAC channel 1
|
||||
DAC_Channel_2 = (u32)0x00000010 ///< DAC Channel 2
|
||||
} emDACCH_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DAC_Data_Alignement
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DAC_Align_12b_R = ((u32)0x00000000),
|
||||
DAC_Align_12b_L = ((u32)0x00000004),
|
||||
DAC_Align_8b_R = ((u32)0x00000008)
|
||||
} emDACALIGN_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DAC_Output_Buffer
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DAC_OutputBuffer_Enable = 0x00000000, ///< DAC output buffer enable
|
||||
DAC_OutputBuffer_Disable = DAC_CR_BOFF1 ///< DAC output buffer disable
|
||||
} emDACBOFF_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DAC Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
emDACTRIG_TypeDef DAC_Trigger;
|
||||
emDACWAVE_TypeDef DAC_WaveGeneration;
|
||||
emDACAMP_TypeDef DAC_LFSRUnmask_TriangleAmplitude;
|
||||
emDACBOFF_TypeDef DAC_OutputBuffer;
|
||||
} DAC_InitTypeDef;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DAC_Exported_Constants
|
||||
/// @{
|
||||
#define DHR12R1_Offset ((u32)0x00000008)
|
||||
#define DHR12R2_Offset ((u32)0x00000014)
|
||||
#define DHR12RD_Offset ((u32)0x00000020)
|
||||
#define DOR_Offset ((u32)0x0000002C)
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DAC_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_DAC_C_
|
||||
#define GLOBAL
|
||||
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DAC_Exported_Functions
|
||||
/// @{
|
||||
void DAC_DeInit(void);
|
||||
void DAC_Init(emDACCH_TypeDef channel, DAC_InitTypeDef* init_struct);
|
||||
void DAC_StructInit(DAC_InitTypeDef* init_struct);
|
||||
void DAC_Cmd(emDACCH_TypeDef channel, FunctionalState state);
|
||||
void DAC_DMACmd(emDACCH_TypeDef channel, FunctionalState state);
|
||||
void DAC_SoftwareTriggerCmd(emDACCH_TypeDef channel, FunctionalState state);
|
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState state);
|
||||
void DAC_WaveGenerationCmd(emDACCH_TypeDef channel, emDACWAVE_TypeDef wave, FunctionalState state);
|
||||
void DAC_SetChannel1Data(emDACALIGN_TypeDef alignement, u16 data);
|
||||
void DAC_SetChannel2Data(emDACALIGN_TypeDef alignement, u16 data);
|
||||
void DAC_SetDualChannelData(emDACALIGN_TypeDef alignement, u16 data2, u16 data1);
|
||||
|
||||
u16 DAC_GetDataOutputValue(emDACCH_TypeDef channel);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_DAC_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
@@ -0,0 +1,72 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_dbg.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DBG
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_DBG_H
|
||||
#define __HAL_DBG_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
#include "reg_dbg.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DBG_HAL
|
||||
/// @brief DBG HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DBG_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DIV_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_DBG_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DBG_Exported_Functions
|
||||
/// @{
|
||||
void DBGMCU_Configure(u32 periph, FunctionalState state);
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_DBG_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,41 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_device.h
|
||||
/// @author AE team
|
||||
/// @brief CMSIS Cortex-M Peripheral Access Layer for MindMotion
|
||||
/// microcontroller devices
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_DEVICE_H
|
||||
#define __HAL_DEVICE_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#include "mm32_device.h"
|
||||
|
||||
|
||||
#endif // __HAL_device_H
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,306 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_dma.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DMA
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_DMA_H
|
||||
#define __HAL_DMA_H
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
#include "reg_dma.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DMA_HAL
|
||||
/// @brief DMA HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DMA_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA data transfer direction Enumerate definition
|
||||
/// @anchor DMA_data_transfer_direction
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_DIR_PeripheralSRC = 0U,
|
||||
DMA_DIR_PeripheralDST = DMA_CCR_DIR // 0x00000010U
|
||||
} DMA_data_transfer_direction_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA peripheral incremented mode Enumerate definition
|
||||
/// @anchor DMA_peripheral_incremented_mode
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_PeripheralInc_Disable = 0U,
|
||||
DMA_PeripheralInc_Enable = DMA_CCR_PINC // 0x00000040U
|
||||
} DMA_peripheral_incremented_mode_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA memory incremented mode Enumerate definition
|
||||
/// @anchor DMA_memory_incremented_mode
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_MemoryInc_Disable = 0U,
|
||||
DMA_MemoryInc_Enable = DMA_CCR_MINC // 0x00000080U
|
||||
} DMA_memory_incremented_mode_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA peripheral data size Enumerate definition
|
||||
/// @anchor DMA_peripheral_data_size
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_PeripheralDataSize_Byte = 0U,
|
||||
DMA_PeripheralDataSize_HalfWord = DMA_CCR_PSIZE_HALFWORD,
|
||||
DMA_PeripheralDataSize_Word = DMA_CCR_PSIZE_WORD
|
||||
} DMA_peripheral_data_size_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA memory data size Enumerate definition
|
||||
/// @anchor DMA_memory_data_size
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_MemoryDataSize_Byte = 0U,
|
||||
DMA_MemoryDataSize_HalfWord = DMA_CCR_MSIZE_HALFWORD, // 0x00000400U
|
||||
DMA_MemoryDataSize_Word = DMA_CCR_MSIZE_WORD // 0x00000800U
|
||||
} DMA_memory_data_size_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA circular normal mode Enumerate definition
|
||||
/// @anchor DMA_circular_normal_mode
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_Mode_Normal = 0U,
|
||||
DMA_Mode_Circular = DMA_CCR_CIRC // 0x00000020U
|
||||
} DMA_circular_normal_mode_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA priority level Enumerate definition
|
||||
/// @anchor DMA_priority_level
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_Priority_Low = 0U,
|
||||
DMA_Priority_Medium = DMA_CCR_PL_Medium, // 0x00001000U
|
||||
DMA_Priority_High = DMA_CCR_PL_High, // 0x00002000U
|
||||
DMA_Priority_VeryHigh = DMA_CCR_PL_VeryHigh // 0x00003000U
|
||||
} DMA_priority_level_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA memory to memory Enumerate definition
|
||||
/// @anchor DMA_memory_to_memory
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_M2M_Disable = 0U,
|
||||
DMA_M2M_Enable = DMA_CCR_M2M // 0x00004000U
|
||||
} DMA_memory_to_memory_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA auto reload Enumerate definition
|
||||
/// @anchor DMA_auto_reload
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_Auto_Reload_Disable = 0U, //
|
||||
DMA_Auto_Reload_Enable = DMA_CCR_ARE
|
||||
} DMA_auto_reload_TypeDef;
|
||||
/// @brief DMA Interrupt Setting Enumerate definition
|
||||
/// @anchor DMA_auto_reload
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMA_IT_TC = DMA_CCR_TCIE, //(0x00000002UL),
|
||||
DMA_IT_HT = DMA_CCR_HTIE, //(0x00000004UL),
|
||||
DMA_IT_TE = DMA_CCR_TEIE, //(0x00000008UL),
|
||||
} DMA_Interrupt_EN_TypeDef;
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA interrupts Enumerate definition
|
||||
/// @anchor DMA_Flags
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
DMAx_IT_GLy = (0x00000001UL),
|
||||
DMAx_IT_TCy = (0x00000002UL),
|
||||
DMAx_IT_HTy = (0x00000004UL),
|
||||
DMAx_IT_TEy = (0x00000008UL),
|
||||
DMA1_IT_GL1 = (0x00000001UL),
|
||||
DMA1_IT_TC1 = (0x00000002UL),
|
||||
DMA1_IT_HT1 = (0x00000004UL),
|
||||
DMA1_IT_TE1 = (0x00000008UL),
|
||||
DMA1_IT_GL2 = (0x00000010UL),
|
||||
DMA1_IT_TC2 = (0x00000020UL),
|
||||
DMA1_IT_HT2 = (0x00000040UL),
|
||||
DMA1_IT_TE2 = (0x00000080UL),
|
||||
DMA1_IT_GL3 = (0x00000100UL),
|
||||
DMA1_IT_TC3 = (0x00000200UL),
|
||||
DMA1_IT_HT3 = (0x00000400UL),
|
||||
DMA1_IT_TE3 = (0x00000800UL),
|
||||
DMA1_IT_GL4 = (0x00001000UL),
|
||||
DMA1_IT_TC4 = (0x00002000UL),
|
||||
DMA1_IT_HT4 = (0x00004000UL),
|
||||
DMA1_IT_TE4 = (0x00008000UL),
|
||||
DMA1_IT_GL5 = (0x00010000UL),
|
||||
DMA1_IT_TC5 = (0x00020000UL),
|
||||
DMA1_IT_HT5 = (0x00040000UL),
|
||||
DMA1_IT_TE5 = (0x00080000UL),
|
||||
DMA1_IT_GL6 = (0x00100000UL),
|
||||
DMA1_IT_TC6 = (0x00200000UL),
|
||||
DMA1_IT_HT6 = (0x00400000UL),
|
||||
DMA1_IT_TE6 = (0x00800000UL),
|
||||
DMA1_IT_GL7 = (0x01000000UL),
|
||||
DMA1_IT_TC7 = (0x02000000UL),
|
||||
DMA1_IT_HT7 = (0x04000000UL),
|
||||
DMA1_IT_TE7 = (0x08000000UL),
|
||||
DMA2_IT_GL1 = (0x10000001UL),
|
||||
DMA2_IT_TC1 = (0x10000002UL),
|
||||
DMA2_IT_HT1 = (0x10000004UL),
|
||||
DMA2_IT_TE1 = (0x10000008UL),
|
||||
DMA2_IT_GL2 = (0x10000010UL),
|
||||
DMA2_IT_TC2 = (0x10000020UL),
|
||||
DMA2_IT_HT2 = (0x10000040UL),
|
||||
DMA2_IT_TE2 = (0x10000080UL),
|
||||
DMA2_IT_GL3 = (0x10000100UL),
|
||||
DMA2_IT_TC3 = (0x10000200UL),
|
||||
DMA2_IT_HT3 = (0x10000400UL),
|
||||
DMA2_IT_TE3 = (0x10000800UL),
|
||||
DMA2_IT_GL4 = (0x10001000UL),
|
||||
DMA2_IT_TC4 = (0x10002000UL),
|
||||
DMA2_IT_HT4 = (0x10004000UL),
|
||||
DMA2_IT_TE4 = (0x10008000UL),
|
||||
DMA2_IT_GL5 = (0x10010000UL),
|
||||
DMA2_IT_TC5 = (0x10020000UL),
|
||||
DMA2_IT_HT5 = (0x10040000UL),
|
||||
DMA2_IT_TE5 = (0x10080000UL),
|
||||
} DMA_Interrupts_TypeDef;
|
||||
typedef enum {
|
||||
DMAx_FLAG_GLy = (0x00000001UL),
|
||||
DMAx_FLAG_TCy = (0x00000002UL),
|
||||
DMAx_FLAG_HTy = (0x00000004UL),
|
||||
DMAx_FLAG_TEy = (0x00000008UL),
|
||||
DMA1_FLAG_GL1 = (0x00000001UL),
|
||||
DMA1_FLAG_TC1 = (0x00000002UL),
|
||||
DMA1_FLAG_HT1 = (0x00000004UL),
|
||||
DMA1_FLAG_TE1 = (0x00000008UL),
|
||||
DMA1_FLAG_GL2 = (0x00000010UL),
|
||||
DMA1_FLAG_TC2 = (0x00000020UL),
|
||||
DMA1_FLAG_HT2 = (0x00000040UL),
|
||||
DMA1_FLAG_TE2 = (0x00000080UL),
|
||||
DMA1_FLAG_GL3 = (0x00000100UL),
|
||||
DMA1_FLAG_TC3 = (0x00000200UL),
|
||||
DMA1_FLAG_HT3 = (0x00000400UL),
|
||||
DMA1_FLAG_TE3 = (0x00000800UL),
|
||||
DMA1_FLAG_GL4 = (0x00001000UL),
|
||||
DMA1_FLAG_TC4 = (0x00002000UL),
|
||||
DMA1_FLAG_HT4 = (0x00004000UL),
|
||||
DMA1_FLAG_TE4 = (0x00008000UL),
|
||||
DMA1_FLAG_GL5 = (0x00010000UL),
|
||||
DMA1_FLAG_TC5 = (0x00020000UL),
|
||||
DMA1_FLAG_HT5 = (0x00040000UL),
|
||||
DMA1_FLAG_TE5 = (0x00080000UL),
|
||||
DMA1_FLAG_GL6 = (0x00100000UL),
|
||||
DMA1_FLAG_TC6 = (0x00200000UL),
|
||||
DMA1_FLAG_HT6 = (0x00400000UL),
|
||||
DMA1_FLAG_TE6 = (0x00800000UL),
|
||||
DMA1_FLAG_GL7 = (0x01000000UL),
|
||||
DMA1_FLAG_TC7 = (0x02000000UL),
|
||||
DMA1_FLAG_HT7 = (0x04000000UL),
|
||||
DMA1_FLAG_TE7 = (0x08000000UL),
|
||||
DMA2_FLAG_GL1 = (0x10000001UL),
|
||||
DMA2_FLAG_TC1 = (0x10000002UL),
|
||||
DMA2_FLAG_HT1 = (0x10000004UL),
|
||||
DMA2_FLAG_TE1 = (0x10000008UL),
|
||||
DMA2_FLAG_GL2 = (0x10000010UL),
|
||||
DMA2_FLAG_TC2 = (0x10000020UL),
|
||||
DMA2_FLAG_HT2 = (0x10000040UL),
|
||||
DMA2_FLAG_TE2 = (0x10000080UL),
|
||||
DMA2_FLAG_GL3 = (0x10000100UL),
|
||||
DMA2_FLAG_TC3 = (0x10000200UL),
|
||||
DMA2_FLAG_HT3 = (0x10000400UL),
|
||||
DMA2_FLAG_TE3 = (0x10000800UL),
|
||||
DMA2_FLAG_GL4 = (0x10001000UL),
|
||||
DMA2_FLAG_TC4 = (0x10002000UL),
|
||||
DMA2_FLAG_HT4 = (0x10004000UL),
|
||||
DMA2_FLAG_TE4 = (0x10008000UL),
|
||||
DMA2_FLAG_GL5 = (0x10010000UL),
|
||||
DMA2_FLAG_TC5 = (0x10020000UL),
|
||||
DMA2_FLAG_HT5 = (0x10040000UL),
|
||||
DMA2_FLAG_TE5 = (0x10080000UL),
|
||||
} DMA_Flags_TypeDef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief DMA Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u32 DMA_PeripheralBaseAddr; ///< the peripheral base address for DMA Channeln.
|
||||
u32 DMA_MemoryBaseAddr; ///< the memory base address for DMA Channeln.
|
||||
DMA_data_transfer_direction_TypeDef DMA_DIR; ///< the peripheral is the source or destination.
|
||||
u32 DMA_BufferSize; ///< Specifies the buffer size, in data unit, of the Buffer size
|
||||
DMA_peripheral_incremented_mode_TypeDef DMA_PeripheralInc; ///< Specifies whether the Peripheral address increment or not
|
||||
DMA_memory_incremented_mode_TypeDef DMA_MemoryInc; ///< Specifies whether the memory address register is increment or not
|
||||
DMA_peripheral_data_size_TypeDef DMA_PeripheralDataSize; ///< Specifies the Peripheral data width.
|
||||
DMA_memory_data_size_TypeDef DMA_MemoryDataSize; ///< Specifies the Memory data width.
|
||||
DMA_circular_normal_mode_TypeDef DMA_Mode; ///< Specifies the operation mode of the DMA Channeln circular or normal mode.
|
||||
DMA_priority_level_TypeDef DMA_Priority; ///< Specifies the software priority for the DMA priority level
|
||||
DMA_memory_to_memory_TypeDef DMA_M2M; ///< Specifies if the DMA Channeln will be used in memory-to-memory transfer.
|
||||
DMA_auto_reload_TypeDef DMA_Auto_reload; ///< Specifies if the DMA Channeln will auto reload the CNDTR register
|
||||
} DMA_InitTypeDef;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DMA_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_DMA_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DMA_Exported_Functions
|
||||
/// @{
|
||||
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* channel);
|
||||
void DMA_Init(DMA_Channel_TypeDef* channel, DMA_InitTypeDef* init_struct);
|
||||
void DMA_StructInit(DMA_InitTypeDef* init_struct);
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* channel, FunctionalState state);
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* channel, DMA_Interrupt_EN_TypeDef it, FunctionalState state);
|
||||
void DMA_ClearFlag(DMA_Flags_TypeDef flag);
|
||||
void DMA_ClearITPendingBit(DMA_Interrupts_TypeDef it);
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* channel, u16 length);
|
||||
u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* channel);
|
||||
FlagStatus DMA_GetFlagStatus(DMA_Flags_TypeDef flag);
|
||||
ITStatus DMA_GetITStatus(DMA_Interrupts_TypeDef it);
|
||||
|
||||
void exDMA_SetPeripheralAddress(DMA_Channel_TypeDef* channel, u32 addr);
|
||||
void exDMA_SetTransmitLen(DMA_Channel_TypeDef* channel, u16 len);
|
||||
void exDMA_SetMemoryAddress(DMA_Channel_TypeDef* channel, u32 addr);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_DMA_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,729 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file HAL_eth.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE HAL_eth.h EXAMPLES.
|
||||
/// ////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef __HAL_ETH_H
|
||||
#define __HAL_ETH_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "mm32_device.h"
|
||||
#include "HAL_eth_conf.h"
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup ETH_HAL
|
||||
/// @brief ETH HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup ETH_Exported_Types
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ETH | Header | Extra | VLAN tag | Payload | CRC |
|
||||
// Size | 14 | 2 | 4 | 46 ~ 1500 | 4 |
|
||||
#define ETH_MAX_PACKET_SIZE 1524
|
||||
#define ETH_HEADER 14 ///< MAC Dest Addr 6 byte + MAC Src Addr 6 byte + Lenth/Type 2 byte
|
||||
#define ETH_EXTRA 2
|
||||
#define VLAN_TAG 4
|
||||
#define ETH_PAYLOAD_MIN 46
|
||||
#define ETH_PAYLOAD_MAX 1500
|
||||
#define JUMBO_FRAME_PAYLOAD 9000
|
||||
|
||||
#ifndef ETH_RX_BUF_SIZE
|
||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
|
||||
#endif
|
||||
|
||||
#ifndef ETH_RX_BUF_NUM
|
||||
#define ETH_RX_BUF_NUM 4
|
||||
#endif
|
||||
|
||||
#ifndef ETH_TX_BUF_SIZE
|
||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
|
||||
#endif
|
||||
|
||||
#ifndef ETH_TX_BUF_NUM
|
||||
#define ETH_TX_BUF_NUM 4
|
||||
#endif
|
||||
|
||||
#define ETH_DMA_RDES_FL_Pos 16 ///< Ethernet DMA Received Frame Length Position
|
||||
|
||||
#define ETH_WAKEUP_REGISTER_LENGTH 8 ///< ETHERNET Remote Wake-up frame register length
|
||||
|
||||
#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 ///< ETHERNET Missed frames counter Shift
|
||||
|
||||
#define ETH_DMA_TDES_COLLISION_COUNTSHIFT 3 ///< ETHERNET DMA Tx descriptors Collision Count Shift
|
||||
#define ETH_DMA_TDES_BUFFER2_SIZESHIFT 11 ///< ETHERNET DMA Tx descriptors Buffer2 Size Shift
|
||||
|
||||
#define ETH_DMA_RDES_FRAME_LENGTHSHIFT 16 ///< ETHERNET DMA Rx descriptors Frame Length Shift
|
||||
#define ETH_DMA_RDES_BUFFER2_SIZESHIFT 11 ///< ETHERNET DMA Rx descriptors Buffer2 Size Shift
|
||||
|
||||
///< ETHERNET errors
|
||||
#define ETH_ERROR ((u32)0)
|
||||
#define ETH_SUCCESS ((u32)1)
|
||||
|
||||
|
||||
#ifdef _HAL_ETH_C_
|
||||
#define GLOBAL
|
||||
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief ETH Init Structure Definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
__IO u32 ETH_AutoNegotiation;
|
||||
__IO u32 ETH_Watchdog;
|
||||
__IO u32 ETH_Jabber;
|
||||
__IO u32 ETH_InterFrameGap;
|
||||
__IO u32 ETH_CarrierSense;
|
||||
__IO u32 ETH_Speed;
|
||||
__IO u32 ETH_ReceiveOwn;
|
||||
__IO u32 ETH_LoopbackMode;
|
||||
__IO u32 ETH_Mode;
|
||||
__IO u32 ETH_ChecksumOffload;
|
||||
__IO u32 ETH_RetryTransmission;
|
||||
__IO u32 ETH_AutomaticPadCRCStrip;
|
||||
__IO u32 ETH_BackOffLimit;
|
||||
__IO u32 ETH_DeferralCheck;
|
||||
__IO u32 ETH_ReceiveAll;
|
||||
__IO u32 ETH_SourceAddrFilter;
|
||||
__IO u32 ETH_PassControlFrames;
|
||||
__IO u32 ETH_BroadcastFramesReception;
|
||||
__IO u32 ETH_DestinationAddrFilter;
|
||||
__IO u32 ETH_PromiscuousMode;
|
||||
__IO u32 ETH_MulticastFramesFilter;
|
||||
__IO u32 ETH_UnicastFramesFilter;
|
||||
__IO u32 ETH_HashTableHigh;
|
||||
__IO u32 ETH_HashTableLow;
|
||||
__IO u32 ETH_PauseTime;
|
||||
__IO u32 ETH_ZeroQuantaPause;
|
||||
__IO u32 ETH_PauseLowThreshold;
|
||||
__IO u32 ETH_UnicastPauseFrameDetect;
|
||||
__IO u32 ETH_ReceiveFlowControl;
|
||||
__IO u32 ETH_TransmitFlowControl;
|
||||
__IO u32 ETH_VLANTagComparison;
|
||||
__IO u32 ETH_VLANTagIdentifier;
|
||||
__IO u32 ETH_DropTCPIPChecksumErrorFrame;
|
||||
__IO u32 ETH_ReceiveStoreForward;
|
||||
__IO u32 ETH_FlushReceivedFrame;
|
||||
__IO u32 ETH_TransmitStoreForward;
|
||||
__IO u32 ETH_TransmitThresholdControl;
|
||||
__IO u32 ETH_ForwardErrorFrames;
|
||||
__IO u32 ETH_ForwardUndersizedGoodFrames;
|
||||
__IO u32 ETH_ReceiveThresholdControl;
|
||||
__IO u32 ETH_SecondFrameOperate;
|
||||
__IO u32 ETH_AddressAlignedBeats;
|
||||
__IO u32 ETH_FixedBurst;
|
||||
__IO u32 ETH_RxDMABurstLength;
|
||||
__IO u32 ETH_TxDMABurstLength;
|
||||
__IO u32 ETH_DescriptorSkipLength;
|
||||
__IO u32 ETH_DMAArbitration;
|
||||
} ETH_InitTypeDef;
|
||||
|
||||
typedef struct {
|
||||
__IO u32 CS; ///< Control and Status
|
||||
__IO u32 BL; ///< Buffer1, Buffer2 lengths
|
||||
__IO u32 BUF1ADDR; ///< Buffer1 address pointer
|
||||
__IO u32 BUF2NDADDR; ///< Buffer2 or next descriptor address pointer
|
||||
|
||||
#ifdef USE_ENHANCED_DMA_DESCRIPTORS ///< Enhanced ETHERNET DMA PTP Descriptors
|
||||
__IO u32 ExtendedStatus; ///< Extended status for PTP receive descriptor
|
||||
__IO u32 Reserved1; ///< Reserved
|
||||
__IO u32 TimeStampLow; ///< Time Stamp Low value for transmit and receive
|
||||
__IO u32 TimeStampHigh; ///< Time Stamp High value for transmit and receive
|
||||
#endif
|
||||
} ETH_DMADESCTypeDef;
|
||||
|
||||
typedef struct {
|
||||
__IO u32 len;
|
||||
__IO u32 buf;
|
||||
__IO ETH_DMADESCTypeDef* ptrDesc;
|
||||
} FrameTypeDef;
|
||||
|
||||
typedef struct {
|
||||
__IO ETH_DMADESCTypeDef* ptrFS_Rx_Desc; ///< First Segment Rx Desc
|
||||
__IO ETH_DMADESCTypeDef* ptrLS_Rx_Desc; ///< Last Segment Rx Desc
|
||||
__IO u32 cnt; ///< Segment count
|
||||
} ETH_DMA_Rx_Frame_infos;
|
||||
|
||||
|
||||
|
||||
#define ETH_DMA_TDES_OWN ((u32)0x80000000) ///< OWN bit: descriptor is owned by DMA engine
|
||||
#define ETH_DMA_TDES_ES ((u32)0x00008000) ///< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT
|
||||
#define ETH_DMA_TDES_JT ((u32)0x00004000) ///< Jabber Timeout
|
||||
#define ETH_DMA_TDES_FF ((u32)0x00002000) ///< Frame Flushed: DMA/MTL flushed the frame due to SW flush
|
||||
#define ETH_DMA_TDES_LCA ((u32)0x00000800) ///< Loss of Carrier: carrier lost during transmission
|
||||
#define ETH_DMA_TDES_NC ((u32)0x00000400) ///< No Carrier: no carrier signal from the transceiver
|
||||
#define ETH_DMA_TDES_LCO ((u32)0x00000200) ///< Late Collision: transmission aborted due to collision
|
||||
#define ETH_DMA_TDES_EC ((u32)0x00000100) ///< Excessive Collision: transmission aborted after 16 collisions
|
||||
#define ETH_DMA_TDES_VF ((u32)0x00000080) ///< VLAN Frame
|
||||
#define ETH_DMA_TDES_CC ((u32)0x00000078) ///< Collision Count
|
||||
#define ETH_DMA_TDES_ED ((u32)0x00000004) ///< Excessive Deferral
|
||||
#define ETH_DMA_TDES_UF ((u32)0x00000002) ///< Underflow Error: late data arrival from the memory
|
||||
#define ETH_DMA_TDES_DB ((u32)0x00000001) ///< Deferred Bit
|
||||
|
||||
#define ETH_DMA_TDES_IC ((u32)0x80000000) ///< Interrupt on Completion
|
||||
#define ETH_DMA_TDES_LS ((u32)0x40000000) ///< Last Segment
|
||||
#define ETH_DMA_TDES_FS ((u32)0x20000000) ///< First Segment
|
||||
#define ETH_DMA_TDES_DC ((u32)0x04000000) ///< Disable CRC
|
||||
#define ETH_DMA_TDES_TER ((u32)0x02000000) ///< Transmit end of ring
|
||||
#define ETH_DMA_TDES_TCH ((u32)0x01000000) ///< Second Address Chained
|
||||
#define ETH_DMA_TDES_DP ((u32)0x00800000) ///< Disable Padding
|
||||
#define ETH_DMA_TDES_TBS2 ((u32)0x003FF800) ///< Transmit Buffer 2 Size
|
||||
#define ETH_DMA_TDES_TBS1 ((u32)0x000007FF) ///< Transmit Buffer 1 Size
|
||||
|
||||
#define ETH_DMA_TDES_B1AP ((u32)0xFFFFFFFF) ///< Buffer 1 Address Pointer
|
||||
|
||||
#define ETH_DMA_TDES_B2AP ((u32)0xFFFFFFFF) ///< Buffer 2 Address Pointer
|
||||
|
||||
#if defined(USE_ENHANCED_DMA_DESCRIPTORS)
|
||||
#define ETH_DMA_PTP_TDES_TTSL ((u32)0xFFFFFFFF) ///< Transmit Time Stamp Low
|
||||
#define ETH_DMA_PTP_TDES_TTSH ((u32)0xFFFFFFFF) ///< Transmit Time Stamp High
|
||||
#endif
|
||||
|
||||
#define ETH_DMA_RDES_OWN ((u32)0x80000000) ///< OWN bit: descriptor is owned by DMA engine
|
||||
#define ETH_DMA_RDES_AFM ((u32)0x40000000) ///< DA Filter Fail for the rx frame
|
||||
#define ETH_DMA_RDES_FL ((u32)0x3FFF0000) ///< Receive descriptor frame length
|
||||
#define ETH_DMA_RDES_ES ((u32)0x00008000) ///< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE
|
||||
#define ETH_DMA_RDES_DE ((u32)0x00004000) ///< Descriptor error: no more descriptors for receive frame
|
||||
#define ETH_DMA_RDES_SAF ((u32)0x00002000) ///< SA Filter Fail for the received frame
|
||||
#define ETH_DMA_RDES_LE ((u32)0x00001000) ///< Frame size not matching with length field
|
||||
#define ETH_DMA_RDES_OE ((u32)0x00000800) ///< Overflow Error: Frame was damaged due to buffer overflow
|
||||
#define ETH_DMA_RDES_VLAN ((u32)0x00000400) ///< VLAN Tag: received frame is a VLAN frame
|
||||
#define ETH_DMA_RDES_FS ((u32)0x00000200) ///< First descriptor of the frame
|
||||
#define ETH_DMA_RDES_LS ((u32)0x00000100) ///< Last descriptor of the frame
|
||||
#define ETH_DMA_RDES_IPV4HCE ((u32)0x00000080) ///< IPC Checksum Error: Rx Ipv4 header checksum error
|
||||
#define ETH_DMA_RDES_LC ((u32)0x00000040) ///< Late collision occurred during reception
|
||||
#define ETH_DMA_RDES_FT ((u32)0x00000020) ///< Frame type - Ethernet, otherwise 802.3
|
||||
#define ETH_DMA_RDES_RWT ((u32)0x00000010) ///< Receive Watchdog Timeout: watchdog timer expired during reception
|
||||
#define ETH_DMA_RDES_RE ((u32)0x00000008) ///< Receive error: error reported by MII interface
|
||||
#define ETH_DMA_RDES_DBE ((u32)0x00000004) ///< Dribble bit error: frame contains non int multiple of 8 bits
|
||||
#define ETH_DMA_RDES_CE ((u32)0x00000002) ///< CRC error
|
||||
#define ETH_DMA_RDES_MAMPCE ((u32)0x00000001) ///< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
|
||||
|
||||
#define ETH_DMA_RDES_DIC ((u32)0x80000000) ///< Disable Interrupt on Completion
|
||||
#define ETH_DMA_RDES_RER ((u32)0x02000000) ///< Receive End of Ring
|
||||
#define ETH_DMA_RDES_RCH ((u32)0x01000000) ///< Second Address Chained
|
||||
#define ETH_DMA_RDES_RBS2 ((u32)0x003FF800) ///< Receive Buffer2 Size
|
||||
#define ETH_DMA_RDES_RBS1 ((u32)0x000007FF) ///< Receive Buffer1 Size
|
||||
|
||||
#define ETH_DMA_RDES_B1AP ((u32)0xFFFFFFFF) ///< Buffer 1 Address Pointer
|
||||
|
||||
#define ETH_DMA_RDES_B2AP ((u32)0xFFFFFFFF) ///< Buffer 2 Address Pointer
|
||||
|
||||
|
||||
#if defined(USE_ENHANCED_DMA_DESCRIPTORS)
|
||||
#define ETH_DMA_PTP_RDES_PTPV ((u32)0x00002000) ///< PTP Version
|
||||
#define ETH_DMA_PTP_RDES_PTPFT ((u32)0x00001000) ///< PTP Frame Type
|
||||
#define ETH_DMA_PTP_RDES_PTPMT ((u32)0x00000F00) ///< PTP Message Type
|
||||
#define ETH_DMA_PTP_RDES_PTPMT_Sync ((u32)0x00000100) ///< SYNC message (all clock types)
|
||||
#define ETH_DMA_PTP_RDES_PTPMT_FollowUp ((u32)0x00000200) ///< FollowUp message (all clock types)
|
||||
#define ETH_DMA_PTP_RDES_PTPMT_DelayReq ((u32)0x00000300) ///< DelayReq message (all clock types)
|
||||
#define ETH_DMA_PTP_RDES_PTPMT_DelayResp ((u32)0x00000400) ///< DelayResp message (all clock types)
|
||||
#define ETH_DMA_PTP_RDES_PTPMT_PdelayReq_Announce ((u32)0x00000500) ///< PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock)
|
||||
#define ETH_DMA_PTP_RDES_PTPMT_PdelayResp_Manag ((u32)0x00000600) ///< PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock)
|
||||
#define ETH_DMA_PTP_RDES_PTPMT_PdelayRespFollowUp_Signal ((u32)0x00000700) ///< PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock)
|
||||
#define ETH_DMA_PTP_RDES_IPV6PR ((u32)0x00000080) ///< IPv6 Packet Received
|
||||
#define ETH_DMA_PTP_RDES_IPV4PR ((u32)0x00000040) ///< IPv4 Packet Received
|
||||
#define ETH_DMA_PTP_RDES_IPCB ((u32)0x00000020) ///< IP Checksum Bypassed
|
||||
#define ETH_DMA_PTP_RDES_IPPE ((u32)0x00000010) ///< IP Payload Error
|
||||
#define ETH_DMA_PTP_RDES_IPHE ((u32)0x00000008) ///< IP Header Error
|
||||
#define ETH_DMA_PTP_RDES_IPPT ((u32)0x00000007) ///< IP Payload Type
|
||||
#define ETH_DMA_PTP_RDES_IPPT_UDP ((u32)0x00000001) ///< UDP payload encapsulated in the IP datagram
|
||||
#define ETH_DMA_PTP_RDES_IPPT_TCP ((u32)0x00000002) ///< TCP payload encapsulated in the IP datagram
|
||||
#define ETH_DMA_PTP_RDES_IPPT_ICMP ((u32)0x00000003) ///< ICMP payload encapsulated in the IP datagram
|
||||
|
||||
|
||||
|
||||
#define ETH_DMA_PTP_RDES_TTSL ((u32)0xFFFFFFFF) ///< Receive Time Stamp Low
|
||||
#define ETH_DMA_PTP_RDES_TTSH ((u32)0xFFFFFFFF) ///< Receive Time Stamp High
|
||||
#endif
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#define PHY_READ_TIMEOUT ((u32)0x0004FFFF)
|
||||
#define PHY_WRITE_TIMEOUT ((u32)0x0004FFFF)
|
||||
|
||||
#define PHY_BCR 0 ///< Transceiver Basic Control Register
|
||||
#define PHY_BSR 1 ///< Transceiver Basic Status Register
|
||||
|
||||
#define PHY_Reset ((u16)0x8000) ///< PHY Reset
|
||||
#define PHY_Loopback ((u16)0x4000) ///< Select loop-back mode
|
||||
#define PHY_FULLDUPLEX_100M ((u16)0x2100) ///< Set the full-duplex mode at 100 Mb/s
|
||||
#define PHY_HALFDUPLEX_100M ((u16)0x2000) ///< Set the half-duplex mode at 100 Mb/s
|
||||
#define PHY_FULLDUPLEX_10M ((u16)0x0100) ///< Set the full-duplex mode at 10 Mb/s
|
||||
#define PHY_HALFDUPLEX_10M ((u16)0x0000) ///< Set the half-duplex mode at 10 Mb/s
|
||||
#define PHY_AutoNegotiation ((u16)0x1000) ///< Enable auto-negotiation function
|
||||
#define PHY_Restart_AutoNegotiation ((u16)0x0200) ///< Restart auto-negotiation function
|
||||
#define PHY_Powerdown ((u16)0x0800) ///< Select the power down mode
|
||||
#define PHY_Isolate ((u16)0x0400) ///< Isolate PHY from MII
|
||||
|
||||
#define PHY_AutoNego_Complete ((u16)0x0020) ///< Auto-Negotiation process completed
|
||||
#define PHY_Linked_Status ((u16)0x0004) ///< Valid link established
|
||||
#define PHY_Jabber_detection ((u16)0x0002) ///< Jabber condition detected
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#define ETH_AutoNegotiation_Enable ((u32)0x00000001)
|
||||
#define ETH_AutoNegotiation_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_Watchdog_Enable ((u32)0x00000000)
|
||||
#define ETH_Watchdog_Disable ((u32)0x00800000)
|
||||
|
||||
#define ETH_Jabber_Enable ((u32)0x00000000)
|
||||
#define ETH_Jabber_Disable ((u32)0x00400000)
|
||||
|
||||
#define ETH_InterFrameGap_96Bit ((u32)0x00000000) ///< minimum IFG between frames during transmission is 96Bit
|
||||
#define ETH_InterFrameGap_88Bit ((u32)0x00020000) ///< minimum IFG between frames during transmission is 88Bit
|
||||
#define ETH_InterFrameGap_80Bit ((u32)0x00040000) ///< minimum IFG between frames during transmission is 80Bit
|
||||
#define ETH_InterFrameGap_72Bit ((u32)0x00060000) ///< minimum IFG between frames during transmission is 72Bit
|
||||
#define ETH_InterFrameGap_64Bit ((u32)0x00080000) ///< minimum IFG between frames during transmission is 64Bit
|
||||
#define ETH_InterFrameGap_56Bit ((u32)0x000A0000) ///< minimum IFG between frames during transmission is 56Bit
|
||||
#define ETH_InterFrameGap_48Bit ((u32)0x000C0000) ///< minimum IFG between frames during transmission is 48Bit
|
||||
#define ETH_InterFrameGap_40Bit ((u32)0x000E0000) ///< minimum IFG between frames during transmission is 40Bit
|
||||
|
||||
#define ETH_CarrierSense_Enable ((u32)0x00000000)
|
||||
#define ETH_CarrierSense_Disable ((u32)0x00010000)
|
||||
|
||||
#define ETH_Speed_10M ((u32)0x00000000)
|
||||
#define ETH_Speed_100M ((u32)0x00004000)
|
||||
|
||||
#define ETH_ReceiveOwn_Enable ((u32)0x00000000)
|
||||
#define ETH_ReceiveOwn_Disable ((u32)0x00002000)
|
||||
|
||||
#define ETH_LoopbackMode_Enable ((u32)0x00001000)
|
||||
#define ETH_LoopbackMode_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_Mode_FullDuplex ((u32)0x00000800)
|
||||
#define ETH_Mode_HalfDuplex ((u32)0x00000000)
|
||||
|
||||
#define ETH_ChecksumOffload_Enable ((u32)0x00000400)
|
||||
#define ETH_ChecksumOffload_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_RetryTransmission_Enable ((u32)0x00000000)
|
||||
#define ETH_RetryTransmission_Disable ((u32)0x00000200)
|
||||
|
||||
#define ETH_AutomaticPadCRCStrip_Enable ((u32)0x00000080)
|
||||
#define ETH_AutomaticPadCRCStrip_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_BackOffLimit_10 ((u32)0x00000000)
|
||||
#define ETH_BackOffLimit_8 ((u32)0x00000020)
|
||||
#define ETH_BackOffLimit_4 ((u32)0x00000040)
|
||||
#define ETH_BackOffLimit_1 ((u32)0x00000060)
|
||||
|
||||
#define ETH_DeferralCheck_Enable ((u32)0x00000010)
|
||||
#define ETH_DeferralCheck_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_ReceiveAll_Enable ((u32)0x80000000)
|
||||
#define ETH_ReceiveAll_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_SourceAddrFilter_Normal_Enable ((u32)0x00000200)
|
||||
#define ETH_SourceAddrFilter_Inverse_Enable ((u32)0x00000300)
|
||||
#define ETH_SourceAddrFilter_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_PassControlFrames_BlockAll ((u32)0x00000040) ///< MAC filters all control frames from reaching the application
|
||||
#define ETH_PassControlFrames_ForwardAll ((u32)0x00000080) ///< MAC forwards all control frames to application even if they fail the Address Filter
|
||||
#define ETH_PassControlFrames_ForwardPassedAddrFilter ((u32)0x000000C0) ///< MAC forwards control frames that pass the Address Filter.
|
||||
|
||||
#define ETH_BroadcastFramesReception_Enable ((u32)0x00000000)
|
||||
#define ETH_BroadcastFramesReception_Disable ((u32)0x00000020)
|
||||
|
||||
#define ETH_DestinationAddrFilter_Normal ((u32)0x00000000)
|
||||
#define ETH_DestinationAddrFilter_Inverse ((u32)0x00000008)
|
||||
|
||||
#define ETH_PromiscuousMode_Enable ((u32)0x00000001)
|
||||
#define ETH_PromiscuousMode_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_MulticastFramesFilter_PerfectHashTable ((u32)0x00000404)
|
||||
#define ETH_MulticastFramesFilter_HashTable ((u32)0x00000004)
|
||||
#define ETH_MulticastFramesFilter_Perfect ((u32)0x00000000)
|
||||
#define ETH_MulticastFramesFilter_None ((u32)0x00000010)
|
||||
|
||||
#define ETH_UnicastFramesFilter_PerfectHashTable ((u32)0x00000402)
|
||||
#define ETH_UnicastFramesFilter_HashTable ((u32)0x00000002)
|
||||
#define ETH_UnicastFramesFilter_Perfect ((u32)0x00000000)
|
||||
|
||||
#define ETH_ZeroQuantaPause_Enable ((u32)0x00000000)
|
||||
#define ETH_ZeroQuantaPause_Disable ((u32)0x00000080)
|
||||
|
||||
#define ETH_PauseLowThreshold_Minus4 ((u32)0x00000000) ///< Pause time minus 4 slot times
|
||||
#define ETH_PauseLowThreshold_Minus28 ((u32)0x00000010) ///< Pause time minus 28 slot times
|
||||
#define ETH_PauseLowThreshold_Minus144 ((u32)0x00000020) ///< Pause time minus 144 slot times
|
||||
#define ETH_PauseLowThreshold_Minus256 ((u32)0x00000030) ///< Pause time minus 256 slot times
|
||||
|
||||
#define ETH_UnicastPauseFrameDetect_Enable ((u32)0x00000008)
|
||||
#define ETH_UnicastPauseFrameDetect_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_ReceiveFlowControl_Enable ((u32)0x00000004)
|
||||
#define ETH_ReceiveFlowControl_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_TransmitFlowControl_Enable ((u32)0x00000002)
|
||||
#define ETH_TransmitFlowControl_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_VLANTagComparison_12Bit ((u32)0x00010000)
|
||||
#define ETH_VLANTagComparison_16Bit ((u32)0x00000000)
|
||||
|
||||
#define ETH_MAC_FLAG_TST ((u32)0x00000200) ///< Time stamp trigger flag (on MAC)
|
||||
#define ETH_MAC_FLAG_MMCT ((u32)0x00000040) ///< MMC transmit flag
|
||||
#define ETH_MAC_FLAG_MMCR ((u32)0x00000020) ///< MMC receive flag
|
||||
#define ETH_MAC_FLAG_MMC ((u32)0x00000010) ///< MMC flag (on MAC)
|
||||
#define ETH_MAC_FLAG_PMT ((u32)0x00000008) ///< PMT flag (on MAC)
|
||||
|
||||
#define ETH_MAC_IT_TST ((u32)0x00000200) ///< Time stamp trigger interrupt (on MAC)
|
||||
#define ETH_MAC_IT_MMCT ((u32)0x00000040) ///< MMC transmit interrupt
|
||||
#define ETH_MAC_IT_MMCR ((u32)0x00000020) ///< MMC receive interrupt
|
||||
#define ETH_MAC_IT_MMC ((u32)0x00000010) ///< MMC interrupt (on MAC)
|
||||
#define ETH_MAC_IT_PMT ((u32)0x00000008) ///< PMT interrupt (on MAC)
|
||||
|
||||
#define ETH_MAC_Address0 ((u32)0x00000000)
|
||||
#define ETH_MAC_Address1 ((u32)0x00000008)
|
||||
#define ETH_MAC_Address2 ((u32)0x00000010)
|
||||
#define ETH_MAC_Address3 ((u32)0x00000018)
|
||||
|
||||
#define ETH_MAC_AddressFilter_SA ((u32)0x00000000)
|
||||
#define ETH_MAC_AddressFilter_DA ((u32)0x00000008)
|
||||
|
||||
#define ETH_MAC_AddressMask_Byte6 ((u32)0x20000000) ///< Mask MAC Address high reg bits [15:8]
|
||||
#define ETH_MAC_AddressMask_Byte5 ((u32)0x10000000) ///< Mask MAC Address high reg bits [7:0]
|
||||
#define ETH_MAC_AddressMask_Byte4 ((u32)0x08000000) ///< Mask MAC Address low reg bits [31:24]
|
||||
#define ETH_MAC_AddressMask_Byte3 ((u32)0x04000000) ///< Mask MAC Address low reg bits [23:16]
|
||||
#define ETH_MAC_AddressMask_Byte2 ((u32)0x02000000) ///< Mask MAC Address low reg bits [15:8]
|
||||
#define ETH_MAC_AddressMask_Byte1 ((u32)0x01000000) ///< Mask MAC Address low reg bits [70]
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#define ETH_DMA_TDES_LastSegment ((u32)0x40000000) ///< Last Segment
|
||||
#define ETH_DMA_TDES_FirstSegment ((u32)0x20000000) ///< First Segment
|
||||
|
||||
#define ETH_DMA_TDES_ChecksumByPass ((u32)0x00000000) ///< Checksum engine bypass
|
||||
#define ETH_DMA_TDES_ChecksumIPV4Header ((u32)0x00400000) ///< IPv4 header checksum insertion
|
||||
#define ETH_DMA_TDES_ChecksumTCPUDPICMPSegment ((u32)0x00800000) ///< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present
|
||||
#define ETH_DMA_TDES_ChecksumTCPUDPICMPFull ((u32)0x00C00000) ///< TCP/UDP/ICMP checksum fully in hardware including pseudo header
|
||||
|
||||
#define ETH_DMA_RDES_Buffer1 ((u32)0x00000000) ///< DMA Rx Desc Buffer1
|
||||
#define ETH_DMA_RDES_Buffer2 ((u32)0x00000001) ///< DMA Rx Desc Buffer2
|
||||
|
||||
#define ETH_DropTCPIPChecksumErrorFrame_Enable ((u32)0x00000000)
|
||||
#define ETH_DropTCPIPChecksumErrorFrame_Disable ((u32)0x04000000)
|
||||
|
||||
#define ETH_ReceiveStoreForward_Enable ((u32)0x02000000)
|
||||
#define ETH_ReceiveStoreForward_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_FlushReceivedFrame_Enable ((u32)0x00000000)
|
||||
#define ETH_FlushReceivedFrame_Disable ((u32)0x01000000)
|
||||
|
||||
#define ETH_TransmitStoreForward_Enable ((u32)0x00200000)
|
||||
#define ETH_TransmitStoreForward_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_TransmitThresholdControl_64Bytes ((u32)0x00000000) ///< threshold level of the MTL Transmit FIFO is 64 Bytes
|
||||
#define ETH_TransmitThresholdControl_128Bytes ((u32)0x00004000) ///< threshold level of the MTL Transmit FIFO is 128 Bytes
|
||||
#define ETH_TransmitThresholdControl_192Bytes ((u32)0x00008000) ///< threshold level of the MTL Transmit FIFO is 192 Bytes
|
||||
#define ETH_TransmitThresholdControl_256Bytes ((u32)0x0000C000) ///< threshold level of the MTL Transmit FIFO is 256 Bytes
|
||||
#define ETH_TransmitThresholdControl_40Bytes ((u32)0x00010000) ///< threshold level of the MTL Transmit FIFO is 40 Bytes
|
||||
#define ETH_TransmitThresholdControl_32Bytes ((u32)0x00014000) ///< threshold level of the MTL Transmit FIFO is 32 Bytes
|
||||
#define ETH_TransmitThresholdControl_24Bytes ((u32)0x00018000) ///< threshold level of the MTL Transmit FIFO is 24 Bytes
|
||||
#define ETH_TransmitThresholdControl_16Bytes ((u32)0x0001C000) ///< threshold level of the MTL Transmit FIFO is 16 Bytes
|
||||
|
||||
#define ETH_ForwardErrorFrames_Enable ((u32)0x00000080)
|
||||
#define ETH_ForwardErrorFrames_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_ForwardUndersizedGoodFrames_Enable ((u32)0x00000040)
|
||||
#define ETH_ForwardUndersizedGoodFrames_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_ReceiveThresholdControl_64Bytes ((u32)0x00000000) ///< threshold level of the MTL Receive FIFO is 64 Bytes
|
||||
#define ETH_ReceiveThresholdControl_32Bytes ((u32)0x00000008) ///< threshold level of the MTL Receive FIFO is 32 Bytes
|
||||
#define ETH_ReceiveThresholdControl_96Bytes ((u32)0x00000010) ///< threshold level of the MTL Receive FIFO is 96 Bytes
|
||||
#define ETH_ReceiveThresholdControl_128Bytes ((u32)0x00000018) ///< threshold level of the MTL Receive FIFO is 128 Bytes
|
||||
|
||||
#define ETH_SecondFrameOperate_Enable ((u32)0x00000004)
|
||||
#define ETH_SecondFrameOperate_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_AddressAlignedBeats_Enable ((u32)0x02000000)
|
||||
#define ETH_AddressAlignedBeats_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_FixedBurst_Enable ((u32)0x00010000)
|
||||
#define ETH_FixedBurst_Disable ((u32)0x00000000)
|
||||
|
||||
#define ETH_RxDMABurstLength_1Beat ((u32)0x00020000) ///< maximum number of beats to be transferred in one RxDMA transaction is 1
|
||||
#define ETH_RxDMABurstLength_2Beat ((u32)0x00040000) ///< maximum number of beats to be transferred in one RxDMA transaction is 2
|
||||
#define ETH_RxDMABurstLength_4Beat ((u32)0x00080000) ///< maximum number of beats to be transferred in one RxDMA transaction is 4
|
||||
#define ETH_RxDMABurstLength_8Beat ((u32)0x00100000) ///< maximum number of beats to be transferred in one RxDMA transaction is 8
|
||||
#define ETH_RxDMABurstLength_16Beat ((u32)0x00200000) ///< maximum number of beats to be transferred in one RxDMA transaction is 16
|
||||
#define ETH_RxDMABurstLength_32Beat ((u32)0x00400000) ///< maximum number of beats to be transferred in one RxDMA transaction is 32
|
||||
#define ETH_RxDMABurstLength_4xPBL_4Beat ((u32)0x01020000) ///< maximum number of beats to be transferred in one RxDMA transaction is 4
|
||||
#define ETH_RxDMABurstLength_4xPBL_8Beat ((u32)0x01040000) ///< maximum number of beats to be transferred in one RxDMA transaction is 8
|
||||
#define ETH_RxDMABurstLength_4xPBL_16Beat ((u32)0x01080000) ///< maximum number of beats to be transferred in one RxDMA transaction is 16
|
||||
#define ETH_RxDMABurstLength_4xPBL_32Beat ((u32)0x01100000) ///< maximum number of beats to be transferred in one RxDMA transaction is 32
|
||||
#define ETH_RxDMABurstLength_4xPBL_64Beat ((u32)0x01200000) ///< maximum number of beats to be transferred in one RxDMA transaction is 64
|
||||
#define ETH_RxDMABurstLength_4xPBL_128Beat ((u32)0x01400000) ///< maximum number of beats to be transferred in one RxDMA transaction is 128
|
||||
|
||||
#define ETH_TxDMABurstLength_1Beat ((u32)0x00000100) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1
|
||||
#define ETH_TxDMABurstLength_2Beat ((u32)0x00000200) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2
|
||||
#define ETH_TxDMABurstLength_4Beat ((u32)0x00000400) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4
|
||||
#define ETH_TxDMABurstLength_8Beat ((u32)0x00000800) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8
|
||||
#define ETH_TxDMABurstLength_16Beat ((u32)0x00001000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16
|
||||
#define ETH_TxDMABurstLength_32Beat ((u32)0x00002000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32
|
||||
#define ETH_TxDMABurstLength_4xPBL_4Beat ((u32)0x01000100) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4
|
||||
#define ETH_TxDMABurstLength_4xPBL_8Beat ((u32)0x01000200) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8
|
||||
#define ETH_TxDMABurstLength_4xPBL_16Beat ((u32)0x01000400) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16
|
||||
#define ETH_TxDMABurstLength_4xPBL_32Beat ((u32)0x01000800) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32
|
||||
#define ETH_TxDMABurstLength_4xPBL_64Beat ((u32)0x01001000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64
|
||||
#define ETH_TxDMABurstLength_4xPBL_128Beat ((u32)0x01002000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128
|
||||
|
||||
#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((u32)0x00000000)
|
||||
#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((u32)0x00004000)
|
||||
#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((u32)0x00008000)
|
||||
#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((u32)0x0000C000)
|
||||
#define ETH_DMAArbitration_RxPriorTx ((u32)0x00000002)
|
||||
|
||||
#define ETH_DMA_FLAG_TST ((u32)0x20000000) ///< Time-stamp trigger interrupt (on DMA)
|
||||
#define ETH_DMA_FLAG_PMT ((u32)0x10000000) ///< PMT interrupt (on DMA)
|
||||
#define ETH_DMA_FLAG_MMC ((u32)0x08000000) ///< MMC interrupt (on DMA)
|
||||
#define ETH_DMA_FLAG_DataTransferError ((u32)0x00800000) ///< Error bits 0-Rx DMA, 1-Tx DMA
|
||||
#define ETH_DMA_FLAG_ReadWriteError ((u32)0x01000000) ///< Error bits 0-write trnsf, 1-read transfr
|
||||
#define ETH_DMA_FLAG_AccessError ((u32)0x02000000) ///< Error bits 0-data buffer, 1-desc. access
|
||||
#define ETH_DMA_FLAG_NIS ((u32)0x00010000) ///< Normal interrupt summary flag
|
||||
#define ETH_DMA_FLAG_AIS ((u32)0x00008000) ///< Abnormal interrupt summary flag
|
||||
#define ETH_DMA_FLAG_ER ((u32)0x00004000) ///< Early receive flag
|
||||
#define ETH_DMA_FLAG_FBE ((u32)0x00002000) ///< Fatal bus error flag
|
||||
#define ETH_DMA_FLAG_ET ((u32)0x00000400) ///< Early transmit flag
|
||||
#define ETH_DMA_FLAG_RWT ((u32)0x00000200) ///< Receive watchdog timeout flag
|
||||
#define ETH_DMA_FLAG_RPS ((u32)0x00000100) ///< Receive process stopped flag
|
||||
#define ETH_DMA_FLAG_RBU ((u32)0x00000080) ///< Receive buffer unavailable flag
|
||||
#define ETH_DMA_FLAG_R ((u32)0x00000040) ///< Receive flag
|
||||
#define ETH_DMA_FLAG_TU ((u32)0x00000020) ///< Underflow flag
|
||||
#define ETH_DMA_FLAG_RO ((u32)0x00000010) ///< Overflow flag
|
||||
#define ETH_DMA_FLAG_TJT ((u32)0x00000008) ///< Transmit jabber timeout flag
|
||||
#define ETH_DMA_FLAG_TBU ((u32)0x00000004) ///< Transmit buffer unavailable flag
|
||||
#define ETH_DMA_FLAG_TPS ((u32)0x00000002) ///< Transmit process stopped flag
|
||||
#define ETH_DMA_FLAG_T ((u32)0x00000001) ///< Transmit flag
|
||||
|
||||
#define ETH_DMA_IT_TST ((u32)0x20000000) ///< Time-stamp trigger interrupt (on DMA)
|
||||
#define ETH_DMA_IT_PMT ((u32)0x10000000) ///< PMT interrupt (on DMA)
|
||||
#define ETH_DMA_IT_MMC ((u32)0x08000000) ///< MMC interrupt (on DMA)
|
||||
#define ETH_DMA_IT_NIS ((u32)0x00010000) ///< Normal interrupt summary
|
||||
#define ETH_DMA_IT_AIS ((u32)0x00008000) ///< Abnormal interrupt summary
|
||||
#define ETH_DMA_IT_ER ((u32)0x00004000) ///< Early receive interrupt
|
||||
#define ETH_DMA_IT_FBE ((u32)0x00002000) ///< Fatal bus error interrupt
|
||||
#define ETH_DMA_IT_ET ((u32)0x00000400) ///< Early transmit interrupt
|
||||
#define ETH_DMA_IT_RWT ((u32)0x00000200) ///< Receive watchdog timeout interrupt
|
||||
#define ETH_DMA_IT_RPS ((u32)0x00000100) ///< Receive process stopped interrupt
|
||||
#define ETH_DMA_IT_RBU ((u32)0x00000080) ///< Receive buffer unavailable interrupt
|
||||
#define ETH_DMA_IT_R ((u32)0x00000040) ///< Receive interrupt
|
||||
#define ETH_DMA_IT_TU ((u32)0x00000020) ///< Underflow interrupt
|
||||
#define ETH_DMA_IT_RO ((u32)0x00000010) ///< Overflow interrupt
|
||||
#define ETH_DMA_IT_TJT ((u32)0x00000008) ///< Transmit jabber timeout interrupt
|
||||
#define ETH_DMA_IT_TBU ((u32)0x00000004) ///< Transmit buffer unavailable interrupt
|
||||
#define ETH_DMA_IT_TPS ((u32)0x00000002) ///< Transmit process stopped interrupt
|
||||
#define ETH_DMA_IT_T ((u32)0x00000001) ///< Transmit interrupt
|
||||
|
||||
#define ETH_DMA_TransmitProcess_Stopped ((u32)0x00000000) ///< Stopped - Reset or Stop Tx Command issued
|
||||
#define ETH_DMA_TransmitProcess_Fetching ((u32)0x00100000) ///< Running - fetching the Tx descriptor
|
||||
#define ETH_DMA_TransmitProcess_Waiting ((u32)0x00200000) ///< Running - waiting for status
|
||||
#define ETH_DMA_TransmitProcess_Reading ((u32)0x00300000) ///< Running - reading the data from host memory
|
||||
#define ETH_DMA_TransmitProcess_Suspended ((u32)0x00600000) ///< Suspended - Tx Descriptor unavailable
|
||||
#define ETH_DMA_TransmitProcess_Closing ((u32)0x00700000) ///< Running - closing Rx descriptor
|
||||
|
||||
#define ETH_DMA_ReceiveProcess_Stopped ((u32)0x00000000) ///< Stopped - Reset or Stop Rx Command issued
|
||||
#define ETH_DMA_ReceiveProcess_Fetching ((u32)0x00020000) ///< Running - fetching the Rx descriptor
|
||||
#define ETH_DMA_ReceiveProcess_Waiting ((u32)0x00060000) ///< Running - waiting for packet
|
||||
#define ETH_DMA_ReceiveProcess_Suspended ((u32)0x00080000) ///< Suspended - Rx Descriptor unavailable
|
||||
#define ETH_DMA_ReceiveProcess_Closing ((u32)0x000A0000) ///< Running - closing descriptor
|
||||
#define ETH_DMA_ReceiveProcess_Queuing ((u32)0x000E0000) ///< Running - queuing the receive frame into host memory
|
||||
|
||||
#define ETH_DMA_Overflow_RxFIFOCounter ((u32)0x10000000) ///< Overflow bit for FIFO overflow counter
|
||||
#define ETH_DMA_Overflow_MissedFrameCounter ((u32)0x00010000) ///< Overflow bit for missed frame counter
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#define ETH_PMT_FLAG_WUFFRPR ((u32)0x80000000) ///< Wake-Up Frame Filter Register Pointer Reset
|
||||
#define ETH_PMT_FLAG_WUFR ((u32)0x00000040) ///< Wake-Up Frame Received
|
||||
#define ETH_PMT_FLAG_MPR ((u32)0x00000020) ///< Magic Packet Received
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#define ETH_MMC_IT_TGF ((u32)0x00200000) ///< When Tx good frame counter reaches half the maximum value
|
||||
#define ETH_MMC_IT_TGFMSC ((u32)0x00008000) ///< When Tx good multi col counter reaches half the maximum value
|
||||
#define ETH_MMC_IT_TGFSC ((u32)0x00004000) ///< When Tx good single col counter reaches half the maximum value
|
||||
|
||||
#define ETH_MMC_IT_RGUF ((u32)0x10020000) ///< When Rx good unicast frames counter reaches half the maximum value
|
||||
#define ETH_MMC_IT_RFAE ((u32)0x10000040) ///< When Rx alignment error counter reaches half the maximum value
|
||||
#define ETH_MMC_IT_RFCE ((u32)0x10000020) ///< When Rx crc error counter reaches half the maximum value
|
||||
|
||||
#define ETH_MMCCR ((u32)0x00000100) ///< MMC CR register
|
||||
#define ETH_MMCRIR ((u32)0x00000104) ///< MMC RIR register
|
||||
#define ETH_MMCTIR ((u32)0x00000108) ///< MMC TIR register
|
||||
#define ETH_MMCRIMR ((u32)0x0000010C) ///< MMC RIMR register
|
||||
#define ETH_MMCTIMR ((u32)0x00000110) ///< MMC TIMR register
|
||||
#define ETH_MMCTGFSCCR ((u32)0x0000014C) ///< MMC TGFSCCR register
|
||||
#define ETH_MMCTGFMSCCR ((u32)0x00000150) ///< MMC TGFMSCCR register
|
||||
#define ETH_MMCTGFCR ((u32)0x00000168) ///< MMC TGFCR register
|
||||
#define ETH_MMCRFCECR ((u32)0x00000194) ///< MMC RFCECR register
|
||||
#define ETH_MMCRFAECR ((u32)0x00000198) ///< MMC RFAECR register
|
||||
#define ETH_MMCRGUFCR ((u32)0x000001C4) ///< MMC RGUFCR register
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#define ETH_PTP_FineUpdate ((u32)0x00000001) ///< Fine Update method
|
||||
#define ETH_PTP_CoarseUpdate ((u32)0x00000000) ///< Coarse Update method
|
||||
|
||||
#define ETH_PTP_FLAG_TSARU ((u32)0x00000020) ///< Addend Register Update
|
||||
#define ETH_PTP_FLAG_TSITE ((u32)0x00000010) ///< Time Stamp Interrupt Trigger
|
||||
#define ETH_PTP_FLAG_TSSTU ((u32)0x00000008) ///< Time Stamp Update
|
||||
#define ETH_PTP_FLAG_TSSTI ((u32)0x00000004) ///< Time Stamp Initialize
|
||||
|
||||
#define ETH_PTP_FLAG_TSTTR ((u32)0x10000002) ///< Time stamp target time reached
|
||||
#define ETH_PTP_FLAG_TSSO ((u32)0x10000001) ///< Time stamp seconds overflow
|
||||
|
||||
#define ETH_PTP_PositiveTime ((u32)0x00000000) ///< Positive time value
|
||||
#define ETH_PTP_NegativeTime ((u32)0x80000000) ///< Negative time value
|
||||
|
||||
#define ETH_PTPTSCR ((u32)0x00000700) ///< PTP TSCR register
|
||||
#define ETH_PTPSSIR ((u32)0x00000704) ///< PTP SSIR register
|
||||
#define ETH_PTPTSHR ((u32)0x00000708) ///< PTP TSHR register
|
||||
#define ETH_PTPTSLR ((u32)0x0000070C) ///< PTP TSLR register
|
||||
#define ETH_PTPTSHUR ((u32)0x00000710) ///< PTP TSHUR register
|
||||
#define ETH_PTPTSLUR ((u32)0x00000714) ///< PTP TSLUR register
|
||||
#define ETH_PTPTSAR ((u32)0x00000718) ///< PTP TSAR register
|
||||
#define ETH_PTPTTHR ((u32)0x0000071C) ///< PTP TTHR register
|
||||
#define ETH_PTPTTLR ((u32)0x00000720) ///< PTP TTLR register
|
||||
|
||||
#define ETH_PTPTSSR ((u32)0x00000728) ///< PTP TSSR register
|
||||
|
||||
#define ETH_PTP_OrdinaryClock ((u32)0x00000000) ///< Ordinary Clock
|
||||
#define ETH_PTP_BoundaryClock ((u32)0x00010000) ///< Boundary Clock
|
||||
#define ETH_PTP_EndToEndTransparentClock ((u32)0x00020000) ///< End To End Transparent Clock
|
||||
#define ETH_PTP_PeerToPeerTransparentClock ((u32)0x00030000) ///< Peer To Peer Transparent Clock
|
||||
|
||||
#define ETH_PTP_SnapshotMasterMessage ((u32)0x00008000) ///< Time stamp snapshot for message relevant to master enable
|
||||
#define ETH_PTP_SnapshotEventMessage ((u32)0x00004000) ///< Time stamp snapshot for event message enable
|
||||
#define ETH_PTP_SnapshotIPV4Frames ((u32)0x00002000) ///< Time stamp snapshot for IPv4 frames enable
|
||||
#define ETH_PTP_SnapshotIPV6Frames ((u32)0x00001000) ///< Time stamp snapshot for IPv6 frames enable
|
||||
#define ETH_PTP_SnapshotPTPOverEthernetFrames ((u32)0x00000800) ///< Time stamp snapshot for PTP over ethernet frames enable
|
||||
#define ETH_PTP_SnapshotAllReceivedFrames ((u32)0x00000100) ///< Time stamp snapshot for all received frames enable
|
||||
|
||||
#define ETH_MAC_ADDR_HBASE (ETH_BASE + 0x40) ///< ETHERNET MAC address high offset
|
||||
#define ETH_MAC_ADDR_LBASE (ETH_BASE + 0x44) ///< ETHERNET MAC address low offset
|
||||
|
||||
#define MACMIIAR_CR_MASK ((u32)0xFFFFFFE3)
|
||||
|
||||
#define MACCR_CLEAR_MASK ((u32)0xFF20810F)
|
||||
#define MACFCR_CLEAR_MASK ((u32)0x0000FF41)
|
||||
#define DMAOMR_CLEAR_MASK ((u32)0xF8DE3F23)
|
||||
|
||||
|
||||
|
||||
GLOBAL __IO ETH_DMADESCTypeDef* DMATxDescToSet;
|
||||
GLOBAL __IO ETH_DMADESCTypeDef* DMARxDescToGet;
|
||||
|
||||
GLOBAL ETH_DMA_Rx_Frame_infos RX_Frame_Descriptor;
|
||||
GLOBAL __IO ETH_DMA_Rx_Frame_infos* DMA_RX_FRAME_infos;
|
||||
GLOBAL __IO u32 Frame_Rx_index;
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
void ETH_DeInit(void);
|
||||
void ETH_StructInit(ETH_InitTypeDef* ptr);
|
||||
u32 ETH_Init(ETH_InitTypeDef* ptr, u16 phy_addr);
|
||||
void ETH_Start(void);
|
||||
void ETH_Stop(void);
|
||||
void ETH_MACTransmissionCmd(FunctionalState sta);
|
||||
void ETH_MACReceptionCmd(FunctionalState sta);
|
||||
FlagStatus ETH_GetFlowControlBusyStatus(void);
|
||||
void ETH_InitiatePauseControlFrame(void);
|
||||
void ETH_BackPressureActivationCmd(FunctionalState sta);
|
||||
void ETH_MACAddressConfig(u32 reg_addr, u8* mac_addr);
|
||||
void ETH_GetMACAddress(u32 reg_addr, u8* mac_addr);
|
||||
void ETH_MACAddressPerfectFilterCmd(u32 reg_addr, FunctionalState sta);
|
||||
void ETH_MACAddressFilterConfig(u32 reg_addr, u32 sta);
|
||||
void ETH_MACAddressMaskBytesFilterConfig(u32 reg_addr, u32 mask_byte);
|
||||
FrameTypeDef ETH_Get_Received_Frame(void);
|
||||
FrameTypeDef ETH_Get_Received_Frame_interrupt(void);
|
||||
u32 ETH_Prepare_Transmit_Descriptors(u16 len);
|
||||
void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt);
|
||||
u32 ETH_CheckFrameReceived(void);
|
||||
void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt);
|
||||
FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag);
|
||||
u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef* ptr_desc);
|
||||
void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc);
|
||||
void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
|
||||
void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val);
|
||||
void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val);
|
||||
void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
|
||||
void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
|
||||
void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
|
||||
void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef* ptr_desc, u32 buf1_size, u32 buf2_size);
|
||||
FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag);
|
||||
void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc);
|
||||
u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef* ptr_desc);
|
||||
void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
|
||||
u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef* ptr_desc, u32 buf);
|
||||
u32 ETH_GetRxPktSize(ETH_DMADESCTypeDef* ptr_desc);
|
||||
void ETH_SoftwareReset(void);
|
||||
FlagStatus ETH_GetSoftwareResetStatus(void);
|
||||
FlagStatus ETH_GetDMAFlagStatus(u32 flag);
|
||||
void ETH_DMAClearFlag(u32 flag);
|
||||
void ETH_DMAITConfig(u32 it, FunctionalState sta);
|
||||
ITStatus ETH_GetDMAITStatus(u32 it);
|
||||
void ETH_DMAClearITPendingBit(u32 it);
|
||||
u32 ETH_GetTransmitProcessState(void);
|
||||
u32 ETH_GetReceiveProcessState(void);
|
||||
void ETH_FlushTransmitFIFO(void);
|
||||
FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
|
||||
void ETH_DMATransmissionCmd(FunctionalState sta);
|
||||
void ETH_DMAReceptionCmd(FunctionalState sta);
|
||||
FlagStatus ETH_GetDMAOverflowStatus(u32 val);
|
||||
u32 ETH_GetRxOverflowMissedFrameCounter(void);
|
||||
u32 ETH_GetBufferUnavailableMissedFrameCounter(void);
|
||||
u32 ETH_GetCurrentTxDescStartAddress(void);
|
||||
u32 ETH_GetCurrentRxDescStartAddress(void);
|
||||
u32 ETH_GetCurrentTxBufferAddress(void);
|
||||
u32 ETH_GetCurrentRxBufferAddress(void);
|
||||
void ETH_ResumeDMATransmission(void);
|
||||
void ETH_ResumeDMAReception(void);
|
||||
void ETH_SetReceiveWatchdogTimer(u8 val);
|
||||
u16 ETH_ReadPHYRegister(u16 addr, u16 reg);
|
||||
u16 ETH_WritePHYRegister(u16 addr, u16 reg, u16 val);
|
||||
u32 ETH_PHYLoopBackCmd(u16 addr, FunctionalState sta);
|
||||
void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
|
||||
void ETH_SetWakeUpFrameFilterRegister(u32* buf);
|
||||
void ETH_GlobalUnicastWakeUpCmd(FunctionalState sta);
|
||||
FlagStatus ETH_GetPMTFlagStatus(u32 flag);
|
||||
void ETH_WakeUpFrameDetectionCmd(FunctionalState sta);
|
||||
void ETH_MagicPacketDetectionCmd(FunctionalState sta);
|
||||
void ETH_PowerDownCmd(FunctionalState sta);
|
||||
void ETH_MMCCounterFullPreset(void);
|
||||
void ETH_MMCCounterHalfPreset(void);
|
||||
void ETH_MMCCounterFreezeCmd(FunctionalState sta);
|
||||
void ETH_MMCResetOnReadCmd(FunctionalState sta);
|
||||
void ETH_MMCCounterRolloverCmd(FunctionalState sta);
|
||||
void ETH_MMCCountersReset(void);
|
||||
void ETH_MMCITConfig(u32 it, FunctionalState sta);
|
||||
ITStatus ETH_GetMMCITStatus(u32 it);
|
||||
u32 ETH_GetMMCRegister(u32 reg);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_ETH_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,68 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_eth_conf.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE hal_eth_conf.h EXAMPLES.
|
||||
/// ////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef __HAL_ETH_CONF_H
|
||||
#define __HAL_ETH_CONF_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup ETH_HAL
|
||||
/// @brief ETH HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup ETH_Exported_Types
|
||||
/// @{
|
||||
|
||||
|
||||
// #define USE_ENHANCED_DMA_DESCRIPTORS
|
||||
// #define CUSTOM_DRIVER_BUFFERS_CONFIG
|
||||
#define DP83848
|
||||
|
||||
#ifdef CUSTOM_DRIVER_BUFFERS_CONFIG
|
||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
|
||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
|
||||
#define ETH_RX_BUF_NUM 4
|
||||
#define ETH_TX_BUF_NUM 4
|
||||
#endif
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#if defined(DP83848)
|
||||
#define PHY_SR ((u16)0x10)
|
||||
#define PHY_SR_LINKSTATUS ((u16)0x0001)
|
||||
#define PHY_SPEED_STATUS ((u16)0x0002)
|
||||
#define PHY_DUPLEX_STATUS ((u16)0x0004)
|
||||
|
||||
#define PHY_MICR ((u16)0x11)
|
||||
#define PHY_MICR_INT_EN ((u16)0x0002)
|
||||
#define PHY_MICR_INT_OE ((u16)0x0001)
|
||||
|
||||
#define PHY_MISR ((u16)0x12)
|
||||
#define PHY_MISR_LINK_INT_EN ((u16)0x0020)
|
||||
#define PHY_LINK_STATUS ((u16)0x2000)
|
||||
#endif
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_ETH_CONF_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,181 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_exti.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE EXTI
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_EXTI_H
|
||||
#define __HAL_EXTI_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
#include "reg_exti.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup EXTI_HAL
|
||||
/// @brief EXTI HAL modules
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup EXTI_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief EXTI mode enumeration
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
EXTI_Mode_Interrupt = 0x00, ///< EXTI interrupt mode
|
||||
EXTI_Mode_Event = 0x04 ///< EXTI event mode
|
||||
} EXTIMode_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief EXTI Trigger enumeration
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
EXTI_Trigger_Rising = 0x08, ///< EXTI rising edge triggering
|
||||
EXTI_Trigger_Falling = 0x0C, ///< EXTI falling edge triggering
|
||||
EXTI_Trigger_Rising_Falling = 0x10 ///< EXTI rising and falling edge triggers
|
||||
} EXTITrigger_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief EXTI Init Structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u32 EXTI_Line; ///< Specifies the EXTI lines to be enabled or disabled.
|
||||
///< This parameter can be any combination of @ref EXTI_Lines
|
||||
EXTIMode_TypeDef EXTI_Mode; ///< Specifies the mode for the EXTI lines.
|
||||
///< This parameter can be a value of @ref EXTIMode_TypeDef
|
||||
EXTITrigger_TypeDef EXTI_Trigger; ///< Specifies the trigger signal active edge for the EXTI lines.
|
||||
///< This parameter can be a value of @ref EXTIMode_TypeDef
|
||||
FunctionalState EXTI_LineCmd; ///< Specifies the new state of the selected EXTI lines.
|
||||
///< This parameter can be set either to ENABLE or DISABLE
|
||||
} EXTI_InitTypeDef;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup EXTI_Exported_Constants
|
||||
/// @{
|
||||
|
||||
|
||||
|
||||
#define EXTI_LineNone ((u32)0x0000000) ///< No interrupt selected
|
||||
#define EXTI_Line0 ((u32)0x0000001) ///< External interrupt line 0
|
||||
#define EXTI_Line1 ((u32)0x0000002) ///< External interrupt line 1
|
||||
#define EXTI_Line2 ((u32)0x0000004) ///< External interrupt line 2
|
||||
#define EXTI_Line3 ((u32)0x0000008) ///< External interrupt line 3
|
||||
#define EXTI_Line4 ((u32)0x0000010) ///< External interrupt line 4
|
||||
#define EXTI_Line5 ((u32)0x0000020) ///< External interrupt line 5
|
||||
#define EXTI_Line6 ((u32)0x0000040) ///< External interrupt line 6
|
||||
#define EXTI_Line7 ((u32)0x0000080) ///< External interrupt line 7
|
||||
#define EXTI_Line8 ((u32)0x0000100) ///< External interrupt line 8
|
||||
#define EXTI_Line9 ((u32)0x0000200) ///< External interrupt line 9
|
||||
#define EXTI_Line10 ((u32)0x0000400) ///< External interrupt line 10
|
||||
#define EXTI_Line11 ((u32)0x0000800) ///< External interrupt line 11
|
||||
#define EXTI_Line12 ((u32)0x0001000) ///< External interrupt line 12
|
||||
#define EXTI_Line13 ((u32)0x0002000) ///< External interrupt line 13
|
||||
#define EXTI_Line14 ((u32)0x0004000) ///< External interrupt line 14
|
||||
#define EXTI_Line15 ((u32)0x0008000) ///< External interrupt line 15
|
||||
#define EXTI_Line16 ((u32)0x0010000) ///< External interrupt line 16 Connected to the PVD Output
|
||||
#define EXTI_Line17 ((u32)0x0020000) ///< External interrupt line 17 Connected to the RTC Alarm event
|
||||
#define EXTI_Line18 ((u32)0x0040000) ///< External interrupt line 18 Connected to the USB Wakeup from suspend event
|
||||
#define EXTI_Line19 ((u32)0x0080000) ///< External interrupt line 19
|
||||
#define EXTI_Line20 ((u32)0x0100000) ///< External interrupt line 20
|
||||
#define EXTI_Line21 ((u32)0x0200000) ///< External interrupt line 21
|
||||
#define EXTI_Line22 ((u32)0x0400000) ///< External interrupt line 22
|
||||
#define EXTI_Line23 ((u32)0x0800000) ///< External interrupt line 23
|
||||
#define EXTI_Line24 ((u32)0x1000000) ///< External interrupt line 24
|
||||
|
||||
#define EXTI_PortSourceGPIOA (0x00U)
|
||||
#define EXTI_PortSourceGPIOB (0x01U)
|
||||
#define EXTI_PortSourceGPIOC (0x02U)
|
||||
#define EXTI_PortSourceGPIOD (0x03U)
|
||||
#define EXTI_PortSourceGPIOE (0x04U)
|
||||
#define EXTI_PortSourceGPIOF (0x05U)
|
||||
|
||||
#define EXTI_PinSource0 (0x00U)
|
||||
#define EXTI_PinSource1 (0x01U)
|
||||
#define EXTI_PinSource2 (0x02U)
|
||||
#define EXTI_PinSource3 (0x03U)
|
||||
#define EXTI_PinSource4 (0x04U)
|
||||
#define EXTI_PinSource5 (0x05U)
|
||||
#define EXTI_PinSource6 (0x06U)
|
||||
#define EXTI_PinSource7 (0x07U)
|
||||
#define EXTI_PinSource8 (0x08U)
|
||||
#define EXTI_PinSource9 (0x09U)
|
||||
#define EXTI_PinSource10 (0x0AU)
|
||||
#define EXTI_PinSource11 (0x0BU)
|
||||
#define EXTI_PinSource12 (0x0CU)
|
||||
#define EXTI_PinSource13 (0x0DU)
|
||||
#define EXTI_PinSource14 (0x0EU)
|
||||
#define EXTI_PinSource15 (0x0FU)
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup EXTI_Exported_Variables
|
||||
/// @{
|
||||
|
||||
#ifdef _HAL_EXTI_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup EXTI_Exported_Functions
|
||||
/// @{
|
||||
|
||||
FlagStatus EXTI_GetFlagStatus(u32 line);
|
||||
ITStatus EXTI_GetITStatus(u32 line);
|
||||
|
||||
void EXTI_DeInit(void);
|
||||
void EXTI_Init(EXTI_InitTypeDef* init_struct);
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* init_struct);
|
||||
void EXTI_GenerateSWInterrupt(u32 line);
|
||||
void EXTI_ClearFlag(u32 line);
|
||||
void EXTI_ClearITPendingBit(u32 line);
|
||||
void exEXTI_LineDisable(u32 line);
|
||||
u32 exEXTI_GetAllFlagStatus(void);
|
||||
|
||||
|
||||
void EXTI_MemoryRemapConfig(u32 memory_remap);
|
||||
void EXTI_LineConfig(u8 port_source_gpio, u8 pin_source);
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_EXTI_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,230 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_flash.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE FLASH
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_FLASH_H
|
||||
#define __HAL_FLASH_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
#include "reg_flash.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup FLASH_HAL
|
||||
/// @brief FLASH HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup FLASH_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief FLASH Status
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
FLASH_BUSY = 1, ///< FLASH busy status
|
||||
FLASH_ERROR_PG, ///< FLASH programming error status
|
||||
FLASH_ERROR_WRP, ///< FLASH write protection error status
|
||||
FLASH_COMPLETE, ///< FLASH end of operation status
|
||||
FLASH_TIMEOUT ///< FLASH Last operation timed out status
|
||||
} FLASH_Status;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief FLASH Latency
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
FLASH_Latency_0 = FLASH_ACR_LATENCY_0, ///< FLASH Zero Latency cycle
|
||||
FLASH_Latency_1 = FLASH_ACR_LATENCY_1, ///< FLASH One Latency cycle
|
||||
FLASH_Latency_2 = FLASH_ACR_LATENCY_2, ///< FLASH Two Latency cycles
|
||||
FLASH_Latency_3 = FLASH_ACR_LATENCY_3 ///< FLASH Three Latency cycles
|
||||
} FLASH_Latency_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Half_Cycle_Enable_Disable
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
FLASH_HalfCycleAccess_Enable = FLASH_ACR_HLFCYA, ///< FLASH Half Cycle Enable
|
||||
FLASH_HalfCycleAccess_Disable = (s32)~FLASH_ACR_HLFCYA ///< FLASH Half Cycle Disable
|
||||
} FLASH_HalfCycleAccess_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Prefetch_Buffer_Enable_Disable
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
FLASH_PrefetchBuffer_Enable = FLASH_ACR_PRFTBE, ///< FLASH Prefetch Buffer Enable
|
||||
FLASH_PrefetchBuffer_Disable = (s32)~FLASH_ACR_PRFTBE ///< FLASH Prefetch Buffer Disable
|
||||
} FLASH_PrefetchBuffer_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Option_Bytes_IWatchdog
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
OB_IWDG_SW = 0x0001, ///< Software IWDG selected
|
||||
OB_IWDG_HW = 0x0000 ///< Hardware IWDG selected
|
||||
} OB_IWDG_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Option_Bytes_nRST_STOP
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
OB_STOP_NoRST = 0x0002, ///< No reset generated when entering in STOP
|
||||
OB_STOP_RST = 0x0000 ///< Reset generated when entering in STOP
|
||||
} OB_STOP_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Option_Bytes_nRST_STDBY
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
OB_STDBY_NoRST = 0x0004, ///< No reset generated when entering in STANDBY
|
||||
OB_STDBY_RST = 0x0000 ///< Reset generated when entering in STANDBY
|
||||
} OB_STDBY_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief FLASH_Interrupts
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
FLASH_IT_ERROR = FLASH_CR_ERRIE, ///< FPEC error interrupt source
|
||||
FLASH_IT_EOP = FLASH_CR_EOPIE ///< End of FLASH Operation Interrupt source
|
||||
} FLASH_IT_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief FLASH_Flags
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
FLASH_FLAG_EOP = FLASH_SR_EOP, ///< FLASH End of Operation flag
|
||||
FLASH_FLAG_PGERR = FLASH_SR_PGERR, ///< FLASH Program error flag
|
||||
FLASH_FLAG_WRPRTERR = FLASH_SR_WRPRTERR, ///< FLASH Write protected error flag
|
||||
FLASH_FLAG_BSY = FLASH_SR_BUSY, ///< FLASH Busy flag
|
||||
FLASH_FLAG_OPTERR = FLASH_OBR_OPTERR ///< FLASH Option Byte error flag
|
||||
} FLASH_FLAG_TypeDef;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup FLASH_Exported_Constants
|
||||
/// @{
|
||||
|
||||
|
||||
#define RDP_Key ((u16)0x00A5)
|
||||
#define FLASH_KEY1 ((u32)0x45670123)
|
||||
#define FLASH_KEY2 ((u32)0xCDEF89AB)
|
||||
#define EraseTimeout ((u32)0x00000FFF)
|
||||
#define ProgramTimeout ((u32)0x0000000F)
|
||||
|
||||
#define FLASH_WRProt_Pages0to3 ((u32)0x00000001) ///< Write protection of page 0 to 3
|
||||
#define FLASH_WRProt_Pages4to7 ((u32)0x00000002) ///< Write protection of page 4 to 7
|
||||
#define FLASH_WRProt_Pages8to11 ((u32)0x00000004) ///< Write protection of page 8 to 11
|
||||
#define FLASH_WRProt_Pages12to15 ((u32)0x00000008) ///< Write protection of page 12 to 15
|
||||
#define FLASH_WRProt_Pages16to19 ((u32)0x00000010) ///< Write protection of page 16 to 19
|
||||
#define FLASH_WRProt_Pages20to23 ((u32)0x00000020) ///< Write protection of page 20 to 23
|
||||
#define FLASH_WRProt_Pages24to27 ((u32)0x00000040) ///< Write protection of page 24 to 27
|
||||
#define FLASH_WRProt_Pages28to31 ((u32)0x00000080) ///< Write protection of page 28 to 31
|
||||
#define FLASH_WRProt_Pages32to35 ((u32)0x00000100) ///< Write protection of page 32 to 35
|
||||
#define FLASH_WRProt_Pages36to39 ((u32)0x00000200) ///< Write protection of page 36 to 39
|
||||
#define FLASH_WRProt_Pages40to43 ((u32)0x00000400) ///< Write protection of page 40 to 43
|
||||
#define FLASH_WRProt_Pages44to47 ((u32)0x00000800) ///< Write protection of page 44 to 47
|
||||
#define FLASH_WRProt_Pages48to51 ((u32)0x00001000) ///< Write protection of page 48 to 51
|
||||
#define FLASH_WRProt_Pages52to55 ((u32)0x00002000) ///< Write protection of page 52 to 55
|
||||
#define FLASH_WRProt_Pages56to59 ((u32)0x00004000) ///< Write protection of page 56 to 59
|
||||
#define FLASH_WRProt_Pages60to63 ((u32)0x00008000) ///< Write protection of page 60 to 63
|
||||
#define FLASH_WRProt_Pages64to67 ((u32)0x00010000) ///< Write protection of page 64 to 67
|
||||
#define FLASH_WRProt_Pages68to71 ((u32)0x00020000) ///< Write protection of page 68 to 71
|
||||
#define FLASH_WRProt_Pages72to75 ((u32)0x00040000) ///< Write protection of page 72 to 75
|
||||
#define FLASH_WRProt_Pages76to79 ((u32)0x00080000) ///< Write protection of page 76 to 79
|
||||
#define FLASH_WRProt_Pages80to83 ((u32)0x00100000) ///< Write protection of page 80 to 83
|
||||
#define FLASH_WRProt_Pages84to87 ((u32)0x00200000) ///< Write protection of page 84 to 87
|
||||
#define FLASH_WRProt_Pages88to91 ((u32)0x00400000) ///< Write protection of page 88 to 91
|
||||
#define FLASH_WRProt_Pages92to95 ((u32)0x00800000) ///< Write protection of page 92 to 95
|
||||
#define FLASH_WRProt_Pages96to99 ((u32)0x01000000) ///< Write protection of page 96 to 99
|
||||
#define FLASH_WRProt_Pages100to103 ((u32)0x02000000) ///< Write protection of page 100 to 103
|
||||
#define FLASH_WRProt_Pages104to107 ((u32)0x04000000) ///< Write protection of page 104 to 107
|
||||
#define FLASH_WRProt_Pages108to111 ((u32)0x08000000) ///< Write protection of page 108 to 111
|
||||
#define FLASH_WRProt_Pages112to115 ((u32)0x10000000) ///< Write protection of page 112 to 115
|
||||
#define FLASH_WRProt_Pages116to119 ((u32)0x20000000) ///< Write protection of page 115 to 119
|
||||
#define FLASH_WRProt_Pages120to123 ((u32)0x40000000) ///< Write protection of page 120 to 123
|
||||
#define FLASH_WRProt_Pages124to127 ((u32)0x80000000) ///< Write protection of page 124 to 127
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup FLASH_Exported_Variables
|
||||
/// @{
|
||||
|
||||
#ifdef _HAL_FLASH_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup FLASH_Exported_Functions
|
||||
/// @{
|
||||
void FLASH_SetLatency(FLASH_Latency_TypeDef latency);
|
||||
void FLASH_HalfCycleAccessCmd(FLASH_HalfCycleAccess_TypeDef half_cycle_access);
|
||||
void FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_TypeDef prefetch_buffer);
|
||||
void FLASH_Unlock(void);
|
||||
void FLASH_Lock(void);
|
||||
void FLASH_OPTB_Enable(void);
|
||||
void FLASH_ITConfig(FLASH_IT_TypeDef interrupt, FunctionalState state);
|
||||
void FLASH_ClearFlag(u16 flag);
|
||||
void exFLASH_EraseEE(u32 page_address);
|
||||
void exFLASH_ProgramEE(u16* buf, u32 address, u16 len);
|
||||
void exFLASH_WriteEE(u16* buf, u32 page_address, u16 len);
|
||||
void* exFLASH_Locate(u32 page_address, u16 len);
|
||||
void* exFLASH_ReadEE(u32 page_address, u16 len);
|
||||
|
||||
u8 exFLASH_FindEmpty(u16* ptr, u16 len);
|
||||
u32 FLASH_GetUserOptionByte(void);
|
||||
u32 FLASH_GetWriteProtectionOptionByte(void);
|
||||
|
||||
FLASH_Status FLASH_ErasePage(u32 page_address);
|
||||
FLASH_Status FLASH_EraseAllPages(void);
|
||||
FLASH_Status FLASH_EraseOptionBytes(void);
|
||||
FLASH_Status FLASH_EraseProtect(void);
|
||||
FLASH_Status FLASH_ProgramHalfWord(u32 address, u16 data);
|
||||
FLASH_Status FLASH_ProgramWord(u32 address, u32 data);
|
||||
FLASH_Status FLASH_ProgramOptionHalfWord(u32 address, u16 data);
|
||||
FLASH_Status FLASH_ProgramOptionByteData(u32 address, u8 data);
|
||||
FLASH_Status FLASH_ProgramProtect(u32 address, u16 data);
|
||||
FLASH_Status FLASH_EnableWriteProtection(u32 page);
|
||||
FLASH_Status FLASH_UserOptionByteConfig(OB_IWDG_TypeDef ob_iwdg, OB_STOP_TypeDef ob_stop, OB_STDBY_TypeDef ob_standby);
|
||||
FLASH_Status FLASH_GetStatus(void);
|
||||
FLASH_Status FLASH_WaitForLastOperation(u32 time_out);
|
||||
FLASH_Status FLASH_ReadOutProtection(FunctionalState state);
|
||||
FlagStatus FLASH_GetPrefetchBufferStatus(void);
|
||||
FlagStatus FLASH_GetFlagStatus(u16 flag);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_FLASH_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,147 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_fsmc.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SDIO
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_FSMC_H
|
||||
#define __HAL_FSMC_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
#include "reg_fsmc.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup FSMC_HAL
|
||||
/// @brief FSMC HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup FSMC_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief FSMC_interrupts_define
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// Timing parameter configuration register set selection register set0 register set1 register set2
|
||||
|
||||
#define FSMC_TimingRegSelect_0 ((u32)0x00000000)
|
||||
#define FSMC_TimingRegSelect_1 ((u32)0x00000100)
|
||||
#define FSMC_TimingRegSelect_2 ((u32)0x00000200)
|
||||
|
||||
// Capacity of external device
|
||||
#define FSMC_MemSize_None ((u32)0x00000000)
|
||||
#define FSMC_MemSize_64KB ((u32)0x00000001)
|
||||
#define FSMC_MemSize_128KB ((u32)0x00000002)
|
||||
#define FSMC_MemSize_256KB ((u32)0x00000002)
|
||||
#define FSMC_MemSize_512KB ((u32)0x00000004)
|
||||
#define FSMC_MemSize_1MB ((u32)0x00000005)
|
||||
#define FSMC_MemSize_2MB ((u32)0x00000006)
|
||||
#define FSMC_MemSize_4MB ((u32)0x00000007)
|
||||
#define FSMC_MemSize_8MB ((u32)0x00000008)
|
||||
#define FSMC_MemSize_16MB ((u32)0x00000009)
|
||||
#define FSMC_MemSize_32MB ((u32)0x0000000A)
|
||||
#define FSMC_MemSize_64MB ((u32)0x0000000B)
|
||||
#define FSMC_MemSize_128MB ((u32)0x0000000C)
|
||||
#define FSMC_MemSize_256MB ((u32)0x0000000D)
|
||||
#define FSMC_MemSize_512MB ((u32)0x0000000E)
|
||||
#define FSMC_MemSize_1GB ((u32)0x0000000F)
|
||||
#define FSMC_MemSize_2GB ((u32)0x00000010)
|
||||
#define FSMC_MemSize_4GB ((u32)0x00000011)
|
||||
|
||||
|
||||
// Memory data bus bit width setting
|
||||
typedef enum {
|
||||
FSMC_DataWidth_16bits = (0x0000), //16bits
|
||||
FSMC_DataWidth_32bits = (0x0001), //32bits
|
||||
FSMC_DataWidth_64bits = (0x0002), //64bits
|
||||
FSMC_DataWidth_128bits = (0x0003), //128bits
|
||||
FSMC_DataWidth_8bits = (0x0004), //8bits
|
||||
} FSMC_NORSRAM_DataWidth_TypeDef;
|
||||
|
||||
typedef enum {
|
||||
FSMC_NORSRAM_BANK0 = 0,
|
||||
FSMC_NORSRAM_BANK1 = 1,
|
||||
FSMC_NORSRAM_BANK2 = 2,
|
||||
} FSMC_NORSRAM_BANK_TypeDef;
|
||||
|
||||
typedef struct {
|
||||
u32 FSMC_SMReadPipe; //sm_read_pipe[1:0] The cycle of latching read data, that is, the cycle when ready_resp is pulled high
|
||||
|
||||
u32 FSMC_ReadyMode; //Select whether the hready_resp signal comes from the FSMC IP internal or external DEVICE, only for writing and reading external DEVICE operations.
|
||||
//0: Internal FSMC 1: External DEVICE (ie from FSMC_NWAIT)
|
||||
u32 FSMC_WritePeriod; //Write cycle
|
||||
|
||||
u32 FSMC_WriteHoldTime; //Address/data hold time during write operation
|
||||
|
||||
u32 FSMC_AddrSetTime; //Address establishment time
|
||||
|
||||
u32 FSMC_ReadPeriod; //Read cycle
|
||||
|
||||
FSMC_NORSRAM_DataWidth_TypeDef FSMC_DataWidth;
|
||||
|
||||
} FSMC_NORSRAM_Bank_InitTypeDef;
|
||||
|
||||
typedef struct {
|
||||
u32 FSMC_Mode;
|
||||
u32 FSMC_TimingRegSelect;
|
||||
u32 FSMC_MemSize;
|
||||
u32 FSMC_MemType;
|
||||
u32 FSMC_AddrDataMode;
|
||||
} FSMC_InitTypeDef;
|
||||
|
||||
|
||||
#define FSMC_MemType_SDRAM ((u32)0x0<<5)
|
||||
#define FSMC_MemType_NorSRAM ((u32)0x1<<5)
|
||||
#define FSMC_MemType_FLASH ((u32)0x2<<5)
|
||||
#define FSMC_MemType_RESERVED ((u32)0x3<<5)
|
||||
//SYSCFG_CFGR1
|
||||
#define FSMC_Mode_6800 ((u32)0x40000000)
|
||||
#define FSMC_Mode_8080 ((u32)0x20000000)
|
||||
#define FSMC_Mode_NorFlash ((u32)0x00000000)
|
||||
|
||||
#define FSMC_AddrDataMUX ((u32)0x00000000)
|
||||
#define FSMC_AddrDataDeMUX ((u32)0x10000000)
|
||||
|
||||
|
||||
|
||||
|
||||
void FSMC_NORSRAMStructInit(FSMC_InitTypeDef* init_struct);
|
||||
void FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef* init_struct);
|
||||
void FSMC_NORSRAMInit(FSMC_InitTypeDef* init_struct);
|
||||
void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_TypeDef bank);
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_FSMC_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,198 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_gpio.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GPIO
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_GPIO_H
|
||||
#define __HAL_GPIO_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_gpio.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup GPIO_HAL
|
||||
/// @brief GPIO HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup GPIO_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Output Maximum frequency selection
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
GPIO_Speed_50MHz = 1, ///< Maximum speed is 50MHz
|
||||
GPIO_Speed_20MHz, ///< Maximum speed is 20MHz
|
||||
GPIO_Speed_10MHz ///< Maximum speed is 10MHz
|
||||
} GPIOSpeed_TypeDef;
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Configuration Mode enumeration
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
GPIO_Mode_AIN = 0x00, ///< Analog input
|
||||
GPIO_Mode_FLOATING = 0x04, ///< Floating input
|
||||
GPIO_Mode_IPD = 0x28, ///< Pull down input
|
||||
GPIO_Mode_IPU = 0x48, ///< Pull up input
|
||||
GPIO_Mode_Out_OD = 0x14, ///< Universal open drain output
|
||||
GPIO_Mode_Out_PP = 0x10, ///< Universal push-pull output
|
||||
GPIO_Mode_AF_OD = 0x1C, ///< Multiplex open drain output
|
||||
GPIO_Mode_AF_PP = 0x18 ///< Multiplexed push-pull output
|
||||
} GPIOMode_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Bit_SET and Bit_RESET enumeration
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
Bit_RESET = 0, ///< bit reset
|
||||
Bit_SET ///< bit set
|
||||
} BitAction;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief GPIO Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u16 GPIO_Pin; ///< GPIO_Pin
|
||||
GPIOSpeed_TypeDef GPIO_Speed; ///< GPIO_Speed
|
||||
GPIOMode_TypeDef GPIO_Mode; ///< GPIO_Mode
|
||||
} GPIO_InitTypeDef;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup GPIO_Exported_Constants
|
||||
/// @{
|
||||
|
||||
#define GPIO_Speed_2MHz GPIO_Speed_20MHz
|
||||
|
||||
#define GPIO_Pin_0 (0x0001U) ///< Pin 0 selected
|
||||
#define GPIO_Pin_1 (0x0002U) ///< Pin 1 selected
|
||||
#define GPIO_Pin_2 (0x0004U) ///< Pin 2 selected
|
||||
#define GPIO_Pin_3 (0x0008U) ///< Pin 3 selected
|
||||
#define GPIO_Pin_4 (0x0010U) ///< Pin 4 selected
|
||||
#define GPIO_Pin_5 (0x0020U) ///< Pin 5 selected
|
||||
#define GPIO_Pin_6 (0x0040U) ///< Pin 6 selected
|
||||
#define GPIO_Pin_7 (0x0080U) ///< Pin 7 selected
|
||||
#define GPIO_Pin_8 (0x0100U) ///< Pin 8 selected
|
||||
#define GPIO_Pin_9 (0x0200U) ///< Pin 9 selected
|
||||
#define GPIO_Pin_10 (0x0400U) ///< Pin 10 selected
|
||||
#define GPIO_Pin_11 (0x0800U) ///< Pin 11 selected
|
||||
#define GPIO_Pin_12 (0x1000U) ///< Pin 12 selected
|
||||
#define GPIO_Pin_13 (0x2000U) ///< Pin 13 selected
|
||||
#define GPIO_Pin_14 (0x4000U) ///< Pin 14 selected
|
||||
#define GPIO_Pin_15 (0x8000U) ///< Pin 15 selected
|
||||
#define GPIO_Pin_All (0xFFFFU) ///< All pins selected
|
||||
|
||||
|
||||
#define GPIO_AF_0 (0x00U) ///< Alternative function 0
|
||||
#define GPIO_AF_1 (0x01U) ///< Alternative function 1
|
||||
#define GPIO_AF_2 (0x02U) ///< Alternative function 2
|
||||
#define GPIO_AF_3 (0x03U) ///< Alternative function 3
|
||||
#define GPIO_AF_4 (0x04U) ///< Alternative function 4
|
||||
#define GPIO_AF_5 (0x05U) ///< Alternative function 5
|
||||
#define GPIO_AF_6 (0x06U) ///< Alternative function 6
|
||||
#define GPIO_AF_7 (0x07U) ///< Alternative function 7
|
||||
#define GPIO_AF_8 (0x08U) ///< Alternative function 8
|
||||
#define GPIO_AF_9 (0x09U) ///< Alternative function 9
|
||||
#define GPIO_AF_10 (0x0AU) ///< Alternative function 10
|
||||
#define GPIO_AF_11 (0x0BU) ///< Alternative function 11
|
||||
#define GPIO_AF_12 (0x0CU) ///< Alternative function 12
|
||||
#define GPIO_AF_13 (0x0DU) ///< Alternative function 13
|
||||
#define GPIO_AF_14 (0x0EU) ///< Alternative function 14
|
||||
#define GPIO_AF_15 (0x0FU) ///< Alternative function 15
|
||||
#define GPIO_PortSourceGPIOA (0x00U)
|
||||
#define GPIO_PortSourceGPIOB (0x01U)
|
||||
#define GPIO_PortSourceGPIOC (0x02U)
|
||||
#define GPIO_PortSourceGPIOD (0x03U)
|
||||
|
||||
#define GPIO_PinSource0 (0x00U)
|
||||
#define GPIO_PinSource1 (0x01U)
|
||||
#define GPIO_PinSource2 (0x02U)
|
||||
#define GPIO_PinSource3 (0x03U)
|
||||
#define GPIO_PinSource4 (0x04U)
|
||||
#define GPIO_PinSource5 (0x05U)
|
||||
#define GPIO_PinSource6 (0x06U)
|
||||
#define GPIO_PinSource7 (0x07U)
|
||||
#define GPIO_PinSource8 (0x08U)
|
||||
#define GPIO_PinSource9 (0x09U)
|
||||
#define GPIO_PinSource10 (0x0AU)
|
||||
#define GPIO_PinSource11 (0x0BU)
|
||||
#define GPIO_PinSource12 (0x0CU)
|
||||
#define GPIO_PinSource13 (0x0DU)
|
||||
#define GPIO_PinSource14 (0x0EU)
|
||||
#define GPIO_PinSource15 (0x0FU)
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup GPIO_Exported_Variables
|
||||
/// @{
|
||||
|
||||
#ifdef _HAL_GPIO_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup GPIO_Exported_Functions
|
||||
/// @{
|
||||
void GPIO_DeInit(GPIO_TypeDef* gpio);
|
||||
void GPIO_AFIODeInit(void);
|
||||
void GPIO_Init(GPIO_TypeDef* gpio, GPIO_InitTypeDef* init_struct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* init_struct);
|
||||
void GPIO_SetBits(GPIO_TypeDef* gpio, u16 pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef* gpio, u16 pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef* gpio, u16 pin, BitAction value);
|
||||
void GPIO_Write(GPIO_TypeDef* gpio, u16 value);
|
||||
void GPIO_PinLock(GPIO_TypeDef* gpio, u16 pin, FunctionalState state);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* gpio, u16 pin);
|
||||
bool GPIO_ReadInputDataBit(GPIO_TypeDef* gpio, u16 pin);
|
||||
bool GPIO_ReadOutputDataBit(GPIO_TypeDef* gpio, u16 pin);
|
||||
|
||||
u16 GPIO_ReadInputData(GPIO_TypeDef* gpio);
|
||||
u16 GPIO_ReadOutputData(GPIO_TypeDef* gpio);
|
||||
|
||||
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* gpio, u8 pin, u8 alternate_function);
|
||||
|
||||
void exGPIO_PinAFConfig(GPIO_TypeDef* gpio, u16 pin, s32 remap, s8 alternate_function);
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_GPIO_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,255 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_i2c.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE I2C
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_I2C_H
|
||||
#define __HAL_I2C_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_i2c.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_HAL
|
||||
/// @brief I2C HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup DRV_Exported_Constants
|
||||
/// @{
|
||||
|
||||
#define I2C_OWN_ADDRESS 0x20
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief I2C Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
union {
|
||||
u16 Mode; ///< Specifies the I2C mode. This parameter can be a value of I2C_mode.
|
||||
u16 I2C_Mode;
|
||||
};
|
||||
union {
|
||||
u16 Speed; ///< Specifies the I2C speed. This parameter can be a value of I2C_speed.
|
||||
u16 I2C_Speed;
|
||||
};
|
||||
union {
|
||||
u16 OwnAddress; ///< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.
|
||||
u16 I2C_OwnAddress;
|
||||
};
|
||||
|
||||
union {
|
||||
u32 ClockSpeed; ///< Specifies the clock speed.
|
||||
u32 I2C_ClockSpeed;
|
||||
};
|
||||
} I2C_InitTypeDef;
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_Exported_Constants
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief I2C DMA Direction
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RDMAE_SET = 1, // 1 - DMA read
|
||||
TDMAE_SET // 2 - DMA transmit
|
||||
} I2C_DMA_Dir_TypeDef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief I2C Transfer Direction
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
I2C_Direction_Transmitter, // I2C Transmitter
|
||||
I2C_Direction_Receiver // I2C Receiver
|
||||
} I2C_Trans_Dir_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief I2C Acknowledged Address
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
I2C_AcknowledgedAddress_7bit = 0x4000, // 7-bit address
|
||||
I2C_AcknowledgedAddress_10bit = 0xC000 // 10-bit address
|
||||
} I2C_ACKaddr_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_Private_Defines
|
||||
/// @{
|
||||
#define INTR_MASK ((u16)0xC000)
|
||||
#define FLAG_Mask ((u32)0x00793FFF)
|
||||
#define IC_TAR_ENDUAL_Set ((u16)0x1000)
|
||||
#define IC_TAR_ENDUAL_Reset ((u16)0xEFFF)
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_modes
|
||||
/// @{
|
||||
#define TX_EMPTY_CTRL I2C_CR_EMPINT
|
||||
#define IC_SLAVE_DISABLE I2C_CR_SLAVEDIS
|
||||
#define IC_RESTART_EN I2C_CR_REPEN
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_interrupts_definition
|
||||
/// @{
|
||||
#define I2C_IT_RX_UNDER ((u16)0x0001)
|
||||
#define I2C_IT_RX_OVER ((u16)0x0002)
|
||||
#define I2C_IT_RX_FULL ((u16)0x0004)
|
||||
#define I2C_IT_TX_OVER ((u16)0x0008)
|
||||
#define I2C_IT_TX_EMPTY ((u16)0x0010)
|
||||
#define I2C_IT_RD_REQ ((u16)0x0020)
|
||||
#define I2C_IT_TX_ABRT ((u16)0x0040)
|
||||
#define I2C_IT_RX_DONE ((u16)0x0080)
|
||||
#define I2C_IT_ACTIVITY ((u16)0x0100)
|
||||
#define I2C_IT_STOP_DET ((u16)0x0200)
|
||||
#define I2C_IT_START_DET ((u16)0x0400)
|
||||
#define I2C_IT_GEN_CALL ((u16)0x0800)
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_flags_definition
|
||||
/// @{
|
||||
#define I2C_FLAG_RX_UNDER ((u16)0x0001)
|
||||
#define I2C_FLAG_RX_OVER ((u16)0x0002)
|
||||
#define I2C_FLAG_RX_FULL ((u16)0x0004)
|
||||
#define I2C_FLAG_TX_OVER ((u16)0x0008)
|
||||
#define I2C_FLAG_TX_EMPTY ((u16)0x0010)
|
||||
#define I2C_FLAG_RD_REQ ((u16)0x0020)
|
||||
#define I2C_FLAG_TX_ABRT ((u16)0x0040)
|
||||
#define I2C_FLAG_RX_DONE ((u16)0x0080)
|
||||
#define I2C_FLAG_ACTIVITY ((u16)0x0100)
|
||||
#define I2C_FLAG_STOP_DET ((u16)0x0200)
|
||||
#define I2C_FLAG_START_DET ((u16)0x0400)
|
||||
#define I2C_FLAG_GEN_CALL ((u16)0x0800)
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_Events
|
||||
/// @{
|
||||
#define I2C_EVENT_RX_UNDER ((u16)0x0001)
|
||||
#define I2C_EVENT_RX_OVER ((u16)0x0002)
|
||||
#define I2C_EVENT_RX_FULL ((u16)0x0004)
|
||||
#define I2C_EVENT_TX_OVER ((u16)0x0008)
|
||||
#define I2C_EVENT_TX_EMPTY ((u16)0x0010)
|
||||
#define I2C_EVENT_RD_REQ ((u16)0x0020)
|
||||
#define I2C_EVENT_TX_ABRT ((u16)0x0040)
|
||||
#define I2C_EVENT_RX_DONE ((u16)0x0080)
|
||||
#define I2C_EVENT_ACTIVITY ((u16)0x0100)
|
||||
#define I2C_EVENT_STOP_DET ((u16)0x0200)
|
||||
#define I2C_EVENT_START_DET ((u16)0x0400)
|
||||
#define I2C_EVENT_GEN_CALL ((u16)0x0800)
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_Statusflags_definition
|
||||
/// @{
|
||||
#define I2C_STATUS_FLAG_ACTIVITY ((u16)0x8001)
|
||||
#define I2C_STATUS_FLAG_TFNF ((u16)0x8002)
|
||||
#define I2C_STATUS_FLAG_TFE ((u16)0x8004)
|
||||
#define I2C_STATUS_FLAG_RFNE ((u16)0x8008)
|
||||
#define I2C_STATUS_FLAG_RFF ((u16)0x8010)
|
||||
#define I2C_STATUS_FLAG_M_ACTIVITY ((u16)0x8020)
|
||||
#define I2C_STATUS_FLAG_S_ACTIVITY ((u16)0x8040)
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
#define IC_SLAVE_ENABLE (0x0000<<6)
|
||||
#define IC_7BITADDR_MASTER (0x0000<<4)
|
||||
#define IC_7BITADDR_SLAVE (0x0000<<3)
|
||||
#define I2C_Speed_STANDARD ((u16)0x0002)
|
||||
#define I2C_Speed_FAST ((u16)0x0004)
|
||||
#define I2C_Mode_MASTER ((u16)0x0001)
|
||||
#define I2C_Mode_SLAVE ((u16)0x0000)
|
||||
#define CMD_READ ((u16)0x0100)
|
||||
#define CMD_WRITE ((u16)0x0000)
|
||||
#define I2C_Mode_I2C ((u16)0x0000)
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_I2C_C_
|
||||
|
||||
#define GLOBAL
|
||||
|
||||
static u8 I2C_CMD_DIR = 0;
|
||||
u16 I2C_DMA_DIR = 0;
|
||||
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_Exported_Functions
|
||||
/// @{
|
||||
void I2C_DeInit(I2C_TypeDef* i2c);
|
||||
void I2C_Init(I2C_TypeDef* i2c, I2C_InitTypeDef* init_struct);
|
||||
void I2C_StructInit(I2C_InitTypeDef* init_struct);
|
||||
void I2C_Cmd(I2C_TypeDef* i2c, FunctionalState state);
|
||||
void I2C_DMACmd(I2C_TypeDef* i2c, FunctionalState state);
|
||||
void I2C_GenerateSTART(I2C_TypeDef* i2c, FunctionalState state);
|
||||
void I2C_GenerateSTOP(I2C_TypeDef* i2c, FunctionalState state);
|
||||
void I2C_OwnAddress2Config(I2C_TypeDef* i2c, u8 addr);
|
||||
void I2C_DualAddressCmd(I2C_TypeDef* i2c, FunctionalState state);
|
||||
void I2C_GeneralCallCmd(I2C_TypeDef* i2c, FunctionalState state);
|
||||
void I2C_ITConfig(I2C_TypeDef* i2c, u16 it, FunctionalState state);
|
||||
void I2C_SendData(I2C_TypeDef* i2c, u8 dat);
|
||||
void I2C_ReadCmd(I2C_TypeDef* i2c);
|
||||
void I2C_Send7bitAddress(I2C_TypeDef* i2c, u8 addr, u8 dir);
|
||||
void I2C_ClearFlag(I2C_TypeDef* i2c, u32 flag);
|
||||
void I2C_ClearITPendingBit(I2C_TypeDef* i2c, u32 it);
|
||||
|
||||
u8 I2C_ReceiveData(I2C_TypeDef* i2c);
|
||||
u16 I2C_ReadRegister(I2C_TypeDef* i2c, u8 reg);
|
||||
u32 I2C_GetLastEvent(I2C_TypeDef* i2c);
|
||||
|
||||
ErrorStatus I2C_CheckEvent(I2C_TypeDef* i2c, u32 event);
|
||||
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* i2c, u32 flag);
|
||||
ITStatus I2C_GetITStatus(I2C_TypeDef* i2c, u32 it);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Extended function interface
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void I2C_SendSlaveAddress(I2C_TypeDef* i2c, u8 addr);
|
||||
void I2C_SlaveConfigure(I2C_TypeDef* i2c, FunctionalState state);
|
||||
void I2C_DMAConfigure(I2C_TypeDef* i2c, u8 dir);
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_I2C_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,130 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_iwdg.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE IWDG
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_IWDG_H
|
||||
#define __HAL_IWDG_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_iwdg.h"
|
||||
#include "reg_common.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup IWDG_HAL
|
||||
/// @brief IWDG HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup IWDG_Exported_Constants
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief IWDG prescaler
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
IWDG_Prescaler_4 = IWDG_PR_PRE_DIV4,
|
||||
IWDG_Prescaler_8 = IWDG_PR_PRE_DIV8,
|
||||
IWDG_Prescaler_16 = IWDG_PR_PRE_DIV16,
|
||||
IWDG_Prescaler_32 = IWDG_PR_PRE_DIV32,
|
||||
IWDG_Prescaler_64 = IWDG_PR_PRE_DIV64,
|
||||
IWDG_Prescaler_128 = IWDG_PR_PRE_DIV128,
|
||||
IWDG_Prescaler_256 = IWDG_PR_PRE_DIV256
|
||||
} IWDGPrescaler_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief IWDG flag
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
IWDG_FLAG_PVU = 0x0001, // IWDG prescaler value update flag
|
||||
IWDG_FLAG_RVU = 0x0002 // IWDG counter reload value update flag
|
||||
} IWDGFlag_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Write access to IWDG_PR and IWDG_RLR registers
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
IWDG_WriteAccess_Enable = 0x5555, // Enable write
|
||||
IWDG_WriteAccess_Disable = 0x0000 // Disable write
|
||||
} IWDGWriteAccess_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief IWDG Key Reload
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
KR_KEY_Reload = 0xAAAA, // Reload value
|
||||
KR_KEY_Enable = 0xCCCC // Start IWDG
|
||||
} IWDGKey_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief IWDG Overflow Configration
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
IWDG_Overflow_Reset = 0, //
|
||||
IWDG_Overflow_Interrupt = IWDG_CR_IRQSEL //
|
||||
} IWDGOverflowConfig_TypeDef;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup IWDG_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_IWDG_C_
|
||||
#define GLOBAL
|
||||
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup IWDG_Exported_Functions
|
||||
/// @{
|
||||
FlagStatus IWDG_GetFlagStatus(u16 flag);
|
||||
|
||||
void IWDG_WriteAccessCmd(u16 write_access);
|
||||
void IWDG_SetPrescaler(u8 prescaler);
|
||||
void IWDG_SetReload(u16 reload);
|
||||
u32 IWDG_GetReload(void);
|
||||
void IWDG_ReloadCounter(void);
|
||||
void IWDG_Enable(void);
|
||||
void PVU_CheckStatus(void);
|
||||
void RVU_CheckStatus(void);
|
||||
|
||||
void IWDG_OverflowConfig(IWDGOverflowConfig_TypeDef overflow_config);
|
||||
void IWDG_ClearITPendingBit(void);
|
||||
void IWDG_EnableIT(void);
|
||||
void IWDG_Reset(void);
|
||||
void IWDG_ClearIT(void);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_IWDG_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,128 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_misc.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE NVIC
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_MISC_H
|
||||
#define __HAL_MISC_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup NVIC_HAL
|
||||
/// @brief NVIC HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup NVIC_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief NVIC Init Structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u8 NVIC_IRQChannel;
|
||||
u8 NVIC_IRQChannelPreemptionPriority;
|
||||
u8 NVIC_IRQChannelSubPriority;
|
||||
FunctionalState NVIC_IRQChannelCmd;
|
||||
} NVIC_InitTypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief NVIC New Init Structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u8 NVIC_IRQChannel;
|
||||
u8 NVIC_IRQChannelPreemptionPriority; // Cortex-M0 not used
|
||||
u8 NVIC_IRQChannelSubPriority;
|
||||
FunctionalState NVIC_IRQChannelCmd;
|
||||
} exNVIC_Init_TypeDef;
|
||||
|
||||
/// @}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup NVIC_Exported_Constants
|
||||
/// @{
|
||||
|
||||
#define NVIC_VectTab_RAM (0x20000000U)
|
||||
#define NVIC_VectTab_FLASH (0x08000000U)
|
||||
|
||||
#define NVIC_LP_SEVONPEND (0x10U)
|
||||
#define NVIC_LP_SLEEPDEEP (0x04U)
|
||||
#define NVIC_LP_SLEEPONEXIT (0x02U)
|
||||
|
||||
#define NVIC_PriorityGroup_0 (0x0700U) // 0 bits for pre-emption priority 4 bits for subpriority
|
||||
#define NVIC_PriorityGroup_1 (0x0600U) // 1 bits for pre-emption priority 3 bits for subpriority
|
||||
#define NVIC_PriorityGroup_2 (0x0500U) // 2 bits for pre-emption priority 2 bits for subpriority
|
||||
#define NVIC_PriorityGroup_3 (0x0400U) // 3 bits for pre-emption priority 1 bits for subpriority
|
||||
#define NVIC_PriorityGroup_4 (0x0300U) // 4 bits for pre-emption priority 0 bits for subpriority
|
||||
|
||||
#define AIRCR_VECTKEY_MASK (0x05FA0000U)
|
||||
|
||||
#define SysTick_CLKSource_HCLK_Div8 (0xFFFFFFFBU)
|
||||
|
||||
|
||||
#define SysTick_CLKSource_EXTCLK (0xFFFFFFFBU)
|
||||
#define SysTick_CLKSource_HCLK (0x00000004U)
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup NVIC_Exported_Variables
|
||||
/// @{
|
||||
|
||||
#ifdef _HAL_NVIC_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup NVIC_Exported_Functions
|
||||
/// @{
|
||||
|
||||
void NVIC_PriorityGroupConfig(u32 priority_group);
|
||||
void NVIC_SetVectorTable(u32 vect_tab, u32 offset);
|
||||
|
||||
void NVIC_SystemLPConfig(u8 low_power_mode, FunctionalState state);
|
||||
void NVIC_Init(NVIC_InitTypeDef* init_struct);
|
||||
|
||||
void SysTick_CLKSourceConfig(u32 systick_clk_source);
|
||||
|
||||
void exNVIC_Init(exNVIC_Init_TypeDef* init_struct);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_NVIC_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,156 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_pwr.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE PWR
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_PWR_H
|
||||
#define __HAL_PWR_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_pwr.h"
|
||||
#include "reg_syscfg.h"
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup PWR_HAL
|
||||
/// @brief PWR HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup PWR_Exported_Types
|
||||
/// @{
|
||||
|
||||
typedef enum {
|
||||
emWUP_Pin1 = 0,
|
||||
emWUP_Pin2 = 1,
|
||||
emWUP_Pin3,
|
||||
emWUP_Pin4,
|
||||
emWUP_Pin5,
|
||||
emWUP_Pin6,
|
||||
} emWUP_Pin_Typedef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief PVD_detection_level
|
||||
|
||||
typedef enum {
|
||||
emPVD_LEVEL0 = SYSCFG_PDETCSR_PLS_1V7,
|
||||
emPVD_LEVEL1 = SYSCFG_PDETCSR_PLS_2V0,
|
||||
emPVD_LEVEL2 = SYSCFG_PDETCSR_PLS_2V3,
|
||||
emPVD_LEVEL3 = SYSCFG_PDETCSR_PLS_2V6,
|
||||
emPVD_LEVEL4 = SYSCFG_PDETCSR_PLS_2V9,
|
||||
emPVD_LEVEL5 = SYSCFG_PDETCSR_PLS_3V2,
|
||||
emPVD_LEVEL6 = SYSCFG_PDETCSR_PLS_3V5,
|
||||
emPVD_LEVEL7 = SYSCFG_PDETCSR_PLS_3V8,
|
||||
emPVD_LEVEL8 = SYSCFG_PDETCSR_PLS_4V1,
|
||||
emPVD_LEVEL9 = SYSCFG_PDETCSR_PLS_4V4,
|
||||
emPVD_LEVEL10 = SYSCFG_PDETCSR_PLS_4V7
|
||||
} emPVD_Level_Typedef;
|
||||
#define PWR_PVDLevel_1V7 SYSCFG_PDETCSR_PLS_1V7
|
||||
#define PWR_PVDLevel_2V0 SYSCFG_PDETCSR_PLS_2V0
|
||||
#define PWR_PVDLevel_2V3 SYSCFG_PDETCSR_PLS_2V3
|
||||
#define PWR_PVDLevel_2V6 SYSCFG_PDETCSR_PLS_2V6
|
||||
#define PWR_PVDLevel_2V9 SYSCFG_PDETCSR_PLS_2V9
|
||||
#define PWR_PVDLevel_3V2 SYSCFG_PDETCSR_PLS_3V2
|
||||
#define PWR_PVDLevel_3V5 SYSCFG_PDETCSR_PLS_3V5
|
||||
#define PWR_PVDLevel_3V8 SYSCFG_PDETCSR_PLS_3V8
|
||||
#define PWR_PVDLevel_4V1 SYSCFG_PDETCSR_PLS_4V1
|
||||
#define PWR_PVDLevel_4V4 SYSCFG_PDETCSR_PLS_4V4
|
||||
#define PWR_PVDLevel_4V7 SYSCFG_PDETCSR_PLS_4V7
|
||||
/// @brief Regulator_state_is_STOP_mode
|
||||
typedef enum {
|
||||
PWR_Regulator_ON = 0x00000000,
|
||||
PWR_Regulator_LowPower = 0x00000001
|
||||
|
||||
} emPWR_Reg_Stop_mode_Typedef;
|
||||
|
||||
/// @brief STOP_mode_entry
|
||||
typedef enum {
|
||||
PWR_STOPEntry_WFI = 0x00000001,
|
||||
PWR_STOPEntry_WFE = 0x00000002
|
||||
|
||||
} emPWR_STOP_ModeEn_Typedef;
|
||||
|
||||
/// @brief Low Power Mode
|
||||
typedef enum {
|
||||
LP_STOP_MODE = 0,
|
||||
LP_SLEEP_MODE = 1,
|
||||
LP_STANDBY_MODE = 2
|
||||
} emPWR_LP_Mode_Typedef;
|
||||
|
||||
/// @brief Wait_for_mode
|
||||
typedef enum {
|
||||
LP_WFI,
|
||||
LP_WFE
|
||||
} emPWR_Wait_Mode_Typedef;
|
||||
//typedef enum {
|
||||
// PWR_FLAG_WU = PWR_CSR_WUF,
|
||||
// PWR_FLAG_SB = PWR_CSR_SBF,
|
||||
|
||||
// PWR_FLAG_PVDO = PWR_CSR_PVDO
|
||||
|
||||
|
||||
//} emPWR_PWR_Flag_Typedef;
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup PWR_Exported_Variables
|
||||
/// @{
|
||||
|
||||
#ifdef _HAL_PWR_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup PWR_Exported_Functions
|
||||
/// @{
|
||||
|
||||
void PWR_DeInit(void);
|
||||
|
||||
void PWR_BackupAccessCmd(FunctionalState state);
|
||||
|
||||
void PWR_PVDCmd(FunctionalState state);
|
||||
void PWR_PVDLevelConfig(emPVD_Level_Typedef pvd_level);
|
||||
void PWR_WakeUpPinCmd(FunctionalState state);
|
||||
void PWR_EnterSTOPMode(emPWR_Reg_Stop_mode_Typedef regulator, emPWR_STOP_ModeEn_Typedef stop_entry);
|
||||
void PWR_EnterSTANDBYMode(void);
|
||||
|
||||
|
||||
void PWR_ClearFlag(u32 flag);
|
||||
FlagStatus PWR_GetFlagStatus(u32 flag);
|
||||
FlagStatus PWR_GetPVDOFlagStatus(u32 flag);
|
||||
void exPWR_EnterLowPowerMode(emPWR_LP_Mode_Typedef lp_mode, emPWR_Wait_Mode_Typedef wait_mode);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_PWR_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,329 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_rcc.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE RCC
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_RCC_H
|
||||
#define __HAL_RCC_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
#include "mm32_reg.h"
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RCC_HAL
|
||||
/// @brief RCC HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RCC_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RCC_Exported_Constants
|
||||
/// @{
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RCC_Exported_Enumeration
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief HSE configuration
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_HSE_OFF = 0, // HSE OFF
|
||||
RCC_HSE_ON = RCC_CR_HSEON, // HSE ON
|
||||
RCC_HSE_Bypass = RCC_CR_HSEBYP // HSE Bypass
|
||||
} RCCHSE_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Used for flags
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CR_REG_INDEX = 1, //
|
||||
BDCR_REG_INDEX = 2, //
|
||||
CSR_REG_INDEX = 3, //
|
||||
RCC_FLAG_MASK = 0x1FU //
|
||||
} RCC_RegisterFlag_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief RCC Flag
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
// Flags in the CR register
|
||||
RCC_FLAG_HSIRDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)), ///< Internal High Speed clock ready flag
|
||||
RCC_FLAG_HSERDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)), ///< External High Speed clock ready flag
|
||||
|
||||
RCC_FLAG_PLLRDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)), ///< PLL clock ready flag
|
||||
|
||||
// Flags in the CSR register
|
||||
RCC_FLAG_LSIRDY = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)), ///< Internal Low Speed oscillator Ready
|
||||
RCC_FLAG_PINRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)), ///< PIN reset flag
|
||||
RCC_FLAG_PORRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)), ///< POR/PDR reset flag
|
||||
RCC_FLAG_SFTRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)), ///< Software Reset flag
|
||||
RCC_FLAG_IWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)), ///< Independent Watchdog reset flag
|
||||
RCC_FLAG_WWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)), ///< Window watchdog reset flag
|
||||
|
||||
// Flags in the BDCR register
|
||||
RCC_FLAG_LSERDY = ((u8)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) ///< External Low Speed oscillator Ready
|
||||
} RCC_FLAG_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief System clock source
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_HSI = 0, // Set HSI as systemCLOCK
|
||||
RCC_HSE = 1, // Set HSE as systemCLOCK
|
||||
RCC_PLL = 2, // Set PLL as systemCLOCK
|
||||
RCC_LSI = 3 // Set LSI as systemCLOCK
|
||||
} SYSCLK_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief PLL entry clock source
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef enum {
|
||||
RCC_HSI_Div4 = 0,
|
||||
RCC_HSI_Div = 0,
|
||||
RCC_HSE_Div1 = RCC_PLLCFGR_PLLSRC,
|
||||
RCC_HSE_Div2 = (RCC_PLLCFGR_PLLXTPRE | RCC_PLLCFGR_PLLSRC),
|
||||
} RCC_PLLSource_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief PLL multiplication factor
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_PLLMul_2 = 0x00000000U,
|
||||
RCC_PLLMul_3 = 0x00040000U,
|
||||
RCC_PLLMul_4 = 0x00080000U,
|
||||
RCC_PLLMul_5 = 0x000C0000U,
|
||||
RCC_PLLMul_6 = 0x00100000U,
|
||||
RCC_PLLMul_7 = 0x00140000U,
|
||||
RCC_PLLMul_8 = 0x00180000U,
|
||||
RCC_PLLMul_9 = 0x001C0000U,
|
||||
RCC_PLLMul_10 = 0x00200000U,
|
||||
RCC_PLLMul_11 = 0x00240000U,
|
||||
RCC_PLLMul_12 = 0x00280000U,
|
||||
RCC_PLLMul_13 = 0x002C0000U,
|
||||
RCC_PLLMul_14 = 0x00300000U,
|
||||
RCC_PLLMul_15 = 0x00340000U,
|
||||
RCC_PLLMul_16 = 0x00380000U
|
||||
} RCC_PLLMul_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief AHB clock source
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_SYSCLK_Div1 = RCC_CFGR_HPRE_DIV1,
|
||||
RCC_SYSCLK_Div2 = RCC_CFGR_HPRE_DIV2,
|
||||
RCC_SYSCLK_Div4 = RCC_CFGR_HPRE_DIV4,
|
||||
RCC_SYSCLK_Div8 = RCC_CFGR_HPRE_DIV8,
|
||||
RCC_SYSCLK_Div16 = RCC_CFGR_HPRE_DIV16,
|
||||
RCC_SYSCLK_Div64 = RCC_CFGR_HPRE_DIV64,
|
||||
RCC_SYSCLK_Div128 = RCC_CFGR_HPRE_DIV128,
|
||||
RCC_SYSCLK_Div256 = RCC_CFGR_HPRE_DIV256,
|
||||
RCC_SYSCLK_Div512 = RCC_CFGR_HPRE_DIV512
|
||||
} RCC_AHB_CLK_TypeDef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief APB1 and APB2clock source
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_HCLK_Div1 = RCC_CFGR_PPRE1_DIV1,
|
||||
RCC_HCLK_Div2 = RCC_CFGR_PPRE1_DIV2,
|
||||
RCC_HCLK_Div4 = RCC_CFGR_PPRE1_DIV4,
|
||||
RCC_HCLK_Div8 = RCC_CFGR_PPRE1_DIV8,
|
||||
RCC_HCLK_Div16 = RCC_CFGR_PPRE1_DIV16
|
||||
} RCC_APB1_APB2_CLK_TypeDef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief USB Device clock source
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_USBCLKSource_PLLCLK_Div1 = 0,
|
||||
RCC_USBCLKSource_PLLCLK_Div2 = 1,
|
||||
RCC_USBCLKSource_PLLCLK_Div3 = 2,
|
||||
RCC_USBCLKSource_PLLCLK_Div4 = 3
|
||||
} RCC_USBCLKSOURCE_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief ADC clock source
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_PCLK2_Div2 = (0x00000000),
|
||||
RCC_PCLK2_Div4 = (0x00004000),
|
||||
RCC_PCLK2_Div6 = (0x00008000),
|
||||
RCC_PCLK2_Div8 = (0x0000C000)
|
||||
} RCC_ADCCLKSOURCE_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief LSE configuration
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_LSE_OFF = 0, // LSE OFF
|
||||
RCC_LSE_ON = RCC_BDCR_LSEON, // LSE ON
|
||||
RCC_LSE_Bypass = RCC_BDCR_LSEBYP // LSE Bypass
|
||||
} RCC_LSE_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief RTC clock source
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_RTCCLKSource_LSE = RCC_BDCR_RTCSEL_LSE,
|
||||
RCC_RTCCLKSource_LSI = RCC_BDCR_RTCSEL_LSI,
|
||||
RCC_RTCCLKSource_HSE_Div128 = RCC_BDCR_RTCSEL_HSE
|
||||
} RCC_RTCCLKSOURCE_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Clock source to output on MCO pin
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_MCO_NoClock = RCC_CFGR_MCO_NOCLOCK,
|
||||
RCC_MCO_LSI = RCC_CFGR_MCO_LSI,
|
||||
RCC_MCO_LSE = RCC_CFGR_MCO_LSE,
|
||||
RCC_MCO_SYSCLK = RCC_CFGR_MCO_SYSCLK,
|
||||
RCC_MCO_HSI = RCC_CFGR_MCO_HSI,
|
||||
RCC_MCO_HSE = RCC_CFGR_MCO_HSE,
|
||||
RCC_MCO_PLLCLK_Div2 = RCC_CFGR_MCO_PLL
|
||||
} RCC_MCO_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief RCC Interrupt source
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RCC_IT_LSIRDY = RCC_CIR_LSIRDYF,
|
||||
RCC_IT_LSERDY = RCC_CIR_LSERDYF,
|
||||
RCC_IT_HSIRDY = RCC_CIR_HSIRDYF,
|
||||
RCC_IT_HSERDY = RCC_CIR_HSERDYF,
|
||||
RCC_IT_PLLRDY = RCC_CIR_PLLRDYF,
|
||||
RCC_IT_CSS = RCC_CIR_CSSF
|
||||
} RCC_IT_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief RCC clock frequency type definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u32 SYSCLK_Frequency; ///< returns SYSCLK clock frequency.
|
||||
u32 HCLK_Frequency; ///< returns hclk clock frequency.
|
||||
u32 PCLK1_Frequency; ///< returns PCLK1 clock frequency.
|
||||
u32 PCLK2_Frequency; ///< returns PCLK2 clock frequency.
|
||||
u32 ADCCLK_Frequency; ///< returns ADCCLK clock frequency.
|
||||
} RCC_ClocksTypeDef;
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RCC_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_RCC_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RCC_Exported_Functions
|
||||
/// @{
|
||||
void RCC_DeInit(void);
|
||||
void RCC_HSEConfig(RCCHSE_TypeDef state);
|
||||
void RCC_HSICmd(FunctionalState state);
|
||||
void RCC_SYSCLKConfig(SYSCLK_TypeDef sys_clk_src);
|
||||
void RCC_PLLDMDNConfig(u32 plldn, u32 plldm);
|
||||
void RCC_PLLConfig(RCC_PLLSource_TypeDef pll_src, RCC_PLLMul_TypeDef pll_mul);
|
||||
void RCC_PLLCmd(FunctionalState state);
|
||||
void RCC_HCLKConfig(RCC_AHB_CLK_TypeDef sys_clk);
|
||||
void RCC_PCLK1Config(RCC_APB1_APB2_CLK_TypeDef hclk);
|
||||
void RCC_PCLK2Config(RCC_APB1_APB2_CLK_TypeDef hclk);
|
||||
void RCC_USBCLKConfig(RCC_USBCLKSOURCE_TypeDef usb_clk_src);
|
||||
void RCC_ADCCLKConfig(RCC_ADCCLKSOURCE_TypeDef pclk2);
|
||||
void RCC_LSICmd(FunctionalState state);
|
||||
|
||||
void RCC_RTCCLKCmd(FunctionalState state);
|
||||
void RCC_LSEConfig(RCC_LSE_TypeDef state);
|
||||
void RCC_RTCCLKConfig(RCC_RTCCLKSOURCE_TypeDef rtc_clk_src);
|
||||
void RCC_BackupResetCmd(FunctionalState state);
|
||||
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef* clk);
|
||||
void RCC_AHBPeriphClockCmd(u32 ahb_periph, FunctionalState state);
|
||||
void RCC_AHB2PeriphClockCmd(u32 ahb_periph, FunctionalState state);
|
||||
void RCC_AHB3PeriphClockCmd(u32 ahb_periph, FunctionalState state);
|
||||
void RCC_AHBPeriphResetCmd(u32 ahb_periph, FunctionalState state);
|
||||
void RCC_AHB2PeriphResetCmd(u32 ahb_periph, FunctionalState state);
|
||||
void RCC_AHB3PeriphResetCmd(u32 ahb_periph, FunctionalState state);
|
||||
void RCC_APB2PeriphClockCmd(u32 apb2_periph, FunctionalState state);
|
||||
void RCC_APB1PeriphClockCmd(u32 apb1_periph, FunctionalState state);
|
||||
void RCC_APB2PeriphResetCmd(u32 apb2_periph, FunctionalState state);
|
||||
void RCC_APB1PeriphResetCmd(u32 apb1_periph, FunctionalState state);
|
||||
|
||||
void RCC_ClockSecuritySystemCmd(FunctionalState state);
|
||||
void RCC_MCOConfig(RCC_MCO_TypeDef mco_src);
|
||||
void RCC_ClearFlag(void);
|
||||
void RCC_ITConfig(RCC_IT_TypeDef it, FunctionalState state);
|
||||
void RCC_ClearITPendingBit(u8 it);
|
||||
|
||||
u8 RCC_GetSYSCLKSource(void);
|
||||
u32 RCC_GetSysClockFreq(void);
|
||||
u32 RCC_GetHCLKFreq(void);
|
||||
|
||||
u32 RCC_GetPCLK1Freq(void);
|
||||
u32 RCC_GetPCLK2Freq(void);
|
||||
FlagStatus RCC_GetFlagStatus(RCC_FLAG_TypeDef flag);
|
||||
ErrorStatus RCC_WaitForHSEStartUp(void);
|
||||
ErrorStatus RCC_WaitForFlagStartUp(RCC_FLAG_TypeDef flag);
|
||||
ITStatus RCC_GetITStatus(RCC_IT_TypeDef it);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Extended function interface
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//ErrorStatus exRCC_Init(RCCInitStruct_TypeDef* para);
|
||||
void exRCC_SystickDisable(void);
|
||||
void exRCC_SystickEnable(u32 sys_tick_period);
|
||||
void exRCC_APB1PeriphReset(u32 apb1_periph);
|
||||
void exRCC_APB2PeriphReset(u32 apb2_periph);
|
||||
void exRCC_BackupReset(void);
|
||||
void RCC_ADC_ClockCmd(ADC_TypeDef* peripheral, FunctionalState state);
|
||||
void RCC_GPIO_ClockCmd(GPIO_TypeDef* peripheral, FunctionalState state);
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_RCC_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
@@ -0,0 +1,102 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_redefine.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE REDEFINE
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_REDEFINE_H
|
||||
#define __HAL_REDEFINE_H
|
||||
|
||||
// Files includes
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
/////////////////////////////////////1///////////////////////////////////////////
|
||||
/// @defgroup REDEFINE_HAL
|
||||
/// @brief REDEFINE HAL modules
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup REDEFINE_Exported_Types
|
||||
/// @{
|
||||
///
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup REDEFINE_Exported_Constants
|
||||
/// @{
|
||||
//Lib redefine
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief HAL_lib Version compatibility definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM compatibility definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define TIM_TRGOSource_Reset TIM_TRIGSource_Reset
|
||||
#define TIM_TRGOSource_Enable TIM_TRIGSource_Enable
|
||||
#define TIM_TRGOSource_Update TIM_TRIGSource_Update
|
||||
#define TIM_TRGOSource_OC1 TIM_TRIGSource_OC1
|
||||
#define TIM_TRGOSource_OC1Ref TIM_TRIGSource_OC1Ref
|
||||
#define TIM_TRGOSource_OC2Ref TIM_TRIGSource_OC2Ref
|
||||
#define TIM_TRGOSource_OC3Ref TIM_TRIGSource_OC3Ref
|
||||
#define TIM_TRGOSource_OC4Ref TIM_TRIGSource_OC4Ref
|
||||
///< The UG bit in the TIM_EGR register is used as the trigger output (TRIG).
|
||||
///< The Counter Enable CEN is used as the trigger output (TRIG).
|
||||
///< The update event is used as the trigger output (TRIG).
|
||||
///< The trigger output sends a positive pulse when the CC1IF flag ///< is to be set, as soon as a capture or compare match occurs (TRIG).
|
||||
///< OC1REF signal is used as the trigger output (TRIG).
|
||||
///< OC2REF signal is used as the trigger output (TRIG).
|
||||
///< OC3REF signal is used as the trigger output (TRIG).
|
||||
///< OC4REF signal is used as the trigger output (TRIG).
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup REDEFINE_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_REDEFINE_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup REDEFINE_Exported_Functions
|
||||
/// @{
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_REDEFINE_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,114 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_rtc.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE RTC
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_RTC_H
|
||||
#define __HAL_RTC_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
#include "reg_rtc.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RTC_HAL
|
||||
/// @brief RTC HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RTC_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief RTC_interrupts_define
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RTC_IT_OW = RTC_CR_OWIE, ///< Overflow interrupt
|
||||
RTC_IT_ALR = RTC_CR_ALRIE, ///< Alarm interrupt
|
||||
RTC_IT_SEC = RTC_CR_SECIE ///< Second interrupt
|
||||
} RTC_IT_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief RTC_interrupts_flags
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
RTC_FLAG_RTOFF = RTC_CSR_RTOFF, ///< RTC Operation OFF flag
|
||||
RTC_FLAG_RSF = RTC_CSR_RSF, ///< Registers Synchronized flag
|
||||
RTC_FLAG_OW = RTC_CSR_OWF, ///< Overflow flag
|
||||
RTC_FLAG_ALR = RTC_CSR_ALRF, ///< Alarm flag
|
||||
RTC_FLAG_SEC = RTC_CSR_SECF ///< Second flag
|
||||
} RTC_FLAG_TypeDef;
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RTC_Exported_Constants
|
||||
/// @{
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RTC_Exported_Variables
|
||||
/// @{
|
||||
|
||||
#ifdef _HAL_RTC_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
GLOBAL bool accessRTC;
|
||||
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup RTC_Exported_Functions
|
||||
/// @{
|
||||
void RTC_ITConfig(RTC_IT_TypeDef it, FunctionalState state);
|
||||
void RTC_ClearFlag(RTC_FLAG_TypeDef flag);
|
||||
void RTC_ClearITPendingBit(RTC_IT_TypeDef it);
|
||||
void RTC_EnterConfigMode(void);
|
||||
void RTC_SetCounter(u32 count);
|
||||
void RTC_SetPrescaler(u32 prescaler);
|
||||
void RTC_SetAlarm(u32 alarm);
|
||||
void RTC_ExitConfigMode(void);
|
||||
void RTC_WaitForLastTask(void);
|
||||
void RTC_WaitForSynchro(void);
|
||||
|
||||
u32 RTC_GetCounter(void);
|
||||
u32 RTC_GetDivider(void);
|
||||
|
||||
FlagStatus RTC_GetFlagStatus(RTC_FLAG_TypeDef flag);
|
||||
ITStatus RTC_GetITStatus(RTC_IT_TypeDef it);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_RTC_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,503 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_gpio.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GPIO
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_SDIO_H
|
||||
#define __HAL_SDIO_H
|
||||
|
||||
// Files includes
|
||||
#include "mm32_reg.h"
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup GPIO_HAL
|
||||
/// @brief GPIO HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup GPIO_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Output Maximum frequency selection
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#define SDIO_FLAG_CCRCFAIL ((u32)0x00000001)
|
||||
#define SDIO_FLAG_DCRCFAIL ((u32)0x00000002)
|
||||
#define SDIO_FLAG_CTIMEOUT ((u32)0x00000004)
|
||||
#define SDIO_FLAG_DTIMEOUT ((u32)0x00000008)
|
||||
#define SDIO_FLAG_TXUNDERR ((u32)0x00000010)
|
||||
#define SDIO_FLAG_RXOVERR ((u32)0x00000020)
|
||||
#define SDIO_FLAG_CMDREND ((u32)0x00000040)
|
||||
#define SDIO_FLAG_CMDSENT ((u32)0x00000080)
|
||||
#define SDIO_FLAG_DATAEND ((u32)0x00000100)
|
||||
#define SDIO_FLAG_STBITERR ((u32)0x00000200)
|
||||
#define SDIO_FLAG_DBCKEND ((u32)0x00000400)
|
||||
#define SDIO_FLAG_CMDACT ((u32)0x00000800)
|
||||
#define SDIO_FLAG_TXACT ((u32)0x00001000)
|
||||
#define SDIO_FLAG_RXACT ((u32)0x00002000)
|
||||
#define SDIO_FLAG_TXFIFOHE ((u32)0x00004000)
|
||||
#define SDIO_FLAG_RXFIFOHF ((u32)0x00008000)
|
||||
#define SDIO_FLAG_TXFIFOF ((u32)0x00010000)
|
||||
#define SDIO_FLAG_RXFIFOF ((u32)0x00020000)
|
||||
#define SDIO_FLAG_TXFIFOE ((u32)0x00040000)
|
||||
#define SDIO_FLAG_RXFIFOE ((u32)0x00080000)
|
||||
#define SDIO_FLAG_TXDAVL ((u32)0x00100000)
|
||||
#define SDIO_FLAG_RXDAVL ((u32)0x00200000)
|
||||
#define SDIO_FLAG_SDIOIT ((u32)0x00400000)
|
||||
#define SDIO_FLAG_CEATAEND ((u32)0x00800000)
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//SDIO working mode define ,SDIO working mode definition, set through the SD_SetDevice Mode function.
|
||||
#define SD_POLLING_MODE 0 /// Query mode. In this mode, it is recommended to increase the setting of SDIO_TRANSFER_CLK_DIV if there are problems with reading and writing.
|
||||
#define SD_DMA_MODE 1 /// In DMA mode, it is recommended to increase the setting of SDIO_TRANSFER_CLK_DIV if there are problems with reading and writing.
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SDIO Various error enumeration definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef enum {
|
||||
SD_CMD_CRC_FAIL = 1, ///< Command response received (but CRC check failed)
|
||||
SD_DATA_CRC_FAIL, ///< Data bock sent/received (CRC check Failed)
|
||||
SD_CMD_RSP_TIMEOUT, ///< Command response timeout
|
||||
SD_DATA_TIMEOUT, ///< Data time out
|
||||
SD_TX_UNDERRUN, ///< Transmit FIFO under-run
|
||||
SD_RX_OVERRUN, ///< Receive FIFO over-run
|
||||
SD_START_BIT_ERR, ///< Start bit not detected on all data signals in widE bus mode
|
||||
SD_CMD_OUT_OF_RANGE, ///< CMD's argument was out of range.
|
||||
SD_ADDR_MISALIGNED, ///< Misaligned address
|
||||
SD_BLOCK_LEN_ERR, ///< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length
|
||||
SD_ERASE_SEQ_ERR, ///< An error in the sequence of erase command occurs.
|
||||
SD_BAD_ERASE_PARAM, ///< An Invalid selection for erase groups
|
||||
SD_WRITE_PROT_VIOLATION, ///< Attempt to program a write protect block
|
||||
SD_LOCK_UNLOCK_FAILED, ///< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card
|
||||
SD_COM_CRC_FAILED, ///< CRC check of the previous command failed
|
||||
SD_ILLEGAL_CMD, ///< Command is not legal for the card state
|
||||
SD_CARD_ECC_FAILED, ///< Card internal ECC was applied but failed to correct the data
|
||||
SD_CC_ERROR, ///< Internal card controller error
|
||||
SD_GENERAL_UNKNOWN_ERROR, ///< General or Unknown error
|
||||
SD_STREAM_READ_UNDERRUN, ///< The card could not sustain data transfer in stream read operation.
|
||||
SD_STREAM_WRITE_OVERRUN, ///< The card could not sustain data programming in stream mode
|
||||
SD_CID_CSD_OVERWRITE, ///< CID/CSD overwrite error
|
||||
SD_WP_ERASE_SKIP, ///< only partial address space was erased
|
||||
SD_CARD_ECC_DISABLED, ///< Command has been executed without using internal ECC
|
||||
SD_ERASE_RESET, ///< Erase sequence was cleared before executing because an out of erase sequence command was received
|
||||
SD_AKE_SEQ_ERROR, ///< Error in sequence of authentication.
|
||||
SD_INVALID_VOLTRANGE, ///< SD invalid voltage range,
|
||||
SD_ADDR_OUT_OF_RANGE, ///< SD addresses are out of range,
|
||||
SD_SWITCH_ERROR, ///< SD switch error,
|
||||
SD_SDIO_DISABLED, ///< SD SDIO disability,
|
||||
SD_SDIO_FUNCTION_BUSY, ///< SD SDIO function busy,
|
||||
SD_SDIO_FUNCTION_FAILED, ///< SD SDIO failed,
|
||||
SD_SDIO_UNKNOWN_FUNCTION, ///< SDIO unknown function,
|
||||
SD_INTERNAL_ERROR, ///< SD internal error,
|
||||
SD_NOT_CONFIGURED, ///< SD is not configured,
|
||||
SD_REQUEST_PENDING, ///< The SD request waits,
|
||||
SD_REQUEST_NOT_APPLICABLE, ///< The SD requirement does not apply,
|
||||
SD_INVALID_PARAMETER, ///< Invalid SD parameter,
|
||||
SD_UNSUPPORTED_FEATURE, ///< Features not supported by SD,
|
||||
SD_UNSUPPORTED_HW, ///< HW not supported by SD,
|
||||
SD_ERROR, ///< SD error
|
||||
SD_OK = 0 ///< SD OK
|
||||
} SD_Error;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SD card CSD register data
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u8 CSDStruct; ///< CSD structure
|
||||
u8 SysSpecVersion; ///< System specification version
|
||||
u8 Reserved1; ///< Reserved
|
||||
u8 TAAC; ///< Data read access-time 1
|
||||
u8 NSAC; ///< Data read access-time 2 in CLK cycles
|
||||
u8 MaxBusClkFrec; ///< Max. bus clock frequency
|
||||
u16 CardComdClasses; ///< Card command classes
|
||||
u8 RdBlockLen; ///< Max. read data block length
|
||||
u8 PartBlockRead; ///< Partial blocks for read allowed
|
||||
u8 WrBlockMisalign; ///< Write block misalignment
|
||||
u8 RdBlockMisalign; ///< Read block misalignment
|
||||
u8 DSRImpl; ///< DSR implemented
|
||||
u8 Reserved2; ///< Reserved
|
||||
u32 DeviceSize; ///< Device Size
|
||||
u8 MaxRdCurrentVDDMin; ///< Max. read current @ VDD min
|
||||
u8 MaxRdCurrentVDDMax; ///< Max. read current @ VDD max
|
||||
u8 MaxWrCurrentVDDMin; ///< Max. write current @ VDD min
|
||||
u8 MaxWrCurrentVDDMax; ///< Max. write current @ VDD max
|
||||
u8 DeviceSizeMul; ///< Device size multiplier
|
||||
u8 EraseGrSize; ///< Erase group size
|
||||
u8 EraseGrMul; ///< Erase group size multiplier
|
||||
u8 WrProtectGrSize; ///< Write protect group size
|
||||
u8 WrProtectGrEnable; ///< Write protect group enable
|
||||
u8 ManDeflECC; ///< Manufacturer default ECC
|
||||
u8 WrSpeedFact; ///< Write speed factor
|
||||
u8 MaxWrBlockLen; ///< Max. write data block length
|
||||
u8 WriteBlockPaPartial; ///< Partial blocks for write allowed
|
||||
u8 Reserved3; ///< Reserded
|
||||
u8 ContentProtectAppli; ///< Content protection application
|
||||
u8 FileFormatGrouop; ///< File format group
|
||||
u8 CopyFlag; ///< Copy flag (OTP)
|
||||
u8 PermWrProtect; ///< Permanent write protection
|
||||
u8 TempWrProtect; ///< Temporary write protection
|
||||
u8 FileFormat; ///< File Format
|
||||
u8 ECC; ///< ECC code
|
||||
u8 CSD_CRC; ///< CSD CRC
|
||||
u8 Reserved4; ///< always 1
|
||||
} SD_CSD;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SD card CID register data
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u8 ManufacturerID; ///< ManufacturerID
|
||||
u16 OEM_AppliID; ///< OEM/Application ID
|
||||
u32 ProdName1; ///< Product Name part1
|
||||
u8 ProdName2; ///< Product Name part2
|
||||
u8 ProdRev; ///< Product Revision
|
||||
u32 ProdSN; ///< Product Serial Number
|
||||
u8 Reserved1; ///< Reserved1
|
||||
u16 ManufactDate; ///< Manufacturing Date
|
||||
u8 CID_CRC; ///< CID CRC
|
||||
u8 Reserved2; ///< always 1
|
||||
} SD_CID;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SD state
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SD_CARD_READY = ((u32)0x00000001),
|
||||
SD_CARD_IDENTIFICATION = ((u32)0x00000002),
|
||||
SD_CARD_STANDBY = ((u32)0x00000003),
|
||||
SD_CARD_TRANSFER = ((u32)0x00000004),
|
||||
SD_CARD_SENDING = ((u32)0x00000005),
|
||||
SD_CARD_RECEIVING = ((u32)0x00000006),
|
||||
SD_CARD_PROGRAMMING = ((u32)0x00000007),
|
||||
SD_CARD_DISCONNECTED = ((u32)0x00000008),
|
||||
SD_CARD_ERROR = ((u32)0x000000FF)
|
||||
} SDCardState;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SD message ,include CSD,CID data
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
SD_CSD SD_csd;
|
||||
SD_CID SD_cid;
|
||||
long long CardCapacity;
|
||||
u32 CardBlockSize;
|
||||
u16 RCA;
|
||||
u8 CardType;
|
||||
} SD_CardInfo;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SDIO init
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u8 SDIO_MDEN;
|
||||
u8 SDIO_DATWT;
|
||||
u8 SDIO_SelPTSM;
|
||||
u8 SDIO_CLKSP;
|
||||
u8 SDIO_OUTM;
|
||||
u8 SDIO_SelSM;
|
||||
u8 SDIO_OPMSel;
|
||||
} SDIO_InitTypeDef;
|
||||
|
||||
typedef struct {
|
||||
u32 SDIO_Argument; ///Specifies the SDIO command argument which is sent
|
||||
///to a card as part of a command message. If a command
|
||||
///contains an argument, it must be loaded into this register
|
||||
///before writing the command to the command register
|
||||
|
||||
u32 SDIO_CmdIndex; ///Specifies the SDIO command index. It must be lower than 0x40.
|
||||
|
||||
u32 SDIO_Response; ///Specifies the SDIO response type.
|
||||
///This parameter can be a value of @ref SDIO_Response_Type
|
||||
|
||||
u32 SDIO_Wait; ///Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
|
||||
///This parameter can be a value of @ref SDIO_Wait_Interrupt_State
|
||||
|
||||
/// u32 SDIO_CPSM; ///Specifies whether SDIO Command path state machine (CPSM)
|
||||
///is enabled or disabled.
|
||||
///This parameter can be a value of @ref SDIO_CPSM_State
|
||||
} SDIO_CmdInitTypeDef;
|
||||
typedef struct {
|
||||
u32 SDIO_DataTimeOut; // < Specifies the data timeout period in card bus clock periods.
|
||||
//
|
||||
u32 SDIO_DataLength; // < Specifies the number of data bytes to be transferred.
|
||||
//
|
||||
u32 SDIO_DataBlockSize; // < Specifies the data block size for block transfer.
|
||||
// This parameter can be a value of @ref SDIO_Data_Block_Size
|
||||
//
|
||||
u32 SDIO_TransferDir; // < Specifies the data transfer direction, whether the transfer
|
||||
// is a read or write.
|
||||
// This parameter can be a value of @ref SDIO_Transfer_Direction
|
||||
//
|
||||
// u32 SDIO_TransferMode; // < Specifies whether data transfer is in stream or block mode.
|
||||
// // This parameter can be a value of @ref SDIO_Transfer_Type
|
||||
// //
|
||||
// u32 SDIO_DPSM; // < Specifies whether SDIO Data path state machine (DPSM)
|
||||
// // is enabled or disabled.
|
||||
// // This parameter can be a value of @ref SDIO_DPSM_State
|
||||
} SDIO_DataInitTypeDef;
|
||||
|
||||
|
||||
|
||||
extern SD_CardInfo SDCardInfo;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SDIO ָinstruction set
|
||||
/// @{
|
||||
#define SD_CMD_GO_IDLE_STATE ((u8)0)
|
||||
#define SD_CMD_SEND_OP_COND ((u8)1)
|
||||
#define SD_CMD_ALL_SEND_CID ((u8)2)
|
||||
#define SD_CMD_SET_REL_ADDR ((u8)3)
|
||||
#define SD_CMD_SET_DSR ((u8)4)
|
||||
#define SD_CMD_SDIO_SEN_OP_COND ((u8)5)
|
||||
#define SD_CMD_HS_SWITCH ((u8)6)
|
||||
#define SD_CMD_SEL_DESEL_CARD ((u8)7)
|
||||
#define SD_CMD_HS_SEND_EXT_CSD ((u8)8)
|
||||
#define SD_CMD_SEND_CSD ((u8)9)
|
||||
#define SD_CMD_SEND_CID ((u8)10)
|
||||
#define SD_CMD_READ_DAT_UNTIL_STOP ((u8)11)
|
||||
#define SD_CMD_STOP_TRANSMISSION ((u8)12)
|
||||
#define SD_CMD_SEND_STATUS ((u8)13)
|
||||
#define SD_CMD_HS_BUSTEST_READ ((u8)14)
|
||||
#define SD_CMD_GO_INACTIVE_STATE ((u8)15)
|
||||
#define SD_CMD_SET_BLOCKLEN ((u8)16)
|
||||
#define SD_CMD_READ_SINGLE_BLOCK ((u8)17)
|
||||
#define SD_CMD_READ_MULT_BLOCK ((u8)18)
|
||||
#define SD_CMD_HS_BUSTEST_WRITE ((u8)19)
|
||||
#define SD_CMD_WRITE_DAT_UNTIL_STOP ((u8)20)
|
||||
#define SD_CMD_SET_BLOCK_COUNT ((u8)23)
|
||||
#define SD_CMD_WRITE_SINGLE_BLOCK ((u8)24)
|
||||
#define SD_CMD_WRITE_MULT_BLOCK ((u8)25)
|
||||
#define SD_CMD_PROG_CID ((u8)26)
|
||||
#define SD_CMD_PROG_CSD ((u8)27)
|
||||
#define SD_CMD_SET_WRITE_PROT ((u8)28)
|
||||
#define SD_CMD_CLR_WRITE_PROT ((u8)29)
|
||||
#define SD_CMD_SEND_WRITE_PROT ((u8)30)
|
||||
#define SD_CMD_SD_ERASE_GRP_START ((u8)32)
|
||||
#define SD_CMD_SD_ERASE_GRP_END ((u8)33)
|
||||
#define SD_CMD_ERASE_GRP_START ((u8)35)
|
||||
#define SD_CMD_ERASE_GRP_END ((u8)36)
|
||||
#define SD_CMD_ERASE ((u8)38)
|
||||
#define SD_CMD_FAST_IO ((u8)39)
|
||||
#define SD_CMD_GO_IRQ_STATE ((u8)40)
|
||||
#define SD_CMD_LOCK_UNLOCK ((u8)42)
|
||||
#define SD_CMD_APP_CMD ((u8)55)
|
||||
#define SD_CMD_GEN_CMD ((u8)56)
|
||||
#define SD_CMD_NO_CMD ((u8)64)
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup Following commands are SD Card Specific commands.
|
||||
/// @{
|
||||
#define SD_CMD_APP_SD_SET_BUSWIDTH ((u8)6)
|
||||
#define SD_CMD_SD_APP_STAUS ((u8)13)
|
||||
#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((u8)22)
|
||||
#define SD_CMD_SD_APP_OP_COND ((u8)41)
|
||||
#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((u8)42)
|
||||
#define SD_CMD_SD_APP_SEND_SCR ((u8)51)
|
||||
#define SD_CMD_SDIO_RW_DIRECT ((u8)52)
|
||||
#define SD_CMD_SDIO_RW_EXTENDED ((u8)53)
|
||||
|
||||
#define SD_CMD_SD_APP_GET_MKB ((u8)43)
|
||||
#define SD_CMD_SD_APP_GET_MID ((u8)44)
|
||||
#define SD_CMD_SD_APP_SET_CER_RN1 ((u8)45)
|
||||
#define SD_CMD_SD_APP_GET_CER_RN2 ((u8)46)
|
||||
#define SD_CMD_SD_APP_SET_CER_RES2 ((u8)47)
|
||||
#define SD_CMD_SD_APP_GET_CER_RES1 ((u8)48)
|
||||
#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((u8)18)
|
||||
#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((u8)25)
|
||||
#define SD_CMD_SD_APP_SECURE_ERASE ((u8)38)
|
||||
#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((u8)49)
|
||||
#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((u8)48)
|
||||
/// @}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SD support define.
|
||||
/// @{
|
||||
#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((u32)0x00000000)
|
||||
#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((u32)0x00000001)
|
||||
#define SDIO_HIGH_CAPACITY_SD_CARD ((u32)0x00000002)
|
||||
#define SDIO_MULTIMEDIA_CARD ((u32)0x00000003)
|
||||
#define SDIO_SECURE_DIGITAL_IO_CARD ((u32)0x00000004)
|
||||
#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((u32)0x00000005)
|
||||
#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((u32)0x00000006)
|
||||
#define SDIO_HIGH_CAPACITY_MMC_CARD ((u32)0x00000007)
|
||||
/// @}
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0
|
||||
#endif
|
||||
#define SDIO_STATIC_FLAGS ((u32)0x000005FF)
|
||||
#define SDIO_CMD0TIMEOUT ((u32)0x00010000)
|
||||
#define SDIO_DATATIMEOUT ((u32)0xFFFFFFFF)
|
||||
#define SDIO_FIFO_Address ((u32)0x40018080)
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup Mask for errors Card Status R1 (OCR Register)
|
||||
/// @{
|
||||
#define SD_OCR_ADDR_OUT_OF_RANGE ((u32)0x80000000)
|
||||
#define SD_OCR_ADDR_MISALIGNED ((u32)0x40000000)
|
||||
#define SD_OCR_BLOCK_LEN_ERR ((u32)0x20000000)
|
||||
#define SD_OCR_ERASE_SEQ_ERR ((u32)0x10000000)
|
||||
#define SD_OCR_BAD_ERASE_PARAM ((u32)0x08000000)
|
||||
#define SD_OCR_WRITE_PROT_VIOLATION ((u32)0x04000000)
|
||||
#define SD_OCR_LOCK_UNLOCK_FAILED ((u32)0x01000000)
|
||||
#define SD_OCR_COM_CRC_FAILED ((u32)0x00800000)
|
||||
#define SD_OCR_ILLEGAL_CMD ((u32)0x00400000)
|
||||
#define SD_OCR_CARD_ECC_FAILED ((u32)0x00200000)
|
||||
#define SD_OCR_CC_ERROR ((u32)0x00100000)
|
||||
#define SD_OCR_GENERAL_UNKNOWN_ERROR ((u32)0x00080000)
|
||||
#define SD_OCR_STREAM_READ_UNDERRUN ((u32)0x00040000)
|
||||
#define SD_OCR_STREAM_WRITE_OVERRUN ((u32)0x00020000)
|
||||
#define SD_OCR_CID_CSD_OVERWRIETE ((u32)0x00010000)
|
||||
#define SD_OCR_WP_ERASE_SKIP ((u32)0x00008000)
|
||||
#define SD_OCR_CARD_ECC_DISABLED ((u32)0x00004000)
|
||||
#define SD_OCR_ERASE_RESET ((u32)0x00002000)
|
||||
#define SD_OCR_AKE_SEQ_ERROR ((u32)0x00000008)
|
||||
#define SD_OCR_ERRORBITS ((u32)0xFDFFE008)
|
||||
/// @}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup Masks for R6 Response
|
||||
/// @{
|
||||
#define SD_R6_GENERAL_UNKNOWN_ERROR ((u32)0x00002000)
|
||||
#define SD_R6_ILLEGAL_CMD ((u32)0x00004000)
|
||||
#define SD_R6_COM_CRC_FAILED ((u32)0x00008000)
|
||||
/// @}
|
||||
#define SD_VOLTAGE_WINDOW_SD ((u32)0x80100000)
|
||||
#define SD_HIGH_CAPACITY ((u32)0x40000000)
|
||||
#define SD_STD_CAPACITY ((u32)0x00000000)
|
||||
#define SD_CHECK_PATTERN ((u32)0x000001AA)
|
||||
#define SD_VOLTAGE_WINDOW_MMC ((u32)0x80FF8000)
|
||||
|
||||
#define SD_MAX_VOLT_TRIAL ((u32)0x0000FFFF)
|
||||
#define SD_ALLZERO ((u32)0x00000000)
|
||||
|
||||
#define SD_WIDE_BUS_SUPPORT ((u32)0x00040000)
|
||||
#define SD_SINGLE_BUS_SUPPORT ((u32)0x00010000)
|
||||
#define SD_CARD_LOCKED ((u32)0x02000000)
|
||||
#define SD_CARD_PROGRAMMING ((u32)0x00000007)
|
||||
#define SD_CARD_RECEIVING ((u32)0x00000006)
|
||||
#define SD_DATATIMEOUT ((u32)0xFFFFFFFF)
|
||||
#define SD_0TO7BITS ((u32)0x000000FF)
|
||||
#define SD_8TO15BITS ((u32)0x0000FF00)
|
||||
#define SD_16TO23BITS ((u32)0x00FF0000)
|
||||
#define SD_24TO31BITS ((u32)0xFF000000)
|
||||
#define SD_MAX_DATA_LENGTH ((u32)0x01FFFFFF)
|
||||
|
||||
#define SD_HALFFIFO ((u32)0x00000008)
|
||||
#define SD_HALFFIFOBYTES ((u32)0x00000020)
|
||||
|
||||
#define SD_CCCC_LOCK_UNLOCK ((u32)0x00000080)
|
||||
#define SD_CCCC_WRITE_PROT ((u32)0x00000040)
|
||||
#define SD_CCCC_ERASE ((u32)0x00000020)
|
||||
|
||||
|
||||
#define SDIO_SEND_IF_COND ((u32)0x00000008)
|
||||
|
||||
#define SDIO_Response_No ((u32)0x00)
|
||||
#define SDIO_Response_Short ((u32)0x01)
|
||||
#define SDIO_Response_Long ((u32)0x03)
|
||||
|
||||
#define SDIO_DataBlockSize_1b ((u32)0x00000000)
|
||||
#define SDIO_DataBlockSize_2b ((u32)0x00000001)
|
||||
#define SDIO_DataBlockSize_4b ((u32)0x00000002)
|
||||
#define SDIO_DataBlockSize_8b ((u32)0x00000003)
|
||||
#define SDIO_DataBlockSize_16b ((u32)0x00000004)
|
||||
#define SDIO_DataBlockSize_32b ((u32)0x00000005)
|
||||
#define SDIO_DataBlockSize_64b ((u32)0x00000006)
|
||||
#define SDIO_DataBlockSize_128b ((u32)0x00000007)
|
||||
#define SDIO_DataBlockSize_256b ((u32)0x00000008)
|
||||
#define SDIO_DataBlockSize_512b ((u32)0x00000009)
|
||||
#define SDIO_DataBlockSize_1024b ((u32)0x0000000A)
|
||||
#define SDIO_DataBlockSize_2048b ((u32)0x0000000B)
|
||||
#define SDIO_DataBlockSize_4096b ((u32)0x0000000C)
|
||||
#define SDIO_DataBlockSize_8192b ((u32)0x0000000D)
|
||||
#define SDIO_DataBlockSize_16384b ((u32)0x0000000E)
|
||||
//Define the data block length when the block data transfer mode is selected:
|
||||
//0000: (0 decimal) lock length = 2^0 = 1 byte
|
||||
//0001: (1 decimal) lock length = 2^1 = 2 bytes
|
||||
//0010: (2 decimal) lock length = 2^2 = 4 bytes
|
||||
//0011: (3 decimal) lock length = 2^3 = 8 bytes
|
||||
//0100: (4 decimal) lock length = 2^4 = 16 bytes
|
||||
//0101: (5 decimal) lock length = 2^5 = 32 bytes
|
||||
//0110: (6 decimal) lock length = 2^6 = 64 bytes
|
||||
//0111: (7 decimal) lock length = 2^7 = 128 bytes
|
||||
//1000: (8 decimal) lock length = 2^8 = 256 bytes
|
||||
//1001: (9 decimal) lock length = 2^9 = 512 bytes
|
||||
//1010: (10 decimal) lock length = 2^10 = 1024 bytes
|
||||
//1011: (11 decimal) lock length = 2^11 = 2048 bytes
|
||||
//1100: (12 decimal) lock length = 2^12 = 4096 bytes
|
||||
//1101: (13 decimal) lock length = 2^13 = 8192 bytes
|
||||
//1110: (14 decimal) lock length = 2^14 = 16384 bytes
|
||||
//1111: (15 decimal) reserved
|
||||
|
||||
|
||||
#define SDIO_TransferDir_ToCard ((u32)0x00000000)
|
||||
#define SDIO_TransferDir_ToSDIO ((u32)0x00000002)
|
||||
|
||||
#define SDIO_Wait_No ((u32)0x00000000) // SDIO No Wait, TimeOut is enabled
|
||||
#define SDIO_Wait_IT ((u32)0x00000100) //SDIO Wait Interrupt Request
|
||||
#define SDIO_Wait_Pend ((u32)0x00000200) // SDIO Wait End of transfer
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup I2C_Exported_Functions
|
||||
/// @{
|
||||
void SDIO_DeInit(void);
|
||||
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||
void SDIO_ClockSet(u32 value);
|
||||
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||
void SDIO_ITConfig(u32 SDIO_IT, FunctionalState state);
|
||||
void SDIO_CRCConfig(u32 SDIO_CRC, FunctionalState state);
|
||||
void SDIO_Clock_Set(u8 clkdiv);
|
||||
void SDIO_Send_Cmd(u8 cmdindex, u8 waitrsp, u32 arg);
|
||||
SD_Error SD_PowerOFF(void);
|
||||
SD_Error CmdError(void);
|
||||
SD_Error CmdResp2Error(void);
|
||||
SD_Error CmdResp3Error(void);
|
||||
SD_Error CmdResp6Error(u8 cmd, u16* prca);
|
||||
SD_Error CmdResp7Error(void);
|
||||
SD_Error CmdResp1Error(u8 cmd);
|
||||
void SDIO_Send_Data_Cfg(u32 datatimeout, u32 datalen, u8 blksize, u8 dir);
|
||||
void SDIO_ClearITPendingBit(u32 SDIO_IT);
|
||||
FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG);
|
||||
u32 SDIO_GetTimeOutCounter(void);
|
||||
u32 SDIO_ReadData(void);
|
||||
void SDIO_WriteData(u32 tempbuff);
|
||||
void SDIO_DMACmd(FunctionalState state);
|
||||
/// @}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,351 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_spi.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SPI
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_SPI_H
|
||||
#define __HAL_SPI_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_spi.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SPI_HAL
|
||||
/// @brief SPI HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SPI_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI mode enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_Mode_Slave = 0x0000, ///< SPI slave mode
|
||||
SPI_Mode_Master = SPI_GCR_MODE ///< SPI master mode
|
||||
} SPI_Mode_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI data size enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_DataSize_8b = 0x0000, ///< 8 bits valid data
|
||||
SPI_DataSize_32b = SPI_GCR_DWSEL ///< 32 bits valid data
|
||||
} SPI_DataSize_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI clock polarity enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_CPOL_Low = 0x0000, ///< The clock is low in idle state.
|
||||
SPI_CPOL_High = SPI_CCR_CPOL ///< The clock is high in idle state.
|
||||
} SPI_CPOL_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI clock phase enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_CPHA_2Edge = 0x0000, ///< Data sampling starts from the second clock edge.
|
||||
SPI_CPHA_1Edge = SPI_CCR_CPHA ///< Data sampling starts from the first clock edge.
|
||||
} SPI_CPHA_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI nss control mode enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_NSS_Soft = 0x0000,
|
||||
SPI_NSS_Hard = SPI_GCR_NSS
|
||||
} SPI_NSS_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI baud rate prescaler enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_BaudRatePrescaler_2 = 0x0002, ///< SCK clock devide by 2
|
||||
SPI_BaudRatePrescaler_4 = 0x0004, ///< SCK clock devide by 4
|
||||
SPI_BaudRatePrescaler_8 = 0x0008, ///< SCK clock devide by 7
|
||||
SPI_BaudRatePrescaler_16 = 0x0010, ///< SCK clock devide by 16
|
||||
SPI_BaudRatePrescaler_32 = 0x0020, ///< SCK clock devide by 32
|
||||
SPI_BaudRatePrescaler_64 = 0x0040, ///< SCK clock devide by 64
|
||||
SPI_BaudRatePrescaler_128 = 0x0080, ///< SCK clock devide by 128
|
||||
SPI_BaudRatePrescaler_256 = 0x0100 ///< SCK clock devide by 256
|
||||
} SPI_BaudRatePrescaler_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI first bit enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_FirstBit_MSB = 0x0000, ///< Data transfers start from MSB
|
||||
SPI_FirstBit_LSB = SPI_CCR_LSBFE ///< Data transfers start from LSB
|
||||
} SPI_FirstBit_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI FIFO trigger level enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_RXTLF = SPI_GCR_RXTLF_Half, ///< RX FIFO trigger level
|
||||
SPI_TXTLF = SPI_GCR_TXTLF_Half ///< TX FIFO trigger level
|
||||
} SPI_TLF_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI bit derection enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_Direction_Rx, ///< Receive enable
|
||||
SPI_Direction_Tx, ///< Transmit enable
|
||||
SPI_Disable_Rx, ///< Receive disable
|
||||
SPI_Disable_Tx ///< Transmit disable
|
||||
} SPI_Direction_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI flag enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_FLAG_RXAVL = SPI_SR_RXAVL, ///< Receive 1 byte available data flag
|
||||
SPI_FLAG_TXEPT = SPI_SR_TXEPT, ///< Transmitter empty flag
|
||||
SPI_FLAG_TXFULL = SPI_SR_TXFULL, ///< Transmitter FIFO full status flag
|
||||
SPI_FLAG_RXAVL_4BYTE = SPI_SR_RXAVL_4BYTE ///< Receive 4 bytes available data flag
|
||||
} SPI_FLAG_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI slave mode data edge adjust enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_SlaveAdjust_LOW, ///< SPI slave mode data edge adjust in low speed mode
|
||||
SPI_SlaveAdjust_FAST ///< SPI slave mode data edge adjust in fast speed mode
|
||||
} SPI_SlaveAdjust_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI data edge adjust enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_DataEdgeAdjust_LOW, ///< SPI data edge adjust in low speed mode
|
||||
SPI_DataEdgeAdjust_FAST ///< SPI data edge adjust in fast speed mode
|
||||
} SPI_DataEdgeAdjust_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI interruput enum definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
SPI_IT_TXEPT = 0x40, ///< Transmitter empty interrupt
|
||||
SPI_IT_RXFULL = 0x20, ///< RX FIFO full interrupt
|
||||
SPI_IT_RXMATCH = 0x10, ///< Receive data match the RXDNR number interrut
|
||||
SPI_IT_RXOERR = 0x08, ///< Receive overrun error interrupt
|
||||
SPI_IT_UNDERRUN = 0x04, ///< Underrun interrupt
|
||||
SPI_IT_RX = 0x02, ///< Receive available data interrupt
|
||||
SPI_IT_TX = 0x01 ///< Transmit FIFO available interrupt
|
||||
} SPI_IT_TypeDef;
|
||||
|
||||
|
||||
typedef enum {
|
||||
I2S_Standard_Phillips = 0x0000,
|
||||
I2S_Standard_MSB = 0x0010,
|
||||
I2S_Standard_LSB = 0x0020,
|
||||
I2S_Standard_PCMShort = 0x0030,
|
||||
I2S_Standard_PCMLong = 0x00B0,
|
||||
} SPI_I2S_STANDARD_TypeDef;
|
||||
|
||||
|
||||
typedef enum {
|
||||
I2S_DataFormat_16b = 0x0000,
|
||||
I2S_DataFormat_16bextended = 0x0001,
|
||||
I2S_DataFormat_24b = 0x0003,
|
||||
I2S_DataFormat_32b = 0x0005,
|
||||
} SPI_I2S_DATAFORMAT_TypeDef;
|
||||
typedef enum {
|
||||
I2S_AudioFreq_192k = (192000),
|
||||
I2S_AudioFreq_96k = (96000),
|
||||
I2S_AudioFreq_48k = (48000),
|
||||
I2S_AudioFreq_44k = (44100),
|
||||
I2S_AudioFreq_32k = (32000),
|
||||
I2S_AudioFreq_24k = (24000),
|
||||
I2S_AudioFreq_22k = (22050),
|
||||
I2S_AudioFreq_16k = (16000),
|
||||
I2S_AudioFreq_11k = (11025),
|
||||
I2S_AudioFreq_12k = (12000),
|
||||
I2S_AudioFreq_8k = (8000),
|
||||
I2S_AudioFreq_4k = (4000),
|
||||
I2S_AudioFreq_Default = (2),
|
||||
} SPI_I2S_AUDIO_FREQ_TypeDef;
|
||||
typedef enum {
|
||||
I2S_Mode_SlaveTx = 0x0000,
|
||||
I2S_Mode_SlaveRx = 0x0100,
|
||||
I2S_Mode_MasterTx = 0x0200,
|
||||
I2S_Mode_MasterRx = 0x0300,
|
||||
} SPI_I2S_TRANS_MODE_TypeDef;
|
||||
|
||||
typedef enum {
|
||||
I2S_MCLKOutput_Enable = 0x0800,
|
||||
I2S_MCLKOutput_Disable = 0x0000,
|
||||
} SPI_I2S_MCLK_OUTPUT_TypeDef;
|
||||
|
||||
typedef enum {
|
||||
I2S_CPOL_Low = 0x0000, ///< The clock is low in idle state.
|
||||
I2S_CPOL_High = SPI_CCR_CPOL ///< The clock is high in idle state.
|
||||
} SPI_I2S_CPOL_TypeDef;
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SPI Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
SPI_Mode_TypeDef SPI_Mode; ///< Specifies the SPI operating mode
|
||||
SPI_DataSize_TypeDef SPI_DataSize; ///< Specifies the SPI available data size
|
||||
u8 SPI_DataWidth; ///< SPI data length
|
||||
SPI_CPOL_TypeDef SPI_CPOL; ///< Specifies the serial clock steady state
|
||||
SPI_CPHA_TypeDef SPI_CPHA; ///< Specifies the clock active edge for the bit capture
|
||||
SPI_NSS_TypeDef SPI_NSS; ///< Specifies whether the NSS signal is managed by hardware or by software
|
||||
SPI_BaudRatePrescaler_TypeDef SPI_BaudRatePrescaler; ///< Specifies the Baud Rate prescaler value which will be
|
||||
///< used to configure the transmit and receive SCK clock
|
||||
SPI_FirstBit_TypeDef SPI_FirstBit; ///< Specifies whether data transfers start from MSB or LSB bit
|
||||
// u16 SPI_length;
|
||||
} SPI_InitTypeDef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief I2S Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
SPI_I2S_TRANS_MODE_TypeDef I2S_Mode; ///< Specifies the I2S operating mode.
|
||||
SPI_I2S_STANDARD_TypeDef I2S_Standard; ///< Specifies the standard used for the I2S communication.
|
||||
SPI_I2S_DATAFORMAT_TypeDef I2S_DataFormat; ///< Specifies the data format for the I2S communication.
|
||||
SPI_I2S_MCLK_OUTPUT_TypeDef I2S_MCLKOutput; ///< Specifies whether the I2S MCLK output is enabled or not.
|
||||
SPI_I2S_AUDIO_FREQ_TypeDef I2S_AudioFreq; ///< Specifies the frequency selected for the I2S communication.
|
||||
SPI_I2S_CPOL_TypeDef I2S_CPOL; ///< Specifies the idle state of the I2S clock.
|
||||
} I2S_InitTypeDef;
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SPI_Exported_Constants
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SPI_Register_Mask
|
||||
/// @{
|
||||
|
||||
#define GCR_Mask ((u32)0x0FFF)
|
||||
#define CCR_Mask ((u32)0x003F)
|
||||
#define BRR_Mask ((u32)0xFFFF)
|
||||
#define ECR_Mask ((u32)0x001F)
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
// SPI_7bit_8bit data width
|
||||
#define SPI_DataWidth_1b ((u16)0x0001)
|
||||
#define SPI_DataWidth_2b ((u16)0x0002)
|
||||
#define SPI_DataWidth_3b ((u16)0x0003)
|
||||
#define SPI_DataWidth_4b ((u16)0x0004)
|
||||
#define SPI_DataWidth_5b ((u16)0x0005)
|
||||
#define SPI_DataWidth_6b ((u16)0x0006)
|
||||
#define SPI_DataWidth_7b ((u16)0x0007)
|
||||
#define SPI_DataWidth_8b ((u16)0x0008)
|
||||
#define SPI_DataWidth_9b ((u16)0x0009)
|
||||
#define SPI_DataWidth_10b ((u16)0x000a)
|
||||
#define SPI_DataWidth_11b ((u16)0x000b)
|
||||
#define SPI_DataWidth_12b ((u16)0x000c)
|
||||
#define SPI_DataWidth_13b ((u16)0x000d)
|
||||
#define SPI_DataWidth_14b ((u16)0x000e)
|
||||
#define SPI_DataWidth_15b ((u16)0x000f)
|
||||
#define SPI_DataWidth_16b ((u16)0x0010)
|
||||
#define SPI_DataWidth_17b ((u16)0x0011)
|
||||
#define SPI_DataWidth_18b ((u16)0x0012)
|
||||
#define SPI_DataWidth_19b ((u16)0x0013)
|
||||
#define SPI_DataWidth_20b ((u16)0x0014)
|
||||
#define SPI_DataWidth_21b ((u16)0x0015)
|
||||
#define SPI_DataWidth_22b ((u16)0x0016)
|
||||
#define SPI_DataWidth_23b ((u16)0x0017)
|
||||
#define SPI_DataWidth_24b ((u16)0x0018)
|
||||
#define SPI_DataWidth_25b ((u16)0x0019)
|
||||
#define SPI_DataWidth_26b ((u16)0x001a)
|
||||
#define SPI_DataWidth_27b ((u16)0x001b)
|
||||
#define SPI_DataWidth_28b ((u16)0x001c)
|
||||
#define SPI_DataWidth_29b ((u16)0x001d)
|
||||
#define SPI_DataWidth_30b ((u16)0x001e)
|
||||
#define SPI_DataWidth_31b ((u16)0x001f)
|
||||
#define SPI_DataWidth_32b ((u16)0x0000)
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SPI_Exported_Variables
|
||||
/// @{
|
||||
|
||||
#ifdef _HAL_SPI_C_
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SPI_Exported_Functions
|
||||
/// @{
|
||||
|
||||
void SPI_DeInit(SPI_TypeDef* spi);
|
||||
void SPI_Init(SPI_TypeDef* spi, SPI_InitTypeDef* init_struct);
|
||||
void SPI_StructInit(SPI_InitTypeDef* init_struct);
|
||||
void SPI_Cmd(SPI_TypeDef* spi, FunctionalState state);
|
||||
void SPI_ITConfig(SPI_TypeDef* spi, u8 interrupt, FunctionalState state);
|
||||
void SPI_DMACmd(SPI_TypeDef* spi, FunctionalState state);
|
||||
void SPI_FifoTrigger(SPI_TypeDef* spi, SPI_TLF_TypeDef fifo_trigger_value, FunctionalState state);
|
||||
void SPI_SendData(SPI_TypeDef* spi, u32 data);
|
||||
void SPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state);
|
||||
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* spi, SPI_NSS_TypeDef nss);
|
||||
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef* spi, SPI_Direction_TypeDef direction);
|
||||
void SPI_ClearITPendingBit(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt);
|
||||
void SPI_RxBytes(SPI_TypeDef* spi, u16 number);
|
||||
void SPI_SlaveAdjust(SPI_TypeDef* spi, SPI_SlaveAdjust_TypeDef adjust_value);
|
||||
|
||||
bool SPI_DataSizeConfig(SPI_TypeDef* spi, u8 data_size);
|
||||
void SPI_DataSizeTypeConfig(SPI_TypeDef* spi, SPI_DataSize_TypeDef SPI_DataSize);
|
||||
u32 SPI_ReceiveData(SPI_TypeDef* spi);
|
||||
|
||||
FlagStatus SPI_GetFlagStatus(SPI_TypeDef* spi, SPI_FLAG_TypeDef flag);
|
||||
|
||||
ITStatus SPI_GetITStatus(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Extended function interface
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
void exSPI_ITCmd(SPI_TypeDef* spi, FunctionalState state);
|
||||
void exSPI_ITConfig(SPI_TypeDef* spi, SPI_IT_TypeDef interrput, FunctionalState state);
|
||||
void exSPI_DMACmd(SPI_TypeDef* spi, FunctionalState state);
|
||||
void exSPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state);
|
||||
void exSPI_DataEdgeAdjust(SPI_TypeDef* spi, SPI_DataEdgeAdjust_TypeDef adjust_value);
|
||||
void I2S_Cmd(SPI_TypeDef* spi, FunctionalState state);
|
||||
void I2S_Init(SPI_TypeDef* spi, I2S_InitTypeDef* I2S_InitStruct);
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_SPI_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,83 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_syscfg.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE EXTI
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_SYSCFG_H
|
||||
#define __HAL_SYSCFG_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "mm32_device.h"
|
||||
#include "hal_EXTI.H"
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SYSCFG_HAL
|
||||
/// @brief SYSCFG HAL modules
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup SYSCFG_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief SYSCFG mode enumeration
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// @defgroup SYSCFG_Memory_Remap_Config
|
||||
#define SYSCFG_MemoryRemap_Flash ((u8)0x00)
|
||||
#define SYSCFG_MemoryRemap_SystemMemory ((u8)0x01)
|
||||
#define SYSCFG_MemoryRemap_SRAM ((u8)0x03)
|
||||
|
||||
|
||||
|
||||
|
||||
///
|
||||
/// @}
|
||||
///
|
||||
|
||||
|
||||
|
||||
|
||||
// Exported macro ------------------------------------------------------------
|
||||
// Exported functions -------------------------------------------------------
|
||||
|
||||
// Function used to set the SYSCFG configuration to the default reset state
|
||||
#define SYSCFG_DeInit EXTI_DeInit
|
||||
#define SYSCFG_MemoryRemapConfig EXTI_MemoryRemapConfig
|
||||
#define SYSCFG_EXTILineConfig EXTI_LineConfig
|
||||
u32 SYSCFG_GetPendingIT(u32 ITSourceLine);
|
||||
void SYSCFG_BreakConfig(u32 SYSCFG_Break);
|
||||
FlagStatus SYSCFG_GetFlagStatus(u32 SYSCFG_Flag);
|
||||
void SYSCFG_ClearFlag(u32 SYSCFG_Flag);
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif //__HAL_SYSCFG_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,755 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_tim.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE TIM
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_TIM_H
|
||||
#define __HAL_TIM_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_tim.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup TIM_HAL
|
||||
/// @brief TIM HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup TIM_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Channel
|
||||
/// @anchor TIM_Channel
|
||||
typedef enum {
|
||||
TIM_Channel_1 = 0x0000, ///< TIM Channel 1
|
||||
TIM_Channel_2 = 0x0004, ///< TIM Channel 2
|
||||
TIM_Channel_3 = 0x0008, ///< TIM Channel 3
|
||||
TIM_Channel_4 = 0x000C, ///< TIM Channel 4
|
||||
TIM_Channel_5 = 0x0010 ///< TIM Channel 5
|
||||
} TIMCHx_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Counter_Mode
|
||||
/// @anchor TIM_Counter_Mode
|
||||
typedef enum {
|
||||
TIM_CounterMode_Up = 0x0000, ///< TIM Up Counting Mode
|
||||
TIM_CounterMode_Down = TIM_CR1_DIR, ///< TIM Down Counting Mode
|
||||
TIM_CounterMode_CenterAligned1 = TIM_CR1_CMS_CENTERALIGNED1, ///< TIM Center Aligned Mode1
|
||||
TIM_CounterMode_CenterAligned2 = TIM_CR1_CMS_CENTERALIGNED2, ///< TIM Center Aligned Mode2
|
||||
TIM_CounterMode_CenterAligned3 = TIM_CR1_CMS_CENTERALIGNED3 ///< TIM Center Aligned Mode3
|
||||
} TIMCOUNTMODE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_and_PWM_modes_and_Forced_Action
|
||||
/// @anchor TIM_Output_Compare_and_PWM_modes_and_Forced_Action
|
||||
typedef enum {
|
||||
TIM_OCMode_Timing = 0x0000, ///< Output compare mode: Timing
|
||||
TIM_OCMode_Active = 0x0010, ///< Output compare mode: Active
|
||||
TIM_OCMode_Inactive = 0x0020, ///< Output compare mode: Inactive
|
||||
TIM_OCMode_Toggle = 0x0030, ///< Output compare mode: Toggle
|
||||
TIM_OCMode_PWM1 = 0x0060, ///< Output compare mode: PWM1
|
||||
TIM_OCMode_PWM2 = 0x0070, ///< Output compare mode: PWM2
|
||||
TIM_ForcedAction_Active = 0x0050, ///< Force active level on OCnREF
|
||||
TIM_ForcedAction_InActive = 0x0040 ///< Force inactive level on OCnREF
|
||||
} TIMOCMODE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Clock_Division_CKD
|
||||
/// @anchor TIM_Clock_Division_CKD
|
||||
typedef enum {
|
||||
TIM_CKD_DIV1 = TIM_CR1_CKD_DIV1, ///< TDTS = Tck_tim
|
||||
TIM_CKD_DIV2 = TIM_CR1_CKD_DIV2, ///< TDTS = 2 * Tck_tim
|
||||
TIM_CKD_DIV4 = TIM_CR1_CKD_DIV4 ///< TDTS = 4 * Tck_tim
|
||||
} TIMCKD_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Internal_Trigger_Selection
|
||||
/// @anchor TIM_Internal_Trigger_Selection
|
||||
typedef enum {
|
||||
TIM_TS_ITR0 = TIM_SMCR_TS_ITR0, ///< Internal Trigger 0
|
||||
TIM_TS_ITR1 = TIM_SMCR_TS_ITR1, ///< Internal Trigger 1
|
||||
TIM_TS_ITR2 = TIM_SMCR_TS_ITR2, ///< Internal Trigger 2
|
||||
TIM_TS_ITR3 = TIM_SMCR_TS_ITR3, ///< Internal Trigger 3
|
||||
TIM_TS_TI1F_ED = TIM_SMCR_TS_TI1F_ED, ///< TI1 Edge Detector
|
||||
TIM_TS_TI1FP1 = TIM_SMCR_TS_TI1FP1, ///< Filtered Timer Input 1
|
||||
TIM_TS_TI2FP2 = TIM_SMCR_TS_TI2FP2, ///< Filtered Timer Input 2
|
||||
TIM_TS_ETRF = TIM_SMCR_TS_ETRF ///< TI1 Edge Detector
|
||||
} TIMTS_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Trigger_Output_Source
|
||||
/// @anchor TIM_Trigger_Output_Source
|
||||
typedef enum {
|
||||
TIM_TRIGSource_Reset = TIM_CR2_MMS_RESET, ///< The UG bit in the TIM_EGR register is used as the trigger output (TRIG).
|
||||
TIM_TRIGSource_Enable = TIM_CR2_MMS_ENABLE, ///< The Counter Enable CEN is used as the trigger output (TRIG).
|
||||
TIM_TRIGSource_Update = TIM_CR2_MMS_UPDATE, ///< The update event is used as the trigger output (TRIG).
|
||||
TIM_TRIGSource_OC1 = TIM_CR2_MMS_OC1, ///< The trigger output sends a positive pulse when the CC1IF flag
|
||||
///< is to be set, as soon as a capture or compare match occurs (TRIG).
|
||||
TIM_TRIGSource_OC1Ref = TIM_CR2_MMS_OC1REF, ///< OC1REF signal is used as the trigger output (TRIG).
|
||||
TIM_TRIGSource_OC2Ref = TIM_CR2_MMS_OC2REF, ///< OC2REF signal is used as the trigger output (TRIG).
|
||||
TIM_TRIGSource_OC3Ref = TIM_CR2_MMS_OC3REF, ///< OC3REF signal is used as the trigger output (TRIG).
|
||||
TIM_TRIGSource_OC4Ref = TIM_CR2_MMS_OC4REF ///< OC4REF signal is used as the trigger output (TRIG).
|
||||
} TIMMMS_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Slave_Mode
|
||||
/// @anchor TIM_Slave_Mode
|
||||
typedef enum {
|
||||
TIM_SlaveMode_Reset = TIM_SMCR_SMS_RESET, ///< Rising edge of the selected trigger signal (TRGI) re-initializes
|
||||
///< the counter and triggers an update of the registers.
|
||||
TIM_SlaveMode_Gated = TIM_SMCR_SMS_GATED, ///< The counter clock is enabled when the trigger signal (TRGI) is high.
|
||||
TIM_SlaveMode_Trigger = TIM_SMCR_SMS_TRIGGER, ///< The counter starts at a rising edge of the trigger TRGI.
|
||||
TIM_SlaveMode_External1 = TIM_SMCR_SMS_EXTERNAL1 ///< Rising edges of the selected trigger (TRGI) clock the counter.
|
||||
} TIMSMSMODE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Event_Source
|
||||
/// @anchor TIM_Event_Source
|
||||
typedef enum {
|
||||
TIM_EventSource_Update = TIM_EGR_UG, ///< Timer update Event source
|
||||
TIM_EventSource_CC1 = TIM_EGR_CC1G, ///< Timer Capture Compare 1 Event source
|
||||
TIM_EventSource_CC2 = TIM_EGR_CC2G, ///< Timer Capture Compare 2 Event source
|
||||
TIM_EventSource_CC3 = TIM_EGR_CC3G, ///< Timer Capture Compare 3 Event source
|
||||
TIM_EventSource_CC4 = TIM_EGR_CC4G, ///< Timer Capture Compare 4 Event source
|
||||
TIM_EventSource_COM = TIM_EGR_COMG, ///< Timer COM event source
|
||||
TIM_EventSource_Trigger = TIM_EGR_TG, ///< Timer Trigger Event source
|
||||
TIM_EventSource_Break = TIM_EGR_BG, ///< Timer Break event source
|
||||
TIM_EventSource_CC5 = (s32)0x00010000, ///< Timer Capture Compare 5 Event source
|
||||
} TIMEGR_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_External_Trigger_Prescaler
|
||||
/// @anchor TIM_External_Trigger_Prescaler
|
||||
typedef enum {
|
||||
TIM_ExtTRGPSC_OFF = TIM_SMCR_ETPS_OFF, ///< ETRP Prescaler OFF
|
||||
TIM_ExtTRGPSC_DIV2 = TIM_SMCR_ETPS_DIV2, ///< ETRP frequency divided by 2
|
||||
TIM_ExtTRGPSC_DIV4 = TIM_SMCR_ETPS_DIV4, ///< ETRP frequency divided by 4
|
||||
TIM_ExtTRGPSC_DIV8 = TIM_SMCR_ETPS_DIV8 ///< ETRP frequency divided by 8
|
||||
} TIMEXTTRGPSC_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_TIx_External_Clock_Source
|
||||
/// @anchor TIM_TIx_External_Clock_Source
|
||||
typedef enum {
|
||||
TIM_TIxExternalCLK1Source_TI1 = TIM_SMCR_TS_TI1FP1, ///< Filtered Timer Input 1
|
||||
TIM_TIxExternalCLK1Source_TI2 = TIM_SMCR_TS_TI2FP2, ///< Filtered Timer Input 2
|
||||
TIM_TIxExternalCLK1Source_TI1ED = TIM_SMCR_TS_TI1F_ED ///< TI1 Edge Detector
|
||||
} TIM_TIEXTCLKSRC_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Lock_level
|
||||
/// @anchor Lock_level
|
||||
typedef enum {
|
||||
TIM_LOCKLevel_OFF = TIM_BDTR_LOCK_OFF, ///< No bit is write protected.
|
||||
TIM_LOCKLevel_1 = TIM_BDTR_LOCK_1, ///< DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
|
||||
///< register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
|
||||
TIM_LOCKLevel_2 = TIM_BDTR_LOCK_2, ///< LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
|
||||
///< register, as s32 as the related channel is configured in output through the CCxS
|
||||
///< bits) as well as OSSR and OSSI bits can no longer be written.
|
||||
TIM_LOCKLevel_3 = TIM_BDTR_LOCK_3 ///< LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers,
|
||||
///< as s32 as the related channel is configured in output through the CCxS bits)
|
||||
///< can no longer be written.
|
||||
} TIMLOCKLEVEL_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_One_Pulse_Mode
|
||||
/// @anchor TIM_One_Pulse_Mode
|
||||
typedef enum {
|
||||
TIM_OPMode_Repetitive = 0, ///< Counter is not stopped at update event
|
||||
TIM_OPMode_Single = TIM_CR1_OPM ///< Counter stops counting at the next update event (clearing the bit CEN)
|
||||
} TIMOPMODE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_Polarity
|
||||
/// @anchor TIM_Output_Compare_Polarity
|
||||
typedef enum {
|
||||
TIM_OCPolarity_High, ///< Output Compare active high
|
||||
TIM_OCPolarity_Low = TIM_CCER_CC1P ///< Output Compare active low
|
||||
} TIMCCxP_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_N_Polarity
|
||||
/// @anchor TIM_Output_Compare_N_Polarity
|
||||
typedef enum {
|
||||
TIM_OCNPolarity_High, ///< Output Compare active high
|
||||
TIM_OCNPolarity_Low = TIM_CCER_CC1NP ///< Output Compare active low
|
||||
} TIMCCxNP_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_state
|
||||
/// @anchor TIM_Output_Compare_state
|
||||
typedef enum {
|
||||
TIM_OutputState_Disable = 0, ///< Output Compare Disable
|
||||
TIM_OutputState_Enable = TIM_CCER_CC1EN ///< Output Compare Enable
|
||||
} TIMOUTPUTSTATE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_N_state
|
||||
/// @anchor TIM_Output_Compare_N_state
|
||||
typedef enum {
|
||||
TIM_OutputNState_Disable = 0, ///< Output Compare N Disable
|
||||
TIM_OutputNState_Enable = TIM_CCER_CC1NEN ///< Output Compare N Enable
|
||||
} TIMOUTPUTNSTATE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Capture_Compare_state
|
||||
/// @anchor TIM_Capture_Compare_state
|
||||
typedef enum {
|
||||
TIM_CCx_Disable = 0, ///< Capture/Compare Enable
|
||||
TIM_CCx_Enable = TIM_CCER_CC1EN ///< Capture/Compare Enable
|
||||
} TIMCCxE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Capture_Compare_N_state
|
||||
/// @anchor TIM_Capture_Compare_N_state
|
||||
typedef enum {
|
||||
TIM_CCxN_Disable = 0, ///< Capture/Compare N Enable
|
||||
TIM_CCxN_Enable = TIM_CCER_CC1NEN ///< Capture/Compare N Enable
|
||||
} TIMCCxNE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Break_Input_enable_disable
|
||||
/// @anchor Break_Input_enable_disable
|
||||
typedef enum {
|
||||
TIM_Break_Disable = 0, ///< Break inputs (BRK and CSS clock failure event) disabled
|
||||
TIM_Break_Enable = TIM_BDTR_BKEN ///< Break inputs (BRK and CSS clock failure event) enabled
|
||||
} TIMBKE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief Break_Polarity
|
||||
/// @anchor Break_Polarity
|
||||
typedef enum {
|
||||
TIM_BreakPolarity_Low = 0, ///< Break input BRK is active low
|
||||
TIM_BreakPolarity_High = TIM_BDTR_BKP ///< Break input BRK is active high
|
||||
} TIMBKP_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_AOE_Bit_Set_Reset
|
||||
/// @anchor TIM_AOE_Bit_Set_Reset
|
||||
typedef enum {
|
||||
TIM_AutomaticOutput_Disable = 0, ///< MOE can be set only by software.
|
||||
TIM_AutomaticOutput_Enable = TIM_BDTR_AOEN ///< MOE can be set by software or automatically at the next
|
||||
///< update event (if the break input is not be active).
|
||||
} TIMAOE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_DOE_Bit_Set_Reset
|
||||
/// @anchor TIM_DOE_Bit_Set_Reset
|
||||
typedef enum {
|
||||
TIM_DirectOutput_Disable = 0, ///< Direct output disable, output waiting for dead time
|
||||
TIM_DirectOutput_Enable = TIM_BDTR_DOEN ///< Direct output enable, no longer waiting for output after dead time
|
||||
} TIMDOE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief OSSI_Off_State_Selection_for_Idle_mode_state
|
||||
/// @anchor OSSI_Off_State_Selection_for_Idle_mode_state
|
||||
typedef enum {
|
||||
TIM_OSSIState_Disable = 0, ///< When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
|
||||
TIM_OSSIState_Enable = TIM_BDTR_OSSI ///< When inactive, OC/OCN outputs are forced first with their idle level
|
||||
///< as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1).
|
||||
} TIMOSSI_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief OSSR_Off_State_Selection_for_Run_mode_state
|
||||
/// @anchor OSSR_Off_State_Selection_for_Run_mode_state
|
||||
typedef enum {
|
||||
TIM_OSSRState_Disable = 0, ///< When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
|
||||
TIM_OSSRState_Enable = TIM_BDTR_OSSR ///< When inactive, OC/OCN outputs are enabled with their inactive level
|
||||
///< as soon as CCxE=1 or CCxNE=1. Then, OC/OCN enable output signal=1.
|
||||
} TIMOSSR_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_Idle_State
|
||||
/// @anchor TIM_Output_Compare_Idle_State
|
||||
typedef enum {
|
||||
TIM_OCIdleState_Reset = 0, ///< OCn=0 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4)
|
||||
TIM_OCIdleState_Set = TIM_CR2_OIS1 ///< OCn=1 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4)
|
||||
} TIMOIS_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_N_Idle_State
|
||||
/// @anchor TIM_Output_Compare_N_Idle_State
|
||||
typedef enum {
|
||||
TIM_OCNIdleState_Reset = 0, ///< OCnN=0 after a dead-time when MOE=0.(n= 0 : 4)
|
||||
TIM_OCNIdleState_Set = TIM_CR2_OIS1N ///< OCnN=1 after a dead-time when MOE=0.(n= 0 : 4)
|
||||
} TIMOISN_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Input_Capture_Selection
|
||||
/// @anchor TIM_Input_Capture_Selection
|
||||
typedef enum {
|
||||
TIM_ICSelection_DirectTI = TIM_CCMR1_CC1S_DIRECTTI,
|
||||
TIM_ICSelection_IndirectTI = TIM_CCMR1_CC1S_INDIRECTTI,
|
||||
TIM_ICSelection_TRC = TIM_CCMR1_CC1S_TRC ///< TIM Input is selected to be connected to TRC.
|
||||
} TIMICSEL_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Input_Capture_Prescaler
|
||||
/// @anchor TIM_Input_Capture_Prescaler
|
||||
typedef enum {
|
||||
TIM_ICPSC_DIV1 = 0x0000, ///< no prescaler
|
||||
TIM_ICPSC_DIV2 = 0x0004, ///< capture is done once every 2 events
|
||||
TIM_ICPSC_DIV4 = 0x0008, ///< capture is done once every 4 events
|
||||
TIM_ICPSC_DIV8 = 0x000C ///< capture is done once every 8 events
|
||||
} TIMICPSC_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Input_Capture_Polarity
|
||||
/// @anchor TIM_Input_Capture_Polarity
|
||||
typedef enum {
|
||||
TIM_ICPolarity_Rising = 0, ///< IC Rising edge
|
||||
TIM_ICPolarity_Falling = TIM_CCER_CC1P, ///< IC Falling edge
|
||||
TIM_ICPolarity_BothEdge = TIM_CCER_CC1P | TIM_CCER_CC1NP
|
||||
} TIMICP_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_External_Trigger_Polarity
|
||||
/// @anchor TIM_External_Trigger_Polarity
|
||||
typedef enum {
|
||||
TIM_ExtTRGPolarity_NonInverted = 0, ///< Active high or rising edge active
|
||||
TIM_ExtTRGPolarity_Inverted = TIM_SMCR_ETP ///< Active low or falling edge active
|
||||
} TIMETP_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Prescaler_Reload_Mode
|
||||
/// @anchor TIM_Prescaler_Reload_Mode
|
||||
typedef enum {
|
||||
TIM_PSCReloadMode_Update = 0, ///< The Prescaler is loaded at the update event
|
||||
TIM_PSCReloadMode_Immediate = TIM_EGR_UG ///< The Prescaler is loaded immediately
|
||||
} TIMUG_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Encoder_Mode
|
||||
/// @anchor TIM_Encoder_Mode
|
||||
typedef enum {
|
||||
TIM_EncoderMode_TI1 = TIM_SMCR_SMS_ENCODER1, ///< Counter counts on TI1FP1 edge depending on TI2FP2 level.
|
||||
TIM_EncoderMode_TI2 = TIM_SMCR_SMS_ENCODER2, ///< Counter counts on TI2FP2 edge depending on TI1FP1 level.
|
||||
TIM_EncoderMode_TI12 = TIM_SMCR_SMS_ENCODER3 ///< Counter counts on both TI1FP1 and TI2FP2 edges depending
|
||||
///< on the level of the other input.
|
||||
} TIMSMSENCODER_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Update_Source
|
||||
/// @anchor TIM_Update_Source
|
||||
typedef enum {
|
||||
TIM_UpdateSource_Global = 0, ///< Source of update is counter overflow/underflow.
|
||||
TIM_UpdateSource_Regular = TIM_CR1_URS ///< Source of update is the counter overflow/underflow
|
||||
///< or the setting of UG bit, or an update generation
|
||||
///< through the slave mode controller.
|
||||
} TIMURS_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_Preload_State
|
||||
/// @anchor TIM_Output_Compare_Preload_State
|
||||
typedef enum {
|
||||
TIM_OCPreload_Disable = 0, ///< TIM output compare preload disable
|
||||
TIM_OCPreload_Enable = TIM_CCMR1_OC1PEN ///< TIM output compare preload enable
|
||||
} TIMOCPE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_Fast_State
|
||||
/// @anchor TIM_Output_Compare_Fast_State
|
||||
typedef enum {
|
||||
TIM_OCFast_Disable = 0, ///< TIM output compare fast disable
|
||||
TIM_OCFast_Enable = TIM_CCMR1_OC1FEN, ///< TIM output compare fast enable
|
||||
} TIMOCFE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Output_Compare_Clear_State
|
||||
/// @anchor TIM_Output_Compare_Clear_State
|
||||
typedef enum {
|
||||
TIM_OCClear_Disable = 0, ///< TIM Output clear disable
|
||||
TIM_OCClear_Enable = TIM_CCMR1_OC1CEN ///< TIM Output clear enable
|
||||
} TIMOCCE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Master_Slave_Mode
|
||||
/// @anchor TIM_Master_Slave_Mode
|
||||
typedef enum {
|
||||
TIM_MasterSlaveMode_Disable = 0, ///< No action
|
||||
TIM_MasterSlaveMode_Enable = TIM_SMCR_MSM ///< synchronization between the current timer and its slaves (through TRIG)
|
||||
} TIMMSM_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_interrupt_sources
|
||||
/// @anchor TIM_Master_Slave_Mode
|
||||
typedef enum {
|
||||
TIM_IT_Update = TIM_DIER_UI, ///< TIM update Interrupt source
|
||||
TIM_IT_CC1 = TIM_DIER_CC1I, ///< TIM Capture Compare 1 Interrupt source
|
||||
TIM_IT_CC2 = TIM_DIER_CC2I, ///< TIM Capture Compare 2 Interrupt source
|
||||
TIM_IT_CC3 = TIM_DIER_CC3I, ///< TIM Capture Compare 3 Interrupt source
|
||||
TIM_IT_CC4 = TIM_DIER_CC4I, ///< TIM Capture Compare 4 Interrupt source
|
||||
TIM_IT_COM = TIM_DIER_COMI, ///< TIM Commutation Interrupt source
|
||||
TIM_IT_Trigger = TIM_DIER_TI, ///< TIM Trigger Interrupt source
|
||||
TIM_IT_Break = TIM_DIER_BI ///< TIM Break Interrupt source
|
||||
, TIM_IT_CC5 = TIM_DIER_CC5I ///< TIM Capture Compare 5 Interrupt source
|
||||
} TIMIT_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_Flags
|
||||
/// @anchor TIM_Flags
|
||||
typedef enum {
|
||||
TIM_FLAG_Update = TIM_SR_UI, ///< TIM update Flag
|
||||
TIM_FLAG_CC1 = TIM_SR_CC1I, ///< TIM Capture Compare 1 Flag
|
||||
TIM_FLAG_CC2 = TIM_SR_CC2I, ///< TIM Capture Compare 2 Flag
|
||||
TIM_FLAG_CC3 = TIM_SR_CC3I, ///< TIM Capture Compare 3 Flag
|
||||
TIM_FLAG_CC4 = TIM_SR_CC4I, ///< TIM Capture Compare 4 Flag
|
||||
TIM_FLAG_COM = TIM_SR_COMI, ///< TIM Commutation Flag
|
||||
TIM_FLAG_Trigger = TIM_SR_TI, ///< TIM Trigger Flag
|
||||
TIM_FLAG_Break = TIM_SR_BI, ///< TIM Break Flag
|
||||
TIM_FLAG_CC1OF = TIM_SR_CC1O, ///< TIM Capture Compare 1 overcapture Flag
|
||||
TIM_FLAG_CC2OF = TIM_SR_CC2O, ///< TIM Capture Compare 2 overcapture Flag
|
||||
TIM_FLAG_CC3OF = TIM_SR_CC3O, ///< TIM Capture Compare 3 overcapture Flag
|
||||
TIM_FLAG_CC4OF = TIM_SR_CC4O ///< TIM Capture Compare 4 overcapture Flag
|
||||
, TIM_FLAG_CC5 = TIM_SR_CC5I ///< TIM Capture Compare 5 Flag
|
||||
} TIMFLAG_Typedef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_DMA_sources
|
||||
/// @anchor TIM_DMA_sources
|
||||
typedef enum {
|
||||
TIM_DMA_Update = TIM_DIER_UD, ///< TIM update Interrupt source
|
||||
TIM_DMA_CC1 = TIM_DIER_CC1D, ///< TIM Capture Compare 1 DMA source
|
||||
TIM_DMA_CC2 = TIM_DIER_CC2D, ///< TIM Capture Compare 2 DMA source
|
||||
TIM_DMA_CC3 = TIM_DIER_CC3D, ///< TIM Capture Compare 3 DMA source
|
||||
TIM_DMA_CC4 = TIM_DIER_CC4D, ///< TIM Capture Compare 4 DMA source
|
||||
TIM_DMA_COM = TIM_DIER_COMD, ///< TIM Commutation DMA source
|
||||
TIM_DMA_Trigger = TIM_DIER_TD ///< TIM Trigger DMA source
|
||||
} TIMDMASRC_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_DMA_Base_address
|
||||
/// @anchor TIM_DMA_Base_address
|
||||
typedef enum {
|
||||
TIM_DMABase_CR1 = 0x0000,
|
||||
TIM_DMABase_CR2 = 0x0001,
|
||||
TIM_DMABase_SMCR = 0x0002,
|
||||
TIM_DMABase_DIER = 0x0003,
|
||||
TIM_DMABase_SR = 0x0004,
|
||||
TIM_DMABase_EGR = 0x0005,
|
||||
TIM_DMABase_CCMR1 = 0x0006,
|
||||
TIM_DMABase_CCMR2 = 0x0007,
|
||||
TIM_DMABase_CCER = 0x0008,
|
||||
TIM_DMABase_CNT = 0x0009,
|
||||
TIM_DMABase_PSC = 0x000A,
|
||||
TIM_DMABase_ARR = 0x000B,
|
||||
TIM_DMABase_RCR = 0x000C,
|
||||
TIM_DMABase_CCR1 = 0x000D,
|
||||
TIM_DMABase_CCR2 = 0x000E,
|
||||
TIM_DMABase_CCR3 = 0x000F,
|
||||
TIM_DMABase_CCR4 = 0x0010,
|
||||
TIM_DMABase_BDTR = 0x0011,
|
||||
TIM_DMABase_DCR = 0x0012
|
||||
} TIMDMABASE_Typedef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM_DMA_Burst_Length
|
||||
/// @anchor TIM_DMA_Burst_Length
|
||||
typedef enum {
|
||||
TIM_DMABurstLength_1Byte = 0x0000,
|
||||
TIM_DMABurstLength_2Bytes = 0x0100,
|
||||
TIM_DMABurstLength_3Bytes = 0x0200,
|
||||
TIM_DMABurstLength_4Bytes = 0x0300,
|
||||
TIM_DMABurstLength_5Bytes = 0x0400,
|
||||
TIM_DMABurstLength_6Bytes = 0x0500,
|
||||
TIM_DMABurstLength_7Bytes = 0x0600,
|
||||
TIM_DMABurstLength_8Bytes = 0x0700,
|
||||
TIM_DMABurstLength_9Bytes = 0x0800,
|
||||
TIM_DMABurstLength_10Bytes = 0x0900,
|
||||
TIM_DMABurstLength_11Bytes = 0x0A00,
|
||||
TIM_DMABurstLength_12Bytes = 0x0B00,
|
||||
TIM_DMABurstLength_13Bytes = 0x0C00,
|
||||
TIM_DMABurstLength_14Bytes = 0x0D00,
|
||||
TIM_DMABurstLength_15Bytes = 0x0E00,
|
||||
TIM_DMABurstLength_16Bytes = 0x0F00,
|
||||
TIM_DMABurstLength_17Bytes = 0x1000,
|
||||
TIM_DMABurstLength_18Bytes = 0x1100
|
||||
} TIMDMABURSTLENGTH_Typedef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM Time Base Init structure definition
|
||||
/// @note This structure is used with all tim.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
u16 TIM_Prescaler; ///< Specifies the prescaler value used to divide the TIM clock.
|
||||
///< This parameter can be a number between 0x0000 and 0xFFFF
|
||||
TIMCOUNTMODE_Typedef TIM_CounterMode; ///< Specifies the counter mode.
|
||||
///< This parameter can be a value of @ref TIM_Counter_Mode
|
||||
u32 TIM_Period; ///< Specifies the period value to be loaded into the active
|
||||
///< Auto-Reload Register at the next update event.
|
||||
///< This parameter must be a number between 0x0000 and 0xFFFF/0xFFFFFFFF.
|
||||
///< @note 0xFFFFFFFF is valid only for MM32 32bit Timers: eg.TIM2 or TIM5.
|
||||
TIMCKD_TypeDef TIM_ClockDivision; ///< Specifies the clock division.
|
||||
///< This parameter can be a value of @ref TIM_Clock_Division_CKD
|
||||
u8 TIM_RepetitionCounter; ///< Specifies the repetition counter value. Each time the RCR downcounter
|
||||
///< reaches zero, an update event is generated and counting restarts
|
||||
///< from the RCR value (N).
|
||||
///< This means in PWM mode that (N+1) corresponds to:
|
||||
///< - the number of PWM periods in edge-aligned mode
|
||||
///< - the number of half PWM period in center-aligned mode
|
||||
///< This parameter must be a number between 0x00 and 0xFF.
|
||||
///< @note This parameter is valid only for TIM1 and TIM8.
|
||||
} TIM_TimeBaseInitTypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM Output Compare Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
TIMOCMODE_Typedef TIM_OCMode; ///< Specifies the TIM mode.
|
||||
///< This parameter can be a value of TIM_Output_Compare_and_PWM_modes
|
||||
TIMOUTPUTSTATE_Typedef TIM_OutputState; ///< Specifies the TIM Output Compare state.
|
||||
///< This parameter can be a value of TIM_Output_Compare_state
|
||||
TIMOUTPUTNSTATE_Typedef TIM_OutputNState; ///< Specifies the TIM complementary Output Compare state.
|
||||
///< This parameter can be a value of TIM_Output_Compare_N_state
|
||||
///< @note This parameter is valid only for TIM1 and TIM8.
|
||||
u32 TIM_Pulse; ///< Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||
///< This parameter can be a number between 0x0000 and 0xFFFF/0xFFFFFFFF
|
||||
///< @note 0xFFFFFFFF is valid only for MM32 32bit Timers: eg.TIM2 or TIM5.
|
||||
TIMCCxP_Typedef TIM_OCPolarity; ///< Specifies the output polarity.
|
||||
///< This parameter can be a value of @ref TIM_Output_Compare_Polarity
|
||||
TIMCCxNP_Typedef TIM_OCNPolarity; ///< Specifies the complementary output polarity.
|
||||
///< This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
|
||||
///< @note This parameter is valid only for TIM1 and TIM8.
|
||||
TIMOIS_Typedef TIM_OCIdleState; ///< Specifies the TIM Output Compare pin state during Idle state.
|
||||
///< This parameter can be a value of @ref TIM_Output_Compare_Idle_State
|
||||
///< @note This parameter is valid only for TIM1 and TIM8.
|
||||
TIMOISN_Typedef TIM_OCNIdleState; ///< Specifies the TIM Output Compare pin state during Idle state.
|
||||
///< This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
|
||||
///< @note This parameter is valid only for TIM1 and TIM8.
|
||||
} TIM_OCInitTypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief TIM Input Capture Init structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
TIMCHx_Typedef TIM_Channel; ///< Specifies the TIM channel.
|
||||
///< This parameter can be a value of @ref TIM_Channel
|
||||
TIMICP_Typedef TIM_ICPolarity; ///< Specifies the active edge of the input signal.
|
||||
///< This parameter can be a value of @ref TIM_Input_Capture_Polarity
|
||||
TIMICSEL_Typedef TIM_ICSelection; ///< Specifies the input.
|
||||
///< This parameter can be a value of @ref TIM_Input_Capture_Selection
|
||||
TIMICPSC_Typedef TIM_ICPrescaler; ///< Specifies the Input Capture Prescaler.
|
||||
///< This parameter can be a value of @ref TIM_Input_Capture_Prescaler
|
||||
u16 TIM_ICFilter; ///< Specifies the input capture filter.
|
||||
///< This parameter can be a number between 0x0 and 0xF
|
||||
} TIM_ICInitTypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief BDTR structure definition
|
||||
/// @note This structure is used only with TIM1 and TIM8.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
TIMOSSR_Typedef TIM_OSSRState; ///< Specifies the Off-State selection used in Run mode.
|
||||
///< This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state
|
||||
TIMOSSI_Typedef TIM_OSSIState; ///< Specifies the Off-State used in Idle state.
|
||||
///< This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state
|
||||
TIMLOCKLEVEL_Typedef TIM_LOCKLevel; ///< Specifies the LOCK level parameters.
|
||||
///< This parameter can be a value of @ref Lock_level
|
||||
u16 TIM_DeadTime; ///< Specifies the delay time between the switching-off and
|
||||
///< the switching-on of the outputs.
|
||||
///< This parameter can be a number between 0x00 and 0xFF
|
||||
TIMBKE_Typedef TIM_Break; ///< Specifies whether the TIM Break input is enabled or not.
|
||||
///< This parameter can be a value of @ref Break_Input_enable_disable
|
||||
TIMBKP_Typedef TIM_BreakPolarity; ///< Specifies the TIM Break Input pin polarity.
|
||||
///< This parameter can be a value of @ref Break_Polarity
|
||||
TIMAOE_Typedef TIM_AutomaticOutput; ///< Specifies whether the TIM Automatic Output feature is enabled or not.
|
||||
///< This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset
|
||||
} TIM_BDTRInitTypeDef;
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup TIM_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_TIM_C_
|
||||
#define GLOBAL
|
||||
|
||||
static void TI1_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
|
||||
static void TI2_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
|
||||
static void TI3_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
|
||||
static void TI4_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
|
||||
|
||||
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup TIM_Exported_Functions
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//================= TimeBase management ======================================
|
||||
void TIM_DeInit(TIM_TypeDef* tim);
|
||||
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* init_struct);
|
||||
void TIM_TimeBaseInit(TIM_TypeDef* tim, TIM_TimeBaseInitTypeDef* init_struct);
|
||||
void TIM_PrescalerConfig(TIM_TypeDef* tim, u16 prescaler, TIMUG_Typedef reload_mode);
|
||||
void TIM_CounterModeConfig(TIM_TypeDef* tim, TIMCOUNTMODE_Typedef counter_mode);
|
||||
void TIM_SetCounter(TIM_TypeDef* tim, u32 counter);
|
||||
void TIM_SetAutoreload(TIM_TypeDef* tim, u16 auto_reload);
|
||||
void TIM_UpdateDisableConfig(TIM_TypeDef* tim, FunctionalState state);
|
||||
void TIM_UpdateRequestConfig(TIM_TypeDef* tim, TIMURS_Typedef source);
|
||||
void TIM_ARRPreloadConfig(TIM_TypeDef* tim, FunctionalState state);
|
||||
void TIM_SelectOnePulseMode(TIM_TypeDef* tim, TIMOPMODE_Typedef mode);
|
||||
void TIM_SetClockDivision(TIM_TypeDef* tim, TIMCKD_TypeDef clock_div);
|
||||
void TIM_Cmd(TIM_TypeDef* tim, FunctionalState state);
|
||||
|
||||
u32 TIM_GetCounter(TIM_TypeDef* tim);
|
||||
u16 TIM_GetPrescaler(TIM_TypeDef* tim);
|
||||
|
||||
//================= Advanced-control timers specific features ================
|
||||
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* init_struct);
|
||||
void TIM_BDTRConfig(TIM_TypeDef* tim, TIM_BDTRInitTypeDef* init_struct);
|
||||
void TIM_CtrlPWMOutputs(TIM_TypeDef* tim, FunctionalState state);
|
||||
|
||||
//================= Output Compare management ================================
|
||||
void TIM_OCStructInit(TIM_OCInitTypeDef* init_struct);
|
||||
void TIM_OC1Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
|
||||
void TIM_OC2Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
|
||||
void TIM_OC3Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
|
||||
void TIM_OC4Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
|
||||
void TIM_SelectOCxM(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMOCMODE_Typedef mode);
|
||||
void TIM_SetCompare1(TIM_TypeDef* tim, u32 compare);
|
||||
void TIM_SetCompare2(TIM_TypeDef* tim, u32 compare);
|
||||
void TIM_SetCompare3(TIM_TypeDef* tim, u32 compare);
|
||||
void TIM_SetCompare4(TIM_TypeDef* tim, u32 compare);
|
||||
void TIM_ForcedOC1Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
|
||||
void TIM_ForcedOC2Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
|
||||
void TIM_ForcedOC3Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
|
||||
void TIM_ForcedOC4Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
|
||||
void TIM_CCPreloadControl(TIM_TypeDef* tim, FunctionalState state);
|
||||
void TIM_OC1PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
|
||||
void TIM_OC2PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
|
||||
void TIM_OC3PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
|
||||
void TIM_OC4PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
|
||||
void TIM_OC1FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
|
||||
void TIM_OC2FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
|
||||
void TIM_OC3FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
|
||||
void TIM_OC4FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
|
||||
void TIM_ClearOC1Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
|
||||
void TIM_ClearOC2Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
|
||||
void TIM_ClearOC3Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
|
||||
void TIM_ClearOC4Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
|
||||
void TIM_OC1PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
|
||||
void TIM_OC1NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity);
|
||||
void TIM_OC2PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
|
||||
void TIM_OC2NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity);
|
||||
void TIM_OC3PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
|
||||
void TIM_OC3NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity);
|
||||
void TIM_OC4PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
|
||||
void TIM_CCxCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxE_Typedef ccx_en);
|
||||
void TIM_CCxNCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxNE_Typedef ccxn_en);
|
||||
void TIM_SelectCOM(TIM_TypeDef* tim, FunctionalState state);
|
||||
|
||||
//================= Input Capture management =================================
|
||||
void TIM_ICStructInit(TIM_ICInitTypeDef* init_struct);
|
||||
void TIM_ICInit(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct);
|
||||
void TIM_PWMIConfig(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct);
|
||||
void TIM_SetIC1Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
|
||||
void TIM_SetIC2Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
|
||||
void TIM_SetIC3Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
|
||||
void TIM_SetIC4Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
|
||||
|
||||
u32 TIM_GetCapture1(TIM_TypeDef* tim);
|
||||
u32 TIM_GetCapture2(TIM_TypeDef* tim);
|
||||
u32 TIM_GetCapture3(TIM_TypeDef* tim);
|
||||
u32 TIM_GetCapture4(TIM_TypeDef* tim);
|
||||
|
||||
//================= Interrupts, DMA and flags management =====================
|
||||
void TIM_ITConfig(TIM_TypeDef* tim, u32 it, FunctionalState state);//TIMIT_TypeDef
|
||||
void TIM_GenerateEvent(TIM_TypeDef* tim, TIMEGR_Typedef source);
|
||||
void TIM_ClearFlag(TIM_TypeDef* tim, TIMFLAG_Typedef flag);
|
||||
void TIM_ClearITPendingBit(TIM_TypeDef* tim, u32 it);//TIMIT_TypeDef
|
||||
void TIM_DMAConfig(TIM_TypeDef* tim, TIMDMABASE_Typedef dma_base, TIMDMABURSTLENGTH_Typedef length);
|
||||
void TIM_DMACmd(TIM_TypeDef* tim, TIMDMASRC_Typedef source, FunctionalState state);
|
||||
void TIM_SelectCCDMA(TIM_TypeDef* tim, FunctionalState state);
|
||||
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* tim, TIMFLAG_Typedef flag);
|
||||
ITStatus TIM_GetITStatus(TIM_TypeDef* tim, TIMIT_TypeDef it);
|
||||
|
||||
//================= Clocks management ========================================
|
||||
void TIM_InternalClockConfig(TIM_TypeDef* tim);
|
||||
void TIM_ITRxExternalClockConfig(TIM_TypeDef* tim, TIMTS_TypeDef source);
|
||||
void TIM_TIxExternalClockConfig(TIM_TypeDef* tim, TIM_TIEXTCLKSRC_Typedef source, TIMICP_Typedef polarity, u16 filter);
|
||||
void TIM_ETRClockMode1Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter);
|
||||
void TIM_ETRClockMode2Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter);
|
||||
|
||||
//================= Synchronization management ===============================
|
||||
void TIM_SelectInputTrigger(TIM_TypeDef* tim, TIMTS_TypeDef source);
|
||||
void TIM_SelectOutputTrigger(TIM_TypeDef* tim, TIMMMS_Typedef source);
|
||||
void TIM_SelectSlaveMode(TIM_TypeDef* tim, TIMSMSMODE_Typedef mode);
|
||||
void TIM_SelectMasterSlaveMode(TIM_TypeDef* tim, TIMMSM_Typedef mode);
|
||||
void TIM_ETRConfig(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter);
|
||||
|
||||
//================= Specific interface management ============================
|
||||
void TIM_EncoderInterfaceConfig(TIM_TypeDef* tim,
|
||||
TIMSMSENCODER_Typedef encoder_mode,
|
||||
TIMICP_Typedef ic1_polarity,
|
||||
TIMICP_Typedef iC2_polarity);
|
||||
void TIM_SelectHallSensor(TIM_TypeDef* tim, FunctionalState state);
|
||||
|
||||
//================= extend Channel IC management ==============================
|
||||
void TIM_SetIC1Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
|
||||
void TIM_SetIC2Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
|
||||
void TIM_SetIC3Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
|
||||
void TIM_SetIC4Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
|
||||
|
||||
#define exTIM_SetIC1Plority TIM_SetIC1Plority
|
||||
#define exTIM_SetIC2Plority TIM_SetIC2Plority
|
||||
#define exTIM_SetIC3Plority TIM_SetIC3Plority
|
||||
#define exTIM_SetIC4Plority TIM_SetIC4Plority
|
||||
//================= extend Channel 5 management ==============================
|
||||
|
||||
void TIM_SetCompare5(TIM_TypeDef* tim, u32 compare);
|
||||
void TIM_OC5Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
|
||||
void TIM_OC5PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
|
||||
void TIM_OC5PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
|
||||
void TIM_OC5FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
|
||||
void TIM_ClearOC5Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
|
||||
u32 TIM_GetCapture5(TIM_TypeDef* tim);
|
||||
|
||||
#define exTIM_SetCompare5 TIM_SetCompare5
|
||||
#define exTIM_OC5Init TIM_OC5Init
|
||||
#define exTIM_OC5PreloadConfig TIM_OC5PreloadConfig
|
||||
#define exTIM_OC5PolarityConfig TIM_OC5PolarityConfig
|
||||
#define exTIM_OC5FastConfig TIM_OC5FastConfig
|
||||
#define exTIM_ClearOC5Ref TIM_ClearOC5Ref
|
||||
#define exTIM_GetCapture5 TIM_GetCapture5
|
||||
|
||||
//============= extend Advanced-control timers specific features ==============
|
||||
void TIM_DirectOutput(TIM_TypeDef* tim, FunctionalState state);
|
||||
#define exTIM_DirectOutput TIM_DirectOutput
|
||||
void TIM_PWMShiftConfig(TIM_TypeDef* tim, u32 it, FunctionalState state);
|
||||
void TIM_SetCCR1FALL(TIM_TypeDef* tim, u32 shift);
|
||||
void TIM_SetCCR2FALL(TIM_TypeDef* tim, u32 shift);
|
||||
void TIM_SetCCR3FALL(TIM_TypeDef* tim, u32 shift);
|
||||
void TIM_SetCCR4FALL(TIM_TypeDef* tim, u32 shift);
|
||||
void TIM_SetCCR5FALL(TIM_TypeDef* tim, u32 shift);
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_TIM_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,211 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_uart.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UART
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_UART_H
|
||||
#define __HAL_UART_H
|
||||
|
||||
// Files includes
|
||||
#include "reg_uart.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
/////////////////////////////////////1///////////////////////////////////////////
|
||||
/// @defgroup UART_HAL
|
||||
/// @brief UART HAL modules
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UART_Exported_Types
|
||||
/// @{
|
||||
///
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief UART Word Length Enumerate definition
|
||||
/// @anchor UART_Word_Length
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
UART_WordLength_5b = 0U,
|
||||
UART_WordLength_6b = 1U << UART_CCR_CHAR_Pos,
|
||||
UART_WordLength_7b = 2U << UART_CCR_CHAR_Pos,
|
||||
UART_WordLength_8b = 3U << UART_CCR_CHAR_Pos
|
||||
} UART_WordLength_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief UART Stop Bits Enumerate definition
|
||||
/// @anchor UART_Stop_Bits
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
UART_StopBits_1 = 0U,
|
||||
UART_StopBits_2 = UART_CCR_SPB,
|
||||
|
||||
UART_StopBits_0_5 = UART_CCR_SPB1,
|
||||
UART_StopBits_1_5 = UART_CCR_SPB1 | UART_CCR_SPB0,
|
||||
} UART_Stop_Bits_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief UART Parity Enumerate definition
|
||||
/// @anchor UART_Parity
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
UART_Parity_No = 0U,
|
||||
UART_Parity_Even = UART_CCR_PEN | UART_CCR_PSEL,
|
||||
UART_Parity_Odd = UART_CCR_PEN
|
||||
} UART_Parity_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief UART Hardware Flow Control Enumerate definition
|
||||
/// @anchor UART_Hardware_Flow_Control
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
UART_HWFlowControl_None = 0U,
|
||||
|
||||
// UART_HWFlowControl_RTS = UART_GCR_AUTOFLOW,
|
||||
// UART_HWFlowControl_CTS = UART_GCR_AUTOFLOW,
|
||||
|
||||
UART_HWFlowControl_RTS_CTS = UART_GCR_AUTOFLOW
|
||||
} UART_HW_FLOWCONTROL_TypeDef;
|
||||
|
||||
typedef enum {
|
||||
UART_WakeUp_IdleLine = 0U, //
|
||||
UART_WakeUp_AddressMark = UART_CCR_WAKE
|
||||
} UART_WakeUp_TypeDef;
|
||||
|
||||
typedef enum {
|
||||
UART_9bit_Polarity_Low = 0U, //
|
||||
UART_9bit_Polarity_High = UART_CCR_B8POL
|
||||
} UART_9bit_Polarity_TypeDef;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief UART Auto BaudRate definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
Data_F8 = 0,
|
||||
Data_FE,
|
||||
ABRMODE_FALLING_TO_RISINGEDGE1BIT,
|
||||
ABRMODE_FALLING_TO_RISINGEDGE2BIT,
|
||||
ABRMODE_FALLING_TO_RISINGEDGE4BIT,
|
||||
ABRMODE_FALLING_TO_RISINGEDGE8BIT,
|
||||
ABRMODE_FALLING_TO_FALLINGEDGE2BIT,
|
||||
ABRMODE_FALLING_TO_FALLINGEDGE4BIT,
|
||||
ABRMODE_FALLING_TO_FALLINGEDGE8BIT,
|
||||
ABRMODE_STARTBIT,
|
||||
ABRMODE_VALUE0X55,
|
||||
ABRMODE_VALUE0x7F,
|
||||
ABRMODE_VALUE0X80,
|
||||
ABRMODE_VALUE0XF7,
|
||||
ABRMODE_VALUE0XF8 = Data_F8,
|
||||
ABRMODE_VALUE0XFE = Data_FE,
|
||||
ABRMODE_VALUE0XFF,
|
||||
} UART_AutoBaud_TypeDef;
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief UART Init Structure definition
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct {
|
||||
union {
|
||||
u32 BaudRate; ///< This member configures the UART communication baud rate.
|
||||
u32 UART_BaudRate;
|
||||
};
|
||||
union {
|
||||
UART_WordLength_TypeDef WordLength; ///< Specifies the number of data bits transmitted or received in a frame.
|
||||
u16 UART_WordLength;
|
||||
};
|
||||
union {
|
||||
UART_Stop_Bits_TypeDef StopBits; ///< Specifies the number of stop bits transmitted.
|
||||
u16 UART_StopBits;
|
||||
};
|
||||
union {
|
||||
UART_Parity_TypeDef Parity; ///< Specifies the parity mode.
|
||||
u16 UART_Parity;
|
||||
};
|
||||
union {
|
||||
u16 Mode; ///< Specifies wether the Receive or Transmit mode is
|
||||
u16 UART_Mode;
|
||||
};
|
||||
union {
|
||||
UART_HW_FLOWCONTROL_TypeDef HWFlowControl; ///< Specifies wether the hardware flow control mode is enabled or disabled.
|
||||
u16 UART_HardwareFlowControl;
|
||||
};
|
||||
} UART_InitTypeDef;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UART_Exported_Constants
|
||||
/// @{
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UART_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_UART_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UART_Exported_Functions
|
||||
/// @{
|
||||
void UART_DeInit(UART_TypeDef* uart);
|
||||
void UART_Init(UART_TypeDef* uart, UART_InitTypeDef* init_struct);
|
||||
void UART_StructInit(UART_InitTypeDef* init_struct);
|
||||
void UART_Cmd(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_ITConfig(UART_TypeDef* uart, u16 it, FunctionalState state);
|
||||
void UART_DMACmd(UART_TypeDef* uart, u16 dma_request, FunctionalState state);
|
||||
void UART_SendData(UART_TypeDef* uart, u16 Data);
|
||||
void UART_ClearITPendingBit(UART_TypeDef* uart, u16 it);
|
||||
|
||||
u16 UART_ReceiveData(UART_TypeDef* uart);
|
||||
FlagStatus UART_GetFlagStatus(UART_TypeDef* uart, u16 flag);
|
||||
|
||||
ITStatus UART_GetITStatus(UART_TypeDef* uart, u16 it);
|
||||
|
||||
void UART_WakeUpConfig(UART_TypeDef* uart, UART_WakeUp_TypeDef mode);
|
||||
void UART_ReceiverWakeUpCmd(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_SetRXAddress(UART_TypeDef* uart, u8 address);
|
||||
void UART_SetRXMASK(UART_TypeDef* uart, u8 address);
|
||||
void UART_Enable9bit(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_Set9bitLevel(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_Set9bitPolarity(UART_TypeDef* uart, UART_9bit_Polarity_TypeDef polarity);
|
||||
void UART_Set9bitAutomaticToggle(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_HalfDuplexCmd(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_SetGuardTime(UART_TypeDef* uart, u8 guard_time);
|
||||
void UART_SmartCardCmd(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_SmartCardNACKCmd(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_SendBreak(UART_TypeDef* uart);
|
||||
void UART_AutoBaudRateCmd(UART_TypeDef* uart, FunctionalState state);
|
||||
void UART_AutoBaudRateSet(UART_TypeDef* uart, UART_AutoBaud_TypeDef value, FunctionalState state);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_UART_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,71 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_uid.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UID
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_UID_H
|
||||
#define __HAL_UID_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_common.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UID_HAL
|
||||
/// @brief UID HAL modules
|
||||
/// @{
|
||||
|
||||
|
||||
/////////////////////////////////////1///////////////////////////////////////////
|
||||
/// @defgroup UID_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_UID_C_
|
||||
#define GLOBAL
|
||||
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
|
||||
|
||||
#endif
|
||||
GLOBAL u8 device_id_data[12];
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UID_Exported_Functions
|
||||
/// @{
|
||||
void GetChipUID(void);
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_UID_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
@@ -0,0 +1,89 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_ver.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UART
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_VER_H
|
||||
#define __HAL_VER_H
|
||||
|
||||
// Files includes
|
||||
#include "reg_common.h"
|
||||
#include "reg_dbg.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
/////////////////////////////////////1///////////////////////////////////////////
|
||||
/// @defgroup UART_HAL
|
||||
/// @brief UART HAL modules
|
||||
/// @{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UART_Exported_Types
|
||||
/// @{
|
||||
///
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief UART Word Length Enumerate definition
|
||||
/// @anchor UART_Word_Length
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UART_Exported_Constants
|
||||
/// @{
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UART_Exported_Variables
|
||||
/// @{
|
||||
#ifdef _HAL_VER_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup UART_Exported_Functions
|
||||
/// @{
|
||||
|
||||
u32 Get_MM32LibVersion(void);
|
||||
u32 Get_ChipsetREVID(void);
|
||||
u32 Get_ChipsetDEVID(void);
|
||||
u32 Get_ChipsetUIDw0(void);
|
||||
u32 Get_ChipsetUIDw1(void);
|
||||
u32 Get_ChipsetUIDw2(void);
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_VER_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -0,0 +1,90 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file hal_wwdg.h
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE WWDG
|
||||
/// FIRMWARE LIBRARY.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT O
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDER
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#ifndef __HAL_WWDG_H
|
||||
#define __HAL_WWDG_H
|
||||
|
||||
// Files includes
|
||||
#include "types.h"
|
||||
#include "reg_wwdg.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @addtogroup MM32_Hardware_Abstract_Layer
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup WWDG_HAL
|
||||
/// @brief WWDG HAL modules
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup WWDG_Exported_Types
|
||||
/// @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @brief WWDG_Prescaler
|
||||
/// @anchor WWDG_Prescaler
|
||||
|
||||
typedef enum {
|
||||
WWDG_Prescaler_1 = WWDG_CFGR_WDGTB_1,
|
||||
WWDG_Prescaler_2 = WWDG_CFGR_WDGTB_2,
|
||||
WWDG_Prescaler_4 = WWDG_CFGR_WDGTB_4,
|
||||
WWDG_Prescaler_8 = WWDG_CFGR_WDGTB_8
|
||||
} WWDG_Prescaler_Typedef;
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup WWDG_Exported_Variables
|
||||
/// @{
|
||||
|
||||
#ifdef _HAL_WWDG_C_
|
||||
|
||||
#define GLOBAL
|
||||
#else
|
||||
#define GLOBAL extern
|
||||
#endif
|
||||
|
||||
#undef GLOBAL
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @defgroup WWDG_Exported_Functions
|
||||
/// @{
|
||||
|
||||
void WWDG_DeInit(void);
|
||||
void WWDG_SetPrescaler(u32 prescaler);
|
||||
void WWDG_SetWindowValue(u8 window_value);
|
||||
void WWDG_EnableIT(void);
|
||||
void WWDG_SetCounter(u8 count);
|
||||
u32 WWDG_GetCounter(void);
|
||||
void WWDG_Enable(u8 count);
|
||||
FlagStatus WWDG_GetFlagStatus(void);
|
||||
void WWDG_ClearFlag(void);
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
/// @}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif // __HAL_WWDG_H
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
Reference in New Issue
Block a user