Add MM32 SDK and USB driver

Signed-off-by: zhangslice <1304224508@qq.com>

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c

@@ -0,0 +1,563 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_adc.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE ADC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_ADC_C_
+
+// Files includes
+#include "hal_adc.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup ADC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup ADC_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the adc peripheral registers to their default
+///         reset values.
+/// @param  adc: select the ADC peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_DeInit(ADC_TypeDef* adc)
+{
+
+    switch (*(vu32*)&adc) {
+
+        case ADC1_BASE:
+            exRCC_APB2PeriphReset(RCC_APB2ENR_ADC1);
+            break;
+        case ADC2_BASE:
+            exRCC_APB2PeriphReset(RCC_APB2ENR_ADC2);
+            break;
+        case ADC3_BASE:
+            exRCC_APB2PeriphReset(RCC_APB2ENR_ADC3);
+            break;
+        default:
+            break;
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the adc peripheral according to the specified parameters
+///         in the init_struct, Please use this function if you want to be
+///         compatible with older versions of the library.
+/// @param  adc: select the ADC peripheral.
+/// @param  init_struct: pointer to an ADC_InitTypeDef structure that contains
+///         the configuration information for the specified ADC peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_Init(ADC_TypeDef* adc, ADC_InitTypeDef* init_struct)
+{
+    adc->ADCFG &= ~(ADC_CFGR_PRE | ADC_CFGR_RSLTCTL);
+    adc->ADCFG |= (u32)(init_struct->ADC_PRESCARE) | init_struct->ADC_Resolution;
+
+    adc->ADCR &= ~(ADC_CR_ALIGN | ADC_CR_MODE | ADC_CR_TRGSEL);
+    adc->ADCR |= ((u32)init_struct->ADC_DataAlign) | init_struct->ADC_ExternalTrigConv | ((u32)init_struct->ADC_Mode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param  init_struct : pointer to an ADC_InitTypeDef structure which will be
+///         initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_StructInit(ADC_InitTypeDef* init_struct)
+{
+    init_struct->ADC_Resolution         = ADC_Resolution_12b;
+    init_struct->ADC_PRESCARE           = ADC_PCLK2_PRESCARE_2;
+    init_struct->ADC_Mode               = ADC_CR_IMM;                           //ADC_Mode_Single;
+    init_struct->ADC_ContinuousConvMode = DISABLE;                              // useless
+    init_struct->ADC_ExternalTrigConv   = ADC1_ExternalTrigConv_T1_CC1;
+    init_struct->ADC_DataAlign          = ADC_DataAlign_Right;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified ADC peripheral.
+/// @param  adc:select the ADC peripheral.
+/// @param  state: new state of the adc peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_Cmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ADCFG |= ADC_CFGR_ADEN) : (adc->ADCFG &= ~ADC_CFGR_ADEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified ADC DMA request.
+/// @param  adc: select the ADC peripheral.
+/// @param  state: New state of the selected ADC DMA transfer.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_DMACmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ADCR |= ADC_CR_DMAEN) : (adc->ADCR &= ~ADC_CR_DMAEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified ADC interrupts.
+/// @param  adc: select the ADC peripheral.
+/// @param  adc_interrupt: specifies the ADC interrupt sources to be enabled or disabled.
+/// @param  state: New state of the specified ADC interrupts.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ITConfig(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt, FunctionalState state)
+{
+    if (adc_interrupt == ADC_IT_EOC)
+        (state) ? (adc->ADCR |= ADC_CR_ADIE) : (adc->ADCR &= ~ADC_CR_ADIE);
+    else
+        (state) ? (adc->ADCR |= ADC_CR_ADWIE) : (adc->ADCR &= ~ADC_CR_ADWIE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the selected ADC software start conversion .
+/// @param  adc:  select the ADC peripheral.
+/// @param  state: New state of the selected ADC software start conversion.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ADCR |= ADC_CR_ADST) : (adc->ADCR &= ~ADC_CR_ADST);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Gets the selected ADC Software start conversion Status.
+/// @param  adc: select the ADC peripheral.
+/// @retval  The new state of ADC software start conversion (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* adc)
+{
+    return (((adc->ADCR & ADC_CR_ADST) != (u32)RESET) ? SET : RESET);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable the selected ADC channel and configure its sample time. Please
+///         use this function if you want to be compatible with older versions
+///         of the library.
+/// @param  adc:  select the ADC peripheral.
+/// @param  channel: the ADC channel to configure.
+/// @param  sample_time: the ADC Channel n Sample time to configure.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_RegularChannelConfig(ADC_TypeDef* adc, u32 channel, u8 rank, u32 sample_time)    //ADCSAM_TypeDef
+{
+
+    u32 tempchan;
+    sample_time = sample_time & 0xF;
+    tempchan = channel;
+    if(tempchan > 8) {
+        tempchan = tempchan & 0xF;
+        tempchan = tempchan - 8;
+        adc->SMPR2 &= ~(0xF << tempchan);
+        adc->SMPR2 |= (sample_time << tempchan);
+    }
+    else {
+        adc->SMPR1 &= ~(0xF << tempchan);
+        adc->SMPR1 |= (sample_time << tempchan);
+    }
+    adc->ADCHS &= ~(1 << channel);
+    adc->ADCHS |=  (1 << channel);
+
+    if (channel & ADC_CHSR_CHT)
+        ADC_TempSensorVrefintCmd(ENABLE);
+    else if (channel & ADC_CHSR_CHV)
+        ADC_TempSensorVrefintCmd(ENABLE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the adc conversion through external trigger.
+/// @param  adc: select the ADC peripheral.
+/// @param  state: New state of the selected ADC external trigger.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ADCR |= ADC_CR_TRGEN) : (adc->ADCR &= ~ADC_CR_TRGEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the adc external trigger for injected channels conversion.
+/// @param  adc:  select the ADC peripheral.
+/// @param  adc_external_trig_source: Configuring the external trigger source
+///         for the ADC.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ExternalTrigConvConfig(ADC_TypeDef* adc, EXTERTRIG_TypeDef adc_external_trig_source)
+{
+    adc->ADCR &= ~ADC_CR_TRGSEL;
+    adc->ADCR |=  adc_external_trig_source;
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the last adc conversion result data for regular channel.
+/// @param  adc: select the ADC peripheral.
+/// @retval The data conversion value.
+////////////////////////////////////////////////////////////////////////////////
+u16 ADC_GetConversionValue(ADC_TypeDef* adc)
+{
+    return (u16)adc->ADDATA;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the last ADC conversion result data in dual mode.
+/// @param  None
+/// @retval The Data conversion value.
+////////////////////////////////////////////////////////////////////////////////
+u32 ADC_GetDualModeConversionValue()
+{
+    return (*(vu32*)ADC1_BASE);
+}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the analog watchdog.
+/// @param  adc:  to select the ADC peripheral.
+/// @param  state: New state of the selected ADC analog watchdog.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ADCFG |= ADC_CFGR_ADWEN) : (adc->ADCFG &= ~ADC_CFGR_ADWEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the high and low thresholds of the analog watchdog.
+/// @param  adc:  select the ADC peripheral.
+/// @param  high_threshold: the ADC analog watchdog High threshold value.
+///         This parameter must be a 12bit value.
+/// @param  low_threshold: the ADC analog watchdog Low threshold value.
+///         This parameter must be a 12bit value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* adc, u16 high_threshold, u16 low_threshold)
+{
+    u32 tempThreshold;
+    tempThreshold = high_threshold;
+    adc->ADCMPR    = (tempThreshold << 16) | low_threshold;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the analog watchdog guarded single channel
+/// @param  adc: select the ADC peripheral.
+/// @param  channel: the ADC channel to configure for the analog watchdog.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel)
+{
+    adc->ADCR &= ~ADC_CR_CMPCH;
+    adc->ADCR |= (channel << ADC_CR_CMPCH_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the temperature sensor and Vrefint channel.
+/// @param  state: New state of the temperature sensor.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_TempSensorVrefintCmd(FunctionalState state)
+{
+    (state) ? (ADC1->ADCFG |=  (ADC_CFGR_TEN | ADC_CFGR_VEN))
+    : (ADC1->ADCFG &= ~(ADC_CFGR_TEN | ADC_CFGR_VEN));
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the temperature sensor .
+/// @param  state: New state of the temperature sensor.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_TempSensorCmd(FunctionalState state)
+{
+    ADC_TempSensorVrefintCmd(state);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Vrefint channel.
+/// @param  state: New state of the Vrefint channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_VrefintCmd(FunctionalState state)
+{
+    ADC_TempSensorVrefintCmd(state);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the temperature sensor and Vrefint channel.
+/// @param  chs: temperature sensor bit & Vrefint bit.
+/// @param  state: New state of the temperature sensor.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exADC_TempSensorVrefintCmd(u32 chs, FunctionalState state)
+{
+    if (chs & ADC_CHSR_CHT) {
+        (state) ? (ADC1->ADCFG |=  ADC_CFGR_TEN)
+        : (ADC1->ADCFG &= ~ADC_CFGR_TEN);
+    }
+    else if (chs & ADC_CHSR_CHV) {
+        (state) ? (ADC1->ADCFG |=  ADC_CFGR_VEN)
+        : (ADC1->ADCFG &= ~ADC_CFGR_VEN);
+    }
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified ADC flag is set or not.
+/// @param  adc: select the ADC peripheral.
+/// @param  adc_flag: specifies the flag to check.
+/// @retval The New state of adc_flag (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag)
+{
+    return (adc_flag == ADC_IT_EOC) ? ((adc->ADSTA & ADC_SR_ADIF) ? SET : RESET) : ((adc->ADSTA & ADC_SR_ADWIF) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the adc's pending flags.
+/// @param  adc: select the ADC peripheral.
+/// @param  adc_flag: specifies the flag to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ClearFlag(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag)
+{
+    (adc_flag == ADC_IT_EOC) ? (adc->ADSTA |= ADC_SR_ADIF) : (adc->ADSTA |= ADC_SR_ADWIF);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified adc's interrupt has occurred or not.
+/// @param  adc: select the ADC peripheral.
+/// @param  adc_interrupt: specifies the ADC interrupt source to check.
+/// @retval The new state of adc_interrupt (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus ADC_GetITStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt)
+{
+    return (adc_interrupt == ADC_IT_EOC) ? ((adc->ADSTA & ADC_SR_ADIF) ? SET : RESET) : ((adc->ADSTA & ADC_SR_ADWIF) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the adc's interrupt pending bits.
+/// @param  adc: select the ADC peripheral.
+/// @param  adc_interrupt: specifies the ADC interrupt pending bit to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ClearITPendingBit(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt)
+{
+    (adc_interrupt == ADC_IT_EOC) ? (adc->ADSTA |= ADC_SR_ADIF) : (adc->ADSTA |= ADC_SR_ADWIF);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the adc any channels conversion rank and channel.
+/// @param  adc: select the ADC peripheral.
+/// @param  rank: rank can be 0x0~0xf for the convert sequence.
+/// @param  adc_channel: Configuring the target channel to be converted.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ANY_CH_Config(ADC_TypeDef* adc, u8 rank, ADCCHANNEL_TypeDef adc_channel)
+{
+    rank = rank & 0xF;
+    if(rank < 8) {
+        adc->CHANY0 &= ~(0x0F << (4 * rank));
+        adc->CHANY0 |= (adc_channel << (4 * rank));
+    }
+    else {
+        adc->CHANY1 &= ~(0x0F << (4 * (rank - 8)));
+        adc->CHANY1 |= (adc_channel << (4 * (rank - 8)));
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the adc any channels conversion Max rank number
+/// @param  adc: select the ADC peripheral.
+/// @param  num: Configuring the max rank number for the ADC.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ANY_NUM_Config(ADC_TypeDef* adc, u8 num)
+{
+    if(num > 15) num = 15;                                                      //15 ? 16 need to be confirmed
+    adc->ANYCFG = num;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the ANY channel converter.
+/// @param  state: enable or disable the ANY channel converter mode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ANY_Cmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ANYCR |= ADC1_CHANY_CR_MDEN) : (adc->ANYCR &= ~ADC1_CHANY_CR_MDEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the selected ADC automatic injected group
+///         conversion after regular one.
+/// @param  adc: where x can be 1, 2 or 3 to select the ADC peripheral.
+/// @param  state: new state of the selected ADC auto injected conversion
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None
+////////////////////////////////////////////////////////////////////////////////
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ANYCR |= ADC_ANY_CR_JAUTO) : (adc->ANYCR &= ~ADC_ANY_CR_JAUTO);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the adc external trigger for injected channels conversion.
+/// @param  adc: where x can be 1, 2 or 3 to select the ADC peripheral.
+/// @param  ADC_ExtInjTrigSource: specifies the ADC trigger to start injected conversion.
+
+/// @retval None
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ExternalTrigInjectedConvertConfig(ADC_TypeDef* adc, EXTER_INJ_TRIG_TypeDef ADC_ExtInjTrigSource)
+{
+    u32 tmpreg = 0;
+    // Get the old register value
+    tmpreg = adc->ANYCR;
+    // Clear the old external event selection for injected group
+    tmpreg &= ADC_ANY_CR_JTRGSEL;
+    // Set the external event selection for injected group
+    tmpreg |= ADC_ExtInjTrigSource;
+    // Store the new register value
+    adc->ANYCR = tmpreg;
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the adc injected channels conversion through
+///         external trigger
+/// @param  adc: where x can be 1, 2 or 3 to select the ADC peripheral.
+/// @param  state: new state of the selected ADC external trigger start of
+///         injected conversion.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ANYCR |= ADC_ANY_CR_JTRGEN) : (adc->ANYCR &= ~ADC_ANY_CR_JTRGEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the selected ADC start of the injected
+///         channels conversion.
+/// @param  adc: where x can be 1, 2 or 3 to select the ADC peripheral.
+/// @param  state: new state of the selected ADC software start injected conversion.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None
+////////////////////////////////////////////////////////////////////////////////
+void ADC_InjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ANYCR |= ADC_ANY_CR_JCEN) : (adc->ANYCR &= ~ADC_ANY_CR_JCEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the selected ADC start of the injected
+///         channels conversion.
+/// @param  adc: where x can be 1, 2 or 3 to select the ADC peripheral.
+/// @param  NewState: new state of the selected ADC software start injected conversion.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None
+////////////////////////////////////////////////////////////////////////////////
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ANYCR |= ADC_ANY_CR_JADST) : (adc->ANYCR &= ~ADC_ANY_CR_JADST);
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable the selected ADC channel and configure its sample time. Please
+///         use this function if you want to be compatible with older versions
+///         of the library.
+/// @param  adc:  select the ADC peripheral.
+/// @param  event: the ADC external event to configure.
+/// @param  sample_time: the ADC Channel n Sample time to configure.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_InjectedSequencerConfig(ADC_TypeDef* adc, u32 event, u32 sample_time)
+{
+    adc->ANYCR &= ~(ADC_ANY_CR_JCEN | ADC_ANY_CR_CHANY_MDEN | ADC_ANY_CR_JTRGSEL_EXTI12 \
+                    | ADC_ANY_CR_JTRGSHIFT_512 | ADC_ANY_CR_JTRGEN);
+    adc->ANYCR |= (ADC_ANY_CR_JCEN | ADC_ANY_CR_CHANY_MDEN | sample_time | event | ADC_ANY_CR_JTRGEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Injection channel length configuration.
+/// @param  adc:  select the ADC peripheral.
+/// @param  Length: Injection channel length.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_LEN_TypeDef Length)
+{
+    adc->JSQR &= ~(0x03 << ADC_JSQR_JL_Pos);
+    adc->JSQR |= Length << ADC_JSQR_JL_Pos;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Injection channel  configuration.
+/// @param  adc  :   select the ADC peripheral.
+/// @param  off_addr :   Injection channel offset address.
+/// @param  channel: The sampling channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_InjectedSequencerChannelConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, ADCCHANNEL_TypeDef channel)
+{
+    adc->JSQR &= ~(0x1F << (off_addr >> 2) * 5);
+    adc->JSQR |= (channel <<  (off_addr >> 2) * 5);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Injection channel  converted value.
+/// @param  adc  :   select the ADC peripheral.
+/// @param  off_addr :   Injection channel offset address.
+/// @retval value.
+////////////////////////////////////////////////////////////////////////////////
+u16 ADC_GetInjectedConversionValue(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr)
+{
+    u32 value;
+    value = (*(vu32*)(*(vu32*)&adc + 0xB0 + off_addr)) - (*(vu32*)(*(vu32*)&adc + 0x7C + off_addr));
+
+    return (u16)value;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Injection current converted value.
+/// @param  adc  :   select the ADC peripheral.
+/// @retval value. Returns the last adc conversion result data for injected channel.
+////////////////////////////////////////////////////////////////////////////////
+u16 ADC_GetInjectedCurrentConvertedValue(ADC_TypeDef* adc)
+{
+    return (u16)adc->JDATA;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Injection channel compensation configuration.
+/// @param  adc         : select the ADC peripheral.
+/// @param  off_addr    : Injection channel.
+/// @param  value       : compensation value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_SetInjectedOffset(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, u16 value)
+{
+    *(vu32*)(*(vu32*)&adc + 0x7C + off_addr) = value;
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Get channel convertion result.
+/// @param  adc  :   select the ADC peripheral.
+/// @param  channel :   Converted channel.
+/// @retval The Data conversion value.
+////////////////////////////////////////////////////////////////////////////////
+u16 ADC_GetChannelConvertedValue(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel)
+{
+    return (u16)(*(vu32*) ((u32)adc + 0x18 + ((u32)channel << 2)));
+}
+
+/// @}
+
+/// @}
+
+/// @}
+

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c

@@ -0,0 +1,231 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_bkp.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE BKP FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_BKP_C_
+
+// Files includes
+#include "types.h"
+#include "hal_pwr.h"
+#include "hal_rcc.h"
+#include "hal_bkp.h"
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup BKP_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup BKP_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the BKP peripheral registers to their default reset
+///         values.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_DeInit(void)
+{
+    RCC_BackupResetCmd(ENABLE);
+    RCC_BackupResetCmd(DISABLE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the Tamper Pin active level.
+/// @param  tamper_pin_level: specifies the Tamper Pin active level.
+///         This parameter can be one of the following values:
+/// @arg    BKP_TamperPinLevel_High: Tamper pin active on high level
+/// @arg    BKP_TamperPinLevel_Low: Tamper pin active on low level
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_TamperPinLevelConfig(BKPTPAL_Typedef tamper_pin_level)
+{
+    BKP->CR = tamper_pin_level;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Tamper Pin activation.
+/// @param  state: new state of the Tamper Pin activation.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_TamperPinCmd(FunctionalState state)
+{
+    (state) ? SET_BIT(BKP->CR, BKP_CR_TPE) : CLEAR_BIT(BKP->CR, BKP_CR_TPE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Tamper Pin Interrupt.
+/// @param  state: new state of the Tamper Pin Interrupt.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_ITConfig(FunctionalState state)
+{
+    (state) ? SET_BIT(BKP->CSR, BKP_CSR_TPIE) : CLEAR_BIT(BKP->CSR, BKP_CSR_TPIE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Select the RTC output source to output on the Tamper pin.
+/// @param  rtc_output_source: specifies the RTC output source.
+///         This parameter can be one of the following values:
+/// @arg    BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
+/// @arg    BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
+///                                          divided by 64 on the Tamper pin.
+/// @arg    BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
+///                                     the Tamper pin.
+/// @arg    BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
+///                                      the Tamper pin.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_RTCOutputConfig(BKPRTCOUTPUTSRC_Typedef rtc_output_source)
+{
+    MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS, rtc_output_source);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets RTC Clock Calibration value.
+/// @param  calibration_value: specifies the RTC Clock Calibration value.
+///         This parameter must be a number between 0 and 0x7F.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_SetRTCCalibrationValue(u8 calibration_value)
+{
+    MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CAL, calibration_value);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the Tamper Pin Event flag is set or not.
+/// @param  None.
+/// @retval State: The new state of the Tamper Pin Event flag (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus BKP_GetFlagStatus(void)
+{
+    return ((BKP->CSR & BKP_CSR_TEF) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears Tamper Pin Event pending flag.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_ClearFlag(void)
+{
+    SET_BIT(BKP->CSR, BKP_CSR_CTE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the Tamper Pin Interrupt has occurred or not.
+/// @param  None.
+/// @retval State: The new state of the Tamper Pin Interrupt (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus BKP_GetITStatus(void)
+{
+    return ((BKP->CSR & BKP_CSR_TIF) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears Tamper Pin Interrupt pending bit.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_ClearITPendingBit(void)
+{
+    SET_BIT(BKP->CSR, BKP_CSR_CTI);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Writes user data to the specified data Backup Register.
+/// @param  bkp_dr: specifies the data Backup Register.
+///         This parameter can be BKP_DRx where x:[1, 10]
+/// @param  data: data to write
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_WriteBackupRegister(BKPDR_Typedef bkp_dr, u16 data)
+{
+    *(vu16*)(BKP_BASE + bkp_dr) = data;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reads data from the specified data Backup Register.
+/// @param  bkp_dr: specifies the data Backup Register.
+///         This parameter can be BKP_DRx where x:[1, 10]
+/// @retval data: The content of the specified data Backup Register
+////////////////////////////////////////////////////////////////////////////////
+u16 BKP_ReadBackupRegister(BKPDR_Typedef bkp_dr)
+{
+    return (*(vu16*)(BKP_BASE + bkp_dr));
+}
+////////////////////////////////////////////////////////////////////////////////
+//          Extended function interface
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the BKP peripheral, enable access to the backup
+///         registers.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exBKP_Init(void)
+{
+    RCC_APB1PeriphClockCmd(RCC_APB1ENR_PWR, ENABLE);
+    //COMMON_EnableIpClock(emCLOCK_PWR);
+    RCC_APB1PeriphClockCmd(RCC_APB1ENR_BKP, ENABLE);
+    //COMMON_EnableIpClock(emCLOCK_BKP);
+
+    RCC->BDCR |= RCC_BDCR_DBP;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Writes user data to the specified data Backup Register immediately.
+/// @param  bkp_dr: specifies the data Backup Register.
+///         This parameter can be BKP_DRx where x:[1, 10]
+/// @param  data: data to write
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exBKP_ImmWrite(BKPDR_Typedef bkp_dr, u16 dat)
+{
+    RCC->BDCR |= RCC_BDCR_DBP;
+    *(vu16*)(BKP_BASE + bkp_dr) = dat;
+    RCC->BDCR &= ~RCC_BDCR_DBP;
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reads data from the specified data Backup Register immediately.
+/// @param  bkp_dr: specifies the data Backup Register.
+///         This parameter can be BKP_DRx where x:[1, 10]
+/// @retval data: The content of the specified data Backup Register
+////////////////////////////////////////////////////////////////////////////////
+u16 exBKP_ImmRead(BKPDR_Typedef bkp_dr)
+{
+    u16 dat;
+    RCC->BDCR |= RCC_BDCR_DBP;
+    dat = (*(vu16*)(BKP_BASE + bkp_dr));
+    RCC->BDCR &= ~RCC_BDCR_DBP;
+    return dat;
+}
+
+/// @}
+
+/// @}
+
+/// @}

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c

@@ -0,0 +1,696 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_can.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE CAN FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define __HAL_CAN_C
+
+// Files includes
+#include "hal_can.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CAN_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CAN_Exported_Functions
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the CAN peripheral registers to their default reset
+/// values.
+/// @param  can: select the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_DeInit(CAN_TypeDef* can)
+{
+    exRCC_APB1PeriphReset(RCC_APB1ENR_CAN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief   Initializes the CAN peripheral according to the specified
+///          parameters in the CAN_InitStruct.
+/// @param   can: select the CAN peripheral.
+/// @param   CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
+///          contains the configuration information for the CAN peripheral.
+/// @retval  Constant indicates initialization succeed which will be
+///          CANINITFAILED or CANINITOK.
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Init(CAN_TypeDef* can, CAN_Basic_InitTypeDef* init_struct)
+{
+    u8 InitStatus = CANINITFAILED;
+
+    can->BTR0 = ((u32)(init_struct->SJW) << 6) | ((u32)(init_struct->BRP));
+    can->BTR1 = ((u32)(init_struct->SAM) << 7) | ((u32)(init_struct->TESG2) << 4) | ((u32)(init_struct->TESG1));
+
+    if (init_struct->GTS == ENABLE) {
+        can->CMR |= (u32)CAN_SleepMode;
+        InitStatus = CANINITFAILED;
+    }
+    else {
+        can->CMR &= ~(u32)CAN_SleepMode;
+        InitStatus = CANINITOK;
+    }
+
+    (init_struct->GTS == ENABLE) ? (can->CMR |= (u32)CAN_SleepMode) : (can->CMR &= ~(u32)CAN_SleepMode);
+
+    can->CDR |=
+        ((init_struct->CBP) << 6) | ((init_struct->RXINTEN) << 5) | ((init_struct->CLOSE_OPEN_CLK) << 3) | (init_struct->CDCLK);
+
+    return InitStatus;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the CAN_Basic reception filter according to the specified
+///         parameters in the basic_filter_init_struct.
+/// @param  basic_filter_init_struct: pointer to a CAN_Basic_FilterInitTypeDef
+///         structure that contains the configuration information.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* basic_filter_init_struct)
+{
+    // Filter Mode
+    CAN1->ACR = basic_filter_init_struct->CAN_FilterId;
+    CAN1->AMR = basic_filter_init_struct->CAN_FilterMaskId;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param  init_struct : pointer to a CAN_Basic_InitTypeDef structure which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_StructInit(CAN_Basic_InitTypeDef* init_struct)
+{
+    // Reset CAN_Basic init structure parameters values
+
+    // initialize the BRP member(where can be set with (0..63))
+    init_struct->BRP = 0x0;
+    // initialize the SJW member(where can be set with (0..3))
+    init_struct->SJW = 0x0;
+    // Initialize the TESG1 member(where can be set with (0..15))
+    init_struct->TESG1 = 0x0;
+    // Initialize the TESG2 member(where can be set with(0..7))
+    init_struct->TESG2 = 0x0;
+    // Initialize the SAM member(where can be set (SET or RESET))
+    init_struct->SAM = RESET;
+    // Initialize the GTS member to Sleep Mode(where can be set (ENABLE or
+    // DISABLE))
+    init_struct->GTS = DISABLE;
+    // Initialize the external pin CLKOUT frequence
+    init_struct->CDCLK = 0x0;
+    // Initialize the external clk is open or close
+    init_struct->CLOSE_OPEN_CLK = 0x0;
+    // Initialize the TX1 pin work as rx interrupt output
+    init_struct->RXINTEN = 0x0;
+    // Initialize the CBP of CDR register
+    init_struct->CBP = 0x0;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified CAN interrupts.
+/// @param  can:  select the CAN peripheral.
+/// @param  it: specifies the CAN interrupt sources to be enabled or
+///         disabled.
+///         This parameter can be: CAN_IT_OIE, CAN_IT_EIE, CAN_IT_TIE,
+///         CAN_IT_RIE.
+/// @param  state: new state of the CAN interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_ITConfig(CAN_TypeDef* can, u32 it, FunctionalState state)
+{
+    (state) ? (can->CR |= it) : (can->CR &= ~it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initiates and transmits a CAN frame message.
+/// @param  can:select the CAN peripheral.
+/// @param  TxMessage: pointer to a structure which contains CAN Id, CAN DLC and
+///         CAN data.
+/// @retval CANTXOK if the CAN driver transmits the message
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Transmit(CAN_TypeDef* can, CanBasicTxMsg* basic_transmit_message)
+{
+    can->TXID0 = (basic_transmit_message->IDH);
+    can->TXID1 = (basic_transmit_message->IDL << 5) | (basic_transmit_message->RTR << 4) | (basic_transmit_message->DLC);
+    if ((FunctionalState)(basic_transmit_message->RTR) != ENABLE) {
+        can->TXDR0 = basic_transmit_message->Data[0];
+        can->TXDR1 = basic_transmit_message->Data[1];
+        can->TXDR2 = basic_transmit_message->Data[2];
+        can->TXDR3 = basic_transmit_message->Data[3];
+        can->TXDR4 = basic_transmit_message->Data[4];
+        can->TXDR5 = basic_transmit_message->Data[5];
+        can->TXDR6 = basic_transmit_message->Data[6];
+        can->TXDR7 = basic_transmit_message->Data[7];
+    }
+
+    can->CMR = CAN_CMR_TR;
+
+    return (can->SR & 0x01);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Cancels a transmit request.
+/// @param  can: select the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_CancelTransmit(CAN_TypeDef* can)
+{
+    // abort transmission
+    can->CMR = CAN_AT;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Releases the specified receive FIFO.
+/// @param  can: select the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_FIFORelease(CAN_TypeDef* can)
+{
+    // Release FIFO
+    can->CMR |= (u32)CAN_RRB;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Receives a correct CAN frame.
+/// @param  can: select the CAN peripheral.
+/// @param  RxMessage: pointer to a structure receive frame which contains CAN
+///         Id,CAN DLC, CAN data and FMI number.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Receive(CAN_TypeDef* can, CanBasicRxMsg* basic_receive_message)
+{
+    u16 tempid;
+
+    basic_receive_message->RTR = (u8)((can->RXID1) >> 4) & 0x1;
+    basic_receive_message->DLC = (u8)((can->RXID1) & 0xf);
+    tempid              = (u16)(((can->RXID1) & 0xe0) >> 5);
+    tempid |= (u16)(can->RXID0 << 3);
+    basic_receive_message->ID      = tempid;
+    basic_receive_message->Data[0] = CAN1->RXDR0;
+    basic_receive_message->Data[1] = CAN1->RXDR1;
+    basic_receive_message->Data[2] = CAN1->RXDR2;
+    basic_receive_message->Data[3] = CAN1->RXDR3;
+    basic_receive_message->Data[4] = CAN1->RXDR4;
+    basic_receive_message->Data[5] = CAN1->RXDR5;
+    basic_receive_message->Data[6] = CAN1->RXDR6;
+    basic_receive_message->Data[7] = CAN1->RXDR7;
+    CAN_FIFORelease(can);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Select the Sleep mode or not in Basic workmode
+/// @param  state to go into the Sleep mode or go out
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Sleep(CAN_TypeDef* can)
+{
+    can->CMR |= CAN_SleepMode;
+    // At this step, sleep mode status
+    return (u8)((can->CMR & 0x10) == CAN_SleepMode) ? CANSLEEPOK : CANSLEEPFAILED;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Wakes the CAN up.
+/// @param  can: where x can be 1 to select the CAN peripheral.
+/// @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case.
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_WakeUp(CAN_TypeDef* can)
+{
+    // Wake up request
+    can->CMR &= ~CAN_SleepMode;
+    return (u8)((can->CMR & 0x01) == 0) ? CANWAKEUPOK : CANWAKEUPFAILED;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified CAN flag is set or not.
+/// @param  can: select the CAN peripheral.
+/// @param  flag: specifies the flag to check.
+///         This parameter can be one of the following values:
+///            @arg CAN_STATUS_RBS: Receive buffer status
+///            @arg CAN_STATUS_DOS: Data overflow status
+///            @arg CAN_STATUS_TBS: Transmit buffer status
+///            @arg CAN_STATUS_TCS: Transmit complete status
+///            @arg CAN_STATUS_RS: Receiving status
+///            @arg CAN_STATUS_TS: Transmiting status
+///            @arg CAN_STATUS_ES: Error status
+///            @arg CAN_STATUS_BS: bus status, close or open
+/// @retval The new state of CAN_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* can, u32 flag)
+{
+    return (FlagStatus)(((can->SR & flag) == flag) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified CAN interrupt has occurred or not.
+/// @param  can: where x can be 1 to select the CAN peripheral.
+/// @param  it: specifies the CAN interrupt source to check.
+///         This parameter can be one of the following values:
+///            @arg CAN_IT_RI: Receive FIFO not empty Interrupt
+///            @arg CAN_IT_TI: Transmit Interrupt
+///            @arg CAN_IT_EI: ERROR Interrupt
+///            @arg CAN_IT_DOI: Data voerflow Interrupt
+///            @arg CAN_IT_WUI: Wakeup Interrupt
+///            @arg CAN_IT_ALL: use it can enble all Interrupt
+/// @retval The current state of it (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus CAN_GetITStatus(CAN_TypeDef* can, u32 it)
+{
+    return (ITStatus)((can->IR & it) != it) ? RESET : SET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Select the can work as peli mode or basic mode
+/// @param  can: where x can be 1 or 2 to to select the CAN peripheral.
+/// @param  CAN_MODE: specifies the work mode:CAN_BASICMode,CAN_PELIMode
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Mode_Cmd(CAN_TypeDef* can, u32 mode)
+{
+    can->CDR |= mode;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Select the Reset mode or not
+/// @param  can: where x can be 1 or 2 to to select the CAN peripheral.
+/// @param  state to go into the Reset mode or go out
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_ResetMode_Cmd(CAN_TypeDef* can, FunctionalState state)
+{
+    (state == ENABLE) ? (can->CR |= CAN_ResetMode) : (can->CR &= ~CAN_ResetMode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clear the data overflow.
+/// @param  can: where x can be 1 or 2 to to select the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_ClearDataOverflow(CAN_TypeDef* can)
+{
+    can->CMR |= (u32)CAN_CDO;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the CAN's IT pending.
+/// @param  can: where x can be 1 or 2 to to select the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_ClearITPendingBit(CAN_TypeDef* can)
+{
+    u32 temp = 0;
+    temp     = temp;
+    temp     = can->IR;  // read this register clear all interrupt
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Select the Sleep mode or not in Peli workmode
+/// @param  state to go into the Sleep mode or go out
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_SleepMode_Cmd(FunctionalState state)
+{
+    (state == ENABLE) ? (CAN1_PELI->MOD |= CAN_SleepMode) : (CAN1_PELI->MOD &= ~CAN_SleepMode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each CAN1_PELI_InitStruct member with its default value.
+/// @param  init_struct : pointer to a CAN_Peli_InitTypeDef structure
+///         which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* init_struct)
+{
+    //--------------- Reset CAN_Peli init structure parameters values
+    //---------------
+    init_struct->BRP   = 0x0;      // initialize the BRP member(where can be set with (0..63))
+    init_struct->SJW   = 0x0;      // initialize the SJW member(where can be set with (0..3))
+    init_struct->TESG1 = 0x0;      // Initialize the TESG1 member(where can be set with (0..15))
+    init_struct->TESG2 = 0x0;      // Initialize the TESG2 member(where can be set with(0..7))
+    init_struct->SAM   = RESET;    // Initialize the SAM member(where can be set (SET or RESET))
+    init_struct->LOM   = DISABLE;  // Initialize the LOM member
+    init_struct->STM   = DISABLE;  // Initialize the STM member
+    init_struct->SM    = DISABLE;  // Initialize the SM member
+    init_struct->SRR   = DISABLE;
+    init_struct->EWLR  = 0x96;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the CAN_Peli peripheral according to the specified
+///         parameters in the init_struct.
+/// @param  init_struct: pointer to a CAN_Peli_InitTypeDef structure that
+///         contains the configuration information for the CAN peripheral in the peli workmode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_Init(CAN_Peli_InitTypeDef* init_struct)
+{
+    CAN1_PELI->BTR0 = ((u32)init_struct->SJW << 6) | ((u32)init_struct->BRP);
+    CAN1_PELI->BTR1 = ((u32)init_struct->SAM << 7) | ((u32)init_struct->TESG2 << 4) | ((u32)init_struct->TESG1);
+    if (init_struct->LOM == ENABLE)
+        CAN1_PELI->MOD |= (u32)CAN_ListenOnlyMode;
+    else
+        CAN1_PELI->MOD &= ~(u32)CAN_ListenOnlyMode;
+    if (init_struct->STM == ENABLE)
+        CAN1_PELI->MOD |= (u32)CAN_SeftTestMode;
+    else
+        CAN1_PELI->MOD &= ~(u32)CAN_SeftTestMode;
+    if (init_struct->SM == ENABLE)
+        CAN1_PELI->MOD |= (u32)CAN_SleepMode;
+    else
+        CAN1_PELI->MOD &= ~(u32)CAN_SleepMode;
+    CAN1_PELI->EWLR = (u32)init_struct->EWLR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the CAN_Peli reception filter according to the specified
+///         parameters in the peli_filter_init_struct.
+/// @param  peli_filter_init_struct: pointer to a CAN_Peli_FilterInitTypeDef
+///         structure that contains the configuration information.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct)
+{
+    (peli_filter_init_struct->AFM == CAN_FilterMode_Singal) ? (CAN1_PELI->MOD |= (u32)CAN_FilterMode_Singal)
+    : (CAN1_PELI->MOD &= (u32)CAN_FilterMode_Double);
+
+    CAN1_PELI->FF    = peli_filter_init_struct->CAN_FilterId0;
+    CAN1_PELI->ID0   = peli_filter_init_struct->CAN_FilterId1;
+    CAN1_PELI->ID1   = peli_filter_init_struct->CAN_FilterId2;
+    CAN1_PELI->DATA0 = peli_filter_init_struct->CAN_FilterId3;
+
+    CAN1_PELI->DATA1 = peli_filter_init_struct->CAN_FilterMaskId0;
+    CAN1_PELI->DATA2 = peli_filter_init_struct->CAN_FilterMaskId1;
+    CAN1_PELI->DATA3 = peli_filter_init_struct->CAN_FilterMaskId2;
+    CAN1_PELI->DATA4 = peli_filter_init_struct->CAN_FilterMaskId3;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each peli_filter_init_struct member with its default value.
+/// @param  peli_filter_init_struct: pointer to a CAN_InitTypeDef structure
+///         which ill be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct)
+{
+    peli_filter_init_struct->CAN_FilterId0 = 0;
+    peli_filter_init_struct->CAN_FilterId1 = 0;
+    peli_filter_init_struct->CAN_FilterId2 = 0;
+    peli_filter_init_struct->CAN_FilterId3 = 0;
+
+    peli_filter_init_struct->CAN_FilterMaskId0 = 0;
+    peli_filter_init_struct->CAN_FilterMaskId1 = 0;
+    peli_filter_init_struct->CAN_FilterMaskId2 = 0;
+    peli_filter_init_struct->CAN_FilterMaskId3 = 0;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initiates and transmits a CAN frame message.
+/// @param  TxMessage: pointer to a structure which contains CAN Id, CAN DLC and
+///         CAN data.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_Transmit(CanPeliTxMsg* peli_transmit_message)
+{
+    CAN1_PELI->FF = (peli_transmit_message->FF << 7) | (peli_transmit_message->RTR << 6) | (peli_transmit_message->DLC);
+    if (((FunctionalState)peli_transmit_message->FF) != ENABLE) {
+        CAN1_PELI->ID0 = (peli_transmit_message->IDHH);
+
+        CAN1_PELI->ID1 = (peli_transmit_message->IDHL & 0xE0);
+        if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
+            CAN1_PELI->DATA0 = peli_transmit_message->Data[0];
+            CAN1_PELI->DATA1 = peli_transmit_message->Data[1];
+            CAN1_PELI->DATA2 = peli_transmit_message->Data[2];
+            CAN1_PELI->DATA3 = peli_transmit_message->Data[3];
+            CAN1_PELI->DATA4 = peli_transmit_message->Data[4];
+            CAN1_PELI->DATA5 = peli_transmit_message->Data[5];
+            CAN1_PELI->DATA6 = peli_transmit_message->Data[6];
+            CAN1_PELI->DATA7 = peli_transmit_message->Data[7];
+        }
+    }
+    else {
+        CAN1_PELI->ID0   = peli_transmit_message->IDHH;
+        CAN1_PELI->ID1   = peli_transmit_message->IDHL;
+        CAN1_PELI->DATA0 = peli_transmit_message->IDLH;
+        CAN1_PELI->DATA1 = peli_transmit_message->IDLL;
+        if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
+            CAN1_PELI->DATA2 = peli_transmit_message->Data[0];
+            CAN1_PELI->DATA3 = peli_transmit_message->Data[1];
+            CAN1_PELI->DATA4 = peli_transmit_message->Data[2];
+            CAN1_PELI->DATA5 = peli_transmit_message->Data[3];
+            CAN1_PELI->DATA6 = peli_transmit_message->Data[4];
+            CAN1_PELI->DATA7 = peli_transmit_message->Data[5];
+            CAN1_PELI->DATA8 = peli_transmit_message->Data[6];
+            CAN1_PELI->DATA9 = peli_transmit_message->Data[7];
+        }
+    }
+
+    (CAN1_PELI->MOD & CAN_MOD_STM) ? (CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT) : (CAN1->CMR = CAN_CMR_TR | CAN_CMR_AT);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initiates and transmits a CAN frame message.
+/// @param  TxMessage: pointer to a structure which contains CAN Id, CAN DLC and
+///         CAN data.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_TransmitRepeat(CanPeliTxMsg* peli_transmit_message)
+{
+    CAN1_PELI->FF = (peli_transmit_message->FF << 7) | (peli_transmit_message->RTR << 6) | (peli_transmit_message->DLC);
+    if (((FunctionalState)peli_transmit_message->FF) != ENABLE) {
+        CAN1_PELI->ID0 = (peli_transmit_message->IDHH);
+
+        CAN1_PELI->ID1 = (peli_transmit_message->IDHL & 0xE0);
+        if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
+            CAN1_PELI->DATA0 = peli_transmit_message->Data[0];
+            CAN1_PELI->DATA1 = peli_transmit_message->Data[1];
+            CAN1_PELI->DATA2 = peli_transmit_message->Data[2];
+            CAN1_PELI->DATA3 = peli_transmit_message->Data[3];
+            CAN1_PELI->DATA4 = peli_transmit_message->Data[4];
+            CAN1_PELI->DATA5 = peli_transmit_message->Data[5];
+            CAN1_PELI->DATA6 = peli_transmit_message->Data[6];
+            CAN1_PELI->DATA7 = peli_transmit_message->Data[7];
+        }
+    }
+    else {
+        CAN1_PELI->ID0   = peli_transmit_message->IDHH;
+        CAN1_PELI->ID1   = peli_transmit_message->IDHL;
+        CAN1_PELI->DATA0 = peli_transmit_message->IDLH;
+        CAN1_PELI->DATA1 = peli_transmit_message->IDLL;
+        if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
+            CAN1_PELI->DATA2 = peli_transmit_message->Data[0];
+            CAN1_PELI->DATA3 = peli_transmit_message->Data[1];
+            CAN1_PELI->DATA4 = peli_transmit_message->Data[2];
+            CAN1_PELI->DATA5 = peli_transmit_message->Data[3];
+            CAN1_PELI->DATA6 = peli_transmit_message->Data[4];
+            CAN1_PELI->DATA7 = peli_transmit_message->Data[5];
+            CAN1_PELI->DATA8 = peli_transmit_message->Data[6];
+            CAN1_PELI->DATA9 = peli_transmit_message->Data[7];
+        }
+    }
+
+    (CAN1_PELI->MOD & CAN_MOD_STM) ? (CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT) : (CAN1->CMR = CAN_CMR_TR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Receives a correct CAN frame.
+/// @param  RxMessage: pointer to a structure receive frame which contains CAN
+///         Id,CAN DLC, CAN data and FMI number.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_Receive(CanPeliRxMsg* peli_receive_message)
+{
+    u32 tempid;
+    peli_receive_message->FF  = (CAN1_PELI->FF) >> 7;
+    peli_receive_message->RTR = ((CAN1_PELI->FF) >> 6) & 0x1;
+    peli_receive_message->DLC = (CAN1_PELI->FF) & 0xf;
+
+    if (((FunctionalState)peli_receive_message->FF) != ENABLE) {
+        tempid = (u32)(CAN1_PELI->ID1 >> 5);
+        tempid |= (u32)(CAN1_PELI->ID0 << 3);
+        peli_receive_message->ID      = tempid;
+        peli_receive_message->Data[0] = CAN1_PELI->DATA0;
+        peli_receive_message->Data[1] = CAN1_PELI->DATA1;
+        peli_receive_message->Data[2] = CAN1_PELI->DATA2;
+        peli_receive_message->Data[3] = CAN1_PELI->DATA3;
+        peli_receive_message->Data[4] = CAN1_PELI->DATA4;
+        peli_receive_message->Data[5] = CAN1_PELI->DATA5;
+        peli_receive_message->Data[6] = CAN1_PELI->DATA6;
+        peli_receive_message->Data[7] = CAN1_PELI->DATA7;
+    }
+    else {
+        tempid = (u32)((CAN1_PELI->DATA1 & 0xf8) >> 3);
+        tempid |= (u32)(CAN1_PELI->DATA0 << 5);
+        tempid |= (u32)(CAN1_PELI->ID1 << 13);
+        tempid |= (u32)(CAN1_PELI->ID0 << 21);
+        peli_receive_message->ID      = tempid;
+        peli_receive_message->Data[0] = CAN1_PELI->DATA2;
+        peli_receive_message->Data[1] = CAN1_PELI->DATA3;
+        peli_receive_message->Data[2] = CAN1_PELI->DATA4;
+        peli_receive_message->Data[3] = CAN1_PELI->DATA5;
+        peli_receive_message->Data[4] = CAN1_PELI->DATA6;
+        peli_receive_message->Data[5] = CAN1_PELI->DATA7;
+        peli_receive_message->Data[6] = CAN1_PELI->DATA8;
+        peli_receive_message->Data[7] = CAN1_PELI->DATA9;
+    }
+    CAN_FIFORelease(CAN1);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Get available current informatoin in receive FIFO only in Peli
+///         workmode.
+/// @retval The value in reg RMC
+////////////////////////////////////////////////////////////////////////////////
+u32 CAN_Peli_GetRxFIFOInfo(void)
+{
+    return CAN1_PELI->RMC;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the CAN's last error code (LEC).
+/// @retval Error code:
+///          - CAN_ERRORCODE_NoErr: No Error
+///          - CAN_ERRORCODE_StuffErr: Stuff Error
+///          - CAN_ERRORCODE_FormErr: Form Error
+///          - CAN_ERRORCODE_ACKErr : Acknowledgment Error
+///          - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
+///          - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
+///          - CAN_ERRORCODE_CRCErr: CRC Error
+///          - CAN_ERRORCODE_SoftwareSetErr: Software Set Error
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Peli_GetLastErrorCode(void)
+{
+    // Return the error code
+    return (u8)CAN1_PELI->ECC;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the CAN Receive Error Counter (REC).
+/// @note   In case of an error during reception, this counter is incremented
+///         by 1 or by 8 depending on the error condition as defined by the CAN
+///         standard. After every successful reception, the counter is
+///         decremented by 1 or reset to 120 if its value was higher than 128.
+///         When the counter value exceeds 127, the CAN controller enters the
+///         error passive state.
+/// @retval CAN Receive Error Counter.
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Peli_GetReceiveErrorCounter(void)
+{
+    // Return the Receive Error Counter
+    return (u8)(CAN1_PELI->RXERR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the LSB of the 9-bit can Transmit Error Counter(TEC).
+/// @retval LSB of the 8-bit CAN Transmit Error Counter.
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Peli_GetLSBTransmitErrorCounter(void)
+{
+    // Return the LSB of the 8-bit CAN Transmit Error Counter(TEC)
+    return (u8)(CAN1_PELI->TXERR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified CAN interrupts in peli workmode.
+/// @param  it: specifies the CAN interrupt sources to be enabled or
+///         disabled.
+///         This parameter can be:
+/// @arg    CAN_IT_RI: Receive FIFO not empty Interrupt
+/// @arg    CAN_IT_TI: Transmit Interrupt
+/// @arg    CAN_IT_EI: ERROR Interrupt
+/// @arg    CAN_IT_DOI: Data voerflow Interrupt
+/// @arg    CAN_IT_WUI: Wakeup Interrupt
+/// @arg    CAN_IT_EPI(only Peli): passive error Interrupt
+/// @arg    CAN_IT_ALI(only Peli): arbiter lose Interrupt
+/// @arg    CAN_IT_BEI(only Peli): bus error Interrupt
+/// @arg    CAN_IT_ALL: use it can enble all Interrupt
+/// @param  state: new state of the CAN interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_ITConfig(u32 it, FunctionalState state)
+{
+    (state) ? (CAN1_PELI->IER |= it) : (CAN1_PELI->IER &= ~it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified CAN interrupt has occurred or not.
+/// @param  it: specifies the CAN interrupt source to check.
+///         This parameter can be one of the following values:
+/// @arg    CAN_IT_RI: Receive FIFO not empty Interrupt
+/// @arg    CAN_IT_TI: Transmit Interrupt
+/// @arg    CAN_IT_EI: ERROR Interrupt
+/// @arg    CAN_IT_DOI: Data voerflow Interrupt
+/// @arg    CAN_IT_WUI: Wakeup Interrupt
+/// @arg    CAN_IT_EPI(only Peli): passive error Interrupt
+/// @arg    CAN_IT_ALI(only Peli): arbiter lose Interrupt
+/// @arg    CAN_IT_BEI(only Peli): bus error Interrupt
+/// @arg    CAN_IT_ALL: use it can enble all Interrupt
+/// @retval The current state of it (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus CAN_Peli_GetITStatus(u32 it)
+{
+    return (ITStatus)(((CAN1_PELI->IR & it) != it) ? RESET : SET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Config CAN_Peli_InitTypeDef baud parameter.
+/// @param  CAN_Peli_InitTypeDef: CAN struct.
+/// @param  src_clk: CAN module clock.
+/// @param  baud: specified baud.
+/// @retval The current state of it (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef* init_struct, u32 src_clk, u32 baud)
+{
+    u32 i, value = baud, record = 1;
+    u32 remain = 0, sumPrescaler = 0;
+    while ((baud == 0) || (src_clk == 0))
+        ;
+    sumPrescaler = src_clk / baud;
+    sumPrescaler = sumPrescaler / 2;
+    for (i = 25; i > 3; i--) {
+        remain = sumPrescaler - ((sumPrescaler / i) * i);
+        if (remain == 0) {
+            record = i;
+            break;
+        }
+        else {
+            if (remain < value) {
+                value  = remain;
+                record = i;
+            }
+        }
+    }
+    init_struct->SJW   = 0;
+    init_struct->BRP   = (sumPrescaler / record) - 1;
+    init_struct->TESG2 = (record - 3) / 3;
+    init_struct->TESG1 = (record - 3) - init_struct->TESG2;
+}
+
+/// @}
+
+/// @}
+
+/// @}
+
+
+

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c

@@ -0,0 +1,226 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_comp.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE COMP FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_COMP_C_
+
+// Files includes
+#include "hal_comp.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup COMP_HAL
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup COMP_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes COMP peripheral registers to their default reset
+///         values.
+/// @param  selection: the selected comparator.
+///         select the COMP peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_DeInit(COMP_Selection_TypeDef selection)
+{
+    *(vu32*)(COMP_BASE + selection) = 0;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the COMP peripheral according to the specified
+/// @param  selection: the selected comparator.
+///         select the COMP peripheral.
+/// @param  init_struct: pointer to an COMP_InitTypeDef structure that
+///         contains the configuration information for the specified COMP
+///         peripheral.
+///         - COMP_InvertingInput specifies the inverting input of COMP
+///         - COMP_NonInvertingInput specifies the non inverting input of COMP
+///         - COMP_Output connect COMP output to selected timer
+///           input (Input capture / Output Compare Reference Clear / Break
+///           Input)
+///         - COMP_BlankingSrce specifies the blanking source of COMP
+///         - COMP_OutputPol select output polarity
+///         - COMP_Hysteresis configures COMP hysteresis value
+///         - COMP_Mode configures COMP power mode
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_Init(COMP_Selection_TypeDef selection, COMP_InitTypeDef* init_struct)
+{
+    *(vu32*)(COMP_BASE + selection) =    init_struct->Invert     |
+                                         init_struct->NonInvert  |
+                                         init_struct->Output     |
+                                         init_struct->OutputPol  |
+                                         init_struct->BlankingSrce   |
+                                         init_struct->Hysteresis |
+                                         init_struct->Mode       |
+                                         init_struct->OFLT;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param  init_struct: pointer to an COMP_InitTypeDef structure which will
+///         be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_StructInit(COMP_InitTypeDef* init_struct)
+{
+
+    init_struct->Invert         = COMP_InvertingInput_IO1;
+    init_struct->NonInvert      = COMP_NonInvertingInput_IO1;
+    init_struct->Output         = COMP_Output_None;
+    init_struct->BlankingSrce   = COMP_BlankingSrce_None;
+    init_struct->OutputPol      = COMP_NonInverted;
+    init_struct->Hysteresis     = COMP_Hysteresis_No;
+    init_struct->Mode           = COMP_Mode_UltraLowPower;
+    init_struct->OFLT           = COMP_Filter_4_Period;                                                               ///< to adjust the speed/consumption.
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable or disable the COMP peripheral.
+/// @param  selection: the selected comparator.
+///         select the COMP peripheral.
+/// @param  NewState: new state of the COMP peripheral.
+///         This parameter can be: ENABLE or DISABLE.
+///         When enabled, the comparator compares the non inverting input with
+///         the inverting input and the comparison result is available on
+///         comparator output.
+///         When disabled, the comparator doesn't perform comparison and the
+///         output level is low.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_Cmd(COMP_Selection_TypeDef selection, FunctionalState state)
+{
+    (state) ? (*(vu32*)(COMP_BASE + selection) |=  COMP_CSR_EN) :
+    (*(vu32*)(COMP_BASE + selection) &= ~COMP_CSR_EN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Select CRV param.
+/// @param  crv_select: Select source for CRV.
+/// @param  crv_level: Set level for CRV.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_SetCrv(u8 crv_select, u8 crv_level)
+{
+    u32 temreg = 0;
+    temreg = COMP->CRV;
+    temreg &= ~COMP_CRV_MASK;
+    // Load config to CRV and enable
+    temreg |= crv_select | crv_level | (1 << 4);
+    COMP->CRV = temreg;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Close or Open the SW1 switch.
+/// @param  selection: the selected comparator.
+///         select the COMP peripheral.
+/// @param  state: new state of the COMP peripheral.
+///         This parameter can be: ENABLE or DISABLE.
+///         When enabled, the comparator compares the non inverting input with
+///         the inverting input and the comparison result is available on
+///         comparator output.
+///         When disabled, the comparator doesn't perform comparison and the
+///         output level is low.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_SwitchCmd(COMP_Selection_TypeDef selection, FunctionalState state)
+{
+    (state) ?
+    (*(vu32*)(COMP_BASE + selection) |=  COMP_CSR_COMPSW1) :
+    (*(vu32*)(COMP_BASE + selection) &= ~COMP_CSR_COMPSW1);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Return the output level (high or low) of the selected comparator.
+///         The output level depends on the selected polarity.
+///         If the polarity is not inverted:
+///           - Comparator output is low when the non-inverting input is at a
+///           lower voltage than the inverting input
+///           - Comparator output is high when the non-inverting input is at a
+///           higher voltage than the inverting input
+///         If the polarity is inverted:
+///           - Comparator output is high when the non-inverting input is at a
+///           lower voltage than the inverting input
+///           - Comparator output is low when the non-inverting input is at a
+///           higher voltage than the inverting input
+/// @param  comp: the selected comparator.
+///         select the COMP peripheral.
+/// @retval  The selected comparator output level: low or high.
+////////////////////////////////////////////////////////////////////////////////
+u32 COMP_GetOutputLevel(COMP_Selection_TypeDef selection)
+{
+    return (((*(vu32*)(COMP_BASE + selection) & COMP_CSR_STA) != 0) ?
+            COMP_OutputLevel_High :
+            COMP_OutputLevel_Low );
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Lock the selected comparator (COMP1/COMP2) configuration.
+/// @param  selection: the selected comparator.
+///         select the COMP peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_LockConfig(COMP_Selection_TypeDef selection)
+{
+    *(vu32*)(COMP_BASE + selection) |= COMP_CSR_LOCK;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable or disable the COMP register.
+/// @param  state: new state of the COMP peripheral.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exCOMP_CrvCmd(FunctionalState state)
+{
+    (state) ? (COMP->CRV |= COMP_CRV_EN_ENABLE) : (COMP->CRV &= ~COMP_CRV_EN_ENABLE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Select comparator external reference voltage.
+/// @param  selection: the selected external reference voltage.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exCOMP_SwitchCrv(u32 crv)
+{
+    COMP->CRV |= crv;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Select comparator external reference voltage source.
+/// @param  selection: the selected external reference voltage source.
+///         This parameter can be: COMP_CRV_SRC_AVDD or COMP_CRV_SRC_VREF.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exCOMP_CrvSrc(u32 src)
+{
+    COMP->CRV |= src;
+}
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c

@@ -0,0 +1,108 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_crc.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE CRC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_CRC_C_
+
+// Files includes
+#include "hal_crc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CRC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CRC_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Resets the CRC Data register (DR).
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CRC_ResetDR()
+{
+    CRC->CR = CRC_CR_RESET;
+}
+//#pragma optimize(0)
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Computes the 32-bit CRC of a given data word(32-bit).
+/// @param  Data: data word(32-bit) to compute its CRC
+/// @retval 32-bit CRC
+////////////////////////////////////////////////////////////////////////////////
+u32 CRC_CalcCRC(u32 data)
+{
+    CRC->DR = data;
+    return (CRC->DR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
+/// @param  buffer: pointer to the buffer containing the data to be computed
+/// @param  length: length of the buffer to be computed
+/// @retval 32-bit CRC
+////////////////////////////////////////////////////////////////////////////////
+u32 CRC_CalcBlockCRC(u32* buffer, u32 length)
+{
+    u32 i;
+    for (i = 0; i < length; i++) {
+        CRC->DR = buffer[i];
+    }
+    return (CRC->DR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the current CRC value.
+/// @param  None.
+/// @retval 32-bit CRC
+////////////////////////////////////////////////////////////////////////////////
+u32 CRC_GetCRC(void)
+{
+    return (CRC->DR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Stores a 8-bit data in the Independent Data(ID) register.
+/// @param  id_value: 8-bit value to be stored in the ID register
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CRC_SetIDRegister(u8 id_value)
+{
+    CRC->IDR = id_value;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the 8-bit data stored in the Independent Data(ID) register
+/// @param  None.
+/// @retval 8-bit value of the ID register
+////////////////////////////////////////////////////////////////////////////////
+u8 CRC_GetIDRegister()
+{
+    return (CRC->IDR);
+}
+
+/// @}
+
+/// @}
+
+/// @}
+
+

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c

@@ -0,0 +1,43 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_crs.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE CRS FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_CRS_C_
+
+// Files includes
+#include "hal_rcc.h"
+#include "hal_crs.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CRS_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CRS_Exported_Functions
+/// @{
+
+/// @}
+
+/// @}
+
+/// @}
+
+

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c

@@ -0,0 +1,184 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_dac.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE DAC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_DAC_C_
+
+// Files includes
+#include "hal_dac.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DAC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DAC_Exported_Functions
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the DAC peripheral registers to their default reset values.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_DeInit(void)
+{
+    exRCC_APB1PeriphReset(RCC_APB1ENR_DAC);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
+/// @param channel: the selected DAC channel.
+/// @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains the configuration information for the specified
+/// DAC channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_Init(emDACCH_TypeDef channel, DAC_InitTypeDef* init_struct)
+{
+    DAC->CR &= ~((DAC_CR_BOFF1 | DAC_CR_TEN1 | DAC_CR_TSEL1 | DAC_CR_WAVE1 | DAC_CR_MAMP1) << channel);
+    DAC->CR |= (((u32)(init_struct->DAC_Trigger) | (u32)(init_struct->DAC_WaveGeneration) |
+                 (u32)(init_struct->DAC_LFSRUnmask_TriangleAmplitude) | (u32)(init_struct->DAC_OutputBuffer))
+                << channel);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each DAC_InitStruct member with its default value.
+/// @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_StructInit(DAC_InitTypeDef* init_struct)
+{
+    init_struct->DAC_Trigger                      = DAC_Trigger_None;
+    init_struct->DAC_WaveGeneration               = DAC_WaveGeneration_None;
+    init_struct->DAC_LFSRUnmask_TriangleAmplitude = DAC_TriangleAmplitude_1;
+    init_struct->DAC_OutputBuffer                 = DAC_OutputBuffer_Enable;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified DAC channel.
+/// @param channel: the selected DAC channel.
+/// @param state: new state of the DAC channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_Cmd(emDACCH_TypeDef channel, FunctionalState state)
+{
+    (state) ? (DAC->CR |= DAC_CR_EN1 << channel) : (DAC->CR &= ~(DAC_CR_EN1 << channel));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified DAC channel DMA request.
+/// @param channel: the selected DAC channel.
+/// @param state: new state of the selected DAC channel DMA request.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_DMACmd(emDACCH_TypeDef channel, FunctionalState state)
+{
+    (state) ? (DAC->CR |= DAC_CR_DMAEN1 << channel) : (DAC->CR &= ~(DAC_CR_DMAEN1 << channel));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the selected DAC channel software trigger.
+/// @param channel: the selected DAC channel.
+/// @param state: new state of the selected DAC channel software trigger.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_SoftwareTriggerCmd(emDACCH_TypeDef channel, FunctionalState state)
+{
+    (state) ? (DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 << (channel >> 4)))
+    : (DAC->SWTRIGR &= ~(DAC_SWTRIGR_SWTRIG1 << (channel >> 4)));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables simultaneously the two DAC channels software triggers.
+/// @param state: new state of the DAC channels software triggers.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_DualSoftwareTriggerCmd(FunctionalState state)
+{
+    (state) ? (DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2))
+    : (DAC->SWTRIGR &= ~(DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the selected DAC channel wave generation.
+/// @param channel: the selected DAC channel.
+/// @param wave: Specifies the wave type to enable or disable.
+/// @param state: new state of the selected DAC channel wave generation.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_WaveGenerationCmd(emDACCH_TypeDef channel, emDACWAVE_TypeDef wave, FunctionalState state)
+{
+    (state) ? (DAC->CR |= wave << channel) : (DAC->CR &= ~(wave << channel));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the specified data holding register value for DAC channel1.
+/// @param alignement: Specifies the data alignement for DAC channel1.
+/// @param data : data to be loaded in the selected data holding register.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_SetChannel1Data(emDACALIGN_TypeDef alignement, u16 data)
+{
+    *((u32*)(DAC_BASE + DHR12R1_Offset + alignement)) = data;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the specified data holding register value for DAC channel2.
+/// @param alignement: Specifies the data alignement for DAC channel2.
+/// @param data : data to be loaded in the selected data holding
+///   register.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_SetChannel2Data(emDACALIGN_TypeDef alignement, u16 data)
+{
+    *((u32*)(DAC_BASE + DHR12R2_Offset + alignement)) = data;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the specified data holding register value for dual channel DAC.
+/// @param alignement: Specifies the data alignement for dual channel DAC.
+/// @param data2: data for DAC Channel2 to be loaded in the selected data holding register.
+/// @param data1: data for DAC Channel1 to be loaded in the selected data holding register.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_SetDualChannelData(emDACALIGN_TypeDef alignement, u16 data2, u16 data1)
+{
+    u32 data = ((alignement == DAC_Align_8b_R) ? ((data2 << 8) | data1) : ((data2 << 16) | data1));
+    *((u32*)(DAC_BASE + DHR12RD_Offset + alignement)) = data;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the last data output value of the selected DAC cahnnel.
+/// @param channel: the selected DAC channel.
+/// @retval  The selected DAC channel data output value.
+////////////////////////////////////////////////////////////////////////////////
+u16 DAC_GetDataOutputValue(emDACCH_TypeDef channel)
+{
+    return (*(vu32*)(DAC_BASE + DOR_Offset + (channel >> 2)));
+}
+/// @}
+
+/// @}
+
+/// @}
+
+

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c

@@ -0,0 +1,53 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_dbg.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE DBG FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_DBG_C
+
+// Files includes
+#include "types.h"
+#include "hal_dbg.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DBG_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DBG_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified DBG peripheral.
+/// @param  periph: DBG peripheral.
+/// @param  state: new state of the specified DBG peripheral.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DBGMCU_Configure(u32 periph, FunctionalState state)
+{
+    (state) ? (DBGMCU->CR |= periph) : (DBGMCU->CR &= ~periph);
+}
+
+/// @}
+
+/// @}
+
+/// @}

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c

@@ -0,0 +1,319 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_dma.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE DMA FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+
+
+
+// Define to prevent recursive inclusion
+#define _HAL_DMA_C_
+
+// Files includes
+#include "types.h"
+#include "hal_dma.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DMA_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DMA_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the DMA Channeln registers to their default reset
+///         values.
+/// @param   select the DMA Channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_DeInit(DMA_Channel_TypeDef* channel)
+{
+    channel->CCR &= ~DMA_CCR_EN;
+    channel->CCR   = 0;
+    channel->CNDTR = 0;
+    channel->CPAR  = 0;
+    channel->CMAR  = 0;
+    if((*(vu32*)&channel) >= (*(vu32*)DMA2_Channel1_BASE)) {
+        DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
+    }
+    else {
+        DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the DMA Channeln according to the specified
+///         parameters in the init_struct.
+/// @param  select the DMA Channel.
+/// @param  init_struct: pointer to a DMA_InitTypeDef structure that
+///         contains the configuration information for the specified DMA
+///         Channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_Init(DMA_Channel_TypeDef* channel, DMA_InitTypeDef* init_struct)
+{
+    MODIFY_REG(
+        channel->CCR,
+        (DMA_CCR_DIR | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL | DMA_CCR_M2M),
+        ((u32)init_struct->DMA_DIR | (u32)init_struct->DMA_Mode | (u32)init_struct->DMA_PeripheralInc |
+         (u32)init_struct->DMA_MemoryInc | (u32)init_struct->DMA_PeripheralDataSize | (u32)init_struct->DMA_MemoryDataSize |
+         (u32)init_struct->DMA_Priority | (u32)init_struct->DMA_M2M));
+
+    MODIFY_REG(channel->CCR, DMA_CCR_ARE, init_struct->DMA_Auto_reload);
+    channel->CNDTR = init_struct->DMA_BufferSize;
+    channel->CPAR  = init_struct->DMA_PeripheralBaseAddr;
+    channel->CMAR  = init_struct->DMA_MemoryBaseAddr;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param  init_struct : pointer to a DMA_InitTypeDef structure which will
+///         be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_StructInit(DMA_InitTypeDef* init_struct)
+{
+    init_struct->DMA_PeripheralBaseAddr = 0;
+    init_struct->DMA_MemoryBaseAddr     = 0;
+    init_struct->DMA_DIR                = DMA_DIR_PeripheralSRC;
+    init_struct->DMA_BufferSize         = 0;
+    init_struct->DMA_PeripheralInc      = DMA_PeripheralInc_Disable;
+    init_struct->DMA_MemoryInc          = DMA_MemoryInc_Disable;
+    init_struct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+    init_struct->DMA_MemoryDataSize     = DMA_MemoryDataSize_Byte;
+    init_struct->DMA_Mode               = DMA_Mode_Normal;
+    init_struct->DMA_Priority           = DMA_Priority_Low;
+    init_struct->DMA_M2M                = DMA_M2M_Disable;
+
+    init_struct->DMA_Auto_reload         = DMA_Auto_Reload_Disable;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified DMA Channeln.
+/// @param  channel: select the DMA Channel.
+/// @param  state: new state of the DMA Channeln.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_Cmd(DMA_Channel_TypeDef* channel, FunctionalState state)
+{
+    MODIFY_REG(channel->CCR, DMA_CCR_EN, state << DMA_CCR_EN_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified DMA Channeln interrupts.
+/// @param  channel: select the DMA Channel.
+/// @param  it: specifies the DMA interrupts sources to be enabled
+///         or disabled.
+///         This parameter can be any combination of the following values:
+///    @arg DMA_IT_TC:  Transfer complete interrupt mask
+///    @arg DMA_IT_HT:  Half transfer interrupt mask
+///    @arg DMA_IT_TE:  Transfer error interrupt mask
+/// @param  state: new state of the specified DMA interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_ITConfig(DMA_Channel_TypeDef* channel, DMA_Interrupt_EN_TypeDef it, FunctionalState state)
+{
+    (state) ? (channel->CCR |= it) : (channel->CCR &= ~it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the number of data units in the select the DMA Channel .
+/// @param  channel: select the DMA Channel
+/// @param  DataNumber: The number of data units in the current DMAy Channelx
+///         transfer.
+/// @note   This function can only be used when the DMAy_Channelx is disabled.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* channel, u16 length)
+{
+    channel->CNDTR = length;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the number of remaining data units in the current
+///         DMA Channeln transfer.
+/// @param  channel: select the DMA Channel.
+/// @retval The number of remaining data units in the current DMA Channeln
+///         transfer.
+////////////////////////////////////////////////////////////////////////////////
+u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* channel)
+{
+    return channel->CNDTR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified DMA Channeln flag is set or not.
+/// @param  flag: specifies the flag to check.
+///         This parameter can be one of the following values:
+///    @arg DMA1_FLAG_GLn: DMA1 Channeln global flag(n = 1..7).
+///    @arg DMA1_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..7).
+///    @arg DMA1_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..7).
+///    @arg DMA1_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..7).
+///    @arg DMA2_FLAG_GLn: DMA1 Channeln global flag(n = 1..5).
+///    @arg DMA2_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
+///    @arg DMA2_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..5).
+///    @arg DMA2_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..5).
+/// @retval The new state of DMAy_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus DMA_GetFlagStatus(DMA_Flags_TypeDef flag)
+{
+    if(flag >= DMA2_FLAG_GL1 ) {
+        return (DMA2->ISR & flag) ? SET : RESET;
+    }
+    return (DMA1->ISR & flag) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the DMA Channeln's pending flags.
+/// @param  flag: specifies the flag to clear.
+///         This parameter can be any combination (for the same DMA) of the
+///         following values:
+///    @arg DMA1_FLAG_GLn: DMA1 Channeln global flag(n = 1..7).
+///    @arg DMA1_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..7).
+///    @arg DMA1_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..7).
+///    @arg DMA1_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..7).
+///    @arg DMA2_FLAG_GLn: DMA1 Channeln global flag(n = 1..5).
+///    @arg DMA2_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
+///    @arg DMA2_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..5).
+///    @arg DMA2_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..5).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_ClearFlag(DMA_Flags_TypeDef flag)
+{
+    if(flag >= DMA2_FLAG_GL1 ) {
+        DMA2->IFCR = flag;
+        return ;
+    }
+    DMA1->IFCR = flag;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified DMA Channeln interrupt has occurred or
+/// not.
+/// @param  it: specifies the DMA interrupt source to check.
+///         This parameter can be one of the following values:
+///    @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
+///    @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
+///    @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
+///    @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
+///    @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
+///    @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
+///    @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
+///    @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
+/// @retval  The new state of DMAy_IT (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus DMA_GetITStatus(DMA_Interrupts_TypeDef it)
+{
+    if(it >= DMA2_IT_GL1 ) {
+        return (DMA2->ISR & it) ? SET : RESET;
+    }
+    return (DMA1->ISR & it) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the DMA Channeln's interrupt pending bits.
+/// @param  it: specifies the DMA interrupt pending bit to clear.
+///         This parameter can be any combination (for the same DMA) of the
+///         following values:
+///    @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
+///    @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
+///    @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
+///    @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
+///    @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
+///    @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
+///    @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
+///    @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_ClearITPendingBit(DMA_Interrupts_TypeDef it)
+{
+    if(it >= DMA2_IT_GL1 ) {
+        DMA2->IFCR = it;
+        return ;
+    }
+    DMA1->IFCR = it;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the DMA Channeln's Peripheral address.
+/// @param  channel : where n can be 1 to 7 for DMA1 to select the DMA Channel.
+/// @param  address : DMA Peripheral address.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exDMA_SetPeripheralAddress(DMA_Channel_TypeDef* channel, u32 address)
+{
+    channel->CPAR = address;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the DMA Channeln's Peripheral address.
+/// @param  channel : select the DMA Channel.
+/// @param  length : Transmit lengths.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exDMA_SetTransmitLen(DMA_Channel_TypeDef* channel, u16 length)
+{
+    channel->CNDTR = length;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the DMA Channeln's Peripheral address.
+/// @param  channel :select the DMA Channel.
+/// @param  address : DMA memery address.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exDMA_SetMemoryAddress(DMA_Channel_TypeDef* channel, u32 address)
+{
+    channel->CMAR = address;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the DMA Channeln's interrupt pending bits.
+/// @param  it: specifies the DMA interrupt pending bit to clear.
+///         This parameter can be any combination (for the same DMA) of the
+///         following values:
+///    @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
+///    @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
+///    @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
+///    @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
+///    @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
+///    @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
+///    @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
+///    @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exDMA_ClearITPendingBit(DMA_Channel_TypeDef* channel, u32 it)
+{
+    if(it >= DMA2_IT_GL1 ) {
+        DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
+        DMA2->IFCR = it;
+        return ;
+    }
+    DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
+    DMA1->IFCR = it;
+}
+/// @}
+
+/// @}
+
+/// @}

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c

@@ -0,0 +1,836 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_eth.c
+/// @author   AE TEM
+/// @brief    THIS FILE PROVIDES ALL THE HAL_eth.c EXAMPLE.
+/// ////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT  MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+#define _HAL_ETH_C_
+#include "hal_rcc.h"
+#include "hal_eth.h"
+#include "reg_eth.h"
+
+
+void ETH_DeInit(void)
+{
+    RCC_AHBPeriphResetCmd(RCC_AHBENR_ETHMAC, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBENR_ETHMAC, DISABLE);
+}
+
+void ETH_StructInit(ETH_InitTypeDef* ptr)
+{
+    ptr->ETH_AutoNegotiation         = ETH_AutoNegotiation_Enable;              ///< PHY Auto-negotiation enabled
+    ptr->ETH_Watchdog                = ETH_Watchdog_Enable;                     ///< MAC watchdog enabled: cuts off long frame
+    ptr->ETH_Jabber                  = ETH_Jabber_Enable;                       ///< MAC Jabber enabled in Half-duplex mode
+    ptr->ETH_InterFrameGap           = ETH_InterFrameGap_96Bit;                 ///< Ethernet interframe gap set to 96 bits
+    ptr->ETH_CarrierSense            = ETH_CarrierSense_Enable;                 ///< Carrier Sense Enabled in Half-Duplex mode
+    ptr->ETH_Speed                   = ETH_Speed_100M;                          ///< PHY speed configured to 100Mbit/s
+    ptr->ETH_ReceiveOwn              = ETH_ReceiveOwn_Enable;                   ///< Receive own Frames in Half-Duplex mode enabled
+    ptr->ETH_LoopbackMode            = ETH_LoopbackMode_Disable;                ///< MAC MII loopback disabled
+    ptr->ETH_Mode                    = ETH_Mode_FullDuplex;                     ///< Full-Duplex mode selected
+    ptr->ETH_ChecksumOffload         = ETH_ChecksumOffload_Disable;             ///< IPv4 and TCP/UDP/ICMP frame Checksum Offload disabled
+    ptr->ETH_RetryTransmission       = ETH_RetryTransmission_Enable;            ///< Retry Transmission enabled for half-duplex mode
+    ptr->ETH_AutomaticPadCRCStrip    = ETH_AutomaticPadCRCStrip_Disable;        ///< Automatic PAD/CRC strip disable
+    ptr->ETH_BackOffLimit            = ETH_BackOffLimit_10;                     ///< half-duplex mode retransmission Backoff time_limit = 10 slot time
+    ptr->ETH_DeferralCheck           = ETH_DeferralCheck_Disable;               ///< half-duplex mode Deferral check disabled
+    ptr->ETH_ReceiveAll              = ETH_ReceiveAll_Disable;                  ///< Receive all frames disabled
+    ptr->ETH_SourceAddrFilter        = ETH_SourceAddrFilter_Disable;            ///< Source address filtering (on the optional MAC addresses) disabled
+    ptr->ETH_PassControlFrames       = ETH_PassControlFrames_BlockAll;          ///< Do not forward control frames that do not pass the address filtering
+    ptr->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;   ///< Disable reception of Broadcast frames
+    ptr->ETH_DestinationAddrFilter   = ETH_DestinationAddrFilter_Normal;        ///< Normal Destination address filtering (not reverse addressing)
+    ptr->ETH_PromiscuousMode         = ETH_PromiscuousMode_Disable;             ///< Promiscuous address filtering mode disabled
+    ptr->ETH_MulticastFramesFilter   = ETH_MulticastFramesFilter_Perfect;       ///< Perfect address filtering for multicast addresses
+    ptr->ETH_UnicastFramesFilter     = ETH_UnicastFramesFilter_Perfect;         ///< Perfect address filtering for unicast addresses
+    ptr->ETH_HashTableHigh           = 0x0;                                     ///< Initialize hash table high and low regs
+    ptr->ETH_HashTableLow            = 0x0;
+    ptr->ETH_PauseTime               = 0x0;                                     ///< Flow control config (flow control disabled)
+    ptr->ETH_ZeroQuantaPause         = ETH_ZeroQuantaPause_Enable;
+    ptr->ETH_PauseLowThreshold       = ETH_PauseLowThreshold_Minus4;
+    ptr->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
+    ptr->ETH_ReceiveFlowControl      = ETH_ReceiveFlowControl_Disable;
+    ptr->ETH_TransmitFlowControl     = ETH_TransmitFlowControl_Disable;
+    ptr->ETH_VLANTagComparison       = ETH_VLANTagComparison_16Bit;             ///< VLANtag config (VLAN field not checked)
+    ptr->ETH_VLANTagIdentifier       = 0x0;
+
+    ptr->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; ///< Drops frames with with TCP/IP checksum errors
+    ptr->ETH_ReceiveStoreForward     = ETH_ReceiveStoreForward_Enable;          ///< Store and forward mode enabled for receive
+    ptr->ETH_FlushReceivedFrame      = ETH_FlushReceivedFrame_Enable;           ///< Flush received frame that created FIFO overflow
+    ptr->ETH_TransmitStoreForward    = ETH_TransmitStoreForward_Enable;         ///< Store and forward mode enabled for transmit
+    ptr->ETH_TransmitThresholdControl = ETH_ReceiveThresholdControl_64Bytes;    ///< Threshold TXFIFO level set to 64 bytes (used when threshold mode is enabled)
+    ptr->ETH_ForwardErrorFrames      = ETH_ForwardErrorFrames_Disable;          ///< Disable forwarding frames with errors (short frames, CRC,...)
+    ptr->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; ///< Disable undersized good frames
+    ptr->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;     ///< Threshold RXFIFO level set to 64 bytes (used when Cut through mode is enabled)
+    ptr->ETH_SecondFrameOperate      = ETH_SecondFrameOperate_Disable;          ///< Disable Operate on second frame (transmit a second frame to FIFO without waiting status of previous frame
+    ptr->ETH_AddressAlignedBeats     = ETH_AddressAlignedBeats_Enable;          ///< DMA works on 32-bit aligned start source and destinations addresses
+    ptr->ETH_FixedBurst              = ETH_FixedBurst_Enable;                   ///< Enabled Fixed Burst Mode (mix of INC4, INC8, INC16 and SINGLE DMA transactions
+    ptr->ETH_RxDMABurstLength        = ETH_RxDMABurstLength_32Beat;             ///< DMA transfer max burst length = 32 beats = 32 x 32bits
+    ptr->ETH_TxDMABurstLength        = ETH_TxDMABurstLength_32Beat;
+    ptr->ETH_DescriptorSkipLength    = 0x0;                                     ///< DMA Ring mode skip length = 0
+    ptr->ETH_DMAArbitration          = ETH_DMAArbitration_RoundRobin_RxTx_1_1;  ///< Equal priority (round-robin) between transmit and receive DMA engines
+}
+
+u32 ETH_Init(ETH_InitTypeDef* ptr, u16 phy_addr)
+{
+    u32 hclk = RCC_GetHCLKFreq();
+    u32 reg = ETH->MACMIIAR & MACMIIAR_CR_MASK;
+    u32 temp_val = 0;
+    hclk = 100000000;
+    ////////////////////////////////////////////////////////////////////////////
+    if (hclk >= 20000000 && hclk < 35000000) {
+        reg |= ETH_MACMIIAR_CR_Div16;                                           ///< HCLK 20 ~ 35 MHz, /16
+    }
+    else if (hclk >= 35000000 && hclk < 60000000) {
+        reg |= ETH_MACMIIAR_CR_Div26;                                           ///< HCLK 35 ~ 60 MHz, /26
+    }
+    else if (hclk >= 60000000 && hclk < 100000000) {
+        reg |= ETH_MACMIIAR_CR_Div42;                                           ///< HCLK 60 ~ 100 MHz, /42
+    }
+    else if (hclk >= 100000000 && hclk < 150000000) {
+        reg |= ETH_MACMIIAR_CR_Div62;                                           ///< HCLK 100 ~ 150 MHz, /62
+    }
+    else {
+        reg |= ETH_MACMIIAR_CR_Div102;                                          ///< HCLK 150 ~ 168 MHz, /102
+    }
+
+    ETH->MACMIIAR = reg;
+
+    ////////////////////////////////////////////////////////////////////////////
+    ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_Reset);
+    if (ptr->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable) {
+        // Wait for linked status
+        while (!(ETH_ReadPHYRegister(phy_addr, PHY_BSR) & PHY_Linked_Status));
+        ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_AutoNegotiation);
+        // Enable Auto-Negitation
+        while (!(ETH_ReadPHYRegister(phy_addr, PHY_BSR) & PHY_AutoNego_Complete)) {
+
+        }
+        // Read the result of the Auto-Negitation
+        temp_val = ETH_ReadPHYRegister(phy_addr, 31);
+
+        if ((temp_val & 0x1C) == 0x4) {
+            ptr->ETH_Speed = ETH_Speed_10M;
+            ptr->ETH_Mode = ETH_Mode_HalfDuplex;
+            SYSCFG->CFGR2 &= ~(1 << 21);
+        }
+        else if((temp_val & 0x1C) == 0x14) {
+            ptr->ETH_Speed = ETH_Speed_10M;
+            ptr->ETH_Mode = ETH_Mode_FullDuplex;
+            SYSCFG->CFGR2 |= 1 << 21;
+        }
+        else if((temp_val & 0x1C) == 0x8) {
+            ptr->ETH_Speed = ETH_Speed_100M;
+            ptr->ETH_Mode = ETH_Mode_HalfDuplex;
+            SYSCFG->CFGR2 &= ~(1 << 21);
+        }
+        else if((temp_val & 0x1C) == 0x18) {
+            ptr->ETH_Speed = ETH_Speed_100M;
+            ptr->ETH_Mode = ETH_Mode_FullDuplex;
+            SYSCFG->CFGR2 |= 1 << 21;
+        }
+    }
+    else {
+        ETH_WritePHYRegister(phy_addr, PHY_BCR, ((u16)(ptr->ETH_Mode >> 3) |
+                             (u16)(ptr->ETH_Speed >> 1)));
+        if(ptr->ETH_Speed == ETH_Speed_10M) {
+            SYSCFG->CFGR2 &= ~(1 << 21);
+        }
+        else {
+            SYSCFG->CFGR2 |= 1 << 21;
+        }
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    ETH->MACCR = ETH->MACCR & MACCR_CLEAR_MASK |   (ptr->ETH_Watchdog |
+                 ptr->ETH_Jabber |
+                 ptr->ETH_InterFrameGap |
+                 ptr->ETH_CarrierSense |
+                 ptr->ETH_Speed |
+                 ptr->ETH_ReceiveOwn |
+                 ptr->ETH_LoopbackMode |
+                 ptr->ETH_Mode |
+                 ptr->ETH_ChecksumOffload |
+                 ptr->ETH_RetryTransmission |
+                 ptr->ETH_AutomaticPadCRCStrip |
+                 ptr->ETH_DeferralCheck);
+
+    ETH->MACFFR =   ptr->ETH_ReceiveAll |
+                    ptr->ETH_SourceAddrFilter |
+                    ptr->ETH_PassControlFrames |
+                    ptr->ETH_BroadcastFramesReception |
+                    ptr->ETH_DestinationAddrFilter |
+                    ptr->ETH_PromiscuousMode |
+                    ptr->ETH_MulticastFramesFilter |
+                    ptr->ETH_UnicastFramesFilter;
+
+    ETH->MACHTHR = ptr->ETH_HashTableHigh;
+    ETH->MACHTLR = ptr->ETH_HashTableLow;
+
+    ETH->MACFCR = ETH->MACFCR & MACFCR_CLEAR_MASK | ((ptr->ETH_PauseTime << ETH_MACFCR_PT_Pos) |
+                  ptr->ETH_ZeroQuantaPause |
+                  ptr->ETH_PauseLowThreshold |
+                  ptr->ETH_UnicastPauseFrameDetect |
+                  ptr->ETH_ReceiveFlowControl |
+                  ptr->ETH_TransmitFlowControl);
+
+    ETH->MACVLANTR = ptr->ETH_VLANTagComparison | ptr->ETH_VLANTagIdentifier;
+
+    ETH->DMAOMR = 0x00200004;
+    ETH->DMAIER = 0x0001A040;
+    ETH->DMABMR = ( ptr->ETH_AddressAlignedBeats |
+                    ptr->ETH_FixedBurst |
+                    ptr->ETH_RxDMABurstLength |                                 // !! if 4xPBL is selected for Tx or Rx it is applied for the other
+                    ptr->ETH_TxDMABurstLength |
+                    ptr->ETH_DescriptorSkipLength << 2 |
+                    ptr->ETH_DMAArbitration);// |
+//                    ETH_DMABMR_USP);                                            // Enable use of separate PBL for Rx and Tx
+
+    return ETH_SUCCESS;
+}
+
+void ETH_Start(void)
+{
+    ETH_MACTransmissionCmd(ENABLE);
+    ETH_MACReceptionCmd(ENABLE);
+    ETH_FlushTransmitFIFO();
+    ETH_DMATransmissionCmd(ENABLE);
+    ETH_DMAReceptionCmd(ENABLE);
+}
+
+void ETH_Stop(void)
+{
+    ETH_DMATransmissionCmd(DISABLE);
+    ETH_DMAReceptionCmd(DISABLE);
+    ETH_MACReceptionCmd(DISABLE);
+    ETH_FlushTransmitFIFO();
+    ETH_MACTransmissionCmd(DISABLE);
+}
+
+void ETH_MACTransmissionCmd(FunctionalState sta)
+{
+    sta ? (ETH->MACCR |= ETH_MACCR_TE) : (ETH->MACCR &= ~ETH_MACCR_TE);
+}
+
+void ETH_MACReceptionCmd(FunctionalState sta)
+{
+    sta ? (ETH->MACCR |= ETH_MACCR_RE) : (ETH->MACCR &= ~ETH_MACCR_RE);
+}
+
+FlagStatus ETH_GetFlowControlBusyStatus(void)
+{
+    return (FlagStatus)(ETH->MACFCR & ETH_MACFCR_FCBBPA);
+}
+
+void ETH_InitiatePauseControlFrame(void)
+{
+    ETH->MACFCR |= ETH_MACFCR_FCBBPA;
+}
+
+void ETH_BackPressureActivationCmd(FunctionalState sta)
+{
+    sta ? (ETH->MACFCR |= ETH_MACFCR_FCBBPA) : (ETH->MACFCR &= ~ETH_MACFCR_FCBBPA);
+}
+
+void ETH_MACAddressConfig(u32 reg_addr, u8* mac_addr)
+{
+    *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) =
+        (u32)mac_addr[5] << 8 |
+        (u32)mac_addr[4];
+
+    *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) =
+        (u32)mac_addr[3] << 24 |
+        (u32)mac_addr[2] << 16 |
+        (u32)mac_addr[1] << 8 |
+        (u32)mac_addr[0];
+}
+
+void ETH_GetMACAddress(u32 reg_addr, u8* mac_addr)
+{
+    mac_addr[5] = *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) >> 8 & 0xFF;
+    mac_addr[4] = *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) & 0xFF;
+    mac_addr[3] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 24 & 0xFF;
+    mac_addr[2] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 16 & 0xFF;
+    mac_addr[1] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 8 & 0xFF;
+    mac_addr[0] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) & 0xFF;
+}
+
+void ETH_MACAddressPerfectFilterCmd(u32 reg_addr, FunctionalState sta)
+{
+    sta ?   ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_AE) :
+    ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) &= ~ETH_MACA1HR_AE);
+}
+
+void ETH_MACAddressFilterConfig(u32 reg_addr, u32 sta)
+{
+    sta ?   ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_SA) :
+    ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_SA);
+}
+
+void ETH_MACAddressMaskBytesFilterConfig(u32 reg_addr, u32 mask_byte)
+{
+    (*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) &= ~ETH_MACA1HR_MBC;
+
+    (*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= mask_byte;
+}
+
+FrameTypeDef ETH_Get_Received_Frame(void)
+{
+    FrameTypeDef frame;
+
+    frame.len = ((DMARxDescToGet->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FL_Pos) - 4;
+    frame.buf = (DMA_RX_FRAME_infos->ptrFS_Rx_Desc)->BUF1ADDR;
+    frame.ptrDesc = DMA_RX_FRAME_infos->ptrFS_Rx_Desc;
+
+
+    DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
+
+    return frame;
+}
+
+FrameTypeDef ETH_Get_Received_Frame_interrupt(void)
+{
+    FrameTypeDef frame = {0};
+    __IO u32 desc_cnt = 0;
+
+    while(!(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) && desc_cnt < ETH_RX_BUF_NUM) {
+        desc_cnt++;
+
+        if ( (DMARxDescToGet->CS & ETH_DMA_RDES_FS) &&
+                !(DMARxDescToGet->CS & ETH_DMA_RDES_LS)) {
+            DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
+            DMA_RX_FRAME_infos->cnt = 1;
+            DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
+
+        }
+        else if ( (DMARxDescToGet->CS & ETH_DMA_RDES_FS) &&
+                  (DMARxDescToGet->CS & ETH_DMA_RDES_LS)) {
+            DMA_RX_FRAME_infos->cnt++;
+            DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
+        }
+        else {
+            DMA_RX_FRAME_infos->ptrLS_Rx_Desc = DMARxDescToGet;
+            DMA_RX_FRAME_infos->cnt++;
+
+            if (DMA_RX_FRAME_infos->cnt == 1)
+                DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
+
+            frame.len = ((DMARxDescToGet->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FL_Pos) - 4;
+
+            frame.buf = (DMA_RX_FRAME_infos->cnt > 1) ?
+                        (DMA_RX_FRAME_infos->ptrFS_Rx_Desc->BUF1ADDR) :
+                        (DMARxDescToGet->BUF1ADDR);
+
+            frame.ptrDesc = DMA_RX_FRAME_infos->ptrFS_Rx_Desc;
+
+            DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
+
+            return frame;
+        }
+    }
+
+    return frame;
+}
+
+u32 ETH_Prepare_Transmit_Descriptors(u16 len)
+{
+    u32 cnt = 0, i = 0;
+    __IO ETH_DMADESCTypeDef* temp_desc = DMATxDescToSet;
+
+    if (DMATxDescToSet->CS & ETH_DMA_TDES_OWN)
+        return ETH_ERROR;
+
+    if(len > ETH_TX_BUF_SIZE) {
+        cnt = len / ETH_TX_BUF_SIZE;
+
+        if (len % ETH_TX_BUF_SIZE)
+            cnt++;
+    }
+    else {
+        cnt = 1;
+    }
+
+    if (cnt == 1) {
+        temp_desc->BL &= ~(ETH_DMA_TDES_FS | ETH_DMA_TDES_LS | ETH_DMA_TDES_TBS1);
+
+        temp_desc->BL |=    ETH_DMA_TDES_FS |
+                            ETH_DMA_TDES_LS |
+                            (len & ETH_DMA_TDES_TBS1);
+
+        temp_desc->CS |= ETH_DMA_TDES_OWN;
+        temp_desc = (ETH_DMADESCTypeDef*)(temp_desc->BUF2NDADDR);
+    }
+    else {
+        for (i = 0; i < cnt; i++) {
+            temp_desc->BL &= ~(ETH_DMA_TDES_FS | ETH_DMA_TDES_LS);
+
+            if (i == 0)
+                temp_desc->BL |= ETH_DMA_TDES_FS;
+
+            temp_desc->BL = ETH_TX_BUF_SIZE & ETH_DMA_TDES_TBS1;
+
+            if (i == (cnt - 1)) {
+                temp_desc->BL &= ~ETH_DMA_TDES_TBS1;
+                temp_desc->BL |=    ETH_DMA_TDES_LS |
+                                    ((len - (cnt - 1) * ETH_TX_BUF_SIZE) & ETH_DMA_TDES_TBS1);
+            }
+
+            temp_desc->CS |= ETH_DMA_TDES_OWN;
+            temp_desc = (ETH_DMADESCTypeDef*)(temp_desc->BUF2NDADDR);
+        }
+    }
+
+    DMATxDescToSet = temp_desc;
+
+    if (ETH->DMASR & ETH_DMASR_TBUS) {
+        ETH->DMASR = ETH_DMASR_TBUS;
+        ETH->DMATPDR = 0;
+    }
+
+    return ETH_SUCCESS;
+}
+
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt)
+{
+    u32 i = 0;
+    ETH_DMADESCTypeDef* temp_desc;
+
+    DMARxDescToGet = ptr_desc;
+
+    for (i = 0; i < cnt; i++) {
+        temp_desc = ptr_desc + i;
+        temp_desc->CS = ETH_DMA_RDES_OWN;
+        temp_desc->BL = ETH_DMA_RDES_RCH | ETH_RX_BUF_SIZE;
+        temp_desc->BUF1ADDR = (u32)&buf[i * ETH_RX_BUF_SIZE];
+
+        if (i < cnt - 1) {
+            temp_desc->BUF2NDADDR = (u32)(ptr_desc + i + 1);
+        }
+        else {
+            temp_desc->BUF2NDADDR = (u32)(ptr_desc);
+        }
+    }
+
+    ETH->DMARDLAR = (u32)ptr_desc;
+
+    DMA_RX_FRAME_infos = &RX_Frame_Descriptor;
+}
+
+u32 ETH_CheckFrameReceived(void)
+{
+    if(!(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) &&
+            (DMARxDescToGet->CS & ETH_DMA_RDES_LS)) {
+
+        DMA_RX_FRAME_infos->cnt++;
+
+        if (DMA_RX_FRAME_infos->cnt == 1) {
+            DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
+        }
+        DMA_RX_FRAME_infos->ptrLS_Rx_Desc = DMARxDescToGet;
+        return 1;
+    }
+    else if ( !(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) &&
+              !(DMARxDescToGet->CS & ETH_DMA_RDES_LS)  &&
+              (DMARxDescToGet->CS & ETH_DMA_RDES_FS)) {
+        DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
+        DMA_RX_FRAME_infos->ptrLS_Rx_Desc = (void*)0;
+        DMA_RX_FRAME_infos->cnt = 1;
+    }
+    else if ( !(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) &&
+              !(DMARxDescToGet->CS & ETH_DMA_RDES_LS)  &&
+              !(DMARxDescToGet->CS & ETH_DMA_RDES_FS)) {
+        DMA_RX_FRAME_infos->cnt++;
+        DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
+    }
+
+    return 0;
+}
+
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt)
+{
+    u32 i = 0;
+    ETH_DMADESCTypeDef* temp_desc;
+
+    DMATxDescToSet = ptr_desc;
+
+    for (i = 0; i < cnt; i++) {
+        temp_desc = ptr_desc + i;
+        temp_desc->BL = ETH_DMA_TDES_TCH;
+        temp_desc->BUF1ADDR = (u32)(&buf[i * ETH_TX_BUF_SIZE]);
+
+        if (i < cnt - 1) {
+            temp_desc->BUF2NDADDR = (u32)(ptr_desc + i + 1);
+        }
+        else {
+            temp_desc->BUF2NDADDR = (u32)(ptr_desc);
+        }
+    }
+
+    ETH->DMATDLAR = (u32)ptr_desc;
+}
+
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag)
+{
+    return (FlagStatus)(ptr_desc->CS & flag);
+}
+
+u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef* ptr_desc)
+{
+    return (ptr_desc->CS & ETH_DMA_TDES_CC) >> ETH_DMA_TDES_COLLISION_COUNTSHIFT;
+}
+
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc)
+{
+    ptr_desc->CS |= ETH_DMA_TDES_OWN;
+}
+
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
+{
+    sta ? (ptr_desc->BL |= ETH_DMA_TDES_IC) : (ptr_desc->BL &= ~ETH_DMA_TDES_IC);
+}
+
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val)
+{
+    ptr_desc->CS |= val;
+}
+
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val)
+{
+    ptr_desc->CS |= val;
+}
+
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
+{
+    sta ? (ptr_desc->BL &= ~ETH_DMA_TDES_DC) : (ptr_desc->BL |= ETH_DMA_TDES_DC);
+}
+
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
+{
+    sta ? (ptr_desc->BL |= ETH_DMA_TDES_TCH) : (ptr_desc->BL &= ~ETH_DMA_TDES_TCH);
+}
+
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
+{
+    sta ? (ptr_desc->BL &= ~ETH_DMA_TDES_DP) : (ptr_desc->BL |= ETH_DMA_TDES_DP);
+}
+
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef* ptr_desc, u32 buf1_size, u32 buf2_size)
+{
+    ptr_desc->BL |= buf1_size | (buf2_size << ETH_DMA_TDES_BUFFER2_SIZESHIFT);
+}
+
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag)
+{
+    return (FlagStatus)(ptr_desc->CS & flag);
+}
+
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc)
+{
+    ptr_desc->CS |= ETH_DMA_RDES_OWN;
+}
+
+u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef* ptr_desc)
+{
+    return (ptr_desc->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FRAME_LENGTHSHIFT;
+}
+
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
+{
+    sta ? (ptr_desc->CS &= ~ETH_DMA_RDES_DIC) : (ptr_desc->CS |= ETH_DMA_RDES_DIC);
+}
+
+u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef* ptr_desc, u32 buf)
+{
+    return (buf != ETH_DMA_RDES_Buffer1 ?
+            ((ptr_desc->BL & ETH_DMA_RDES_RBS2) >> ETH_DMA_RDES_BUFFER2_SIZESHIFT) :
+            (ptr_desc->BL & ETH_DMA_RDES_RBS1));
+}
+
+u32 ETH_GetRxPktSize(ETH_DMADESCTypeDef* ptr_desc)
+{
+    u32 len = 0;
+
+    if (    !(ptr_desc->CS & ETH_DMA_RDES_OWN) &&
+            !(ptr_desc->CS & ETH_DMA_RDES_ES) &&
+            (ptr_desc->CS & ETH_DMA_RDES_LS)) {
+        len = ETH_GetDMARxDescFrameLength(ptr_desc);
+    }
+
+    return len;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+void ETH_SoftwareReset(void)
+{
+    ETH->DMABMR |= ETH_DMABMR_SR;
+}
+
+FlagStatus ETH_GetSoftwareResetStatus(void)
+{
+    return (FlagStatus)(ETH->DMABMR & ETH_DMABMR_SR);
+}
+
+FlagStatus ETH_GetDMAFlagStatus(u32 flag)
+{
+    return (FlagStatus)(ETH->DMASR & flag);
+}
+
+void ETH_DMAClearFlag(u32 flag)
+{
+    ETH->DMASR = flag;
+}
+
+void ETH_DMAITConfig(u32 it, FunctionalState sta)
+{
+    sta ? (ETH->DMAIER |= it) : (ETH->DMAIER &= ~it);
+}
+
+ITStatus ETH_GetDMAITStatus(u32 it)
+{
+    return (ITStatus)(ETH->DMASR & it);
+}
+
+void ETH_DMAClearITPendingBit(u32 it)
+{
+    ETH->DMASR = it;
+}
+
+u32 ETH_GetTransmitProcessState(void)
+{
+    return ETH->DMASR & ETH_DMASR_TS;
+}
+
+u32 ETH_GetReceiveProcessState(void)
+{
+    return ETH->DMASR & ETH_DMASR_RS;
+}
+
+void ETH_FlushTransmitFIFO(void)
+{
+    ETH->DMAOMR |= ETH_DMAOMR_FTF;
+}
+
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
+{
+    return (FlagStatus)(ETH->DMAOMR & ETH_DMAOMR_FTF);
+}
+
+void ETH_DMATransmissionCmd(FunctionalState sta)
+{
+    sta ? (ETH->DMAOMR |= ETH_DMAOMR_ST) : (ETH->DMAOMR &= ~ETH_DMAOMR_ST);
+}
+
+void ETH_DMAReceptionCmd(FunctionalState sta)
+{
+    sta ? (ETH->DMAOMR |= ETH_DMAOMR_SR) : (ETH->DMAOMR &= ~ETH_DMAOMR_SR);
+}
+
+FlagStatus ETH_GetDMAOverflowStatus(u32 val)
+{
+    return (FlagStatus)(ETH->DMAMFBOCR & val);
+}
+
+u32 ETH_GetRxOverflowMissedFrameCounter(void)
+{
+    return (ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA) >>
+           ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT;
+}
+
+u32 ETH_GetBufferUnavailableMissedFrameCounter(void)
+{
+    return ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFC;
+}
+
+u32 ETH_GetCurrentTxDescStartAddress(void)
+{
+    return ETH->DMACHTDR;
+}
+
+u32 ETH_GetCurrentRxDescStartAddress(void)
+{
+    return ETH->DMACHRDR;
+}
+
+u32 ETH_GetCurrentTxBufferAddress(void)
+{
+    return ETH->DMACHTBAR;
+}
+
+u32 ETH_GetCurrentRxBufferAddress(void)
+{
+    return ETH->DMACHRBAR;
+}
+
+void ETH_ResumeDMATransmission(void)
+{
+    ETH->DMATPDR = 0;
+}
+
+void ETH_ResumeDMAReception(void)
+{
+    ETH->DMARPDR = 0;
+}
+
+void ETH_SetReceiveWatchdogTimer(u8 val)
+{
+    ETH->DMARSWTR = val;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+u16 ETH_ReadPHYRegister(u16 addr, u16 reg)
+{
+    u32 dat;
+    // Set phy address and reg address, clear write flag
+    ETH->MACMIIAR = (((ETH->MACMIIAR & ~MACMIIAR_CR_MASK) |
+                      (addr << ETH_MACMIIAR_PA_Pos & ETH_MACMIIAR_PA) |
+                      (reg  << ETH_MACMIIAR_MR_Pos & ETH_MACMIIAR_MR)) &
+                     (~ETH_MACMIIAR_MW)) | ETH_MACMIIAR_MB;
+
+    // Check busy flag
+    while(ETH->MACMIIAR & ETH_MACMIIAR_MB);
+    dat = (u16)ETH->MACMIIDR;
+    if(dat == 0xFFFF) {
+        dat = 0;
+    }
+    return dat;
+}
+
+u16 ETH_WritePHYRegister(u16 addr, u16 reg, u16 val)
+{
+    // Load data
+    ETH->MACMIIDR = val;
+
+    // Set phy address, reg address and write flag
+    ETH->MACMIIAR = (ETH->MACMIIAR & ~MACMIIAR_CR_MASK) |
+                    (addr << ETH_MACMIIAR_PA_Pos & ETH_MACMIIAR_PA) |
+                    (reg  << ETH_MACMIIAR_MR_Pos & ETH_MACMIIAR_MR) |
+                    ETH_MACMIIAR_MW |
+                    ETH_MACMIIAR_MB;
+
+    // Check busy flag
+    while(ETH->MACMIIAR & ETH_MACMIIAR_MB);
+
+    return ETH->MACMIIDR;
+}
+
+u32 ETH_PHYLoopBackCmd(u16 addr, FunctionalState sta)
+{
+    u16 temp_val = ETH_ReadPHYRegister(addr, PHY_BCR);
+
+    sta ? (temp_val |= PHY_Loopback) : (temp_val &= ~PHY_Loopback);
+
+    if(ETH_WritePHYRegister(addr, PHY_BCR, temp_val))
+        return ETH_SUCCESS;
+
+    return ETH_ERROR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
+{
+    ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;
+}
+
+void ETH_SetWakeUpFrameFilterRegister(u32* buf)
+{
+    u32 i = 0;
+
+    for (i = 0; i < ETH_WAKEUP_REGISTER_LENGTH; i++) {
+        ETH->MACRWUFFR = buf[i];
+    }
+}
+
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState sta)
+{
+    sta ?   (ETH->MACPMTCSR |= ETH_MACPMTCSR_GU) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU);
+}
+
+FlagStatus ETH_GetPMTFlagStatus(u32 flag)
+{
+    return (FlagStatus)(ETH->MACPMTCSR & flag);
+}
+
+void ETH_WakeUpFrameDetectionCmd(FunctionalState sta)
+{
+    sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE);
+}
+
+void ETH_MagicPacketDetectionCmd(FunctionalState sta)
+{
+    sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE);
+}
+
+void ETH_PowerDownCmd(FunctionalState sta)
+{
+    sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_PD) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+
+void ETH_MMCCounterFullPreset(void)
+{
+    ETH->MMCCR |= ETH_MMCCR_MCFHP | ETH_MMCCR_MCP;
+}
+
+void ETH_MMCCounterHalfPreset(void)
+{
+    ETH->MMCCR &= ~ETH_MMCCR_MCFHP;
+
+    ETH->MMCCR |= ETH_MMCCR_MCP;
+}
+
+void ETH_MMCCounterFreezeCmd(FunctionalState sta)
+{
+    sta ? (ETH->MMCCR |= ETH_MMCCR_MCF) : (ETH->MMCCR &= ~ETH_MMCCR_MCF);
+}
+
+void ETH_MMCResetOnReadCmd(FunctionalState sta)
+{
+    sta ? (ETH->MMCCR |= ETH_MMCCR_ROR) : (ETH->MMCCR &= ~ETH_MMCCR_ROR);
+}
+
+void ETH_MMCCounterRolloverCmd(FunctionalState sta)
+{
+    sta ? (ETH->MMCCR &= ~ETH_MMCCR_CSR) : (ETH->MMCCR |= ETH_MMCCR_CSR);
+}
+
+void ETH_MMCCountersReset(void)
+{
+    ETH->MMCCR |= ETH_MMCCR_CR;
+}
+
+void ETH_MMCITConfig(u32 it, FunctionalState sta)
+{
+    if (it & 0x10000000) {
+        it &= 0xEFFFFFFF;
+
+        sta ? (ETH->MMCRIMR &= ~it) : (ETH->MMCRIMR |= it);
+    }
+    else {
+        sta ? (ETH->MMCTIMR &= ~it) : (ETH->MMCTIMR |= it);
+    }
+}
+
+ITStatus ETH_GetMMCITStatus(u32 it)
+{
+    if (it & 0x10000000) {
+        return (ITStatus)((ETH->MMCRIR & it) && !(ETH->MMCRIMR & it));
+    }
+    else {
+        return (ITStatus)((ETH->MMCTIR & it) && !(ETH->MMCTIMR & it));
+    }
+}
+
+u32 ETH_GetMMCRegister(u32 reg)
+{
+    return *(vu32*)(ETH_BASE + reg);
+}

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c

@@ -0,0 +1,222 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_exti.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE EXTI FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_EXTI_C_
+
+// Files includes
+#include "hal_exti.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup EXTI_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup EXTI_Exported_Functions
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the EXTI peripheral registers to their default reset
+///         values.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the EXTI registers to their default reset values.
+/// @param  None.
+/// @retval None.
+/// @note   MEM_MODE bits are not affected by APB reset.
+/// @note   MEM_MODE bits took the value from the user option bytes.
+/// @note   CFGR2 register is not affected by APB reset.
+/// @note   CLABBB configuration bits are locked when set.
+/// @note   To unlock the configuration, perform a system reset.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_DeInit(void)
+{
+    u16 i;
+    // Clear all
+    exEXTI_LineDisable(~0x00000000);
+
+    // rc_w1
+    EXTI->PR = EXTI->PR;
+
+    // Set EXTI_CFGR1 register to reset value without affecting MEM_MODE bits
+    EXTI->CFGR &= EXTI_CFGR_MEMMODE;
+
+    // Set EXTICRx registers to reset value
+    for (i = 0; i < 4; i++) {
+        EXTI->CR[i] = 0;
+    }
+}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Selects the GPIO pin used as EXTI Line.
+/// @param  port_source_gpio: selects the GPIO port to be used as source for EXTI lines .
+/// @param  pin_source: specifies the EXTI line to be configured.
+/// @note   This parameter can be pin_source where x can be:
+///         For MCU: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOD.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_LineConfig(u8 port_source_gpio, u8 pin_source)
+{
+    EXTI->CR[pin_source >> 0x02] &= ~(0x0F << (0x04 * (pin_source & 0x03)));
+    EXTI->CR[pin_source >> 0x02] |= ((port_source_gpio) << (0x04 * (pin_source & 0x03)));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the EXTI peripheral according to the specified
+///         parameters in the init_struct.
+/// @param  init_struct: pointer to a EXTI_InitTypeDef structure that
+///         contains the configuration information for the EXTI peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_Init(EXTI_InitTypeDef* init_struct)
+{
+    if (init_struct->EXTI_LineCmd != DISABLE) {
+        EXTI->IMR  &= ~init_struct->EXTI_Line;
+        EXTI->EMR  &= ~init_struct->EXTI_Line;
+        if (init_struct->EXTI_Mode == EXTI_Mode_Interrupt) {
+            EXTI->IMR |= init_struct->EXTI_Line;
+        }
+        else {
+            EXTI->EMR |= init_struct->EXTI_Line;
+        }
+        EXTI->RTSR &= ~init_struct->EXTI_Line;
+        EXTI->FTSR &= ~init_struct->EXTI_Line;
+        if (init_struct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) {
+            EXTI->RTSR |= init_struct->EXTI_Line;
+            EXTI->FTSR |= init_struct->EXTI_Line;                               // Rising and Faling    afio
+        }
+        else if (init_struct->EXTI_Trigger == EXTI_Trigger_Rising) {
+            EXTI->RTSR |= init_struct->EXTI_Line;
+        }
+        else {
+            EXTI->FTSR |= init_struct->EXTI_Line;
+        }
+    }
+    else {
+        if (init_struct->EXTI_Mode == EXTI_Mode_Interrupt) {
+            EXTI->IMR &= ~init_struct->EXTI_Line;
+        }
+        else {
+            EXTI->EMR &= ~init_struct->EXTI_Line;
+        }
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its reset value.
+/// @param  init_struct: pointer to a EXTI_InitTypeDef structure which will
+///         be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_StructInit(EXTI_InitTypeDef* init_struct)
+{
+    init_struct->EXTI_Line    = EXTI_LineNone;
+    init_struct->EXTI_Mode    = EXTI_Mode_Interrupt;
+    init_struct->EXTI_Trigger = EXTI_Trigger_Falling;
+    init_struct->EXTI_LineCmd = DISABLE;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Generates a Software interrupt on selected EXTI line.
+/// @param  line: specifies the EXTI line on which the software interrupt
+///         will be generated.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_GenerateSWInterrupt(u32 line)
+{
+    EXTI->SWIER |= line;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified EXTI line flag is set or not.
+/// @param  line: specifies the EXTI line flag to check.
+/// @retval The new state of line (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus EXTI_GetFlagStatus(u32 line)
+{
+    return (EXTI->PR & line) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the EXTI's line pending flags.
+/// @param  line: specifies the EXTI lines flags to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_ClearFlag(u32 line)
+{
+    EXTI->PR = line;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified EXTI line is asserted or not.
+/// @param  line: specifies the EXTI line to check.
+/// @retval The new state of line (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus EXTI_GetITStatus(u32 line)
+{
+    return ((EXTI->PR & line) && (EXTI->IMR & line)) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the EXTI's line pending bits.
+/// @param  line: specifies the EXTI lines to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_ClearITPendingBit(u32 line)
+{
+    EXTI->PR = line;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  EXTI Line Disable
+/// @param  line: specifies the EXTI lines to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exEXTI_LineDisable(u32 line)
+{
+    EXTI->IMR  &= ~line;
+    EXTI->EMR  &= ~line;
+    EXTI->RTSR &= ~line;
+    EXTI->FTSR &= ~line;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the EXTI's line all pending bits.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+u32 exEXTI_GetAllFlagStatus(void)
+{
+    return EXTI->PR;
+}
+
+/// @}
+
+/// @}
+
+/// @}
+

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c

@@ -0,0 +1,548 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_flash.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE FLASH FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_FLASH_C_
+
+// Files includes
+#include "hal_flash.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup FLASH_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup FLASH_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the code latency value.
+/// @note   This function can be used for all MM32 devices.
+/// @param  latency: specifies the FLASH Latency value.
+///         This parameter can be one of the following values:
+/// @arg    FLASH_Latency_0: FLASH Zero Latency cycle
+/// @arg    FLASH_Latency_1: FLASH One Latency cycle
+/// @arg    FLASH_Latency_2: FLASH Two Latency cycles
+/// @arg    FLASH_Latency_3: FLASH Three Latency cycles
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_SetLatency(FLASH_Latency_TypeDef latency)
+{
+    FLASH->ACR = (FLASH->ACR & (~FLASH_ACR_LATENCY)) | latency;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Half cycle flash access.
+/// @note   This function can be used for all MM32 devices.
+/// @param  half_cycle_access: specifies the FLASH Half cycle Access mode.
+///         This parameter can be one of the following values:
+/// @arg    FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
+/// @arg    FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_HalfCycleAccessCmd(FLASH_HalfCycleAccess_TypeDef half_cycle_access)
+{
+    FLASH->ACR &= ~FLASH_ACR_HLFCYA;
+    FLASH->ACR |= half_cycle_access;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Prefetch Buffer.
+/// @note   This function can be used for all MM32 devices.
+/// @param  prefetch_buffer: specifies the Prefetch buffer status.
+///         This parameter can be one of the following values:
+/// @arg    FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
+/// @arg    FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_TypeDef prefetch_buffer)
+{
+    FLASH->ACR &= ~FLASH_ACR_PRFTBE;
+    FLASH->ACR |= prefetch_buffer;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Locks the FLASH Program Erase Controller.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_Lock(void)
+{
+    FLASH->CR |= FLASH_CR_LOCK;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Unlocks the FLASH Program Erase Controller.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_Unlock()
+{
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable to program the FLASH Option Byte.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_OPTB_Enable(void)
+{
+    FLASH->OPTKEYR = FLASH_KEY1;
+    FLASH->OPTKEYR = FLASH_KEY2;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Erases a specified FLASH page.
+/// @note   This function can be used for all MM32 devices.
+/// @param  page_address: The page address to be erased.
+/// @retval FLASH Status: The returned value can be: FLASH_BUSY,
+///         FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ErasePage(u32 page_address)
+{
+    FLASH->CR |= FLASH_CR_PER;
+    FLASH->AR = page_address;
+    FLASH->CR |= FLASH_CR_STRT;
+    return FLASH_WaitForLastOperation(EraseTimeout);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Erases all FLASH pages.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_EraseAllPages()
+{
+    FLASH->AR = FLASH_BASE;
+    FLASH->CR |= (FLASH_CR_MER | FLASH_CR_STRT);
+    return FLASH_WaitForLastOperation(EraseTimeout);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Erases the FLASH option bytes.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_EraseOptionBytes()
+{
+    FLASH_OPTB_Enable();
+    FLASH->AR = OB_BASE;
+    FLASH->CR |= (FLASH_CR_OPTER | FLASH_CR_STRT);
+    return FLASH_WaitForLastOperation(EraseTimeout);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Programs a half word at a specified address.
+/// @note   This function can be used for all MM32 devices.
+/// @param  address: specifies the address to be programmed.
+/// @param  data: specifies the data to be programmed.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ProgramHalfWord(u32 address, u16 data)
+{
+    FLASH->CR |= FLASH_CR_PG;
+
+    *(vu16*)address = data;
+
+
+    return FLASH_WaitForLastOperation(ProgramTimeout);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Programs a word at a specified address.
+/// @note   This function can be used for all MM32 devices.
+/// @param  address: specifies the address to be programmed.
+/// @param  data: specifies the data to be programmed.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ProgramWord(u32 address, u32 data)
+{
+    FLASH_Status ret = FLASH_ProgramHalfWord(address, data);
+    if (ret == FLASH_COMPLETE) {
+        ret = FLASH_ProgramHalfWord(address + 2, data >> 16);
+    }
+    return ret;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Programs a byte at a specified Option Byte Data address.
+/// @note   This function can be used for all MM32 devices.
+/// @param  address: specifies the address to be programmed.
+///         This parameter can be 0x1FFFF804 or 0x1FFFF806.
+/// @param  data: specifies the data to be programmed.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ProgramOptionByteData(u32 address, u8 data)
+{
+    FLASH_Status ret;
+    __IO u16 temp;
+    FLASH_OPTB_Enable();
+    FLASH->CR |= FLASH_CR_OPTPG;
+    temp = (u16)(~data);
+    temp = (temp << 8) & 0xFF00;
+    temp = temp | (u16)data;
+    address = address & (~0x1);
+    *(vu16*)address = temp;
+    ret = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    return ret;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Programs a half word at a specified Option Byte Data address.
+/// @note   This function can be used for all MM32 devices.
+/// @param  address: specifies the address to be programmed.
+///         This parameter can be 0x1FFFF804 or 0x1FFFF806.
+/// @param  data: specifies the data to be programmed.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ProgramOptionHalfWord(u32 address, u16 data)
+{
+    FLASH_Status ret;
+    FLASH_OPTB_Enable();
+    FLASH->CR |= FLASH_CR_OPTPG;
+    *(vu16*)address = data;
+    ret = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    return ret;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Read protection for the specified address
+/// @note   This function can be used for all MM32 devices.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ProgramProtect(u32 address, u16 data)
+{
+    return FLASH_ProgramOptionHalfWord(address, data);
+
+//    FLASH_Status ret;
+//  ret = FLASH_ProgramOptionHalfWord(address, 0x7F80);
+//
+//  if (ret == FLASH_COMPLETE) {
+//      ret = FLASH_ProgramOptionHalfWord(address + 2, 0xFF00);
+//    }
+//    return ret;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Write protection for the specified address
+/// @note   This function can be used for all MM32 devices.
+/// @param  page: specifies the address of the pages to be write
+///         protected.
+///         This parameter is (0x01 << ((Absolute address - 0x08000000)/0x1000))
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_EnableWriteProtection(u32 page)
+{
+    FLASH_Status ret;
+    u8           i;
+    for (i = 0; i < 4; i++) {
+        ret = FLASH_ProgramOptionHalfWord((OB_BASE + 8 + i * 2), ~(page >> (i * 8)));
+        if (ret != FLASH_COMPLETE) {
+            break;
+        }
+    }
+    return ret;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+/// @note   This function can be used for all MM32 devices.
+/// @param  ob_iwdg: Selects the IWDG mode
+/// @param  ob_stop: Reset event when entering STOP mode.
+/// @param  standby: Reset event when entering Standby mode.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_UserOptionByteConfig(OB_IWDG_TypeDef ob_iwdg, OB_STOP_TypeDef ob_stop, OB_STDBY_TypeDef standby)
+{
+    FLASH_OPTB_Enable();
+    FLASH->CR |= FLASH_CR_OPTPG;
+    OB->USER = ob_iwdg;
+    OB->USER |= ob_stop;
+    OB->USER |= standby;
+    OB->USER |= 0xF8;
+    //    OB->USER = iwdg | stop | stdby | 0xF8;
+    return FLASH_WaitForLastOperation(ProgramTimeout);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the FLASH User Option Bytes values.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+///         and RST_STDBY(Bit2).
+////////////////////////////////////////////////////////////////////////////////
+u32 FLASH_GetUserOptionByte()
+{
+    return (FLASH->OBR >> 2);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the FLASH Write Protection Option Bytes Register value.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval The FLASH Write Protection  Option Bytes Register value.
+////////////////////////////////////////////////////////////////////////////////
+u32 FLASH_GetWriteProtectionOptionByte()
+{
+    return (FLASH->WRPR);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the FLASH Prefetch Buffer status is set or not.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval FLASH Prefetch Buffer Status (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus FLASH_GetPrefetchBufferStatus(void)
+{
+    return (FLASH->ACR & FLASH_ACR_PRFTBS) ? SET : RESET;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified FLASH interrupts.
+/// @note   This function can be used for all MM32 devices.
+/// @param  interrupt: specifies the FLASH interrupt sources to be enabled or
+///         disabled.
+/// @param  state: new state of the specified Flash interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_ITConfig(FLASH_IT_TypeDef interrupt, FunctionalState state)
+{
+    (state) ? (FLASH->CR |= interrupt) : (FLASH->CR &= ~interrupt);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified FLASH flag is set or not.
+/// @note   This function can be used for all MM32 devices.
+/// @param  flag: specifies the FLASH flags to clear.
+///         This parameter can be one of the following values:
+/// @arg    FLASH_FLAG_BSY: FLASH Busy flag
+/// @arg    FLASH_FLAG_PGERR: FLASH Program error flag
+/// @arg    FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
+/// @arg    FLASH_FLAG_EOP: FLASH End of Operation flag
+/// @arg    FLASH_FLAG_OPTERR:  FLASH Option Byte error flag
+/// @retval The new state of FLASH_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus FLASH_GetFlagStatus(u16 flag)
+{
+    return ((flag == FLASH_FLAG_OPTERR) ? (FLASH->OBR & FLASH_FLAG_OPTERR) : (FLASH->SR & flag)) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the FLASH's pending flags.
+/// @note   This function can be used for all MM32 devices.
+/// @param  flag: specifies the FLASH flags to clear.
+///         This parameter can be any combination of the following values:
+/// @arg    FLASH_FLAG_PGERR: FLASH Program error flag
+/// @arg    FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
+/// @arg    FLASH_FLAG_EOP: FLASH End of Operation flag
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_ClearFlag(u16 flag)
+{
+    FLASH->SR = flag;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the FLASH Status.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval FLASH Status: The returned value can be: FLASH_BUSY,
+///         FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_GetStatus()
+{
+    return (FLASH_Status)((FLASH->SR & FLASH_FLAG_BSY))
+           ? FLASH_BUSY
+           : ((FLASH->SR & FLASH_FLAG_PGERR) ? FLASH_ERROR_PG
+              : ((FLASH->SR & FLASH_FLAG_WRPRTERR) ? FLASH_ERROR_WRP : FLASH_COMPLETE));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Waits for a Flash operation to complete or a TIMEOUT to occur.
+/// @note   This function can be used for all MM32 devices
+/// @param  time_out: FLASH programming time_out
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_WaitForLastOperation(u32 time_out)
+{
+    u32          i;
+    FLASH_Status ret;
+    do {
+        ret = FLASH_GetStatus();
+        time_out--;
+        for (i = 0xFF; i != 0; i--)
+            ;
+    } while ((ret == FLASH_BUSY) && (time_out != 0x00));
+
+    FLASH->CR = 0;
+    FLASH->SR = FLASH_SR_EOP | FLASH_SR_WRPRTERR | FLASH_SR_PGERR;
+    return (FLASH_Status)((time_out == 0x00) ? FLASH_TIMEOUT : ret);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Erases a specified FLASH page.
+/// @note   This function can be used for all MM32 devices.
+/// @param  Page_Address: The page address to be erased.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exFLASH_EraseEE(u32 page_address)
+{
+    FLASH_Unlock();
+    FLASH_ErasePage(page_address);
+    FLASH_Lock();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Programs a buffer at a specified address.
+/// @note   This function can be used for all MM32 devices.
+/// @param *buf: the pointer of the buffer to be programmed.
+/// @param  addr: specifies the address to be programmed.
+/// @param  len: the number of bytes in the buffer.
+///         This parameter can only be even.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exFLASH_ProgramEE(u16* buf, u32 addr, u16 len)
+{
+    u16 i;
+    FLASH_Unlock();
+    for (i = 0; i < len / 2; i++) {
+        FLASH_ProgramHalfWord(addr, *buf);
+        addr += 2;
+        buf++;
+    }
+    FLASH_Lock();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Determine if the data that at the ptr address with the length is len
+///         is empty.
+/// @note   This function can be used for all MM32 devices.
+/// @param *ptr: the pointer of the starting address.
+/// @param  len: the number of bytes.
+///         This parameter can only be even.
+/// @retval 1 presents the data is empty,
+///         0 presents the data has been written.
+////////////////////////////////////////////////////////////////////////////////
+u8 exFLASH_FindEmpty(u16* ptr, u16 len)
+{
+    u16 i;
+    for (i = 0; i < (len / 2); i++) {
+        if (*(ptr + i) != 0xffff)
+            return 0;
+    }
+    return 1;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Locate the writable area on the specified address.
+/// @note   This function can be used for all MM32 devices.
+/// @param  page_address: specifies the beginning of the EEprom.
+///         The EEprom can be some continuously pages in the flash.
+/// @param  len: the number of bytes to be written.
+///         This parameter can only be even.
+/// @retval the pointer of the starting address.
+////////////////////////////////////////////////////////////////////////////////
+void* exFLASH_Locate(u32 page_address, u16 len)
+{
+    u16 i;
+    u16* ptr = (u16*)page_address;
+    for (i = 0; i < (0x0800 / len); i++) {
+        if (exFLASH_FindEmpty(ptr, len)) {
+            if (i == 0)
+                return 0;
+            break;
+        }
+        ptr += len / 2;
+    }
+    return ptr;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Programs a buffer at a specified address.
+/// @note   This function can be used for all MM32 devices.
+/// @param *buf: the pointer of the buffer to be programmed.
+/// @param  page_address: specifies the beginning of the EEprom.
+///         The EEprom can be some continuously pages in the flash.
+/// @param  len: the number of bytes in the buffer.
+///         This parameter can only be even.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exFLASH_WriteEE(u16* buf, u32 page_address, u16 len)
+{
+    u16* ptr = exFLASH_Locate(page_address, len);
+    if (ptr == 0) {
+        exFLASH_EraseEE(page_address + 0x000);
+        exFLASH_EraseEE(page_address + 0x400);
+        exFLASH_ProgramEE(buf, page_address, len);
+    }
+    else {
+        if (ptr == (u16*)(page_address + ((0x0400 / len) - 1) * len)) {
+            exFLASH_EraseEE(page_address + 0x400);
+            exFLASH_ProgramEE(buf, (u32)ptr, len);
+        }
+        else if (ptr == (u16*)(page_address + 0x0800)) {
+            exFLASH_EraseEE(page_address + 0x000);
+            exFLASH_ProgramEE(buf, (u32)page_address, len);
+        }
+        else {
+            exFLASH_ProgramEE(buf, (u32)ptr, len);
+        }
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Read the beginning address of the last written data.
+/// @note   This function can be used for all MM32 devices.
+/// @param  page_address: specifies the beginning of the EEprom.
+///         The EEprom can be some continuously pages in the flash.
+/// @param  len: the number of bytes have been written.
+///         This parameter can only be even.
+/// @retval the beginning address of the last written data.
+///         0 presents that this is the first time to use this as EEprom.
+////////////////////////////////////////////////////////////////////////////////
+void* exFLASH_ReadEE(u32 page_address, u16 len)
+{
+    u16* ptr = exFLASH_Locate(page_address, len);
+    return (ptr == 0) ? 0 : (ptr - len / 2);
+}
+
+/// @}
+
+/// @}
+
+/// @}

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c

@@ -0,0 +1,124 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_fsmc.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE FSMC FIRMWARE FUNCTIONS.
+///                Interface with SRAM, PSRAM, NOR memories
+///                Interrupts and flags management
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_FSMC_C_
+
+// Files includes
+#include "reg_rcc.h"
+#include "reg_syscfg.h"
+#include "hal_fsmc.h"
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup FSMC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup FSMC_Exported_Functions
+/// @{
+
+
+void FSMC_NORSRAMStructInit(FSMC_InitTypeDef* init_struct)
+{
+    init_struct->FSMC_Mode = FSMC_Mode_NorFlash;
+    init_struct->FSMC_AddrDataMode = FSMC_AddrDataDeMUX;
+
+    init_struct->FSMC_TimingRegSelect = FSMC_TimingRegSelect_0;
+    init_struct->FSMC_MemSize = FSMC_MemSize_64MB;
+    init_struct->FSMC_MemType = FSMC_MemType_NorSRAM;
+}
+void FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef* init_struct)
+{
+
+    init_struct->FSMC_SMReadPipe    = 0;
+    init_struct->FSMC_ReadyMode     = 0;
+    init_struct->FSMC_WritePeriod   = 0x2;
+    init_struct->FSMC_WriteHoldTime = 1;
+    init_struct->FSMC_AddrSetTime   = 3;
+    init_struct->FSMC_ReadPeriod    = 0x1;
+    init_struct->FSMC_DataWidth     = FSMC_DataWidth_16bits;
+}
+void FSMC_NORSRAMInit(FSMC_InitTypeDef* init_struct)
+{
+    SYSCFG->CFGR &= ~(SYSCFG_CFGR_FSMC_MODE | SYSCFG_CFGR_FSMC_AF_ADDR | SYSCFG_CFGR_FSMC_SYNC_EN);
+    SYSCFG->CFGR |= (u32)init_struct->FSMC_Mode | \
+                    (u32)init_struct->FSMC_AddrDataMode;
+
+    FSMC->SMSKR = (u32)init_struct->FSMC_TimingRegSelect | \
+                  (u32)init_struct->FSMC_MemSize | \
+                  (u32)init_struct->FSMC_MemType;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initialize the FSMC_NORSRAM Timing according to the specified
+///         parameters in the FSMC_NORSRAM_TimingTypeDef
+/// @param  FSMC_Bank_InitStruct: Timing Pointer to NORSRAM Timing structure
+/// @param  Bank: NORSRAM bank number
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_TypeDef bank)
+{
+    // Set FSMC_NORSRAM device timing parameters
+    if(bank == FSMC_NORSRAM_BANK0) {
+        FSMC->SMTMGR_SET0 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos)    | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos)     | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos)   | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos)  | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos)    | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
+        FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET0;
+        FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos;
+    }
+    else if(bank == FSMC_NORSRAM_BANK1) {
+        FSMC->SMTMGR_SET1 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos)    | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos)     | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos)   | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos)  | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos)    | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
+        FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET1;
+        FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos;
+    }
+    else if(bank == FSMC_NORSRAM_BANK2) {
+        FSMC->SMTMGR_SET2 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos)    | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos)     | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos)   | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos)  | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos)    | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
+        FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET2;
+        FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos;
+    }
+}
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c

@@ -0,0 +1,344 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_gpio.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE GPIO FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_GPIO_C_
+
+// Files includes
+#include "reg_exti.h"
+#include "hal_rcc.h"
+#include "hal_gpio.h"
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup GPIO_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup GPIO_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the gpio peripheral registers to their default reset
+///         values.
+/// @param  gpio: select the GPIO peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_DeInit(GPIO_TypeDef* gpio)
+{
+    switch (*(vu32*)&gpio) {
+        case (u32)GPIOA:
+            RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, DISABLE);
+            break;
+        case (u32)GPIOB:
+            RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOB, DISABLE);
+            break;
+        case (u32)GPIOC:
+            RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOC, DISABLE);
+            break;
+        case (u32)GPIOD:
+            RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOD, DISABLE);
+            break;
+        case (u32)GPIOE:
+            RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOE, DISABLE);
+            break;
+        default:
+            break;
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the Alternate Functions (remap, event control
+///         and EXTI configuration) registers to their default reset values.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_AFIODeInit()
+{
+    GPIOA->AFRL = 0xFFFFFFFF;
+    GPIOA->AFRH = 0xF00FFFFF;       //  PA14:SWCLK, PA13:PSWDIO
+    GPIOB->AFRL = 0xFFFFFFFF;
+    GPIOB->AFRH = 0xFFFFFFFF;
+    GPIOC->AFRL = 0xFFFFFFFF;
+    GPIOC->AFRH = 0xFFFFFFFF;
+    GPIOD->AFRL = 0xFFFFFFFF;
+    GPIOD->AFRH = 0xFFFFFFFF;
+    GPIOE->AFRL = 0xFFFFFFFF;
+    GPIOE->AFRH = 0xFFFFFFFF;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the gpio peripheral according to the specified
+///         parameters in the init_struct.
+/// @param  gpio: select the GPIO peripheral.
+/// @param  init_struct: pointer to a GPIO_InitTypeDef structure that
+///         contains the configuration information for the specified GPIO
+///         peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_Init(GPIO_TypeDef* gpio, GPIO_InitTypeDef* init_struct)
+{
+    u8   idx;
+    u8 i;
+    u32 tmp;
+    __IO u32* reg ;
+
+    // 1x
+    u32 dat = init_struct->GPIO_Mode & 0x0F;
+    if (init_struct->GPIO_Mode & 0x10)
+        dat |= init_struct->GPIO_Speed;
+
+    // 0x
+    reg  = &gpio->CRL;
+    for (i = 0; i < 8; i++) {
+        idx = i * 4;
+        if ((init_struct->GPIO_Pin) & (1 << i)) {
+            *reg  = (*reg  & ~(0xF << idx)) | (dat << idx);
+        }
+    }
+
+    reg     = &gpio->CRH;
+    tmp = init_struct->GPIO_Pin >> 8;
+    for (i = 0; i < 8; i++) {
+        idx = i * 4;
+        if (tmp & (1 << i)) {
+            *reg  = (*reg  & ~(0xF << idx)) | (dat << idx);
+        }
+    }
+
+    // 2x,4x
+    if (init_struct->GPIO_Mode == GPIO_Mode_IPD)
+        gpio->BRR |= init_struct->GPIO_Pin;
+    else if (init_struct->GPIO_Mode == GPIO_Mode_IPU)
+        gpio->BSRR |= init_struct->GPIO_Pin;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param init_struct : pointer to a GPIO_InitTypeDef structure
+///   which will be initialized.
+/// @retval : None
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_StructInit(GPIO_InitTypeDef* init_struct)
+{
+    // Reset GPIO init structure parameters values
+    init_struct->GPIO_Pin  = GPIO_Pin_All;
+    init_struct->GPIO_Speed = GPIO_Speed_2MHz;
+    init_struct->GPIO_Mode = GPIO_Mode_FLOATING;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reads the input data of specified GPIO port pin.
+/// @param  gpio:  select the GPIO peripheral.
+/// @param  pin:  specifies the port pin to be read.
+///         This parameter can be GPIO_Pin_x where x can be (0..15).
+/// @retval The input port pin value.
+////////////////////////////////////////////////////////////////////////////////
+bool GPIO_ReadInputDataBit(GPIO_TypeDef* gpio, u16 pin)
+{
+    return ((gpio->IDR & pin)) ? Bit_SET : Bit_RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reads all GPIO port pins input data.
+/// @param  gpio: select the GPIO peripheral.
+/// @retval GPIO port input data value.
+////////////////////////////////////////////////////////////////////////////////
+u16 GPIO_ReadInputData(GPIO_TypeDef* gpio)
+{
+    return gpio->IDR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reads the output data of specified GPIO port pin.
+/// @param  gpio: select the GPIO peripheral.
+/// @param  pin:  specifies the port bit to be read.
+///         This parameter can be GPIO_Pin_x where x can be (0..15).
+/// @retval The output port pin value.
+////////////////////////////////////////////////////////////////////////////////
+bool GPIO_ReadOutputDataBit(GPIO_TypeDef* gpio, u16 pin)
+{
+    return (gpio->ODR & pin) ? Bit_SET : Bit_RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reads all GPIO port pins output data.
+/// @param  gpio: select the GPIO peripheral.
+/// @retval GPIO port output data value.
+////////////////////////////////////////////////////////////////////////////////
+u16 GPIO_ReadOutputData(GPIO_TypeDef* gpio)
+{
+    return gpio->ODR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the selected GPIO port pin.
+/// @param  gpio: where x can be (A..D) to select the GPIO peripheral.
+/// @param  pin: specifies the port pins to be written.
+///         This parameter can be any combination of GPIO_Pin_x where x can be
+///         (0..15).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_SetBits(GPIO_TypeDef* gpio, u16 pin)
+{
+    gpio->BSRR = pin;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the selected GPIO port bit.
+/// @param  gpio: where x can be (A..D) to select the GPIO peripheral.
+/// @param  pin: specifies the port pins to be written.
+///         This parameter can be any combination of GPIO_Pin_x where x can be
+///         (0..15).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_ResetBits(GPIO_TypeDef* gpio, u16 pin)
+{
+    gpio->BRR = pin;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets or clears the selected GPIO port pin.
+/// @param  gpio: select the GPIO peripheral.
+/// @param  pin: specifies the port bit to be written.
+///         This parameter can be one of GPIO_Pin_x where x can be (0..15).
+/// @param  value: specifies the value to be written to the selected bit.
+///         This parameter can be one of the BitAction enum values:
+/// @arg    Bit_RESET: to clear the port pin
+/// @arg    Bit_SET: to set the port pin
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_WriteBit(GPIO_TypeDef* gpio, u16 pin, BitAction value)
+{
+    (value) ? (gpio->BSRR = pin) : (gpio->BRR = pin);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Writes data to all GPIO port pins.
+/// @param  gpio: where x can be (A..D) to select the GPIO peripheral.
+/// @param  value: specifies the value to be written to the port output data
+///         register.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_Write(GPIO_TypeDef* gpio, u16 value)
+{
+    gpio->ODR = value;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Locks GPIO Pins configuration.
+/// @param  gpio: to select the GPIO peripheral.
+/// @param  pin: specifies the port bit to be written.
+///         This parameter can be any combination of GPIO_Pin_x where x can be
+///         (0..15).
+/// @param  state: new lock state of the port pin.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_PinLock(GPIO_TypeDef* gpio, u16 pin, FunctionalState state)
+{
+    (state) ? (gpio->LCKR |= pin) : (gpio->LCKR &= ~pin);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Locks GPIO Pins configuration registers until next system reset.
+/// @param  gpio: to select the GPIO peripheral.
+/// @param  pin: specifies the port bit to be written.
+///         This parameter can be any combination of GPIO_Pin_x where x can be
+///         (0..15).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_PinLockConfig(GPIO_TypeDef* gpio, u16 pin)
+{
+    gpio->LCKR = GPIO_LCKR_LCKK | pin;
+    gpio->LCKR = pin;
+    gpio->LCKR = GPIO_LCKR_LCKK | pin;
+    gpio->LCKR;
+    gpio->LCKR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the port pin remapping.
+/// @param  remap: selects the pin to remap.
+/// @param  mask: the corresponding remapping mask of the remapping pin.
+/// @param  state: new state of the port pin remapping.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Writes data to the specified GPIO data port.
+/// @param  gpio: select the GPIO peripheral.
+/// @param  pin: specifies the pin for the Alternate function.
+///         This parameter can be GPIO_PinSourcex where x can be (0..15) for
+///         GPIOA, GPIOB, GPIOD and (0..12) for GPIOC .
+/// @param  alternate_function: selects the pin to used as Alternate function.
+///         This parameter can be the GPIO_AF_x where x can be (0..7).
+/// @note   The pin should be used for Digital IP.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_PinAFConfig(GPIO_TypeDef* gpio, u8 pin, u8 alternate_function)
+{
+    u8 shift = (pin & 0x07) * 4;
+    u32* ptr = (pin < 8) ? (u32*)&gpio->AFRL : (u32*)&gpio->AFRH;
+    *ptr = (*ptr & ~(0x0F << shift)) | (alternate_function << shift);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the remap function and AF function of the GPIO pin.
+/// @param  gpio:select the GPIO peripheral.
+/// @param  pin: specifies the pin for the Alternate function.
+///         This parameter can be GPIO_Pin_x where x can be (0..15) for
+///         GPIOA, GPIOB, GPIOD and (0..12) for GPIOC .
+/// @param  remap: selects the pin to remap.
+/// @param  alternate_function: selects the pin to used as Alternate function.
+///         This parameter can be the GPIO_AF_x where x can be (0..7).
+/// @note   The pin should be used for Digital IP.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exGPIO_PinAFConfig(GPIO_TypeDef* gpio, u16 pin, s32 remap, s8 alternate_function)
+{
+    u8 i;
+    u8 shift;
+    u32* ptr;
+
+    if (alternate_function >= 0) {
+        for (i = 0; i < 32; i++) {
+            if (pin & 0x01) {
+                pin = i;
+                break;
+            }
+            pin >>= 1;
+        }
+
+        shift = (pin & 0x07) * 4;
+        ptr = (pin < 8) ? (u32*)&gpio->AFRL : (u32*)&gpio->AFRH;
+        *ptr = (*ptr & ~(0x0F << shift)) | (alternate_function << shift);
+    }
+}
+
+
+/// @}
+
+/// @}
+
+/// @}
+

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c

@@ -0,0 +1,526 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_i2c.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE I2C FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_I2C_C_
+
+// Files includes
+#include "hal_i2c.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup I2C_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup I2C_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the i2c peripheral registers to their default
+///         reset values.
+/// @param  i2c: where n can be 1 or 2 to select the I2C peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_DeInit(I2C_TypeDef* i2c)
+{
+    switch (*(vu32*)&i2c) {
+        case (u32)I2C1:  // I2C1_BASE:
+            exRCC_APB1PeriphReset(RCC_APB1ENR_I2C1);
+            break;
+        case (u32)I2C2:  // I2C2_BASE:
+            exRCC_APB1PeriphReset(RCC_APB1ENR_I2C2);
+            break;
+        default:
+            break;
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the i2c peripheral according to the specified
+///         parameters in the init_struct.
+/// @param  i2c: select the I2C peripheral.
+/// @param  init_struct: pointer to a I2C_InitTypeDef structure that
+///         contains the configuration information for the specified
+///         I2C peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_Init(I2C_TypeDef* i2c, I2C_InitTypeDef* init_struct)
+{
+    u32 pclk1         = HSI_VALUE;
+    u32 minSclLowTime = 0;
+    u32 i2cPeriod     = 0;
+    u32 pclk1Period   = 0;
+
+
+    i2c->IC_ENABLE &= ~I2C_ENR_ENABLE;
+
+
+    pclk1       = RCC_GetPCLK1Freq();
+    pclk1Period = 1000000000 / pclk1;
+    i2cPeriod   = 1000000000 / init_struct->I2C_ClockSpeed;
+
+    minSclLowTime = pclk1 / init_struct->I2C_ClockSpeed ;
+    i2cPeriod = 82 / pclk1Period;
+
+    if (init_struct->I2C_ClockSpeed <= 100000) {
+        i2c->IC_SS_SCL_LCNT = (minSclLowTime - 13 - i2cPeriod) / 2;
+        i2c->IC_SS_SCL_HCNT = (minSclLowTime - 13 - i2cPeriod - i2c->IC_SS_SCL_LCNT);
+    }
+    else {
+        i2c->IC_FS_SCL_LCNT = (minSclLowTime - 13 - i2cPeriod ) / 2 + 4;
+        i2c->IC_FS_SCL_HCNT = (minSclLowTime - 13 - i2c->IC_FS_SCL_LCNT - i2cPeriod);
+    }
+
+    i2c->IC_CON &= ~(I2C_CR_EMPINT     |   \
+                     I2C_CR_SLAVEDIS   |   \
+                     I2C_CR_REPEN      |   \
+                     I2C_CR_MASTER10   |   \
+                     I2C_CR_SLAVE10    |   \
+                     I2C_CR_FAST       |   \
+                     I2C_CR_MASTER);
+
+    i2c->IC_CON =  I2C_CR_EMPINT       |   \
+                   I2C_CR_REPEN        |   \
+                   ((init_struct->I2C_Speed == I2C_CR_FAST) ? I2C_CR_FAST : I2C_CR_STD) | \
+                   ((init_struct->I2C_Mode)  ? I2C_CR_MASTER : 0x00);
+    i2c->IC_INTR_MASK &= INTR_MASK;
+
+    i2c->IC_RX_TL = 0x00;
+    i2c->IC_TX_TL = 0x00;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param  init_struct: pointer to an I2C_InitTypeDef structure
+///         which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_StructInit(I2C_InitTypeDef* init_struct)
+{
+    init_struct->I2C_Mode       = I2C_CR_MASTER;
+    init_struct->I2C_OwnAddress = I2C_OWN_ADDRESS;
+    init_struct->I2C_Speed      = I2C_CR_STD;
+    init_struct->I2C_ClockSpeed = 100000;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified I2C peripheral.
+/// @param  i2c: select the I2C peripheral.
+/// @param  state: new state of the i2c peripheral. This parameter
+///         can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_Cmd(I2C_TypeDef* i2c, FunctionalState state)
+{
+    (state) ? (i2c->IC_ENABLE |= I2C_ENR_ENABLE) : (i2c->IC_ENABLE &= ~I2C_ENR_ENABLE);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified I2C DMA requests.
+/// @param  i2c: select the I2C peripheral.
+/// @param  state: new state of the I2C DMA transfer.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_DMACmd(I2C_TypeDef* i2c, FunctionalState state)
+{
+    if (state) {
+        if (I2C_DMA_DIR == TDMAE_SET)
+            i2c->IC_DMA_CR |= TDMAE_SET;
+
+        else
+            i2c->IC_DMA_CR |= RDMAE_SET;
+    }
+    else
+        i2c->IC_DMA_CR &= ~(I2C_DMA_RXEN | I2C_DMA_TXEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Generates i2c communication START condition.
+/// @param  i2c: select the I2C peripheral.
+/// @param  state: new state of the I2C START condition generation.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_GenerateSTART(I2C_TypeDef* i2c, FunctionalState state)
+{
+    (state) ? (i2c->IC_CON |= I2C_CR_REPEN) : (i2c->IC_CON &= ~I2C_CR_REPEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Generates i2c communication STOP condition.
+/// @param  i2c: select the I2C peripheral.
+/// @param  state: new state of the I2C STOP condition generation.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_GenerateSTOP(I2C_TypeDef* i2c, FunctionalState state)
+{
+    u16 overTime = 3000;
+
+    i2c->IC_ENABLE |= I2C_ENR_ABORT;
+
+    while (i2c->IC_ENABLE & I2C_ENR_ABORT) {
+        if (overTime-- == 0)
+            break;
+    }
+    i2c->IC_CLR_TX_ABRT;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the specified I2C own address2.
+/// @param  i2c: select the I2C peripheral.
+/// @param  addr: specifies the 7bit I2C own address2.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_OwnAddress2Config(I2C_TypeDef* i2c, u8 addr)
+{
+    MODIFY_REG(i2c->IC_TAR, (u16)I2C_TAR_ADDR, (u16)(addr >> 1));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified I2C dual addressing mode.
+/// @param  i2c: select the I2C peripheral.
+/// @param  state: new state of the I2C dual addressing mode.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_DualAddressCmd(I2C_TypeDef* i2c, FunctionalState state)
+{
+    (state) ? (i2c->IC_TAR |= IC_TAR_ENDUAL_Set) : (i2c->IC_TAR &= IC_TAR_ENDUAL_Reset);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified I2C general call feature.
+/// @param  i2c: select the I2C peripheral.
+/// @param  state: new state of the I2C General call.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_GeneralCallCmd(I2C_TypeDef* i2c, FunctionalState state)
+{
+    (state) ? (i2c->IC_TAR |= I2C_TAR_SPECIAL) : (i2c->IC_TAR &= ~I2C_TAR_SPECIAL);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified I2C interrupts.
+/// @param  i2c: select the I2C peripheral.
+/// @param  it: specifies the I2C interrupts sources to be enabled
+///         or disabled.
+///         This parameter can be any combination of the following values:
+/// @arg    I2C_IT_RX_UNDER   : Rx Buffer is empty interrupt mask
+/// @arg    I2C_IT_RX_OVER    : RX  Buffer Overrun interrupt mask
+/// @arg    I2C_IT_RX_FULL    : Rx buffer full interrupt mask
+/// @arg    I2C_IT_TX_OVER    : TX  Buffer Overrun interrupt mask
+/// @arg    I2C_IT_TX_EMPTY   : TX_FIFO empty interrupt mask
+/// @arg    I2C_IT_RD_REQ     : I2C work as slave or master interrupt mask
+/// @arg    I2C_IT_TX_ABRT    : TX error interrupt  mask(Master mode)
+/// @arg    I2C_IT_RX_DONE    : Master not ack interrupt mask(slave mode)
+/// @arg    I2C_IT_ACTIVITY   : I2C activity interrupt mask
+/// @arg    I2C_IT_STOP_DET   : stop condition  interrupt mask
+/// @arg    I2C_IT_START_DET  : start condition  interrupt mask
+/// @arg    I2C_IT_GEN_CALL   : a general call address and ack interrupt mask
+/// @param  state: new state of the specified I2C interrupts.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_ITConfig(I2C_TypeDef* i2c, u16 it, FunctionalState state)
+{
+    if (it == I2C_IT_RX_FULL)
+        I2C_ReadCmd(i2c);
+    (state) ? SET_BIT(i2c->IC_INTR_MASK, it) : CLEAR_BIT(i2c->IC_INTR_MASK, (u16)it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sends a data byte through the i2c peripheral.
+/// @param  i2c: select the I2C peripheral.
+/// @param  dat: Byte to be transmitted..
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_SendData(I2C_TypeDef* i2c, u8 dat)
+{
+    i2c->IC_DATA_CMD = dat;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the most recent received data by the i2c peripheral.
+/// @param  i2c: select the I2C peripheral.
+/// @retval The value of the received data.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_ReadCmd(I2C_TypeDef* i2c)
+{
+    i2c->IC_DATA_CMD = I2C_DR_CMD;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the most recent received data by the i2c peripheral.
+/// @param  i2c: select the I2C peripheral.
+/// @retval The value of the received data.
+////////////////////////////////////////////////////////////////////////////////
+u8 I2C_ReceiveData(I2C_TypeDef* i2c)
+{
+    I2C_CMD_DIR = 0;
+    return (u8)i2c->IC_DATA_CMD;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Transmits the address byte to select the slave device.
+/// @param  i2c: select the I2C peripheral.
+/// @param  addr: specifies the slave address which will be transmitted
+/// @param  dir: specifies whether the I2C device will be a
+///   Transmitter or a Receiver.
+///   This parameter can be one of the following values
+/// @arg  I2C_Direction_Transmitter: Transmitter mode
+/// @arg  I2C_Direction_Receiver: Receiver mode
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_Send7bitAddress(I2C_TypeDef* i2c, u8 addr, u8 dir)
+{
+    i2c->IC_TAR = addr >> 1;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reads the specified I2C register and returns its value.
+/// @param  i2c: select the I2C peripheral.
+/// @param  reg: specifies the register to read.
+///         This parameter can be one of the following values:
+/// @retval The value of the read register.
+////////////////////////////////////////////////////////////////////////////////
+u16 I2C_ReadRegister(I2C_TypeDef* i2c, u8 reg)
+{
+    return (*(vu16*)(*((u32*)&i2c) + reg));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the last i2c Event.
+/// @param  i2c: select the I2C peripheral.
+/// @retval The last event
+////////////////////////////////////////////////////////////////////////////////
+u32 I2C_GetLastEvent(I2C_TypeDef* i2c)
+{
+    return (u32)i2c->IC_RAW_INTR_STAT & FLAG_Mask;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the last i2c Event is equal to the one passed
+///   as parameter.
+/// @param  i2c: select the I2C peripheral.
+/// @param  event: specifies the event to be checked.
+///   This parameter can be one of the following values:
+/// @arg  I2C_EVENT_RX_UNDER : Rx Buffer is empty event
+/// @arg  I2C_EVENT_RX_OVER  : RX  Buffer Overrun event
+/// @arg  I2C_EVENTT_RX_FULL : Rx buffer full event
+/// @arg  I2C_EVENT_TX_OVER  : TX  Buffer Overrun event
+/// @arg  I2C_EVENT_TX_EMPTY : TX_FIFO empty event
+/// @arg  I2C_EVENT_RD_REQ   : I2C work as slave or master event
+/// @arg  I2C_EVENT_TX_ABRT  : TX error event(Master mode)
+/// @arg  I2C_EVENT_RX_DONE  : Master not ack event(slave mode)
+/// @arg  I2C_EVENT_ACTIVITY : I2C activity event
+/// @arg  I2C_EVENT_STOP_DET : stop condition  event
+/// @arg  I2C_EVENT_START_DET: start condition  event
+/// @arg  I2C_EVENT_GEN_CALL : a general call address and ack event
+/// - SUCCESS: Last event is equal to the I2C_EVENT
+/// - ERROR: Last event is different from the I2C_EVENT
+////////////////////////////////////////////////////////////////////////////////
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* i2c, u32 event)
+{
+    if ((event == I2C_EVENT_RX_FULL) && (I2C_CMD_DIR == 0)) {
+        i2c->IC_DATA_CMD = I2C_DR_CMD;
+        I2C_CMD_DIR       = 1;
+    }
+
+    return (ErrorStatus)((i2c->IC_RAW_INTR_STAT & event) == event);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified I2C flag is set or not.
+/// @param  i2c: select the I2C peripheral.
+/// @param  flag: specifies the flag to check.
+///   This parameter can be one of the following values:
+/// @arg  I2C_FLAG_RX_UNDER : Rx Buffer is empty flag
+/// @arg  I2C_FLAG_RX_OVER  : RX  Buffer Overrun flag
+/// @arg  I2C_FLAG_RX_FULL  : Rx buffer full flag
+/// @arg  I2C_FLAG_TX_OVER  : TX  Buffer Overrun flag
+/// @arg  I2C_FLAG_TX_EMPTY : TX_FIFO empty flag
+/// @arg  I2C_FLAG_RD_REQ   : I2C work as slave or master flag
+/// @arg  I2C_FLAG_TX_ABRT  : TX error flag(Master mode)
+/// @arg  I2C_FLAG_RX_DONE  : Master not ack flag(slave mode)
+/// @arg  I2C_FLAG_ACTIVITY : I2C activity flag
+/// @arg  I2C_FLAG_STOP_DET : stop condition  flag
+/// @arg  I2C_FLAG_START_DET: start condition  flag
+/// @arg  I2C_FLAG_GEN_CALL : a general call address and ack flag
+/// @retval The new state of I2C_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* i2c, u32 flag)
+{
+    if (flag & 0x8000)
+        return ((i2c->IC_STATUS & flag) ? SET : RESET);
+
+    if ((flag == I2C_FLAG_RX_FULL) && (I2C_CMD_DIR == 0)) {
+        i2c->IC_DATA_CMD = I2C_DR_CMD;
+        I2C_CMD_DIR       = 1;
+    }
+    return (((i2c->IC_RAW_INTR_STAT & flag)) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the i2c's pending flags.
+/// @param  i2c: select the I2C peripheral.
+/// @param  flag: specifies the flag to clear.
+///   This parameter can be any combination of the following values:
+/// @arg  I2C_FLAG_RX_UNDER : Rx Buffer is empty flag
+/// @arg  I2C_FLAG_RX_OVER  : RX  Buffer Overrun flag
+/// @arg  I2C_FLAG_RX_FULL  : Rx buffer full flag
+/// @arg  I2C_FLAG_TX_OVER  : TX  Buffer Overrun flag
+/// @arg  I2C_FLAG_TX_EMPTY : TX_FIFO empty flag
+/// @arg  I2C_FLAG_RD_REQ   : I2C work as slave or master flag
+/// @arg  I2C_FLAG_TX_ABRT  : TX error flag(Master mode)
+/// @arg  I2C_FLAG_RX_DONE  : Master not ack flag(slave mode)
+/// @arg  I2C_FLAG_ACTIVITY : I2C activity flag
+/// @arg  I2C_FLAG_STOP_DET : stop condition  flag
+/// @arg  I2C_FLAG_START_DET: start condition  flag
+/// @arg  I2C_FLAG_GEN_CALL : a general call address and ack flag
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_ClearFlag(I2C_TypeDef* i2c, u32 flag)
+{
+    if ((flag & I2C_FLAG_RX_UNDER) == I2C_FLAG_RX_UNDER)
+        i2c->IC_CLR_RX_UNDER;
+    if ((flag & I2C_FLAG_RX_OVER) == I2C_FLAG_RX_OVER)
+        i2c->IC_CLR_RX_OVER;
+    if ((flag & I2C_FLAG_TX_OVER) == I2C_FLAG_TX_OVER)
+        i2c->IC_CLR_TX_OVER;
+    if ((flag & I2C_FLAG_RD_REQ) == I2C_FLAG_RD_REQ)
+        i2c->IC_CLR_RD_REQ;
+    if ((flag & I2C_FLAG_TX_ABRT) == I2C_FLAG_TX_ABRT)
+        i2c->IC_CLR_TX_ABRT;
+    if ((flag & I2C_FLAG_RX_DONE) == I2C_FLAG_RX_DONE)
+        i2c->IC_CLR_RX_DONE;
+    if ((flag & I2C_FLAG_ACTIVITY) == I2C_FLAG_ACTIVITY)
+        i2c->IC_CLR_ACTIVITY;
+    if ((flag & I2C_FLAG_STOP_DET) == I2C_FLAG_STOP_DET)
+        i2c->IC_CLR_STOP_DET;
+    if ((flag & I2C_FLAG_START_DET) == I2C_FLAG_START_DET)
+        i2c->IC_CLR_START_DET;
+    if ((flag & I2C_FLAG_GEN_CALL) == I2C_FLAG_GEN_CALL)
+        i2c->IC_CLR_GEN_CALL;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified I2C interrupt has occurred or not.
+/// @param  i2c: select the I2C peripheral.
+/// @param  it: specifies the interrupt source to check.
+///   This parameter can be one of the following values:
+/// @arg  I2C_IT_RX_UNDER : Rx Buffer is empty interrupt
+/// @arg  I2C_IT_RX_OVER  : RX  Buffer Overrun interrupt
+/// @arg  I2C_IT_RX_FULL  : Rx buffer full interrupt
+/// @arg  I2C_IT_TX_OVER  : TX  Buffer Overrun interrupt
+/// @arg  I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
+/// @arg  I2C_IT_RD_REQ   : I2C work as slave or master interrupt
+/// @arg  I2C_IT_TX_ABRT  : TX error interrupt  (Master mode)
+/// @arg  I2C_IT_RX_DONE  : Master not ack interrupt (slave mode)
+/// @arg  I2C_IT_ACTIVITY : I2C activity interrupt
+/// @arg  I2C_IT_STOP_DET : stop condition  interrupt
+/// @arg  I2C_IT_START_DET: start condition  interrupt
+/// @arg  I2C_IT_GEN_CALL : a general call address and ack interrupt
+/// @retval The new state of I2C_IT (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus I2C_GetITStatus(I2C_TypeDef* i2c, u32 it)
+{
+    return ((i2c->IC_RAW_INTR_STAT & it) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the i2c interrupt pending bits.
+/// @param  i2c: select the I2C peripheral.
+/// @param  it: specifies the interrupt pending bit to clear.
+///   This parameter can be any combination of the following values:
+/// @arg  I2C_IT_RX_UNDER : Rx Buffer is empty interrupt
+/// @arg  I2C_IT_RX_OVER  : RX  Buffer Overrun interrupt
+/// @arg  I2C_IT_RX_FULL  : Rx buffer full interrupt
+/// @arg  I2C_IT_TX_OVER  : TX  Buffer Overrun interrupt
+/// @arg  I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
+/// @arg  I2C_IT_RD_REQ   : I2C work as slave or master interrupt
+/// @arg  I2C_IT_TX_ABRT  : TX error interrupt  (Master mode)
+/// @arg  I2C_IT_RX_DONE  : Master not ack interrupt (slave mode)
+/// @arg  I2C_IT_ACTIVITY : I2C activity interrupt
+/// @arg  I2C_IT_STOP_DET : stop condition  interrupt
+/// @arg  I2C_IT_START_DET: start condition  interrupt
+/// @arg  I2C_IT_GEN_CALL : a general call address and ack interrupt
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_ClearITPendingBit(I2C_TypeDef* i2c, u32 it)
+{
+    if ((it & I2C_IT_RX_UNDER) == I2C_FLAG_RX_UNDER)
+        i2c->IC_CLR_RX_UNDER;
+    if ((it & I2C_IT_RX_OVER) == I2C_FLAG_RX_OVER)
+        i2c->IC_CLR_RX_OVER;
+    if ((it & I2C_IT_TX_OVER) == I2C_FLAG_TX_OVER)
+        i2c->IC_CLR_TX_OVER;
+    if ((it & I2C_IT_RD_REQ) == I2C_FLAG_RD_REQ)
+        i2c->IC_CLR_RD_REQ;
+    if ((it & I2C_IT_TX_ABRT) == I2C_FLAG_TX_ABRT)
+        i2c->IC_CLR_TX_ABRT;
+    if ((it & I2C_IT_RX_DONE) == I2C_FLAG_RX_DONE)
+        i2c->IC_CLR_RX_DONE;
+    if ((it & I2C_IT_ACTIVITY) == I2C_FLAG_ACTIVITY)
+        i2c->IC_CLR_ACTIVITY;
+    if ((it & I2C_IT_STOP_DET) == I2C_FLAG_STOP_DET)
+        i2c->IC_CLR_STOP_DET;
+    if ((it & I2C_IT_START_DET) == I2C_FLAG_START_DET)
+        i2c->IC_CLR_START_DET;
+    if ((it & I2C_IT_GEN_CALL) == I2C_FLAG_GEN_CALL)
+        i2c->IC_CLR_GEN_CALL;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//
+//  New Function Interface
+//
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures slave address.
+/// @param  i2c: select the I2C peripheral.
+/// @param  addr: specifies the slave address which will be transmitted
+///   This parameter can be one of the following values
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_SendSlaveAddress(I2C_TypeDef* i2c, u8 addr)
+{
+    WRITE_REG(i2c->IC_SAR, addr >> 1);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the I2C slave mode.
+/// @param  i2c: select the I2C peripheral.
+/// @param  state: new state of the specified I2C interrupts.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_SlaveConfigure(I2C_TypeDef* i2c, FunctionalState state)
+{
+    (state) ? CLEAR_BIT(i2c->IC_CON, I2C_CR_SLAVEDIS) : SET_BIT(i2c->IC_CON, I2C_CR_SLAVEDIS);
+}
+/// @}
+
+/// @}
+
+/// @}

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c

@@ -0,0 +1,208 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_iwdg.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE IWDG FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_IWDG_C_
+
+// Files includes
+#include "hal_iwdg.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup IWDG_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup IWDG_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables write access to IWDG_PR and IWDG_RLR
+///   registers.
+/// @param  write_access: new state of write access to IWDG_PR and
+///   IWDG_RLR registers.
+///   This parameter can be one of the following values:
+/// @arg IWDG_WriteAccess_Enable: Enable write access to
+///   IWDG_PR and IWDG_RLR registers
+/// @arg IWDG_WriteAccess_Disable: Disable write access to
+///   IWDG_PR and IWDG_RLR registers
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_WriteAccessCmd(u16 write_access)
+{
+    IWDG->KR = write_access;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets IWDG Prescaler value.
+/// @param  prescaler: specifies the IWDG Prescaler value.
+///         This parameter can be one of the following values:
+/// @arg    IWDG_Prescaler_4: IWDG prescaler set to 4
+/// @arg    IWDG_Prescaler_8: IWDG prescaler set to 8
+/// @arg    IWDG_Prescaler_16: IWDG prescaler set to 16
+/// @arg    IWDG_Prescaler_32: IWDG prescaler set to 32
+/// @arg    IWDG_Prescaler_64: IWDG prescaler set to 64
+/// @arg    IWDG_Prescaler_128: IWDG prescaler set to 128
+/// @arg    IWDG_Prescaler_256: IWDG prescaler set to 256
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_SetPrescaler(u8 prescaler)
+{
+    IWDG->PR = prescaler;
+    PVU_CheckStatus();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set IWDG reload value.
+/// @param  reload: specifies the IWDG reload value.
+///         This parameter must be a number between 0 and 0x0FFF.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_SetReload(u16 reload)
+{
+    IWDG->RLR = reload;
+    RVU_CheckStatus();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Get IWDG reload value.
+/// @param  None.
+/// @retval reload: specifies the IWDG reload value.
+////////////////////////////////////////////////////////////////////////////////
+u32 IWDG_GetReload(void)
+{
+    return IWDG->RLR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reloads IWDG counter with value defined in the reload register
+///   (write access to IWDG_PR and IWDG_RLR registers disabled).
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_ReloadCounter(void)
+{
+    IWDG->KR = KR_KEY_Reload;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers
+///         disabled).
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_Enable(void)
+{
+    IWDG->KR = KR_KEY_Enable;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified IWDG flag is set or not.
+/// @param  flag: specifies the flag to check.
+///   This parameter can be one of the following values:
+/// @arg    IWDG_FLAG_PVU: Prescaler Value Update on going
+/// @arg    IWDG_FLAG_RVU: reload Value Update on going
+/// @retval The new state of flag (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus IWDG_GetFlagStatus(u16 flag)
+{
+    return ((IWDG->SR & flag) != (u32)RESET) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks prescaler value has been updated.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PVU_CheckStatus(void)
+{
+    while (IWDG_GetFlagStatus(IWDG_FLAG_PVU) == SET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks count relead value has been updated.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RVU_CheckStatus(void)
+{
+    while (IWDG_GetFlagStatus(IWDG_FLAG_RVU) == SET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  IWDG overflow configuration.
+/// @param  overflow_config
+/// @arg    IWDG_Overflow_Interrupt: Interrupt after overflow.
+/// @arg    IWDG_Overflow_Reset:     Reset after overflow.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_OverflowConfig(IWDGOverflowConfig_TypeDef overflow_config)
+{
+    IWDG->CR &= ~IWDG_CR_IRQSEL;
+    IWDG->CR |= overflow_config;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clear interrupt flag
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_ClearITPendingBit(void)
+{
+    IWDG->CR |= IWDG_CR_IRQCLR;//write 1 clear interrupt Flag
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clear interrupt flag
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_ClearIT(void)
+{
+    IWDG->CR |= IWDG_CR_IRQCLR;//write 1 clear interrupt Flag
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable IWDG interrupt function
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_EnableIT(void)
+{
+    IWDG->CR |= IWDG_CR_IRQSEL;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Disable IWDG interrupt function
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_Reset(void)
+{
+    IWDG->CR &= ~IWDG_CR_IRQSEL;
+}
+
+
+
+/// @}
+
+/// @}
+
+/// @}

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c

@@ -0,0 +1,147 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_misc.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE MSIC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_MISC_C_
+
+// Files includes
+#include "hal_misc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MSIC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MISC_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the NVIC interrupt vector table.
+/// @param  vect_tab
+///         This parameter can be any combination of the following values:
+///    @arg NVIC_VectTab_RAM
+///    @arg NVIC_VectTab_FLASH
+/// @param  offset
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void NVIC_SetVectorTable(u32 vect_tab, u32 offset)
+{
+    SCB->VTOR = vect_tab | (offset & (u32)0x1FFFFF80);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the NVIC interrupt priority group.
+/// @param  priority_group
+///         This parameter can be any combination of the following values:
+///    @arg NVIC_PriorityGroup_0
+///    @arg NVIC_PriorityGroup_1
+///    @arg NVIC_PriorityGroup_2
+///    @arg NVIC_PriorityGroup_3
+///    @arg NVIC_PriorityGroup_4
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void NVIC_PriorityGroupConfig(u32 priority_group)
+{
+    SCB->AIRCR = AIRCR_VECTKEY_MASK | priority_group;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  NVIC initialization.
+/// @param  init_struct
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void NVIC_Init(NVIC_InitTypeDef* init_struct)
+{
+    if (init_struct->NVIC_IRQChannelCmd != DISABLE) {
+        u32 pri = (SCB_AIRCR_PRIGROUP & ~(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk)) >> SCB_AIRCR_PRIGROUP_Pos;
+
+        pri = (((u32)init_struct->NVIC_IRQChannelPreemptionPriority << (0x4 - pri)) |
+               (init_struct->NVIC_IRQChannelSubPriority & (0x0F >> pri)))
+              << 0x04;
+
+        NVIC->IP[init_struct->NVIC_IRQChannel]           = pri;
+        NVIC->ISER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
+    }
+    else {
+        NVIC->ICER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
+    }
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  NVIC initialized extension function.
+/// @param  init_struct
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exNVIC_Init(exNVIC_Init_TypeDef* init_struct)
+{
+    u32 pri;
+
+    if (init_struct->NVIC_IRQChannelCmd != DISABLE) {
+        pri = (SCB_AIRCR_PRIGROUP & ~(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk)) >> SCB_AIRCR_PRIGROUP_Pos;
+
+        pri = (((u32)init_struct->NVIC_IRQChannelPreemptionPriority << (0x4 - pri)) |
+               (init_struct->NVIC_IRQChannelSubPriority & (0x0F >> pri))) << 0x04;
+
+        NVIC->IP[init_struct->NVIC_IRQChannel] = pri;
+        NVIC->ISER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
+    }
+    else {
+        NVIC->ICER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
+    }
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  System low power mode configuration.
+/// @param  low_power_mode
+///         This parameter can be any combination of the following values:
+///    @arg NVIC_LP_SEVONPEND
+///    @arg NVIC_LP_SLEEPDEEP
+///    @arg NVIC_LP_SLEEPONEXIT
+/// @param  state: new state of the low power mode.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void NVIC_SystemLPConfig(u8 low_power_mode, FunctionalState state)
+{
+    (state) ? (SCB->SCR |= low_power_mode) : (SCB->SCR &= ~(u32)low_power_mode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SysTick clock source configuration.
+/// @param  systick_clk_source
+///         This parameter can be any combination of the following values:
+///    @arg SysTick_CLKSource_EXTCLK
+///    @arg SysTick_CLKSource_HCLK
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SysTick_CLKSourceConfig(u32 systick_clk_source)
+{
+    (systick_clk_source == SysTick_CLKSource_HCLK) ? (SysTick->CTRL |= SysTick_CLKSource_HCLK) \
+    : (SysTick->CTRL &= ~SysTick_CLKSource_HCLK);
+}
+
+/// @}
+
+/// @}
+
+/// @}

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c

@@ -0,0 +1,215 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_pwr.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE PWR FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define __HAL_PWR_C_
+
+// Files includes
+#include "hal_pwr.h"
+#include "hal_rcc.h"
+#include "hal_syscfg.h"
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup PWR_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup PWR_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the PWR peripheral registers to their default reset
+/// values.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_DeInit(void)
+{
+    exRCC_APB1PeriphReset(RCC_APB1ENR_PWR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables access to the RTC and backup registers.
+/// @param  state: new state of the access to the RTC and backup
+///         registers. This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_BackupAccessCmd(FunctionalState state)
+{
+    (state) ? (RCC->BDCR |= RCC_BDCR_DBP) : (RCC->BDCR &= ~RCC_BDCR_DBP);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Power Voltage Detector(PVD).
+/// @param  state: new state of the PVD.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_PVDCmd(FunctionalState state)
+{
+    (state) ? (SYSCFG->PDETCSR |= SYSCFG_PDETCSR_PVDE) : (SYSCFG->PDETCSR &= ~SYSCFG_PDETCSR_PVDE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the voltage threshold detected by the Power Voltage
+///         Detector(PVD).
+/// @param  pvd_level: specifies the PVD detection level
+///         This parameter can be one of the following values:
+/// @arg    emPVD_LEVEL0 : PVD detection level set to 1.7V
+/// @arg    emPVD_LEVEL1 : PVD detection level set to 2.0V
+/// @arg    emPVD_LEVEL2 : PVD detection level set to 2.3V
+/// @arg    emPVD_LEVEL3 : PVD detection level set to 2.6V
+/// @arg    emPVD_LEVEL4 : PVD detection level set to 2.9V
+/// @arg    emPVD_LEVEL5 : PVD detection level set to 3.2V
+/// @arg    emPVD_LEVEL6 : PVD detection level set to 3.5V
+/// @arg    emPVD_LEVEL7 : PVD detection level set to 3.8V
+/// @arg    emPVD_LEVEL8 : PVD detection level set to 4.1V
+/// @arg    emPVD_LEVEL9 : PVD detection level set to 4.4V
+/// @arg    emPVD_LEVEL10: PVD detection level set to 4.7V
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_PVDLevelConfig(emPVD_Level_Typedef pvd_level)
+{
+    SYSCFG->PDETCSR = (SYSCFG->PDETCSR & (~SYSCFG_PDETCSR_PLS)) | pvd_level;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the WakeUp Pin functionality.
+/// @param  state: new state of the WakeUp Pin functionality.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_WakeUpPinCmd(FunctionalState state)
+{
+    (state != DISABLE) ? (PWR->CR2 |= PWR_CR2_EWUP1) : (PWR->CSR &= ~PWR_CR2_EWUP1);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the WakeUp Pin functionality.
+/// @param  state: new state of the WakeUp Pin functionality.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_WakeUpPinXCmd(emWUP_Pin_Typedef pin, FunctionalState state)
+{
+    (state != DISABLE) ? (PWR->CR2 |= (PWR_CR2_EWUP1 << pin)) : (PWR->CSR &= ~(PWR_CR2_EWUP1 << pin));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enters STOP mode.
+/// @param  regulator: specifies the regulator state in STOP mode.
+///         This parameter can be one of the following values:
+/// @arg    PWR_Regulator_ON: STOP mode with regulator ON
+/// @arg    PWR_Regulator_LowPower: STOP mode with regulator in low power mode.
+/// @param  stop_entry: specifies if STOP mode in entered with WFI or  WFE
+///         instruction.
+///         This parameter can be one of the following values:
+/// @arg    PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+/// @arg    PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_EnterSTOPMode(emPWR_Reg_Stop_mode_Typedef regulator, emPWR_STOP_ModeEn_Typedef stop_entry)
+{
+
+    MODIFY_REG(PWR->CR, PWR_CR_LDPS, regulator);
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    if(stop_entry == PWR_STOPEntry_WFI) {
+        __WFI();
+    }
+    else {
+        __WFE();
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enters STANDBY mode.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_EnterSTANDBYMode(void)
+{
+    PWR->CR |= PWR_CR_PDDS;
+    PWR->SCR |= PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 | PWR_SCR_CWUF4 | PWR_SCR_CWUF5 | PWR_SCR_CWUF6;
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+#if defined(__CC_ARM)
+    __force_stores();
+#endif
+    __WFI();
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified PWR flag is set or not.
+/// @param  flag: specifies the flag to check.
+///         This parameter can be one of the following values:
+/// @arg    PWR_FLAG_WU: Wake Up flag
+/// @arg    PWR_FLAG_SB: StandBy flag
+/// @arg    PWR_FLAG_PVDO: PVD Output
+/// @retval The new state of PWR_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus PWR_GetPVDOFlagStatus(u32 flag)
+{
+    return (FlagStatus)(SYSCFG->PDETCSR & flag);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the PWR's pending flags.
+/// @param  flag: specifies the flag to clear.
+///         This parameter can be one of the following values:
+/// @arg    PWR_FLAG_WU: Wake Up flag
+/// @arg    PWR_FLAG_SB: StandBy flag
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_ClearPVDOFlag(u32 flag)
+{
+    PWR->CR |= flag << 2;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified PWR flag is set or not.
+/// @param  flag: specifies the flag to check.
+///         This parameter can be one of the following values:
+/// @arg    PWR_FLAG_WU: Wake Up flag
+/// @arg    PWR_FLAG_SB: StandBy flag
+/// @arg    PWR_FLAG_PVDO: PVD Output
+/// @retval The new state of PWR_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus PWR_GetFlagStatus(u32 flag)
+{
+    return (FlagStatus)(PWR->CSR & flag);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the PWR's pending flags.
+/// @param  flag: specifies the flag to clear.
+///         This parameter can be one of the following values:
+/// @arg    PWR_FLAG_WU: Wake Up flag
+/// @arg    PWR_FLAG_SB: StandBy flag
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_ClearFlag(u32 flag)
+{
+    PWR->CR |= flag << 2;
+}
+
+/// @}
+
+/// @}
+
+/// @}

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c

@@ -0,0 +1,995 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_rcc.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE RCC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_RCC_C_
+
+// Files includes
+#include "mm32_reg.h"
+#include "hal_rcc.h"
+
+
+
+u8 tbPresc[] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup RCC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup RCC_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Resets the RCC clock configuration to default state.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_DeInit()
+{
+    SET_BIT(RCC->CR, RCC_CR_HSION);
+    CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
+    CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON );
+    CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL_DN | RCC_PLLCFGR_PLL_DP);
+    CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+    CLEAR_REG(RCC->CFGR);
+    CLEAR_REG(RCC->CIR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the External High Speed oscillator (HSE).
+/// @param  state: specifies the new state of HSE.
+///         This parameter can be one of the following values:
+/// @arg    RCC_HSE_OFF: HSE oscillator OFF
+/// @arg    RCC_HSE_ON: HSE oscillator ON
+/// @arg    RCC_HSE_Bypass: HSE oscillator bypassed with external clock
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_HSEConfig(RCCHSE_TypeDef state)
+{
+    RCC->CR &= ~(RCC_CR_HSEBYP | RCC_CR_HSEON);
+    switch (state) {
+        case RCC_HSE_Bypass:
+            RCC->CR |= RCC_CR_HSEBYP;
+            RCC->CR |= RCC_CR_HSEON;
+            break;
+        case RCC_HSE_ON:
+            RCC->CR |= RCC_CR_HSEON;
+            break;
+        default:
+            break;
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified RCC flag is set or not.
+/// @param  flag: specifies the flag to check.
+///         This parameter can be one of the following values:
+/// @arg    RCC_FLAG_HSIRDY: HSI oscillator clock ready
+/// @arg    RCC_FLAG_HSERDY: HSE oscillator clock ready
+/// @arg    RCC_FLAG_PLLRDY: PLL clock ready
+/// @arg    RCC_FLAG_LSERDY: LSE oscillator clock ready
+/// @arg    RCC_FLAG_LSIRDY: LSI oscillator clock ready
+/// @arg    RCC_FLAG_PINRST: Pin reset
+/// @arg    RCC_FLAG_PORRST: POR/PDR reset
+/// @arg    RCC_FLAG_SFTRST: Software reset
+/// @arg    RCC_FLAG_IWDGRST: Independent Watchdog reset
+/// @arg    RCC_FLAG_WWDGRST: Window Watchdog reset
+/// @arg    RCC_FLAG_LPWRRST: Low Power reset
+/// @retval The new state of flag (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus RCC_GetFlagStatus(RCC_FLAG_TypeDef flag)
+{
+    return ((((flag >> 5) == CR_REG_INDEX) ? RCC->CR : (((flag >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : RCC->CSR)) &
+            (1 << (flag & 0x1F)))
+           ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Waits for HSE start-up.
+/// @param  None.
+/// @retval An ErrorStatus enumuration value:
+///         - SUCCESS: HSE oscillator is stable and ready to use
+///         - ERROR: HSE oscillator not yet ready
+////////////////////////////////////////////////////////////////////////////////
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+    u32 StartUpCounter = 0;
+
+    FlagStatus HSEStatus;
+
+    do {
+        HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+        StartUpCounter++;
+    } while ((HSEStatus == RESET) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    return (ErrorStatus)(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) ? SUCCESS : ERROR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Waits for flag start-up.
+/// @param  flag: specifies the flag to check.
+///         This parameter can be one of the following values:
+/// @arg    RCC_FLAG_HSIRDY: HSI oscillator clock ready
+/// @arg    RCC_FLAG_HSERDY: HSE oscillator clock ready
+/// @arg    RCC_FLAG_PLLRDY: PLL clock ready
+/// @arg    RCC_FLAG_LSERDY: LSE oscillator clock ready
+/// @arg    RCC_FLAG_LSIRDY: LSI oscillator clock ready
+/// @arg    RCC_FLAG_PINRST: Pin reset
+/// @arg    RCC_FLAG_PORRST: POR/PDR reset
+/// @arg    RCC_FLAG_SFTRST: Software reset
+/// @arg    RCC_FLAG_IWDGRST: Independent Watchdog reset
+/// @arg    RCC_FLAG_WWDGRST: Window Watchdog reset
+/// @retval An ErrorStatus enumuration value:
+///         - SUCCESS: HSE oscillator is stable and ready to use
+///         - ERROR: HSE oscillator not yet ready
+////////////////////////////////////////////////////////////////////////////////
+ErrorStatus RCC_WaitForFlagStartUp(RCC_FLAG_TypeDef flag)
+{
+    u32 StartUpCounter = 0;
+
+    while (RCC_GetFlagStatus(flag) == RESET) {
+        if (StartUpCounter++ > HSE_STARTUP_TIMEOUT) {
+            return ERROR;
+        }
+    }
+    return SUCCESS;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Internal High Speed oscillator (HSI).
+/// @param  state: new state of the HSI.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_HSICmd(FunctionalState state)
+{
+    MODIFY_REG(RCC->CR, RCC_CR_HSION, (state << RCC_CR_HSION_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the system clock (SYSCLK).
+/// @param  sys_clk_source: specifies the clock source used as system
+///         clock. This parameter can be one of the following values:
+/// @arg    RCC_HSI: specifies HSI as system clock
+/// @arg    RCC_HSE: specifies HSE as system clock
+/// @arg    RCC_PLL: specifies PLL as system clock
+/// @arg    RCC_LSI: specifies LSI as system clock
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_SYSCLKConfig(SYSCLK_TypeDef sys_clk_source)
+{
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (sys_clk_source << RCC_CFGR_SW_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the PLL clock source and DM DN factor.
+///         This function must be used only when the PLL is disabled.
+/// @param  plldn: specifies the PLL multiplication factor.
+///         This parameter can be RCC_PLLMul_x where x:[31:26]
+/// @param  plldm: specifies the PLL Divsior factor.
+///         This parameter can be RCC_Divsior_x where x:[22:20]
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_PLLDMDNConfig(u32 plldn, u32 plldm)
+{
+    MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLL_DN | RCC_PLLCFGR_PLL_DP), ((plldn << RCC_PLLCFGR_PLL_DN_Pos) | (plldm << RCC_PLLCFGR_PLL_DP_Pos)));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the PLL.
+///   The PLL can not be disabled if it is used as system clock.
+/// @param  state: new state of the PLL.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_PLLCmd(FunctionalState state)
+{
+    MODIFY_REG(RCC->CR, RCC_CR_PLLON, (state << RCC_CR_PLLON_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the PLL clock source and multiplication factor.
+///         This function must be used only when the PLL is disabled.
+/// @param  pll_src: specifies the PLL entry clock source.
+///         This parameter can be one of the following values:
+/// @arg    RCC_HSI_Div4: HSI oscillator clock divided
+///         by 4 selected as PLL clock entry
+/// @arg    RCC_HSE_Div1: HSE oscillator clock selected
+///         as PLL clock entry
+/// @arg    RCC_HSE_Div2: HSE oscillator clock divided
+///         by 2 selected as PLL clock entry
+/// @param  pll_mul: specifies the PLL multiplication factor.
+///         This parameter can be RCC_PLLMul_x where x:[31:26][22:20]
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_PLLConfig(RCC_PLLSource_TypeDef pll_src, RCC_PLLMul_TypeDef pll_mul)
+{
+    const u8 DNDM_Item[] = {0x07, 0x03, 0x05, 0x01, 0x07, 0x01, 0x09, 0x01,  // Frclk*8/4 ; Frclk*6/2 ; Frclk*8/2 ; Frclk*10/2;
+                            0x0B, 0x01, 0x0D, 0x01, 0x0F, 0x01, 0x11, 0x01,  // Frclk*12/2; Frclk*14/2; Frclk*16/2; Frclk*18/2;
+                            0x13, 0x01, 0x15, 0x01, 0x17, 0x01, 0x19, 0x01,  // Frclk*20/2; Frclk*22/2; Frclk*24/2; Frclk*26/2;
+                            0x1B, 0x01, 0x1D, 0x01, 0x1F, 0x01
+                           };             // Frclk*28/2; Frclk*30/2;    // Frclk*32/2;
+    MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLLXTPRE | RCC_PLLCFGR_PLLSRC), pll_src);
+    RCC_PLLDMDNConfig((u32)DNDM_Item[pll_mul >> 17], (u32)DNDM_Item[(pll_mul >> 17) + 1]);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the USB clock (USBCLK).
+/// @param  usb_clk_src: specifies the USB clock source.
+///         This clock is derived from the PLL output.
+///         This parameter can be one of the following values:
+/// @arg    RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
+/// @arg    RCC_USBCLKSource_PLLCLK_Div2: PLL clock divided by 2 selected as USB
+///         clock source
+/// @arg    RCC_USBCLKSource_PLLCLK_Div3: PLL clock divided by 3 selected as USB
+///         clock source
+/// @arg    RCC_USBCLKSource_PLLCLK_Div4: PLL clock divided by 4 selected as USB
+///         clock source
+/// @arg    RCC_USBCLKSource_PLLCLK_Div5: PLL clock divided by 5 selected as USB
+///         clock source
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_USBCLKConfig(RCC_USBCLKSOURCE_TypeDef usb_clk_src)
+{
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (usb_clk_src << RCC_CFGR_USBPRE_Pos));
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the clock source used as system clock.
+/// @param  None.
+/// @retval The clock source used as system clock. The returned value can
+///         be one of the following:
+///         - 0x00: HSI/6 used as system clock
+///         - 0x04: HSE used as system clock
+///         - 0x08: PLL used as system clock
+////////////////////////////////////////////////////////////////////////////////
+u8 RCC_GetSYSCLKSource(void)
+{
+    return ((u8)READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the AHB clock (hclk).
+/// @param  sys_clk: defines the AHB clock divider. This clock is derived
+///                    from the system clock (SYSCLK).
+///         This parameter can be one of the following values:
+/// @arg    RCC_SYSCLK_Div1: AHB clock = SYSCLK
+/// @arg    RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
+/// @arg    RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
+/// @arg    RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
+/// @arg    RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
+/// @arg    RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
+/// @arg    RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+/// @arg    RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+/// @arg    RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_HCLKConfig(RCC_AHB_CLK_TypeDef sys_clk)
+{
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, sys_clk);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the Low Speed APB clock (pclk1).
+/// @param  hclk: defines the APB1 clock divider. This clock is derived from
+///                  the AHB clock (hclk).
+///         This parameter can be one of the following values:
+/// @arg    RCC_HCLK_Div1: APB1 clock = hclk
+/// @arg    RCC_HCLK_Div2: APB1 clock = hclk/2
+/// @arg    RCC_HCLK_Div4: APB1 clock = hclk/4
+/// @arg    RCC_HCLK_Div8: APB1 clock = hclk/8
+/// @arg    RCC_HCLK_Div16: APB1 clock = hclk/16
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_PCLK1Config(RCC_APB1_APB2_CLK_TypeDef hclk)
+{
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, hclk);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the High Speed APB clock (pclk2).
+/// @param  hclk: defines the APB2 clock divider. This clock is derived from
+///                  the AHB clock (hclk).
+///         This parameter can be one of the following values:
+/// @arg    RCC_HCLK_Div1: APB2 clock = hclk
+/// @arg    RCC_HCLK_Div2: APB2 clock = hclk/2
+/// @arg    RCC_HCLK_Div4: APB2 clock = hclk/4
+/// @arg    RCC_HCLK_Div8: APB2 clock = hclk/8
+/// @arg    RCC_HCLK_Div16: APB2 clock = hclk/16
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_PCLK2Config(RCC_APB1_APB2_CLK_TypeDef hclk)
+{
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (hclk << 3));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the ADC clock (ADCCLK).
+/// @param  pclk2: defines the ADC clock divider. This clock is derived from
+///                   the APB2 clock (pclk2).
+///         This parameter can be one of the following values:
+/// @arg    RCC_PCLK2_Div2: ADC clock = pclk2/2
+/// @arg    RCC_PCLK2_Div4: ADC clock = pclk2/4
+/// @arg    RCC_PCLK2_Div6: ADC clock = pclk2/6
+/// @arg    RCC_PCLK2_Div8: ADC clock = pclk2/8
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ADCCLKConfig(RCC_ADCCLKSOURCE_TypeDef pclk2)
+{
+    MODIFY_REG(RCC->CFGR, ADC_CFGR_PRE, pclk2);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the External Low Speed oscillator (LSE).
+/// @param  state: specifies the new state of the LSE.
+///         This parameter can be one of the following values:
+/// @arg    RCC_LSE_OFF: LSE oscillator OFF
+/// @arg    RCC_LSE_ON: LSE oscillator ON
+/// @arg    RCC_LSE_Bypass: LSE oscillator bypassed with external
+///         clock
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_LSEConfig(RCC_LSE_TypeDef state)
+{
+    RCC->BDCR &= ~(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON);
+
+    switch (state) {
+        case RCC_LSE_Bypass:
+            RCC->BDCR |= RCC_BDCR_LSEBYP;
+            RCC->BDCR |= RCC_BDCR_LSEON;
+            break;
+        case RCC_LSE_ON:
+            RCC->BDCR |= RCC_BDCR_LSEON;
+            break;
+        default:
+            break;
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the RTC clock (RTCCLK).
+///         Once the RTC clock is selected it can be changed unless the
+///         Backup domain is reset.
+/// @param  rtc_clk_src: specifies the RTC clock source.
+///         This parameter can be one of the following values:
+/// @arg    RCC_RTCCLKSource_LSE: LSE selected as RTC clock
+/// @arg    RCC_RTCCLKSource_LSI: LSI selected as RTC clock
+/// @arg    RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128
+///         selected as RTC clock
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_RTCCLKConfig(RCC_RTCCLKSOURCE_TypeDef rtc_clk_src)
+{
+    MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, rtc_clk_src);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the RTC clock.
+///         This function must be used only after the RTC clock was
+///         selected using the RCC_RTCCLKConfig function.
+/// @param  state: new state of the RTC clock.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_RTCCLKCmd(FunctionalState state)
+{
+    MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCEN, (state << RCC_BDCR_RTCEN_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Internal Low Speed oscillator (LSI).
+///         LSI can not be disabled if the IWDG is running.
+/// @param  state: new state of the LSI.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_LSICmd(FunctionalState state)
+{
+//    u32 j;
+    MODIFY_REG(RCC->CSR, RCC_CSR_LSION | RCC_CSR_LSIOENLV, RCC_CSR_LSIOENLV | (state << RCC_CSR_LSION_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the clock frequency of different on chip clocks.
+/// @param  None.
+/// @retval sys_clk : System clock frequency
+////////////////////////////////////////////////////////////////////////////////
+u32 RCC_GetSysClockFreq(void)
+{
+    u32 result;
+    u32 clock, mul, div;
+    switch (RCC->CFGR & RCC_CFGR_SWS) {
+        case RCC_CFGR_SWS_LSI:
+            result = LSI_VALUE;
+            break;
+
+        case RCC_CFGR_SWS_HSE:
+            result = HSE_VALUE;
+            break;
+
+        case RCC_CFGR_SWS_PLL:
+            clock = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) ? (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLXTPRE) ? (HSE_VALUE >> 1) : HSE_VALUE)
+                    : HSI_VALUE_PLL_ON;
+            mul = ((RCC->PLLCFGR & (u32)RCC_PLLCFGR_PLL_DN) >> RCC_PLLCFGR_PLL_DN_Pos) + 1;
+            div = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL_DP) >> RCC_PLLCFGR_PLL_DP_Pos) + 1;
+
+            result = clock * mul / div;
+            break;
+        default:
+            result =  HSI_VALUE;
+            break;
+    }
+    return result;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the hclk frequency of different on chip clocks.
+/// @param  None.
+/// @retval hclk frequency
+////////////////////////////////////////////////////////////////////////////////
+u32 RCC_GetHCLKFreq(void)
+{
+    return (RCC_GetSysClockFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the pclk1 frequency of different on chip clocks.
+/// @param  None.
+/// @retval pclk1 frequency
+////////////////////////////////////////////////////////////////////////////////
+u32 RCC_GetPCLK1Freq(void)
+{
+    return (RCC_GetHCLKFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the pclk2 frequency of different on chip clocks.
+/// @param  None.
+/// @retval pclk2 frequency
+////////////////////////////////////////////////////////////////////////////////
+u32 RCC_GetPCLK2Freq(void)
+{
+    return (RCC_GetHCLKFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the frequency of different on chip clocks.
+/// @param  clk: pointer to a RCC_ClocksTypeDef structure which
+///   will hold the clocks frequency.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* clk)
+{
+    u8 tbADCPresc[] = {2, 4, 6, 8};
+
+    clk->SYSCLK_Frequency = RCC_GetSysClockFreq();
+    clk->HCLK_Frequency   = RCC_GetHCLKFreq();
+    clk->PCLK1_Frequency  = RCC_GetPCLK1Freq();
+    clk->PCLK2_Frequency  = RCC_GetPCLK2Freq();
+
+    clk->ADCCLK_Frequency = clk->PCLK2_Frequency / tbADCPresc[(RCC->CFGR & ADC_CFGR_PRE) >> ADC_CFGR_PRE_Pos];
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the AHB peripheral clock.
+/// @param  ahb_periph: specifies the AHB peripheral to gates its clock.
+///   This parameter can be any combination of the following values:
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHBPeriphClockCmd(u32 ahb_periph, FunctionalState state)
+{
+    (state) ? (RCC->AHBENR |= ahb_periph) : (RCC->AHBENR &= ~ahb_periph);
+}
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHB2PeriphClockCmd(u32 ahb_periph, FunctionalState state)
+{
+    (state) ? (RCC->AHB2ENR |= ahb_periph) : (RCC->AHB2ENR &= ~ahb_periph);
+}
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHB3PeriphClockCmd(u32 ahb_periph, FunctionalState state)
+{
+    (state) ? (RCC->AHB3ENR |= ahb_periph) : (RCC->AHB3ENR &= ~ahb_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
+/// @param  apb2_periph: specifies the APB2 peripheral to gates its
+///   clock.
+///   This parameter can be any combination of the following values:
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB2PeriphClockCmd(u32 apb2_periph, FunctionalState state)
+{
+    (state) ? (RCC->APB2ENR |= apb2_periph) : (RCC->APB2ENR &= ~apb2_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
+/// @param  apb1_periph: specifies the APB1 peripheral to gates its
+///   clock.
+///   This parameter can be any combination of the following values:
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB1PeriphClockCmd(u32 apb1_periph, FunctionalState state)
+{
+    (state) ? (RCC->APB1ENR |= apb1_periph) : (RCC->APB1ENR &= ~apb1_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases High Speed APB (APB2) peripheral reset.
+/// @param  apb2_periph: specifies the APB2 peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @param  state: new state of the specified peripheral reset.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB2PeriphResetCmd(u32 apb2_periph, FunctionalState state)
+{
+    (state) ? (RCC->APB2RSTR |= apb2_periph) : (RCC->APB2RSTR &= ~apb2_periph);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
+/// @param  apb1_periph: specifies the APB1 peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB1PeriphResetCmd(u32 apb1_periph, FunctionalState state)
+{
+    (state) ? (RCC->APB1RSTR |= apb1_periph) : (RCC->APB1RSTR &= ~apb1_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases Low Speed AHB peripheral reset.
+/// @param  ahb_periph: specifies the AHB peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHBPeriphResetCmd(u32 ahb_periph, FunctionalState state)
+{
+    (state) ? (RCC->AHBRSTR |= ahb_periph) : (RCC->AHBRSTR &= ~ahb_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases Low Speed AHB2 peripheral reset.
+/// @param  ahb_periph: specifies the AHB peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHB2PeriphResetCmd(u32 ahb_periph, FunctionalState state)
+{
+    (state) ? (RCC->AHB2RSTR |= ahb_periph) : (RCC->AHB2RSTR &= ~ahb_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases Low Speed AHB2 peripheral reset.
+/// @param  ahb_periph: specifies the AHB peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHB3PeriphResetCmd(u32 ahb_periph, FunctionalState state)
+{
+    (state) ? (RCC->AHB3RSTR |= ahb_periph) : (RCC->AHB3RSTR &= ~ahb_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases the Backup domain reset.
+/// @param  state: new state of the Backup domain reset.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_BackupResetCmd(FunctionalState state)
+{
+    MODIFY_REG(RCC->BDCR, RCC_BDCR_BDRST, (state << RCC_BDCR_BDRST_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Clock Security System.
+/// @param  state: new state of the Clock Security System..
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ClockSecuritySystemCmd(FunctionalState state)
+{
+    MODIFY_REG(RCC->CR, RCC_CR_CSSON, (state << RCC_CR_CSSON_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Selects the clock source to output on MCO pin.
+/// @param  mco_src: specifies the clock source to output.
+///   This parameter can be one of the following values:
+/// @arg RCC_MCO_NoClock: No clock selected
+/// @arg RCC_MCO_LSI: LSI oscillator clock selected
+/// @arg RCC_MCO_LSE: LSE oscillator clock selected
+/// @arg RCC_MCO_SYSCLK: System clock selected
+/// @arg RCC_MCO_HSI: HSI oscillator clock selected
+/// @arg RCC_MCO_HSE: HSE oscillator clock selected
+/// @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_MCOConfig(RCC_MCO_TypeDef mco_src)
+{
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, mco_src);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the RCC reset flags.
+///   The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
+///   RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
+///   RCC_FLAG_LPWRRST
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ClearFlag(void)
+{
+    SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified RCC interrupts.
+/// @param  it: specifies the RCC interrupt sources to be enabled or
+/// disabled.
+///   This parameter can be any combination of the following values:
+/// @arg RCC_IT_LSIRDY: LSI ready interrupt
+/// @arg RCC_IT_LSERDY: LSE ready interrupt
+/// @arg RCC_IT_HSIRDY: HSI ready interrupt
+/// @arg RCC_IT_HSERDY: HSE ready interrupt
+/// @arg RCC_IT_PLLRDY: PLL ready interrupt
+/// @param  state: new state of the specified RCC interrupts.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ITConfig(RCC_IT_TypeDef it, FunctionalState state)
+{
+    (state) ? SET_BIT(RCC->CIR, it << RCC_CIR_LSIRDYIE_Pos) : CLEAR_BIT(RCC->CIR, it << RCC_CIR_LSIRDYIE_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified RCC interrupt has occurred or not.
+/// @param  it: specifies the RCC interrupt source to check.
+///   This parameter can be one of the following values:
+/// @arg RCC_IT_LSIRDY: LSI ready interrupt
+/// @arg RCC_IT_LSERDY: LSE ready interrupt
+/// @arg RCC_IT_HSIRDY: HSI ready interrupt
+/// @arg RCC_IT_HSERDY: HSE ready interrupt
+/// @arg RCC_IT_PLLRDY: PLL ready interrupt
+/// @arg RCC_IT_CSS: Clock Security System interrupt
+/// @retval The new state of it (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus RCC_GetITStatus(RCC_IT_TypeDef it)
+{
+    return (ITStatus)READ_BIT(RCC->CIR, (it << RCC_CIR_LSIRDYF_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the RCC�?interrupt pending bits.
+/// @param  it: specifies the interrupt pending bit to clear.
+///   This parameter can be any combination of the following values:
+/// @arg RCC_IT_LSIRDY: LSI ready interrupt
+/// @arg RCC_IT_LSERDY: LSE ready interrupt
+/// @arg RCC_IT_HSIRDY: HSI ready interrupt
+/// @arg RCC_IT_HSERDY: HSE ready interrupt
+/// @arg RCC_IT_PLLRDY: PLL ready interrupt
+/// @arg RCC_IT_CSS: Clock Security System interrupt
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ClearITPendingBit(u8 it)
+{
+    SET_BIT(RCC->CIR, (it << RCC_CIR_LSIRDYC_Pos));
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
+/// @param  apb1_periph: specifies the APB1 peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB1PeriphReset(u32 apb1_periph)
+{
+    RCC->APB1RSTR |= apb1_periph;
+    RCC->APB1RSTR &= ~apb1_periph;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases Low Speed APB (APB2) peripheral reset.
+/// @param  apb2_periph: specifies the APB2 peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB2PeriphReset(u32 apb2_periph)
+{
+    RCC->APB2RSTR |= apb2_periph;
+    RCC->APB2RSTR &= ~apb2_periph;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases High Speed AHB (AHB1) peripheral reset.
+/// @param  ahb1_periph: specifies the AHB1 peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHBPeriphReset(u32 ahb1_periph)
+{
+    RCC->AHBRSTR |= ahb1_periph;
+    RCC->AHBRSTR &= ~ahb1_periph;
+}
+////////////////////////////////////////////////////////////////////////////////
+//
+//  New Function Interface
+//
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
+/// @param  apb1_periph: specifies the APB1 peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_APB1PeriphReset(u32 apb1_periph)
+{
+    RCC->APB1RSTR |= apb1_periph;
+    RCC->APB1RSTR &= ~apb1_periph;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief
+/// @param
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_BackupReset()
+{
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases High Speed APB (APB2) peripheral reset.
+/// @param  apb2_periph: specifies the APB2 peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_APB2PeriphReset(u32 apb2_periph)
+{
+    RCC->APB2RSTR |= apb2_periph;
+    RCC->APB2RSTR &= ~apb2_periph;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases High Speed AHB (AHB1) peripheral reset.
+/// @param  ahb1_periph: specifies the AHB1 peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_AHBPeriphReset(u32 ahb1_periph)
+{
+    RCC->AHBRSTR |= ahb1_periph;
+    RCC->AHBRSTR &= ~ahb1_periph;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Disable systick
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_SystickDisable()
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable systick
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_SystickEnable(u32 sys_tick_period)
+{
+    SysTick_Config(RCC_GetHCLKFreq() / 1000000 * sys_tick_period);
+}
+
+/*
+(state) ? (RCC->AHBENR |= ahb_periph) : (RCC->AHBENR &= ~ahb_periph);
+(state) ? (RCC->APB1ENR |= apb1_periph) : (RCC->APB1ENR &= ~apb1_periph);
+(state) ? (RCC->APB2ENR |= apb2_periph) : (RCC->APB2ENR &= ~apb2_periph);
+*/
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified ADC peripheral Clock.
+/// @param  peripheral:select the ADC peripheral.
+/// @param  state: new state of the ADC peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ADC_ClockCmd(ADC_TypeDef* peripheral, FunctionalState state)
+{
+    switch (*(vu32*)&peripheral) {
+
+        case ADC1_BASE:
+            (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC1) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC1);
+            break;
+        case ADC2_BASE:
+            (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC2) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC2);
+            break;
+        case ADC3_BASE:
+            (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC3) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC3);
+            break;
+        default:
+            break;
+    }
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified BKP peripheral Clock.
+/// @param  peripheral:select the BKP peripheral.
+/// @param  state: new state of the BKP peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_BKP_ClockCmd(BKP_TypeDef* peripheral, FunctionalState state)
+{
+    if(BKP == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_BKP) : (RCC->APB1ENR &= ~RCC_APB1ENR_BKP);
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_PWR) : (RCC->APB1ENR &= ~RCC_APB1ENR_PWR);
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified CAN peripheral Clock.
+/// @param  peripheral:select the CAN peripheral.
+/// @param  state: new state of the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_CAN_ClockCmd(CAN_TypeDef* peripheral, FunctionalState state)
+{
+    if(CAN1 == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_CAN) : (RCC->APB1ENR &= ~RCC_APB1ENR_CAN);
+    }
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified COMP peripheral Clock.
+/// @param  peripheral:select the COMP peripheral.
+/// @param  state: new state of the COMP peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_COMP_ClockCmd(COMP_TypeDef* peripheral, FunctionalState state)
+{
+    if(COMP == peripheral) {
+        (state) ? (RCC->APB2ENR |= RCC_APB2ENR_COMP) : (RCC->APB2ENR &= ~RCC_APB2ENR_COMP);
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified CRC peripheral Clock.
+/// @param  peripheral:select the CRC peripheral.
+/// @param  state: new state of the CRC peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_CRC_ClockCmd(CRC_TypeDef* peripheral, FunctionalState state)
+{
+    if(CRC == peripheral) {
+        (state) ? (RCC->AHBENR |= RCC_AHBENR_CRC) : (RCC->AHBENR &= ~RCC_AHBENR_CRC);
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified DAC peripheral Clock.
+/// @param  peripheral:select the DAC peripheral.
+/// @param  state: new state of the DAC peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_DAC_ClockCmd(DAC_TypeDef* peripheral, FunctionalState state)
+{
+    if(DAC == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_DAC) : (RCC->APB1ENR &= ~RCC_APB1ENR_DAC);
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified DMA peripheral Clock.
+/// @param  peripheral:select the DMA peripheral.
+/// @param  state: new state of the DMA peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_DMA_ClockCmd(DMA_TypeDef* peripheral, FunctionalState state)
+{
+    if(DMA1 == peripheral) {
+        (state) ? (RCC->AHBENR |= RCC_AHBENR_DMA1) : (RCC->AHBENR &= ~RCC_AHBENR_DMA1);
+    }
+    if(DMA2 == peripheral) {
+        (state) ? (RCC->AHBENR |= RCC_AHBENR_DMA2) : (RCC->AHBENR &= ~RCC_AHBENR_DMA2);
+    }
+}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified GPIO peripheral Clock.
+/// @param  peripheral:select the GPIO peripheral.
+/// @param  state: new state of the GPIO peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_GPIO_ClockCmd(GPIO_TypeDef* peripheral, FunctionalState state)
+{
+    switch (*(vu32*)&peripheral) {
+        case (u32)GPIOA:
+            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOA) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOA);
+            break;
+        case (u32)GPIOB:
+            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOB) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOB);
+            break;
+        case (u32)GPIOC:
+            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOC) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOC);
+            break;
+        case (u32)GPIOD:
+            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOD) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOD);
+            break;
+        case (u32)GPIOE:
+            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOE) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOE);
+            break;
+        case (u32)GPIOF:
+            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOF) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOF);
+            break;
+        case (u32)GPIOG:
+            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOG) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOG);
+            break;
+        case (u32)GPIOH:
+            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOH) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOH);
+            break;
+        default:
+            break;
+    }
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the uart peripheral registers to their
+///         default reset values.
+/// @param  peripheral: Select the UART or the UART peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_UART_ClockCmd(UART_TypeDef* peripheral, FunctionalState state)
+{
+    if(UART2 == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART2) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART2);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART2);
+    }
+    if(UART1 == peripheral) {
+        (state) ? (RCC->APB2ENR |= RCC_APB2ENR_UART1) : (RCC->APB2ENR &= ~RCC_APB2ENR_UART1);//exRCC_APB2PeriphReset(RCC_APB2ENR_UART1);
+    }
+    if(UART3 == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART3) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART3);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART3);
+    }
+    if(UART4 == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART4) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART4);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART4);
+    }
+    if(UART5 == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART5) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART5);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART5);
+    }
+    if(UART6 == peripheral) {
+        (state) ? (RCC->APB2ENR |= RCC_APB2ENR_UART6) : (RCC->APB2ENR &= ~RCC_APB2ENR_UART6);//exRCC_APB2PeriphReset(RCC_APB2ENR_UART6);
+    }
+    if(UART7 == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART7) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART7);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART7);
+    }
+    if(UART8 == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART8) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART8);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART8);
+    }
+}
+/// @}
+
+/// @}
+
+/// @}

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c

@@ -0,0 +1,234 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_rtc.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE RTC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_RTC_C_
+
+// Files includes
+#include "hal_rtc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup RTC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup RTC_Exported_Functions
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified RTC interrupts.
+/// @param  it: specifies the RTC interrupts sources to be enabled or
+///         disabled.
+///         This parameter can be any combination of the following values:
+/// @arg    RTC_IT_OW: Overflow interrupt
+/// @arg    RTC_IT_ALR: Alarm interrupt
+/// @arg    RTC_IT_SEC: Second interrupt
+/// @param  state: new state of the specified RTC interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_ITConfig(RTC_IT_TypeDef it, FunctionalState state)
+{
+    (state == ENABLE) ? (RTC->CR |= it) : (RTC->CR &= (u16)~it);
+//    RTC_WaitForLastTask();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enters the RTC configuration mode.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_EnterConfigMode(void)
+{
+//    PWR->CR |= PWR_CR_DBP;
+    RTC->CSR |= RTC_CSR_CNF;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Exits from the RTC configuration mode.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_ExitConfigMode(void)
+{
+    RTC->CSR &= ~RTC_CSR_CNF;
+    while (!(RTC->CSR & RTC_CSR_RTOFF));
+//    PWR->CR  &= ~PWR_CR_DBP;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Gets the RTC counter value.
+/// @param  None.
+/// @retval RTC counter value.
+////////////////////////////////////////////////////////////////////////////////
+u32 RTC_GetCounter(void)
+{
+    u32 dat = RTC->CNTH << 16;
+    return (RTC->CNTL | dat);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the RTC counter value.
+/// @param  count: RTC counter new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_SetCounter(u32 count)
+{
+    RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
+    RTC->CNTH = count >> 16;
+    RTC->CNTL = count;
+    RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
+//    while (!(RTC->CSR & RTC_CSR_RTOFF));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the RTC prescaler value.
+/// @param  prescaler: RTC prescaler new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_SetPrescaler(u32 prescaler)
+{
+    RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
+    RTC->PRLH = prescaler >> 16;
+    RTC->PRLL = prescaler;
+    RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
+//    while (!(RTC->CSR & RTC_CSR_RTOFF));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the RTC alarm value.
+/// @param  alarm: RTC alarm new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_SetAlarm(u32 alarm)
+{
+    RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
+    RTC->ALRH = alarm >> 16;
+    RTC->ALRL = alarm;
+    RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
+//    while (!(RTC->CSR & RTC_CSR_RTOFF));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Gets the RTC divider value.
+/// @param  None.
+/// @retval RTC Divider value.
+////////////////////////////////////////////////////////////////////////////////
+u32 RTC_GetDivider(void)
+{
+    u32 dat = ((u32)(RTC->DIVH & RTC_DIVH_DIV) << 16);
+    return (RTC->DIVL | dat);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Waits until last write operation on RTC registers has finished.
+/// @note   This function must be called before any write to RTC registers.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_WaitForLastTask(void)
+{
+    while (!(RTC->CSR & RTC_CSR_RTOFF));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
+///         are synchronized with RTC APB clock.
+/// @note   This function must be called before any read operation after an APB
+///         reset or an APB clock stop.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_WaitForSynchro(void)
+{
+    RTC->CSR &= ~RTC_CSR_RSF;
+    while (!(RTC->CSR & RTC_CSR_RSF));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified RTC flag is set or not.
+/// @param  flag: specifies the flag to check.
+///         This parameter can be one the following values:
+/// @arg    RTC_FLAG_RTOFF: RTC Operation OFF flag
+/// @arg    RTC_FLAG_RSF: Registers Synchronized flag
+/// @arg    RTC_FLAG_OW: Overflow flag
+/// @arg    RTC_FLAG_ALR: Alarm flag
+/// @arg    RTC_FLAG_SEC: Second flag
+/// @retval The state of RTC_FLAG (SET or RESET).
+/////////////////////////////////////////////////////////////////////////////////
+FlagStatus RTC_GetFlagStatus(RTC_FLAG_TypeDef flag)
+{
+    return  (FlagStatus)(RTC->CSR & flag);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the RTC's pending flags.
+/// @param  flag: specifies the flag to clear.
+///         This parameter can be any combination of the following values:
+/// @arg    RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only
+///         after an APB reset or an APB Clock stop.
+/// @arg    RTC_FLAG_OW: Overflow flag
+/// @arg    RTC_FLAG_ALR: Alarm flag
+/// @arg    RTC_FLAG_SEC: Second flag
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_ClearFlag(RTC_FLAG_TypeDef flag)
+{
+    RTC->CSR &= ~flag;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified RTC interrupt has occurred or not.
+/// @param  it: specifies the RTC interrupts sources to check.
+///         This parameter can be one of the following values:
+/// @arg    RTC_IT_OW: Overflow interrupt
+/// @arg    RTC_IT_ALR: Alarm interrupt
+/// @arg    RTC_IT_SEC: Second interrupt
+/// @retval The state of the RTC_IT (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus RTC_GetITStatus(RTC_IT_TypeDef it)
+{
+    return  (ITStatus)(RTC->CSR & it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the RTC's interrupt pending bits.
+/// @param  it: specifies the interrupt pending bit to clear.
+///         This parameter can be any combination of the following values:
+/// @arg    RTC_IT_OW: Overflow interrupt
+/// @arg    RTC_IT_ALR: Alarm interrupt
+/// @arg    RTC_IT_SEC: Second interrupt
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_ClearITPendingBit(RTC_IT_TypeDef it)
+{
+//    RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
+    RTC->CSR &= ~it;
+//    RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
+}
+
+
+/// @}
+
+/// @}
+
+/// @}

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c

@@ -0,0 +1,527 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_sdio.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE SDIO FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_SDIO_C_
+#include "reg_sdio.h"
+#include "hal_sdio.h"
+#include "hal_rcc.h"
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup SDIO_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup SDIO_Exported_Functions
+/// @{
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the SDIO peripheral registers to their default reset
+///         values.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_DeInit(void)
+{
+    RCC_AHBPeriphResetCmd(RCC_AHBRSTR_SDIO, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBRSTR_SDIO, DISABLE);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each SDIO_InitStruct member with its default value.
+/// @param  SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
+///         will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+    // SDIO_InitStruct members default value
+    SDIO_InitStruct->SDIO_MDEN = 0;
+    SDIO_InitStruct->SDIO_DATWT = 0;
+    SDIO_InitStruct->SDIO_SelPTSM = 0;
+    SDIO_InitStruct->SDIO_CLKSP = 0;
+    SDIO_InitStruct->SDIO_OUTM = 0;
+    SDIO_InitStruct->SDIO_SelSM = 0;
+    SDIO_InitStruct->SDIO_OPMSel = 0;
+}
+
+
+///
+/// @brief  Fills each SDIO_DataInitStruct member with its default value.
+/// @param  SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
+///         will be initialized.
+/// @retval None
+///
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+    /* SDIO_DataInitStruct members default value */
+    SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
+    SDIO_DataInitStruct->SDIO_DataLength = 0x00;
+    SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
+    SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
+//    SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
+//    SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
+}
+
+///
+/// @brief  Initializes the SDIO data path according to the specified
+///   parameters in the SDIO_DataInitStruct.
+/// @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
+///   contains the configuration information for the SDIO command.
+/// @retval None
+///
+//void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+//{
+//    u32 tmpreg = 0;
+
+//    /*---------------------------- SDIO DTIMER Configuration ---------------------*/
+//    /* Set the SDIO Data TimeOut value */
+//    SDIO->MMC_TIMEOUTCNT = SDIO_DataInitStruct->SDIO_DataTimeOut;
+
+//    /*---------------------------- SDIO DLEN Configuration -----------------------*/
+//    /* Set the SDIO DataLength value */
+//    SDIO->MMC_BYTECNTL = SDIO_DataInitStruct->SDIO_DataLength;
+
+//    /*---------------------------- SDIO DCTRL Configuration ----------------------*/
+//    /* Get the SDIO DCTRL value */
+//    tmpreg = SDIO->DCTRL;
+//    /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
+//    tmpreg &= DCTRL_CLEAR_MASK;
+//    /* Set DEN bit according to SDIO_DPSM value */
+//    /* Set DTMODE bit according to SDIO_TransferMode value */
+//    /* Set DTDIR bit according to SDIO_TransferDir value */
+//    /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
+//    tmpreg |= (u32)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir;//
+//              //| SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
+
+//    /* Write to SDIO DCTRL */
+//    SDIO->DCTRL = tmpreg;
+//}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  The frequency division factor is configured to generate the SDIO clock.
+/// @param  value : 1MHz = Fhclk/((mmc_cardsel[5 : 0] + 1) × 2)
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_ClockSet(u32 value)
+{
+//    SDIO->MMC_CARDSEL &= ~SDIO_MMC_CARDSEL_MASK;
+    SDIO->MMC_CARDSEL = (SDIO_MMC_CARDSEL_CTREN | SDIO_MMC_CARDSEL_ENPCLK | (value & 0x3F));
+//    SDIO->MMC_CARDSEL = 0xC0+0x2F;//0xdf;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the SDIO peripheral according to the specified
+///         parameters in the SDIO_InitStruct.
+/// @param  SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
+///         that contains the configuration information for the SDIO peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+    SDIO->MMC_CTRL &= 0x700;
+    SDIO->MMC_CTRL |= (SDIO_InitStruct->SDIO_OPMSel | SDIO_InitStruct->SDIO_SelSM |
+                       SDIO_InitStruct->SDIO_OUTM | SDIO_InitStruct->SDIO_CLKSP |
+                       SDIO_InitStruct->SDIO_SelPTSM | SDIO_InitStruct->SDIO_DATWT |
+                       SDIO_InitStruct->SDIO_MDEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the SDIO interrupts.
+/// @param  SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
+///         state  : new state of the specified SDIO interrupts.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_ITConfig(u32 SDIO_IT, FunctionalState state)
+{
+    (state) ?  (SDIO->MMC_INT_MASK |= SDIO_IT) : (SDIO->MMC_INT_MASK &= ~SDIO_IT);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the SDIO CRC.
+/// @param  SDIO_CRC: specifies the SDIO CRC sources to be enabled or disabled.
+///         state   : new state of the specified SDIO CRC.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_CRCConfig(u32 SDIO_CRC, FunctionalState state)
+{
+    (state) ?  (SDIO->MMC_CRCCTL |= SDIO_CRC) : (SDIO->MMC_CRCCTL &= ~SDIO_CRC);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Port transfer speed mode.
+/// @param  clkdiv : High/low speed.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_Clock_Set(u8 clkdiv)
+{
+    SDIO->MMC_CTRL &= ~SDIO_MMC_CTRL_SelPTSM;
+    (clkdiv) ? (SDIO->MMC_CTRL |= SDIO_MMC_CTRL_SelPTSM) : (SDIO->MMC_CTRL &= ~SDIO_MMC_CTRL_SelPTSM);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Turn off the SDIO switch.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error SD_PowerOFF(void)
+{
+    SDIO->MMC_CARDSEL &= ~(SDIO_MMC_CARDSEL_ENPCLK | SDIO_MMC_CARDSEL_CTREN);
+    return SD_OK;
+}
+///
+/// @brief  Fills each SDIO_CmdInitStruct member with its default value.
+/// @param  SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
+///         structure which will be initialized.
+/// @retval None
+///
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
+{
+    /* SDIO_CmdInitStruct members default value */
+    SDIO_CmdInitStruct->SDIO_Argument = 0x00;
+    SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
+    SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
+    SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
+//    SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SDIO sends command functions.
+/// @param  cmdindex : Type the command.
+///         waitrsp  : Expected correspondence.
+///         arg      : parameter.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_Send_Cmd(u8 cmdindex, u8 waitrsp, u32 arg)
+{
+    SDIO->CMD_BUF0 = (arg >> 0) & 0xFF;
+    SDIO->CMD_BUF1 = (arg >> 8) & 0xFF;
+    SDIO->CMD_BUF2 = (arg >> 16) & 0xFF;
+    SDIO->CMD_BUF3 = (arg >> 24) & 0xFF;
+    SDIO->CMD_BUF4 = 0x40 | cmdindex;
+    SDIO->CLR_MMC_INT |= 0;
+    SDIO->MMC_IO = SDIO_MMC_IO_AUTOTR;
+    while(1) {
+        if(SDIO->CLR_MMC_INT & SDIO_CLR_MMC_INT_CMDDMC) {
+            SDIO->CLR_MMC_INT |= SDIO_CLR_MMC_INT_CMDDMC;
+            break;
+        }
+    }
+    if(waitrsp == SDIO_Response_Short) {
+        SDIO->MMC_IO =  SDIO_MMC_IO_AUTOCLKG | \
+                        SDIO_MMC_IO_AUTOTR | \
+                        SDIO_MMC_IO_RESPCMDSEL;
+    }
+    else if(waitrsp == SDIO_Response_Long) {
+        SDIO->MMC_IO =  SDIO_MMC_IO_AUTOCLKG | \
+                        SDIO_MMC_IO_AUTOTR | \
+                        SDIO_MMC_IO_RESPCMDSEL | \
+                        SDIO_MMC_IO_CID_CSDRD;
+    }
+    else {
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Check the execution status of CMD0.
+/// @param  None.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdError(void)
+{
+    SD_Error errorstatus = SD_OK;
+    u32 timeout = SDIO_CMD0TIMEOUT;
+    while (timeout--) {
+        if(((SDIO->MMC_IO & SDIO_MMC_IO_RESPCMDSEL) == 0) && ((SDIO->MMC_IO & SDIO_MMC_IO_AUTOTR) == 0))
+            break;
+    }
+    if (timeout == 0)
+        return SD_CMD_RSP_TIMEOUT;
+    SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
+    return errorstatus;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Check the error status of the R1 response.
+/// @param  cmd : Current command.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdResp1Error(u8 cmd)
+{
+    u32 status;
+    u32 response;
+    while(1) {
+        status = SDIO->CLR_MMC_INT ;
+        if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
+            break;
+    }
+    if(status & SDIO_CLR_MMC_INT_CRNTMC) {
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
+        return SD_CMD_RSP_TIMEOUT;
+    }
+    if(status & (SDIO_CLR_MMC_INT_CRCEMC)) {
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC;
+        return SD_CMD_CRC_FAIL;
+    }
+    SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
+
+    if((SDIO->CMD_BUF4 & 0x3F) != cmd) {
+        return SD_ILLEGAL_CMD;
+    }
+    response = SDIO->CMD_BUF3 << 24  | SDIO->CMD_BUF2 << 16  | SDIO->CMD_BUF1 << 8  | SDIO->CMD_BUF0;
+    return (SD_Error)(response & SD_OCR_ERRORBITS);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Check the execution status of CMD2.
+/// @param  None.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdResp2Error(void)
+{
+    SD_Error errorstatus = SD_OK;
+    u32 status;
+    u32 timeout = SDIO_CMD0TIMEOUT;
+    while(timeout--) {
+        status = SDIO->CLR_MMC_INT ;
+        if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
+            break;
+    }
+    if((timeout == 0) || (status & SDIO_CLR_MMC_INT_CRNTMC)) {
+        errorstatus = SD_CMD_RSP_TIMEOUT;
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
+        return errorstatus;
+    }
+    if(status & SDIO_CLR_MMC_INT_CRCEMC) {
+        errorstatus = SD_CMD_CRC_FAIL;
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC;
+    }
+    SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
+    return errorstatus;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Check the execution status of CMD3.
+/// @param  None.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdResp3Error(void)
+{
+    u32 status;
+    while(1) {
+        status = SDIO->CLR_MMC_INT ;
+        if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
+            break;
+    }
+    if(status & SDIO_CLR_MMC_INT_CRNTMC) {
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
+        return SD_CMD_RSP_TIMEOUT;
+    }
+    SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
+    return SD_OK;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Check the execution status of CMD6.
+/// @param  None.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdResp6Error(u8 cmd, u16* prca)
+{
+    SD_Error errorstatus = SD_OK;
+    u32 status;
+    u32 rspr1;
+    while(1) {
+        status = SDIO->CLR_MMC_INT ;
+        if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
+            break;
+    }
+    if(status & SDIO_CLR_MMC_INT_CRNTMC) {
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
+        return SD_CMD_RSP_TIMEOUT;
+    }
+    if(status & SDIO_CLR_MMC_INT_CRCEMC) {
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC;
+        return SD_CMD_CRC_FAIL;
+    }
+    if((SDIO->CMD_BUF4 & 0x3F) != cmd) {
+        return SD_ILLEGAL_CMD;
+    }
+    SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
+    rspr1 = SDIO->CMD_BUF3 << 24  | SDIO->CMD_BUF2 << 16  | SDIO->CMD_BUF1 << 8  | SDIO->CMD_BUF0;
+    if(SD_ALLZERO == (rspr1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED))) {
+        *prca = (u16)(rspr1 >> 16);
+        return errorstatus;
+    }
+    if(rspr1 & SD_R6_GENERAL_UNKNOWN_ERROR) {
+        return SD_GENERAL_UNKNOWN_ERROR;
+    }
+    if(rspr1 & SD_R6_ILLEGAL_CMD) {
+        return SD_ILLEGAL_CMD;
+    }
+    if(rspr1 & SD_R6_COM_CRC_FAILED) {
+        return SD_COM_CRC_FAILED;
+    }
+    return errorstatus;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Check the execution status of CMD7.
+/// @param  None.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdResp7Error(void)
+{
+    SD_Error errorstatus = SD_OK;
+    u32 status;
+    u32 timeout = SDIO_CMD0TIMEOUT;
+    while(timeout--) {
+        status = SDIO->CLR_MMC_INT ;
+        if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
+            break;
+    }
+    if((timeout == 0) || (status & SDIO_CLR_MMC_INT_CRNTMC)) { //timeout
+        errorstatus = SD_CMD_RSP_TIMEOUT;
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
+        return errorstatus;
+    }
+    if(status & SDIO_CLR_MMC_INT_CMDDMC) {
+        errorstatus = SD_OK;
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CMDDMC;
+    }
+    return errorstatus;
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Write data direction block size configuration.
+/// @param  datatimeout : maximum latency.
+///         datalen     : data len
+///         blksize     : block count.
+///         dir         :  direction
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_Send_Data_Cfg(u32 datatimeout, u32 datalen, u8 blksize, u8 dir)
+{
+    u32 tmpreg, tmpreg1, tmpreg2 = 0;
+    tmpreg = SDIO->MMC_IO_MBCTL;
+    tmpreg1 = SDIO->MMC_IO;
+    tmpreg &= ~(SDIO_MMC_IO_MBCTL_BTSSel | SDIO_MMC_IO_MBCTL_SPMBDTR | SDIO_MMC_IO_MBCTL_SMBDTD);
+    if (datatimeout < 100) {
+        SDIO->MMC_TIMEOUTCNT = datatimeout;
+    }
+    else if (datatimeout < 10000) {
+        SDIO->MMC_TIMEOUTCNT = datatimeout / 100;
+        tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel;
+    }
+    else if (datatimeout < 1000000) {
+        SDIO->MMC_TIMEOUTCNT = datatimeout / 10000;
+        tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel_2;
+    }
+    else {
+        SDIO->MMC_TIMEOUTCNT = datatimeout / 1000000;
+        tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel;
+    }
+    SDIO->MMC_BYTECNTL = datalen & 0x1FFFFFF; ;
+    SDIO->MMC_BLOCKCNT = blksize;
+    if (dir == 0) {
+        tmpreg |= SDIO_MMC_IO_MBCTL_SMBDTD;
+        tmpreg1 |= SDIO_MMC_IO_TRANSFDIR;
+        tmpreg2 |= SDIO_BUF_CTLL_SBAD;
+    }
+    else {
+        tmpreg &= ~(SDIO_MMC_IO_MBCTL_SMBDTD);
+        tmpreg1 &= ~(SDIO_MMC_IO_TRANSFDIR);
+        tmpreg2 &= ~(SDIO_BUF_CTLL_SBAD);
+    }
+    SDIO->MMC_IO_MBCTL = tmpreg;
+    SDIO->MMC_IO = tmpreg1;
+    SDIO->BUF_CTL = tmpreg2;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the SDIO's Flag pending bits.
+/// @param  SDIO_IT: specifies the flag pending bit to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_ClearFlag(u32 SDIO_FLAG)
+{
+    SDIO->CLR_MMC_INT |= SDIO_FLAG;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the SDIO's interrupt pending bits.
+/// @param  SDIO_IT: specifies the interrupt pending bit to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_ClearITPendingBit(u32 SDIO_IT)
+{
+    SDIO->CLR_MMC_INT |= SDIO_IT;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified SDIO flag is set or not.
+/// @param  SDIO_FLAG: specifies the flag to check.
+/// @retval The new state of SDIO_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG)
+{
+    return ((SDIO->CLR_MMC_INT & SDIO_FLAG) ? SET : RESET);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reads the value of the data transfer timeout count
+/// @param  None.
+/// @retval timeout count.
+////////////////////////////////////////////////////////////////////////////////
+u32 SDIO_GetTimeOutCounter(void)
+{
+    return (SDIO->MMC_TIMEOUTCNT & 0xFF);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Read one data word from FIFO.
+/// @param  None.
+/// @retval Data received.
+////////////////////////////////////////////////////////////////////////////////
+u32 SDIO_ReadData(void)
+{
+    return SDIO->FIFO;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Write one data word to FIFO.
+/// @param  tempbuff : Write data.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_WriteData(u32 tempbuff)
+{
+    SDIO->FIFO = tempbuff;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns number of remaining data bytes to be transferred.
+/// @param  None
+/// @retval Number of remaining data bytes to be transferred
+////////////////////////////////////////////////////////////////////////////////
+u32 SDIO_GetDataCounter(void)
+{
+    return SDIO->MMC_BYTECNTL;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable or Dsiable DMA .
+/// @param  tempbuff : Write data.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_DMACmd(FunctionalState state)
+{
+    (state) ?  ((SDIO->BUF_CTL |= SDIO_BUF_CTLL_DMAHEN), SDIO->BUF_CTL &= (~(SDIO_BUF_CTLL_DRM))) : (SDIO->BUF_CTL &= ~SDIO_BUF_CTLL_DMAHEN);
+}
+
+
+/// @}
+
+/// @}
+
+/// @}
+

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c

@@ -0,0 +1,648 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_spi.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE SPI FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_SPI_C_
+#include <math.h>
+// Files includes
+#include "hal_spi.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup SPI_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+///@addtogroup SPI_Exported_Functions
+///@{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the spi peripheral registers to their
+///         default reset values.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_DeInit(SPI_TypeDef* spi)
+{
+    switch (*(vu32*)&spi) {
+        case (u32)SPI2:  // SPI2_BASE:
+            RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI2, ENABLE);
+            RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI2, DISABLE);
+            break;
+        case (u32)SPI3:  // SPI3_BASE:
+            RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI3, ENABLE);
+            RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI3, DISABLE);
+            break;
+        case (u32)SPI1:  // SPI1_BASE:
+            RCC_APB2PeriphResetCmd(RCC_APB2ENR_SPI1, ENABLE);
+            RCC_APB2PeriphResetCmd(RCC_APB2ENR_SPI1, DISABLE);
+            break;
+        default:
+            break;
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the spi peripheral according to the specified
+///         parameters in the init_struct .
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  init_struct: pointer to a SPI_InitTypeDef structure
+///         that contains the configuration information for the
+///         specified SPI peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_Init(SPI_TypeDef* spi, SPI_InitTypeDef* init_struct)
+{
+    if (init_struct->SPI_DataSize == SPI_DataSize_32b) {
+        SET_BIT(spi->GCR, SPI_GCR_DWSEL);
+    }
+    else {
+        CLEAR_BIT(spi->GCR, SPI_GCR_DWSEL);
+    }
+    MODIFY_REG(spi->GCR, SPI_GCR_NSS, init_struct->SPI_NSS);
+    MODIFY_REG(spi->GCR, SPI_GCR_MODE, init_struct->SPI_Mode);
+    MODIFY_REG(spi->CCR, SPI_CCR_LSBFE, init_struct->SPI_FirstBit);
+    MODIFY_REG(spi->CCR, SPI_CCR_CPOL, init_struct->SPI_CPOL);
+    MODIFY_REG(spi->CCR, SPI_CCR_CPHA, init_struct->SPI_CPHA);
+
+    SET_BIT(spi->CCR, SPI_CCR_SPILEN);
+
+    MODIFY_REG(spi->BRR, BRR_Mask, init_struct->SPI_BaudRatePrescaler);
+
+    if (init_struct->SPI_DataWidth >= 32) {
+        MODIFY_REG(spi->ECR, ECR_Mask, 0);
+    }
+    else {
+        MODIFY_REG(spi->ECR, ECR_Mask, init_struct->SPI_DataWidth);
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param  init_struct: pointer to a SPI_InitTypeDef structure
+///         which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_StructInit(SPI_InitTypeDef* init_struct)
+{
+    init_struct->SPI_Mode              = SPI_Mode_Slave;
+    init_struct->SPI_DataSize          = SPI_DataSize_8b;
+    init_struct->SPI_DataWidth         = 8;
+    init_struct->SPI_CPOL              = SPI_CPOL_Low;
+    init_struct->SPI_CPHA              = SPI_CPHA_1Edge;
+    init_struct->SPI_NSS               = SPI_NSS_Soft;
+    init_struct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+    init_struct->SPI_FirstBit          = SPI_FirstBit_MSB;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified SPI peripheral.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  state: new state of the spi peripheral.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_Cmd(SPI_TypeDef* spi, FunctionalState state)
+{
+    (state) ? SET_BIT(spi->GCR, SPI_GCR_SPIEN) : CLEAR_BIT(spi->GCR, SPI_GCR_SPIEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified SPI interrupts.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:SPI1, SPI2.
+/// @param  interrupt: specifies the SPI interrupt sources to be
+///         enabled or disabled.
+///         This parameter can be one of the following values:
+/// @arg    SPI_IT_TXEPT: Transmitter empty interrupt
+/// @arg    SPI_IT_RXFULL: RX FIFO full interrupt
+/// @arg    SPI_IT_RXMATCH: Receive data match the RXDNR number interrupt
+/// @arg    SPI_IT_RXOERR: Receive overrun error interrupt
+/// @arg    SPI_IT_UNDERRUN: underrun interrupt
+/// @arg    SPI_IT_RX: Receive data available interrupt
+/// @arg    SPI_IT_TX: Transmit FIFO available interrupt
+/// @param  state: new state of the specified spi interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_ITConfig(SPI_TypeDef* spi, u8 interrupt, FunctionalState state)
+{
+    if (state) {
+        SET_BIT(spi->GCR, (u32)SPI_GCR_IEN);
+        SET_BIT(spi->IER, (u32)interrupt);
+    }
+    else {
+        CLEAR_BIT(spi->IER, interrupt);
+        CLEAR_BIT(spi->GCR, SPI_GCR_IEN);
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the SPI DMA interface.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  state: new state of the DMA Request sources.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_DMACmd(SPI_TypeDef* spi, FunctionalState state)
+{
+    (state) ? SET_BIT(spi->GCR, SPI_GCR_DMAEN) : CLEAR_BIT(spi->GCR, SPI_GCR_DMAEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  configure tn Fifo trigger level bit.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  fifo_trigger_value: specifies the Fifo trigger level
+///         This parameter can be any combination of the following values:
+///         SPI_TXTLF : SPI TX FIFO Trigger value set
+///         SPI_RXTLF : SPI RX FIFO Trigger value set
+/// @param  state: new state of the selected SPI transfer request.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_FifoTrigger(SPI_TypeDef* spi, SPI_TLF_TypeDef fifo_trigger_value, FunctionalState state)
+{
+    (state) ? SET_BIT(spi->GCR, (u32)fifo_trigger_value) : CLEAR_BIT(spi->GCR, (u32)fifo_trigger_value);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Transmits a Data through the spi peripheral.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  data : Data to be transmitted.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_SendData(SPI_TypeDef* spi, u32 data)
+{
+    u16 templen;
+    __asm volatile("cpsid i");
+
+    WRITE_REG(spi->TDR, data);
+
+    templen = READ_REG(spi->ECR);
+    if(templen  == 0)
+        templen = 32;
+    if (templen > 8)
+        WRITE_REG(spi->TDR, data >> 8);
+    if (templen > 16)
+        WRITE_REG(spi->TDR, data >> 16);
+    if (templen > 24)
+        WRITE_REG(spi->TDR, data >> 24);
+    __asm volatile("cpsie i");
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the most recent received data by the spi peripheral.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @retval The value of the received data.
+////////////////////////////////////////////////////////////////////////////////
+u32 SPI_ReceiveData(SPI_TypeDef* spi)
+{
+    u32 temp;
+    u8 templen;
+    __asm volatile("cpsid i");
+
+    temp = READ_REG(spi->RDR);
+
+    templen = READ_REG(spi->ECR);
+    if(templen  == 0)
+        templen = 32;
+    if (templen > 8)
+        temp |= (u32)(READ_REG(spi->RDR) << 8);
+    if (templen > 16)
+        temp |= (u32)(READ_REG(spi->RDR) << 16);
+    if (templen > 24)
+        temp |= (u32)(READ_REG(spi->RDR) << 24);
+
+    __asm volatile("cpsie i");
+
+    return temp;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Slave chip csn single by selected
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  state: new state of the selected SPI CS pin
+///         request.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state)
+{
+    (state) ? CLEAR_BIT(spi->NSSR, SPI_NSSR_NSS) : SET_BIT(spi->NSSR, SPI_NSSR_NSS);  // illogical
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the NSS pin control mode for the selected SPI.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  nss: specifies the SPI NSS internal state.
+///         This parameter can be one of the following values:
+/// @arg    SPI_NSS_Soft: NSS pin control by software
+/// @arg    SPI_NSS_Hard: NSS pin control by hardware
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* spi, SPI_NSS_TypeDef nss)
+{
+    (nss != SPI_NSS_Soft) ? SET_BIT(spi->GCR, SPI_NSS_Hard) : CLEAR_BIT(spi->GCR, SPI_NSS_Hard);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the data size for the selected SPI.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  data_size: specifies the SPI data size.
+///         This parameter can be one of the following values:
+///         0 to 31, 0 = 32b, 1 = 1b, 2 = 2b
+/// @arg    DataSize : 0 to 31
+/// @retval None.
+/// @retval None.
+bool SPI_DataSizeConfig(SPI_TypeDef* spi, u8 data_size)
+{
+    if (data_size > 32)
+        return false;
+    data_size &= 0x1F;
+    WRITE_REG(spi->ECR, data_size);
+    return true;
+}
+
+//////////////////////////////////////////////////////////////////////////////////
+void SPI_DataSizeTypeConfig(SPI_TypeDef* spi, SPI_DataSize_TypeDef SPI_DataSize)
+{
+    CLEAR_BIT(spi->GCR, (u32)SPI_DataSize_32b);
+    SET_BIT(spi->GCR, (u32)SPI_DataSize);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Selects the data transfer direction in bi-directional mode
+///         for the specified SPI.
+/// @param spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param direction: specifies the data transfer direction in
+///         bi-directional mode.
+///         This parameter can be one of the following values:
+/// @arg    SPI_Direction_Tx: Selects Tx transmission direction
+/// @arg    SPI_Direction_Rx: Selects Rx receive direction
+/// @arg    SPI_Disable_Tx: Selects Rx receive direction
+/// @arg    SPI_Disable_Rx: Selects Rx receive direction
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* spi, SPI_Direction_TypeDef direction)
+{
+    switch (direction) {
+        case SPI_Direction_Rx:
+            SET_BIT(spi->GCR, SPI_GCR_RXEN);
+            break;
+        case SPI_Direction_Tx:
+            SET_BIT(spi->GCR, SPI_GCR_TXEN);
+            break;
+        case SPI_Disable_Rx:
+            CLEAR_BIT(spi->GCR, SPI_GCR_RXEN);
+            break;
+        case SPI_Disable_Tx:
+            CLEAR_BIT(spi->GCR, SPI_GCR_TXEN);
+            break;
+        default:
+            break;
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified SPI flag is set or not.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  flag: specifies the SPI flag to check.
+///         This parameter can be one of the following values:
+/// @arg    SPI_FLAG_RXAVL: Rx buffer has bytes flag
+/// @arg    SPI_FLAG_TXEPT: Tx buffer and tx shifter empty flag
+/// @arg    SPI_FLAG_TXFULL: Tx buffer full flag
+/// @arg    SPI_FLAG_RXAVL_4BYTE: Receive available 4 byte data message flag.
+/// @retval The new state of SPI_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus SPI_GetFlagStatus(SPI_TypeDef* spi, SPI_FLAG_TypeDef flag)
+{
+//    u8 number;
+    return (spi->SR & flag) ? SET : RESET;
+//  if (spi->ECR == 8 || spi->ECR == 0)
+//      return (spi->SR & SPI_FLAG) ? SET : RESET;
+//  else {
+//      if ((spi->ECR > 0) && (spi->ECR <= 8))
+//          number = 1;
+//      else if ((spi->ECR) <= 16)
+//          number = 2;
+//      else if ((spi->ECR) <= 24)
+//          number = 3;
+//      else if (((spi->ECR) <= 31) || (spi->ECR == 0))
+//          number = 4;
+//      return (((spi->SR & 0xf00) >> 8) >= number) ? SET : RESET;
+//  }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified SPI interrupt has occurred or not.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  interrupt: specifies the SPI interrupt source to check.
+///         This parameter can be one of the following values:
+/// @arg    SPI_IT_TX: Tx buffer empty interrupt
+/// @arg    SPI_IT_RX: Rx buffer  interrupt
+/// @arg    SPI_IT_UNDERRUN: under Error interrupt in slave mode
+/// @arg    SPI_IT_RXOVER: RX OVER Error interrupt
+/// @arg    SPI_IT_RXMATCH: spectials rx data numbers  interrupt
+/// @arg    SPI_IT_RXFULL: Rx buffer full interrupt
+/// @arg    SPI_IT_TXEPT: Tx buffer  and tx shifter empty interrupt
+/// @retval The new state of SPI_IT (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus SPI_GetITStatus(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt)
+{
+    return (spi->ISR & interrupt) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the spi  interrupt pending bit.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  interrupt: specifies the SPI interrupt pending bit to clear.
+/// @arg    SPI_IT_TX: Tx buffer empty interrupt
+/// @arg    SPI_IT_RX: Rx buffer  interrupt
+/// @arg    SPI_IT_UNDERRUN: under Error interrupt in slave mode
+/// @arg    SPI_IT_RXOVER: RX OVER Error interrupt
+/// @arg    SPI_IT_RXMATCH: spectials rx data numbers  interrupt
+/// @arg    SPI_IT_RXFULL: Rx buffer full interrupt
+/// @arg    SPI_IT_TXEPT: Tx buffer  and tx shifter empty interrupt
+///         This function clears only ERR intetrrupt pending bit.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_ClearITPendingBit(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt)
+{
+    SET_BIT(spi->ICR, interrupt);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SPI Hole a count Received bytes in next receive process.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  number: specifies the SPI receive Number.
+///         This parament can be 1-65535.
+///         This function can use only in SPI master single receive mode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_RxBytes(SPI_TypeDef* spi, u16 number)
+{
+    WRITE_REG(spi->RDNR, number);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  slave mode tx data transmit phase adjust set.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  adjust_value: slave mode tx data transmit phase adjust enum.
+///         This parament can be :
+///         SPI_SlaveAdjust_FAST:  fast speed use
+///         SPI_SlaveAdjust_LOW:   low speed use
+///         This function can use only in SPI master single receive mode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_SlaveAdjust(SPI_TypeDef* spi, SPI_SlaveAdjust_TypeDef adjust_value)
+{
+    (adjust_value) ? SET_BIT(spi->CCR, SPI_CCR_RXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_RXEDGE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables all SPI interrupts.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  state: new state of all spi interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exSPI_ITCmd(SPI_TypeDef* spi, FunctionalState state)
+{
+    (state) ? SET_BIT(spi->IER, (u32)SPI_GCR_IEN) : CLEAR_BIT(spi->IER, (u32)SPI_GCR_IEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified SPI interrupts.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  interrupt: specifies the SPI interrupt sources to be enabled or disabled.
+///         This parameter can be one of the following values:
+/// @arg    SPI_IT_TXEPT: Transmitter empty interrupt
+/// @arg    SPI_IT_RXFULL: RX FIFO full interrupt
+/// @arg    SPI_IT_RXMATCH: Receive data match the RXDNR number interrupt
+/// @arg    SPI_IT_RXOERR: Receive overrun error interrupt
+/// @arg    SPI_IT_UNDERRUN: underrun interrupt
+/// @arg    SPI_IT_RX: Receive data available interrupt
+/// @arg    SPI_IT_TX: Transmit FIFO available interrupt
+/// @param  state: new state of the specified spi interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exSPI_ITConfig(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt, FunctionalState state)
+{
+    (state) ? SET_BIT(spi->IER, (u32)interrupt) : CLEAR_BIT(spi->IER, (u32)interrupt);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the SPI DMA request.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  state: new state of the DMA Request.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exSPI_DMACmd(SPI_TypeDef* spi, FunctionalState state)
+{
+    (state) ? SET_BIT(spi->GCR, SPI_GCR_DMAEN) : CLEAR_BIT(spi->GCR, SPI_GCR_DMAEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set or reset Slave chip csn signal output
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  state: new state of Slave chip csn signal output.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exSPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state)
+{
+    (state) ? CLEAR_BIT(spi->NSSR, SPI_NSSR_NSS) : SET_BIT(spi->NSSR, SPI_NSSR_NSS);  // illogical
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  tx data and rx data phase adjust.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  adjust_value: choose adjust mode.
+///         This parament can be :
+///         SPI_DataEdgeAdjust_LOW,
+///         SPI_DataEdgeAdjust_FAST
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exSPI_DataEdgeAdjust(SPI_TypeDef* spi, SPI_DataEdgeAdjust_TypeDef adjust_value)
+{
+    // master mode
+    if (spi->GCR & SPI_GCR_MODE) {
+        adjust_value ? SET_BIT(spi->CCR, SPI_CCR_RXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_RXEDGE);
+    }
+    // slave mode
+    else {
+        adjust_value ? SET_BIT(spi->CCR, SPI_CCR_TXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_TXEDGE);
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set or reset i2s
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2, SPI3.
+/// @param  state: new state of Slave chip csn signal output.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2S_Cmd(SPI_TypeDef* spi, FunctionalState state)
+{
+    (state) ? SET_BIT(spi->CFGR, I2S_CFGR_SPI_I2S) : CLEAR_BIT(spi->CFGR, I2S_CFGR_SPI_I2S);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  i2s Config
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2, SPI3.
+/// @param  state: new state of Slave chip csn signal output.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2S_Init(SPI_TypeDef* spi, I2S_InitTypeDef* I2S_InitStruct)
+{
+    u32 i2sdiv = 2;
+    u32 tmpreg = 0;
+    u32 packetlength = 1;
+    u32 result = 0, yushu = 0;
+    u32 sourceclock = 0;
+    RCC_ClocksTypeDef RCC_Clocks;
+
+    if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) {
+        i2sdiv = 2;
+    }
+    else {
+        if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) {
+            packetlength = 1;
+        }
+        else {
+            packetlength = 2;
+        }
+        RCC_GetClocksFreq(&RCC_Clocks);
+
+        if((SPI2 == spi) || (SPI3 == spi))  {
+            sourceclock = RCC_Clocks.PCLK1_Frequency;
+        }
+        else {
+            sourceclock = RCC_Clocks.PCLK2_Frequency;
+        }
+        if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) {
+            result = (sourceclock) / (256 * (I2S_InitStruct->I2S_AudioFreq));
+            yushu = (sourceclock) % (256 * (I2S_InitStruct->I2S_AudioFreq));
+            if(yushu > (128 * (I2S_InitStruct->I2S_AudioFreq))) {
+                result = result + 1;
+            }
+            i2sdiv = result;
+            if ((i2sdiv < 2) || (i2sdiv > 0x1FF)) {
+                i2sdiv = 2;
+            }
+        }
+        else {
+            result = (sourceclock) / (16 * 2 * packetlength * (I2S_InitStruct->I2S_AudioFreq));
+            yushu = (sourceclock) % (16 * 2 * packetlength * (I2S_InitStruct->I2S_AudioFreq));
+            if(yushu > ((16 * packetlength * (I2S_InitStruct->I2S_AudioFreq)))) {
+                result = result + 1;
+            }
+            if ((i2sdiv < 1) || (i2sdiv > 0x1FF)) {
+                i2sdiv = 1;
+            }
+        }
+    }
+    if(I2S_CPOL_High  == I2S_InitStruct->I2S_CPOL) {
+        spi->CCTL |= SPI_CCR_CPOL;
+    }
+    else {
+        spi->CCTL &= ~SPI_CCR_CPOL;
+    }
+
+    spi->CFGR = 0x2 << I2S_CFGR_I2SDIV_Pos;
+
+    if((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx)) {
+        spi->GCTL |= SPI_GCR_MODE;
+    }
+    else {
+        spi->GCTL &= ~SPI_GCR_MODE;
+    }
+    if((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx)) {
+        spi->GCTL |= SPI_GCR_TXEN;
+        spi->GCTL &= ~SPI_GCR_RXEN;
+    }
+    else {
+        spi->GCTL &= ~SPI_GCR_TXEN;
+        spi->GCTL |= SPI_GCR_RXEN;
+    }
+//    tmpreg = spi->GCTL;
+//    tmpreg &= ~(1 << 2);
+//    tmpreg |= (u16)(I2S_InitStruct->I2S_Mode);
+//    spi->GCTL = tmpreg;
+//
+    tmpreg = 0;
+    tmpreg |= (i2sdiv << I2S_CFGR_I2SDIV_Pos) | \
+              (I2S_InitStruct->I2S_MCLKOutput) | \
+              (I2S_CFGR_SPI_I2S) | \
+              (I2S_InitStruct->I2S_Standard) | \
+              (I2S_InitStruct->I2S_DataFormat);
+    spi->CFGR &= ~I2S_CFGR_I2SDIV;
+    spi->CFGR |= tmpreg;
+
+}
+/// @}
+
+/// @}
+
+/// @}

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c

@@ -0,0 +1,502 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_uart.c
+/// @file     hal_uart.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE UART FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_UART_C_
+
+// Files includes
+#include "hal_rcc.h"
+#include "hal_uart.h"
+#include "hal_gpio.h"
+#include "hal_dma.h"
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+///@addtogroup UART_HAL
+///@{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup UART_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the uart peripheral registers to their
+///         default reset values.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_DeInit(UART_TypeDef* uart)
+{
+
+
+    if(UART2 == uart) {
+        exRCC_APB1PeriphReset(RCC_APB1ENR_UART2);
+    }
+    if(UART1 == uart) {
+        exRCC_APB2PeriphReset(RCC_APB2ENR_UART1);
+    }
+    if(UART3 == uart) {
+        exRCC_APB1PeriphReset(RCC_APB1ENR_UART3);
+    }
+    if(UART4 == uart) {
+        exRCC_APB1PeriphReset(RCC_APB1ENR_UART4);
+    }
+    if(UART5 == uart) {
+        exRCC_APB1PeriphReset(RCC_APB1ENR_UART5);
+    }
+    if(UART6 == uart) {
+        exRCC_APB2PeriphReset(RCC_APB2ENR_UART6);
+    }
+    if(UART7 == uart) {
+        exRCC_APB1PeriphReset(RCC_APB1ENR_UART7);
+    }
+    if(UART8 == uart) {
+        exRCC_APB1PeriphReset(RCC_APB1ENR_UART8);
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the uart peripheral according to the specified
+///         parameters in the UART_InitStruct .
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  init_struct: pointer to a UART_InitTypeDef structure
+///         that contains the configuration information for the
+///         specified UART peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Init(UART_TypeDef* uart, UART_InitTypeDef* init_struct)
+{
+    u32 apbclock = 0x00;
+    // UART CCR Configuration
+    MODIFY_REG(uart->CCR, UART_CCR_CHAR, init_struct->WordLength);
+
+
+    MODIFY_REG(uart->CCR, (UART_CCR_SPB0 | UART_CCR_SPB1), init_struct->StopBits);
+
+    MODIFY_REG(uart->CCR, (UART_CCR_PEN | UART_CCR_PSEL), init_struct->Parity);
+
+    // UART GCR Configuration
+    MODIFY_REG(uart->GCR, (UART_GCR_TX | UART_GCR_RX), init_struct->Mode);
+    MODIFY_REG(uart->GCR, UART_GCR_AUTOFLOW, init_struct->HWFlowControl);
+
+    //UART BRR Configuration
+    //Configure the UART Baud Rate
+    if (uart == UART1) {
+
+        apbclock = RCC_GetPCLK2Freq();
+    }
+    else {
+        apbclock = RCC_GetPCLK1Freq();
+    }
+    // Determine the UART_baud
+    uart->BRR = (apbclock / init_struct->BaudRate) / 16;
+    uart->FRA = (apbclock / init_struct->BaudRate) % 16;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each UART_InitStruct member with its default value.
+/// @param  init_struct: pointer to a UART_InitTypeDef structure
+///         which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_StructInit(UART_InitTypeDef* init_struct)
+{
+    // UART_InitStruct members default value
+    init_struct->BaudRate       = 9600;
+    init_struct->WordLength     = UART_WordLength_8b;
+    init_struct->StopBits       = UART_StopBits_1;
+    init_struct->Parity         = UART_Parity_No;
+    init_struct->Mode           = UART_GCR_RX | UART_GCR_TX;
+    init_struct->HWFlowControl  = UART_HWFlowControl_None;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified UART peripheral.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the uart peripheral.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Cmd(UART_TypeDef* uart, FunctionalState state)
+{
+    MODIFY_REG(uart->GCR, UART_GCR_UART, state << UART_GCR_UART_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified UART interrupts.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  it: specifies the UART interrupt sources to be
+///         enabled or disabled.
+///         This parameter can be one of the following values:
+/// @arg    UART_IT_ERR:  Error interrupt(Frame error,)
+/// @arg    UART_IT_PE:   Parity Error interrupt
+/// @arg    UART_OVER_ERR:  overrun Error interrupt
+/// @arg    UART_IT_RXIEN: Receive Data register interrupt
+/// @arg    UART_IT_TXIEN:  Tansmit Data Register empty interrupt
+///
+/// @param  state: new state of the specified uart interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_ITConfig(UART_TypeDef* uart, u16 it, FunctionalState state)
+{
+    (state) ? (uart->IER |= it) : (uart->IER &= ~it);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the UART DMA interface.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  dma_request: specifies the DMA request.
+///         This parameter can be any combination of the following values:
+/// @arg    UART_DMAReq_EN: UART DMA transmit request
+///
+/// @param  state: new state of the DMA Request sources.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_DMACmd(UART_TypeDef* uart, u16 dma_request, FunctionalState state)
+{
+    MODIFY_REG(uart->GCR, UART_GCR_DMA, state << UART_GCR_DMA_Pos);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Transmits single data through the uart peripheral.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  Data: the data to transmit.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SendData(UART_TypeDef* uart, u16 value)
+{
+    // Transmit Data
+    WRITE_REG(uart->TDR, (value & 0xFFU));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the most recent received data by the uart peripheral.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @retval  The received data.
+////////////////////////////////////////////////////////////////////////////////
+u16 UART_ReceiveData(UART_TypeDef* uart)
+{
+    // Receive Data
+    return (u16)(uart->RDR & 0xFFU);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified UART flag is set or not.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  flag: specifies the flag to check.
+///         This parameter can be one of the following values:
+/// @arg    UART_FLAG_TXEMPTY: Transmit data register empty flag
+/// @arg    UART_FLAG_TXFULL: Transmit data buffer full
+/// @arg    UART_FLAG_RXAVL: RX Buffer has a byte flag
+/// @arg    UART_FLAG_TXEPT: tx and shifter are emptys flag
+/// @retval  The new state of UART_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus UART_GetFlagStatus(UART_TypeDef* uart, u16 flag)
+{
+    return (uart->CSR & flag) ? SET : RESET;
+}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified UART interrupt has occurred or not.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  it: specifies the UART interrupt source to check.
+///         This parameter can be one of the following values:
+/// @arg    UART_IT_ERR:  Error interrupt(Frame error,)
+/// @arg    UART_IT_PE:   Parity Error interrupt
+/// @arg    UART_OVER_ERR:  overrun Error interrupt
+/// @arg    UART_IT_RXIEN: Receive Data register interrupt
+/// @arg    UART_IT_TXIEN:  Tansmit Data Register empty interrupt
+/// @retval  The new state of UART_IT (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus UART_GetITStatus(UART_TypeDef* uart, u16 it)
+{
+    return (uart->ISR & it) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the uart interrupt pending bits.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  it: specifies the interrupt pending bit to clear.
+///         This parameter can be one of the following values:
+/// @arg    UART_IT_ERR:  Error interrupt(Frame error,)
+/// @arg    UART_IT_PE:   Parity Error interrupt
+/// @arg    UART_OVER_ERR:  overrun Error interrupt
+/// @arg    UART_IT_RXIEN: Receive Data register interrupt
+/// @arg    UART_IT_TXIEN:  Tansmit Data Register empty interrupt
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_ClearITPendingBit(UART_TypeDef* uart, u16 it)
+{
+    //clear UART_IT pendings bit
+    uart->ICR = it;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Selects the UART WakeUp method.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  mode: specifies the UART wakeup method.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_WakeUpConfig(UART_TypeDef* uart, UART_WakeUp_TypeDef mode)
+{
+    MODIFY_REG(uart->CCR, UART_CCR_WAKE, mode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Determines if the UART is in mute mode or not.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the UART mute mode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_ReceiverWakeUpCmd(UART_TypeDef* uart, FunctionalState state)
+{
+    MODIFY_REG(uart->CCR, UART_CCR_RWU, state << UART_CCR_RWU_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the address of the UART Rx Address.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  address: Indicates the address of the UART Rx Address.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SetRXAddress(UART_TypeDef* uart, u8 address)
+{
+    MODIFY_REG(uart->RXAR, UART_RXAR_ADDR, address);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the address of the UART Rx MASK.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  address: Indicates the address of the UART Rx MASK.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SetRXMASK(UART_TypeDef* uart, u8 address)
+{
+    MODIFY_REG(uart->RXMR, UART_RXMR_MASK, address);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  ENBALE or DISABLE the UART's 9bit.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the UART 9 bit.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Enable9bit(UART_TypeDef* uart, FunctionalState state)
+{
+    MODIFY_REG(uart->CCR, UART_CCR_B8EN, state << UART_CCR_B8EN_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the UART's 9bit Level.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the UART 9 bit.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Set9bitLevel(UART_TypeDef* uart, FunctionalState state)
+{
+    MODIFY_REG(uart->CCR, UART_CCR_B8TXD, state << UART_CCR_B8TXD_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the UART's 9bit Polarity.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  polarity: new state of the UART 9 bit Polarity.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Set9bitPolarity(UART_TypeDef* uart, UART_9bit_Polarity_TypeDef polarity)
+{
+    MODIFY_REG(uart->CCR, UART_CCR_B8POL, polarity);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the UART's 9bit Automatic Toggle.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the UART 9 bit Automatic Toggle.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Set9bitAutomaticToggle(UART_TypeDef* uart, FunctionalState state)
+{
+    MODIFY_REG(uart->CCR, UART_CCR_B8TOG, state << UART_CCR_B8TOG_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the UART Half Duplex communication.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the UART Communication.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_HalfDuplexCmd(UART_TypeDef* uart, FunctionalState state)
+{
+    MODIFY_REG(uart->SCR, UART_SCR_HDSEL, state << UART_SCR_HDSEL_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the specified UART guard time.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  guard_time: specifies the guard time.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SetGuardTime(UART_TypeDef* uart, u8 guard_time)
+{
+    MODIFY_REG(uart->SCR, UART_SCR_SCFCNT, guard_time << UART_SCR_SCFCNT_Pos);
+    // Clear the UART Guard time
+    // uart->SCR &= SCR_SCFCNT_Mask;
+    // Set the UART guard time
+    // uart->SCR |= (u16)((u16)guard_time << 0x04);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the UART's Smart Card mode.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the Smart Card mode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SmartCardCmd(UART_TypeDef* uart, FunctionalState state)
+{
+    MODIFY_REG(uart->SCR, UART_SCR_SCEN, state << UART_SCR_SCEN_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables NACK transmission.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the NACK transmission.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SmartCardNACKCmd(UART_TypeDef* uart, FunctionalState state)
+{
+    MODIFY_REG(uart->SCR, UART_SCR_SCARB, state << UART_SCR_SCARB_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Transmits break characters.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SendBreak(UART_TypeDef* uart)
+{
+    SET_BIT(uart->CCR, UART_CCR_BRK);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable or Disable Auto Baud-Rate Detection
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the UART AutoBaudRate Detection.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_AutoBaudRateCmd(UART_TypeDef* uart, FunctionalState state)
+{
+    state ? SET_BIT(uart->ABRCR, UART_ABRCR_ABREN) : CLEAR_BIT(uart->ABRCR, UART_ABRCR_ABREN) ;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  AutoBaudRate.
+/// @param  uart: Select the UART or the UART peripheral.
+///         value: special character.
+///         state: ENABLE/DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_AutoBaudRateSet(UART_TypeDef* uart, UART_AutoBaud_TypeDef value, FunctionalState state)
+{
+    CLEAR_BIT(uart->ABRCR, UART_ABRCR_ABREN);
+    //This bit field can only be written when ABREN = 0 or the UART is disabled (UARTEN=0).
+
+    if ((value == ABRMODE_FALLING_TO_RISINGEDGE1BIT) || (value == ABRMODE_STARTBIT) || (value == ABRMODE_VALUE0XFF)) {
+        //UART measures the duration of the start bit (falling edge) to first rising edge
+        //FORMER edge = 0  LATTER edge= 1, from fist falling edge to rising edge = one bit
+        //___   _               _______
+        //   |_|1 x x x x x x x|        = Bxxxx xxx1  F to U = 1 start bit
+        //
+        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+                   UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE0 );
+    }
+    else if((value == ABRMODE_FALLING_TO_RISINGEDGE2BIT) || (value == Data_FE))  {
+        //UART measures the duration of the start bit (falling edge) to first rising edge
+        //FORMER edge = 0  LATTER edge= 1, from fist falling edge to rising edge = two bit
+        //___     _             _______
+        //   |_ _|1 x x x x x x|        = Bxxxx xx10  F to U = 2
+        //
+        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+                   UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE1);
+    }
+    else if((value == ABRMODE_FALLING_TO_RISINGEDGE4BIT) || (value == Data_F8)) {
+        //UART measures the duration of the start bit (falling edge) to first rising edge
+        //FORMER edge = 0  LATTER edge= 1, from fist falling edge to rising edge = four bit
+        //___         _         _______
+        //   |_ _ _ _|1 x x x x|        = Bxxxx 1000  F to U = 4
+        //
+        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+                   UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE2);
+    }
+    else if((value == ABRMODE_FALLING_TO_RISINGEDGE8BIT) || (value == ABRMODE_VALUE0X80))  {
+        //UART measures the duration of the start bit (falling edge) to first rising edge
+        //FORMER edge = 0  LATTER edge= 1, from fist falling edge to rising edge = eight bit
+        //___                 _ ______
+        //   |_ _ _ _ _ _ _ _|1         = B1000 0000  F to U = 8
+        //
+        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+                   UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE3);
+    }
+    else if((value == ABRMODE_FALLING_TO_FALLINGEDGE2BIT) || (value == ABRMODE_VALUE0X55)) {
+        //UART measures the duration of the start bit (falling edge) to next falling edge
+        //FORMER edge = 0  LATTER edge= 0, from fist falling edge to next falling edge = two bit
+        //___   _               ______
+        //   |_|1|_|x x x x x x|        = Bxxxx xx01  F to F = 2 0x55 and Falling to Falling
+        //
+        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+                   UART_ABRCR_BITCNT_MODE1);
+    }
+    else if((value == ABRMODE_FALLING_TO_FALLINGEDGE4BIT) || (value == ABRMODE_VALUE0XF7))  {
+        //UART measures the duration of the start bit (falling edge) to next falling edge
+        //FORMER edge = 0  LATTER edge= 0, from fist falling edge to next falling edge = four bit
+        //___   _ _ _           ______
+        //   |_|1 1 1|_|x x x x|        = Bxxxx 0111  F to F = 4
+        //
+        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+                   UART_ABRCR_BITCNT_MODE2);
+    }
+    else if((value == ABRMODE_FALLING_TO_FALLINGEDGE8BIT) || (value == ABRMODE_VALUE0x7F)) {
+        //UART measures the duration of the start bit (falling edge) to next falling edge
+        //FORMER edge = 0  LATTER edge= 0, from fist falling edge to next falling edge = eight bit
+        //___   _ _ _ _ _ _ _   ______
+        //   |_|1 1 1 1 1 1 1|_|        = B0111 1111  F to F = 8 0x7F
+        //
+        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+                   UART_ABRCR_BITCNT_MODE3);
+    }
+
+    else {
+        //UART measures the duration of the start bit (falling edge) to next falling edge
+        //FORMER edge = 0  LATTER edge= 0, from fist falling edge to next falling edge = eight bit
+        //___   _ _ _ _ _ _ _   ______
+        //   |_|1 1 1 1 1 1 1|_|        = B0111 1111  F to F = 8 0x7F
+        //
+        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+                   UART_ABRCR_BITCNT_MODE3);
+    }
+    if(state == ENABLE) {
+        SET_BIT(uart->ABRCR, UART_ABRCR_ABREN);
+    }
+}
+/// @}
+
+/// @}
+
+/// @}

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c

@@ -0,0 +1,55 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_uid.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE UID FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_UID_C_
+
+// Files includes
+#include "hal_uid.h"
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+///@addtogroup UID_HAL
+///@{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup UID_Exported_Functions
+/// @{
+
+u8 device_id_data[12] = {0};
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Get device ID.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GetChipUID(void)
+{
+    u8 i;
+
+    for (i = 0; i < 12; i++) {
+        device_id_data[i] = *((vu8*)(UID_BASE + i));
+    }
+}
+
+/// @}
+
+/// @}
+
+/// @}

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c

@@ -0,0 +1,131 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_ver.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE LIB AND THE CHIPSET INFORMATION.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_VER_C_
+
+// Files includes
+#include "hal_ver.h"
+
+
+// MM32 Library version is 0.90
+
+#define __MM32_LIB_VERSION_MAIN         (0x0U)                                  //!< [31:24] main version 
+#define __MM32_LIB_VERSION_SUB1         (0x9U)                                  //!< [23:16] sub1 version
+#define __MM32_LIB_VERSION_SUB2         (0x0U)                                  //!< [15:8]  sub2 version
+#define __MM32_LIB_VERSION_RC           (0x00U)                                 //!< [7:0]  release candidate
+#define __MM32_LIB_VERSION              ((__MM32_LIB_VERSION_MAIN << 24U)\
+                                         |(__MM32_LIB_VERSION_SUB1 << 16U)\
+                                         |(__MM32_LIB_VERSION_SUB2 << 8U )\
+                                         |(__MM32_LIB_VERSION_RC))
+
+// MM32 Library release date is 2021-05-10 (YYYY-MM-DD)
+#define __MM32_LIB_RELESE_YEARH         (0x20U)                                  //!< [31:24] release year high 
+#define __MM32_LIB_RELESE_YEARL         (0x21U)                                  //!< [23:16] release year low
+#define __MM32_LIB_RELESE_MONTH         (0x05U)                                  //!< [15:8]  release month
+#define __MM32_LIB_RELESE_DAY           (0x10U)                                //!< [7:0]   release day
+#define __MM32_LIB_RELESE_DATE          ((__MM32_LIB_RELESE_YEARH << 24U)\
+                                         |(__MM32_LIB_RELESE_YEARL << 16U)\
+                                         |(__MM32_LIB_RELESE_MONTH << 8U )\
+                                         |(__MM32_LIB_RELESE_DAY))
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+///@addtogroup VER_HAL
+///@{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup Lib and chipset_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  This method returns the Lib revision.
+/// @param  None.
+/// @retval return the Lib version.
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_MM32LibVersion(void)
+{
+    return __MM32_LIB_VERSION;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  This method returns the Lib release date.
+/// @param  None.
+/// @retval return the Lib release date.
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_MM32LibReleaseDate(void)
+{
+    return __MM32_LIB_RELESE_DATE;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the device revision identifier.
+/// @param  None.
+/// @retval return the device revision identifier.
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_ChipsetREVID(void)
+{
+    return((DBGMCU->IDCODE) & 0xF );
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the device identifier..
+/// @param  None.
+/// @retval return the device Device identifier.
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_ChipsetDEVID(void)
+{
+    return((DBGMCU->IDCODE) );
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns first word of the unique device identifier (UID based on 96 bits)
+/// @param  None.
+/// @retval Device identifier
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_ChipsetUIDw0(void)
+{
+    return(READ_REG(*((vu32*)UID_BASE)));
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns second word of the unique device identifier (UID based on 96 bits)
+/// @param  None.
+/// @retval Device identifier
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_ChipsetUIDw1(void)
+{
+    return(READ_REG(*((vu32*)(UID_BASE + 4U))));
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns third word of the unique device identifier (UID based on 96 bits)
+/// @param  None.
+/// @retval Device identifier
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_ChipsetUIDw2(void)
+{
+    return(READ_REG(*((vu32*)(UID_BASE + 8U))));
+}
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}

hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c

@@ -0,0 +1,147 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_wwdg.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE WWDG FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_WWDG_C_
+
+// Files includes
+#include "hal_wwdg.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup WWDG_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup WWDG_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the WWDG peripheral registers to their default reset
+/// values.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_DeInit()
+{
+    exRCC_APB1PeriphReset(RCC_APB1RSTR_WWDG);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the WWDG Prescaler.
+/// @param  WWDG_Prescaler: specifies the WWDG Prescaler.
+///         This parameter can be one of the following values:
+///             @arg WWDG_Prescaler_1: WWDG counter clock = APB1CLK / 4096 / 1
+///             @arg WWDG_Prescaler_2: WWDG counter clock = APB1CLK / 4096 / 2
+///             @arg WWDG_Prescaler_4: WWDG counter clock = APB1CLK / 4096 / 4
+///             @arg WWDG_Prescaler_8: WWDG counter clock = APB1CLK / 4096 / 8
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_SetPrescaler(u32 prescaler)
+{
+    WWDG->CFGR = (WWDG->CFGR & ~WWDG_CFGR_WDGTB) | prescaler;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the WWDG window value.
+/// @param  WindowValue: specifies the window value to be compared to the
+/// downcounter.
+///          This parameter value must be lower than 0x80.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_SetWindowValue(u8 window_value)
+{
+    WWDG->CFGR = (WWDG->CFGR & ~WWDG_CFGR_WINDOW) | (window_value & WWDG_CFGR_WINDOW);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables the WWDG Early Wakeup interrupt(EWI).
+/// @note   Once enabled this interrupt cannot be disabled except by a system
+/// reset.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_EnableIT()
+{
+    WWDG->CFGR |= WWDG_CFGR_EWI;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the WWDG counter value.
+/// @param  Counter: specifies the watchdog counter value.
+///         This parameter must be a number between 0x40 and 0x7F (to prevent
+///         generating an immediate reset).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_SetCounter(u8 count)
+{
+    WWDG->CR = count & WWDG_CFGR_WINDOW;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables WWDG and load the counter value.
+/// @param  Counter: specifies the watchdog counter value.
+///         This parameter must be a number between 0x40 and 0x7F (to prevent
+///         generating an immediate reset).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+u32 WWDG_GetCounter()
+{
+    return WWDG->CR & WWDG_CR_CNT;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables WWDG and load the counter value.
+/// @param  Counter: specifies the watchdog counter value.
+///         This parameter must be a number between 0x40 and 0x7F (to prevent
+///         generating an immediate reset).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_Enable(u8 count)
+{
+    WWDG->CR = WWDG_CR_WDGA | count;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the Early Wakeup interrupt flag is set or not.
+/// @param  None.
+/// @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus WWDG_GetFlagStatus()
+{
+    return WWDG->SR ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears Early Wakeup interrupt flag.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_ClearFlag()
+{
+    WWDG->SR &= ~WWDG_SR_EWIF;
+}
+
+/// @}
+
+/// @}
+
+/// @}