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Add MM32 SDK and USB driver

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Signed-off-by: zhangslice <1304224508@qq.com>
This commit is contained in:
zhangslice
2021-06-02 09:46:48 +08:00
committed by hathach
parent 2b5bad7362
commit 3ba72b53d8
133 changed files with 96566 additions and 0 deletions
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hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h
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///-----------------------------------------------------------------------------
/// @file mm32_device.h
/// @brief CMSIS Cortex-M Peripheral Access Layer for MindMotion
/// microcontroller devices
///
/// This is a convenience header file for defining the part number on the
/// build command line, instead of specifying the part specific header file.
///
/// Example: Add MM32 series to your build options, to define part
/// Add "#include "mm32_device.h" to your source files
///
///
///
///
///-----------------------------------------------------------------------------
#ifndef __MM32_DEVICE_H
#define __MM32_DEVICE_H
#include "mm32_reg.h"
#endif // __MM32_DEVICE_H
hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h
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////////////////////////////////////////////////////////////////////////////////
/// @file mm32_reg.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
////////////////////////////////////////////////////////////////////////////////
#ifndef __MM32_REG_H
#define __MM32_REG_H
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#include "reg_common.h"
#include "reg_adc.h"
#include "reg_bkp.h"
#include "reg_can.h"
#include "reg_comp.h"
#include "reg_crc.h"
#include "reg_crs.h"
#include "reg_dac.h"
#include "reg_dbg.h"
#include "reg_dma.h"
#include "reg_exti.h"
#include "reg_eth.h"
#include "reg_flash.h"
#include "reg_gpio.h"
#include "reg_i2c.h"
#include "reg_iwdg.h"
#include "reg_pwm.h"
#include "reg_pwr.h"
#include "reg_rcc.h"
#include "reg_rtc.h"
#include "reg_sdio.h"
#include "reg_spi.h"
#include "reg_syscfg.h"
#include "reg_tim.h"
#include "reg_uart.h"
#include "reg_usb_otg_fs.h"
#include "reg_wwdg.h"
////////////////////////////////////////////////////////////////////////////////
#include "mm32_reg_redefine_v1.h"
////////////////////////////////////////////////////////////////////////////////
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif // __MM32_REG_H
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h
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hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_adc.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_ADC_H
#define __REG_ADC_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) ///< Base Address: 0x40012400
#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) ///< Base Address: 0x40012800
#define ADC3_BASE (APB2PERIPH_BASE + 0x4C00) ///< Base Address: 0x40014C00
////////////////////////////////////////////////////////////////////////////////
/// @brief Analog-to-Digital Converter register
////////////////////////////////////////////////////////////////////////////////
#define USENCOMBINEREGISTER
#ifdef USENCOMBINEREGISTER
typedef struct {
union {
__IO u32 DR; ///< ADC data register, offset: 0x00
__IO u32 ADDATA;
};
union {
__IO u32 CFGR; ///< ADC configuration register, offset: 0x04
__IO u32 ADCFG;
};
union {
__IO u32 CR; ///< ADC control register, offset: 0x08
__IO u32 ADCR;
};
union {
__IO u32 CHSR; ///< ADC channel selection register, offset: 0x0C
__IO u32 ADCHS;
};
union {
__IO u32 CMPR; ///< ADC window compare register, offset: 0x10
__IO u32 ADCMPR;
};
union {
__IO u32 SR; ///< ADC status register, offset: 0x14
__IO u32 ADSTA;
};
union {
__IO u32 CH0DR; ///< ADC channel0 data register, offset: 0x18
__IO u32 ADDR0;
};
union {
__IO u32 CH1DR; ///< ADC channel1 data register, offset: 0x1C
__IO u32 ADDR1;
};
union {
__IO u32 CH2DR; ///< ADC channel2 data register, offset: 0x20
__IO u32 ADDR2;
};
union {
__IO u32 CH3DR; ///< ADC channel3 data register, offset: 0x24
__IO u32 ADDR3;
};
union {
__IO u32 CH4DR; ///< ADC channel4 data register, offset: 0x28
__IO u32 ADDR4;
};
union {
__IO u32 CH5DR; ///< ADC channel5 data register, offset: 0x2C
__IO u32 ADDR5;
};
union {
__IO u32 CH6DR; ///< ADC channel6 data register, offset: 0x30
__IO u32 ADDR6;
};
union {
__IO u32 CH7DR; ///< ADC channel7 data register, offset: 0x34
__IO u32 ADDR7;
};
union {
__IO u32 CH8DR; ///< ADC channel8 data register, offset: 0x38
__IO u32 ADDR8;
};
union {
__IO u32 CH9DR; ///< ADC channel9 data register, offset: 0x3C
__IO u32 ADDR9;
};
__IO u32 ADDR10; ///< offset: 0x40
__IO u32 ADDR11; ///< offset: 0x44
__IO u32 ADDR12; ///< offset: 0x48
__IO u32 ADDR13; ///< offset: 0x4C
union {
__IO u32 CH14DR; ///< ADC channel14 data register, offset: 0x50
__IO u32 ADDR14;
};
union {
__IO u32 CH15DR; ///< ADC channel15 data register, offset: 0x54
__IO u32 ADDR15;
};
__IO u32 SREXT; ///< ADC Extended Status Register, offset: 0x58
__IO u32 CHANY0; ///< ADC any Chan Select Register 0, offset: 0x5C
__IO u32 CHANY1; ///< ADC any Chan Select Register 1, offset: 0x60
__IO u32 ANYCFG; ///< ADC any Chan config Register, offset: 0x64
__IO u32 ANYCR; ///< ADC any Chan control Register, offset: 0x68
__IO u32 RESERVED0; ///< offset 0x6C
__IO u32 SMPR1; ///< Sampling configuration register 1 offset 0x70
__IO u32 SMPR2; ///< Sampling configuration register 2 offset 0x74
__IO u32 RESERVED1; ///< offset 0x78
__IO u32 JOFR0; ///< Injection channel data compensation register 0 offset 0x7C
__IO u32 JOFR1; ///< Injection channel data compensation register 1 offset 0x80
__IO u32 JOFR2; ///< Injection channel data compensation register 2 offset 0x84
__IO u32 JOFR3; ///< Injection channel data compensation register 3 offset 0x88
__IO u32 JSQR; ///< Injection sequence register offset 0x8C
__IO u32 JDATA; ///< Inject data register offset 0x90
__IO u32 RESERVED2; ///< offset 0x94
__IO u32 RESERVED3; ///< offset 0x98
__IO u32 RESERVED4; ///< offset 0x9C
__IO u32 RESERVED5; ///< offset 0xA0
__IO u32 RESERVED6; ///< offset 0xA4
__IO u32 RESERVED7; ///< offset 0xA8
__IO u32 RESERVED8; ///< offset 0xAC
__IO u32 JDR0; ///< Injection channel data register 0 offset 0xB0
__IO u32 JDR1; ///< Injection channel data register 1 offset 0xB4
__IO u32 JDR2; ///< Injection channel data register 2 offset 0xB8
__IO u32 JDR3; ///< Injection channel data register 3 offset 0xBC
} ADC_TypeDef;
#endif
#ifdef USENNEWREGISTER
////////////////////////////////////////////////////////////////////////////////
/// @brief Analog-to-Digital Converter register
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 DR; ///< ADC data register, offset: 0x00
__IO u32 CFGR; ///< ADC configuration register, offset: 0x04
__IO u32 CR; ///< ADC control register, offset: 0x08
__IO u32 CHSR; ///< ADC channel selection register, offset: 0x0C
__IO u32 CMPR; ///< ADC window compare register, offset: 0x10
__IO u32 SR; ///< ADC status register, offset: 0x14
__IO u32 CH0DR; ///< ADC channel0 data register, offset: 0x18
__IO u32 CH1DR; ///< ADC channel1 data register, offset: 0x1C
__IO u32 CH2DR; ///< ADC channel2 data register, offset: 0x20
__IO u32 CH3DR; ///< ADC channel3 data register, offset: 0x24
__IO u32 CH4DR; ///< ADC channel4 data register, offset: 0x28
__IO u32 CH5DR; ///< ADC channel5 data register, offset: 0x2C
__IO u32 CH6DR; ///< ADC channel6 data register, offset: 0x30
__IO u32 CH7DR; ///< ADC channel7 data register, offset: 0x34
__IO u32 CH8DR; ///< ADC channel8 data register, offset: 0x38
} ADC_TypeDef;
#endif
#ifdef USENOLDREGISTER
typedef struct {
__IO u32 ADDATA; ///< ADC data register, offset: 0x00
__IO u32 ADCFG; ///< ADC configuration register, offset: 0x04
__IO u32 ADCR; ///< ADC control register, offset: 0x08
__IO u32 ADCHS; ///< ADC channel selection register, offset: 0x0C
__IO u32 ADCMPR; ///< ADC window compare register, offset: 0x10
__IO u32 ADSTA; ///< ADC status register, offset: 0x14
__IO u32 ADDR0; ///< ADC channel0 data register, offset: 0x18
__IO u32 ADDR1; ///< ADC channel1 data register, offset: 0x1C
__IO u32 ADDR2; ///< ADC channel2 data register, offset: 0x20
__IO u32 ADDR3; ///< ADC channel3 data register, offset: 0x24
__IO u32 ADDR4; ///< ADC channel4 data register, offset: 0x28
__IO u32 ADDR5; ///< ADC channel5 data register, offset: 0x2C
__IO u32 ADDR6; ///< ADC channel6 data register, offset: 0x30
__IO u32 ADDR7; ///< ADC channel7 data register, offset: 0x34
__IO u32 ADDR8; ///< ADC channel8 data register, offset: 0x38
} ADC_TypeDef;
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC1 ((ADC_TypeDef*) ADC1_BASE)
#define ADC2 ((ADC_TypeDef*) ADC2_BASE)
#define ADC3 ((ADC_TypeDef*) ADC3_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_DR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_DR_DATA_Pos (0)
#define ADC_DR_DATA (0xFFFFU << ADC_DR_DATA_Pos) ///< ADC 12bit convert data
#define ADC_DR_CH_Pos (16)
#define ADC_DR_CH (0x0FU << ADC_DR_CH_Pos) ///< CHANNELSEL[19:16] (ADC current channel convert data)
#define ADC_DR_CH0 (0x00U << ADC_DR_CH_Pos) ///< ADC Channel select 0
#define ADC_DR_CH1 (0x01U << ADC_DR_CH_Pos) ///< ADC Channel select 1
#define ADC_DR_CH2 (0x02U << ADC_DR_CH_Pos) ///< ADC Channel select 2
#define ADC_DR_CH3 (0x03U << ADC_DR_CH_Pos) ///< ADC Channel select 3
#define ADC_DR_CH4 (0x04U << ADC_DR_CH_Pos) ///< ADC Channel select 4
#define ADC_DR_CH5 (0x05U << ADC_DR_CH_Pos) ///< ADC Channel select 5
#define ADC_DR_CH6 (0x06U << ADC_DR_CH_Pos) ///< ADC Channel select 6
#define ADC_DR_CH7 (0x07U << ADC_DR_CH_Pos) ///< ADC Channel select 7
#define ADC_DR_CH8 (0x08U << ADC_DR_CH_Pos) ///< ADC Channel select 8
#define ADC_DR_CH10 (0x0AU << ADC_DR_CH_Pos) ///< ADC Channel select 10
#define ADC_DR_CH11 (0x0BU << ADC_DR_CH_Pos) ///< ADC Channel select 11
#define ADC_DR_CH13 (0x0CU << ADC_DR_CH_Pos) ///< ADC Channel select 13
#define ADC_DR_CH9 (0x09U << ADC_DR_CH_Pos) ///< ADC Channel select 9
#define ADC_DR_CH14 (0x0EU << ADC_DR_CH_Pos) ///< ADC Channel select 14
#define ADC_DR_CH15 (0x0FU << ADC_DR_CH_Pos) ///< ADC Channel select 15
#define ADC_DR_OVERRUN_Pos (20)
#define ADC_DR_OVERRUN (0x01U << ADC_DR_OVERRUN_Pos) ///< ADC data will be cover
#define ADC_DR_VALID_Pos (21)
#define ADC_DR_VALID (0x01U << ADC_DR_VALID_Pos) ///< ADC data[11:0] is valid
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_CFGR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_CFGR_ADEN_Pos (0)
#define ADC_CFGR_ADEN (0x01U << ADC_CFGR_ADEN_Pos) ///< Enable ADC convert
#define ADC_CFGR_ADWEN_Pos (1)
#define ADC_CFGR_ADWEN (0x01U << ADC_CFGR_ADWEN_Pos) ///< Enable ADC window compare
#define ADC_CFGR_RSLTCTL_Pos (7)
#define ADC_CFGR_RSLTCTL (0x07U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select
#define ADC_CFGR_RSLTCTL_12 (0x00U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 12bit
#define ADC_CFGR_RSLTCTL_11 (0x01U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 11bit
#define ADC_CFGR_RSLTCTL_10 (0x02U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 10bit
#define ADC_CFGR_RSLTCTL_9 (0x03U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 9bit
#define ADC_CFGR_RSLTCTL_8 (0x04U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 8bit
#define ADC_CFGR_TEN_Pos (2)
#define ADC_CFGR_TEN (0x01U << ADC_CFGR_TEN_Pos) ///< Enable ADC temperature sensor
#define ADC_CFGR_VEN_Pos (3)
#define ADC_CFGR_VEN (0x01U << ADC_CFGR_VEN_Pos) ///< Enable ADC voltage reference
#define ADC_CFGR_PRE_Pos (4)
#define ADC_CFGR_PREL_Pos (14)
#define ADC_CFGR_PRE ((0x07U << ADC_CFGR_PRE_Pos) + (0x01U << ADC_CFGR_PREL_Pos))
#define ADC_CFGR_PRE_2 (0x00U << ADC_CFGR_PRE_Pos) ///< ADC preclk 2
#define ADC_CFGR_PRE_4 (0x01U << ADC_CFGR_PRE_Pos) ///< ADC preclk 4
#define ADC_CFGR_PRE_6 (0x02U << ADC_CFGR_PRE_Pos) ///< ADC preclk 6
#define ADC_CFGR_PRE_8 (0x03U << ADC_CFGR_PRE_Pos) ///< ADC preclk 8
#define ADC_CFGR_PRE_10 (0x04U << ADC_CFGR_PRE_Pos) ///< ADC preclk 10
#define ADC_CFGR_PRE_12 (0x05U << ADC_CFGR_PRE_Pos) ///< ADC preclk 12
#define ADC_CFGR_PRE_14 (0x06U << ADC_CFGR_PRE_Pos) ///< ADC preclk 14
#define ADC_CFGR_PRE_16 (0x07U << ADC_CFGR_PRE_Pos) ///< ADC preclk 16
#define ADC_CFGR_PRE_3 ((0x01U << ADC_CFGR_PREL_Pos) + (0x00U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 3
#define ADC_CFGR_PRE_5 ((0x01U << ADC_CFGR_PREL_Pos) + (0x01U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 5
#define ADC_CFGR_PRE_7 ((0x01U << ADC_CFGR_PREL_Pos) + (0x02U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 7
#define ADC_CFGR_PRE_9 ((0x01U << ADC_CFGR_PREL_Pos) + (0x03U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 9
#define ADC_CFGR_PRE_11 ((0x01U << ADC_CFGR_PREL_Pos) + (0x04U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 11
#define ADC_CFGR_PRE_13 ((0x01U << ADC_CFGR_PREL_Pos) + (0x05U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 13
#define ADC_CFGR_PRE_15 ((0x01U << ADC_CFGR_PREL_Pos) + (0x06U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 15
#define ADC_CFGR_PRE_17 ((0x01U << ADC_CFGR_PREL_Pos) + (0x07U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 17
#define ADC_CFGR_JADWEN_Pos (16)
#define ADC_CFGR_JADWEN (0x01U << ADC_CFGR_JADWEN_Pos) ///< Inject ADC conversion window comparison enable
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_CR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_CR_ADIE_Pos (0)
#define ADC_CR_ADIE (0x01U << ADC_CR_ADIE_Pos) ///< ADC interrupt enable
#define ADC_CR_ADWIE_Pos (1)
#define ADC_CR_ADWIE (0x01U << ADC_CR_ADWIE_Pos) ///< ADC window compare interrupt enable
#define ADC_CR_TRGEN_Pos (2)
#define ADC_CR_TRGEN (0x01U << ADC_CR_TRGEN_Pos) ///< extranal trigger single start AD convert
#define ADC_CR_DMAEN_Pos (3)
#define ADC_CR_DMAEN (0x01U << ADC_CR_DMAEN_Pos) ///< ADC DMA enable
#define ADC_CR_ADST_Pos (8)
#define ADC_CR_ADST (0x01U << ADC_CR_ADST_Pos) ///< ADC start convert data
#define ADC_CR_MODE_Pos (9)
#define ADC_CR_MODE (0x03U << ADC_CR_MODE_Pos) ///< ADC convert mode
#define ADC_CR_IMM (0x00U << ADC_CR_MODE_Pos) ///< ADC imm convert mode
#define ADC_CR_SCAN (0x01U << ADC_CR_MODE_Pos) ///< ADC scan convert mode
#define ADC_CR_CONTINUE (0x02U << ADC_CR_MODE_Pos) ///< ADC continue scan convert mode
#define ADC_CR_ALIGN_Pos (11)
#define ADC_CR_ALIGN (0x01U << ADC_CR_ALIGN_Pos) ///< ADC data align
#define ADC_CR_LEFT (0x01U << ADC_CR_ALIGN_Pos) ///< ADC data left align
#define ADC_CR_RIGHT (0x00U << ADC_CR_ALIGN_Pos) ///< ADC data right align
#define ADC_CR_CMPCH_Pos (12)
#define ADC_CR_CMPCH (0x0FU << ADC_CR_CMPCH_Pos) ///< CMPCH[15:12] ADC window compare channel0 convert data
#define ADC_CR_CMPCH_0 (0x00U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 0 Conversion Results
#define ADC_CR_CMPCH_1 (0x01U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 1 Conversion Results
#define ADC_CR_CMPCH_2 (0x02U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 2 Conversion Results
#define ADC_CR_CMPCH_4 (0x04U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 4 Conversion Results
#define ADC_CR_CMPCH_5 (0x05U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 5 Conversion Results
#define ADC_CR_CMPCH_6 (0x06U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 6 Conversion Results
#define ADC_CR_CMPCH_7 (0x07U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 7 Conversion Results
#define ADC_CR_CMPCH_8 (0x08U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 8 Conversion Results
#define ADC_CR_CMPCH_9 (0x09U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 9 Conversion Results
#define ADC_CR_CMPCH_10 (0x0AU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 10 Conversion Results
#define ADC_CR_CMPCH_11 (0x0BU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 11 Conversion Results
#define ADC_CR_CMPCH_13 (0x0DU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 13 Conversion Results
#define ADC_CR_CMPCH_14 (0x0EU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 14 Conversion Results
#define ADC_CR_CMPCH_ALL (0x0FU << ADC_CR_CMPCH_Pos) ///< Select Compare ALL Channel Conversion Results
#define ADC_CR_SCANDIR_Pos (16)
#define ADC_CR_SCANDIR (0x01U << ADC_CR_SCANDIR_Pos) ///< ADC scan direction
#define ADC_CR_TRGSEL_H_Pos (17)
#define ADC_CR_TRGSEL_L_Pos (4)
#define ADC_CR_TRGSEL ((0x03U << ADC_CR_TRGSEL_H_Pos) + (0x07U << ADC_CR_TRGSEL_L_Pos)) ///< TRGSEL[6:4][18:17] ADC external trigger source select
#define ADC_CR_T1_CC1 (0x00U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC1
#define ADC_CR_T1_CC2 (0x01U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC2
#define ADC_CR_T1_CC3 (0x02U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC3
#define ADC_CR_T2_CC2 (0x03U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T2_CC2
#define ADC_CR_T3_TRIG (0x04U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T3_TRIG
#define ADC_CR_T1_CC4_CC5 (0x05U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC4_CC5
#define ADC_CR_T3_CC1 (0x06U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T3_CC1
#define ADC_CR_EXTI_11 (0x07U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is EXTI_11
#define ADC_CR_T1_TRIG ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x00U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T1_TRIG
#define ADC_CR_T8_CC4 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x01U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T8_CC4
#define ADC_CR_T8_CC4_CC5 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x02U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T8_CC4_CC5
#define ADC_CR_T2_CC1 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x03U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T2_CC1
#define ADC_CR_T3_CC4 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x04U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T3_CC4
#define ADC_CR_T2_TRIG ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x05U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T2_TRIG
#define ADC_CR_T8_CC5 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x06U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T8_CC5
#define ADC_CR_EXTI_15 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x07U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is EXTI_15
#define ADC_CR_TIM1_CC4 ((0x02U << ADC_CR_TRGSEL_H_Pos) + (0x00U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is TIM1_CC4
#define ADC_CR_TIM1_CC5 ((0x02U << ADC_CR_TRGSEL_H_Pos) + (0x01U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is TIM1_CC5
#define ADC_CR_TRGSHIFT_Pos (19)
#define ADC_CR_TRGSHIFT (0x07U << ADC_CR_TRGSHIFT_Pos) ///< External trigger shift sample
#define ADC_CR_TRGSHIFT_0 (0x00U << ADC_CR_TRGSHIFT_Pos) ///< No shift
#define ADC_CR_TRGSHIFT_4 (0x01U << ADC_CR_TRGSHIFT_Pos) ///< Shift 4 period
#define ADC_CR_TRGSHIFT_16 (0x02U << ADC_CR_TRGSHIFT_Pos) ///< Shift 16 period
#define ADC_CR_TRGSHIFT_32 (0x03U << ADC_CR_TRGSHIFT_Pos) ///< Shift 32 period
#define ADC_CR_TRGSHIFT_64 (0x04U << ADC_CR_TRGSHIFT_Pos) ///< Shift 64 period
#define ADC_CR_TRGSHIFT_128 (0x05U << ADC_CR_TRGSHIFT_Pos) ///< Shift 128 period
#define ADC_CR_TRGSHIFT_256 (0x06U << ADC_CR_TRGSHIFT_Pos) ///< Shift 256 period
#define ADC_CR_TRGSHIFT_512 (0x07U << ADC_CR_TRGSHIFT_Pos) ///< Shift 512 period
#define ADC_CR_CALIBEN_Pos (22)
#define ADC_CR_CALIBEN (0x01U << ADC_CR_CALIBEN_Pos) ///< Self-calibration enable
#define ADC_CR_CALIBSEL_Pos (23)
#define ADC_CR_CALIBSEL (0x01U << ADC_CR_CALIBSEL_Pos) ///< Self-calibration voltage selection
#define ADC_CR_TRG_EDGE_Pos (24)
#define ADC_CR_TRG_EDGE (0x03U << ADC_CR_TRG_EDGE_Pos) ///< ADC trig edge config
#define ADC_CR_TRG_EDGE_DUAL (0x00U << ADC_CR_TRG_EDGE_Pos) ///< ADC dual edge trig mode
#define ADC_CR_TRG_EDGE_DOWN (0x01U << ADC_CR_TRG_EDGE_Pos) ///< ADC down edge trig mode
#define ADC_CR_TRG_EDGE_UP (0x02U << ADC_CR_TRG_EDGE_Pos) ///< ADC up edge trig mode
#define ADC_CR_TRG_EDGE_MASK (0x03U << ADC_CR_TRG_EDGE_Pos) ///< ADC mask edge trig mode
#define ADC_CR_EOSMPIE_Pos (26)
#define ADC_CR_EOSMPIE (0X01U << ADC_CR_EOSMPIE_Pos) ///< ADC end sampling flag interrupt enable
#define ADC_CR_EOCIE_Pos (27)
#define ADC_CR_EOCIE (0X01U << ADC_CR_EOCIE_Pos) ///< ADC end of conversion interrupt enable
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_CHSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_CHSR_CH0_Pos (0)
#define ADC_CHSR_CH0 (0x01U << ADC_CHSR_CH0_Pos) ///< Enable ADC channel 0
#define ADC_CHSR_CH1_Pos (1)
#define ADC_CHSR_CH1 (0x01U << ADC_CHSR_CH1_Pos) ///< Enable ADC channel 1
#define ADC_CHSR_CH2_Pos (2)
#define ADC_CHSR_CH2 (0x01U << ADC_CHSR_CH2_Pos) ///< Enable ADC channel 2
#define ADC_CHSR_CH3_Pos (3)
#define ADC_CHSR_CH3 (0x01U << ADC_CHSR_CH3_Pos) ///< Enable ADC channel 3
#define ADC_CHSR_CH4_Pos (4)
#define ADC_CHSR_CH4 (0x01U << ADC_CHSR_CH4_Pos) ///< Enable ADC channel 4
#define ADC_CHSR_CH5_Pos (5)
#define ADC_CHSR_CH5 (0x01U << ADC_CHSR_CH5_Pos) ///< Enable ADC channel 5
#define ADC_CHSR_CH6_Pos (6)
#define ADC_CHSR_CH6 (0x01U << ADC_CHSR_CH6_Pos) ///< Enable ADC channel 6
#define ADC_CHSR_CH7_Pos (7)
#define ADC_CHSR_CH7 (0x01U << ADC_CHSR_CH7_Pos) ///< Enable ADC channel 7
#define ADC_CHSR_CH8_Pos (8)
#define ADC_CHSR_CH8 (0x01U << ADC_CHSR_CH8_Pos) ///< Enable ADC channel 8
#define ADC_CHSR_CH9_Pos (9)
#define ADC_CHSR_CH9 (0x01U << ADC_CHSR_CH9_Pos) ///< Enable ADC channel 9
#define ADC_CHSR_CHT_Pos (14)
#define ADC_CHSR_CHT (0x01U << ADC_CHSR_CHT_Pos) ///< Enable Temperature Sensor
#define ADC_CHSR_CHV_Pos (15)
#define ADC_CHSR_CHV (0x01U << ADC_CHSR_CHV_Pos) ///< Enable Voltage Sensor
#define ADC_CHSR_CH10_Pos (10)
#define ADC_CHSR_CH10 (0x01U << ADC_CHSR_CH10_Pos) ///< Enable ADC channel 10
#define ADC_CHSR_CH11_Pos (11)
#define ADC_CHSR_CH11 (0x01U << ADC_CHSR_CH11_Pos) ///< Enable ADC channel 11
#define ADC_CHSR_CH12_Pos (12)
#define ADC_CHSR_CH12 (0x01U << ADC_CHSR_CH12_Pos) ///< Enable ADC channel 12
#define ADC_CHSR_CH13_Pos (13)
#define ADC_CHSR_CH13 (0x01U << ADC_CHSR_CH13_Pos) ///< Enable ADC channel 13
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_CMPR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_CMPR_CMPLDATA_Pos (0)
#define ADC_CMPR_CMPLDATA (0x0FFFU << ADC_CMPR_CMPLDATA_Pos) ///< ADC 12bit window compare DOWN LEVEL DATA
#define ADC_CMPR_CMPHDATA_Pos (16)
#define ADC_CMPR_CMPHDATA (0x0FFFU << ADC_CMPR_CMPHDATA_Pos) ///< ADC 12bit window compare UP LEVEL DATA
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_SR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_SR_ADIF_Pos (0)
#define ADC_SR_ADIF (0x01U << ADC_SR_ADIF_Pos) ///< ADC convert complete flag
#define ADC_SR_ADWIF_Pos (1)
#define ADC_SR_ADWIF (0x01U << ADC_SR_ADWIF_Pos) ///< ADC compare flag
#define ADC_SR_BUSY_Pos (2)
#define ADC_SR_BUSY (0x01U << ADC_SR_BUSY_Pos) ///< ADC busy flag
#define ADC_SR_CH_Pos (4)
#define ADC_SR_CH (0x0FU << ADC_SR_CH_Pos) ///< CHANNEL[7:4] ADC current channel
#define ADC_SR_CH0 (0x00U << ADC_SR_CH_Pos) ///< Channel 0 is the current conversion channel
#define ADC_SR_CH1 (0x01U << ADC_SR_CH_Pos) ///< Channel 1 is the current conversion channel
#define ADC_SR_CH2 (0x02U << ADC_SR_CH_Pos) ///< Channel 2 is the current conversion channel
#define ADC_SR_CH3 (0x03U << ADC_SR_CH_Pos) ///< Channel 3 is the current conversion channel
#define ADC_SR_CH4 (0x04U << ADC_SR_CH_Pos) ///< Channel 4 is the current conversion channel
#define ADC_SR_CH5 (0x05U << ADC_SR_CH_Pos) ///< Channel 5 is the current conversion channel
#define ADC_SR_CH6 (0x06U << ADC_SR_CH_Pos) ///< Channel 6 is the current conversion channel
#define ADC_SR_CH7 (0x07U << ADC_SR_CH_Pos) ///< Channel 7 is the current conversion channel
#define ADC_SR_CH8 (0x08U << ADC_SR_CH_Pos) ///< Channel 8 is the current conversion channel
#define ADC_SR_CH9 (0x09U << ADC_SR_CH_Pos) ///< Channel 9 is the current conversion channel
#define ADC_SR_CH10 (0x0AU << ADC_SR_CH_Pos) ///< Channel 10 is the current conversion channel
#define ADC_SR_CH11 (0x0BU << ADC_SR_CH_Pos) ///< Channel 11 is the current conversion channel
#define ADC_SR_CH13 (0x0DU << ADC_SR_CH_Pos) ///< Channel 13 is the current conversion channel
#define ADC_SR_CH14 (0x0EU << ADC_SR_CH_Pos) ///< Channel 14 is the current conversion channel
#define ADC_SR_CH15 (0x0FU << ADC_SR_CH_Pos) ///< Channel 15 is the current conversion channel
#define ADC_SR_VALID_Pos (8)
#define ADC_SR_VALID (0x0FFFU << ADC_SR_VALID_Pos) ///< VALID[19:8] ADC channel 0..11 valid flag
#define ADC_SR_OVERRUN_Pos (20)
#define ADC_SR_OVERRUN (0x0FFFU << ADC_SR_OVERRUN_Pos) ///< OVERRUN[31:20] ADC channel 0..11 data covered flag
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_CHnDR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_CHDR_DATA_Pos (0)
#define ADC_CHDR_DATA (0xFFFFU << ADC_CHDR_DATA_Pos) ///< ADC channel convert data
#define ADC_CHDR_OVERRUN_Pos (20)
#define ADC_CHDR_OVERRUN (0x01U << ADC_CHDR_OVERRUN_Pos) ///< ADC data covered flag
#define ADC_CHDR_VALID_Pos (21)
#define ADC_CHDR_VALID (0x01U << ADC_CHDR_VALID_Pos) ///< ADC data valid flag
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_SREXT Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_SREXT_VALID_Pos (0)
#define ADC_SREXT_VALID (0x0FU << ADC_SREXT_VALID_Pos) ///< VALID[3:0] ADC channel 12,14..15 valid flag
#define ADC_SREXT_OVERRUN_Pos (4)
#define ADC_SREXT_OVERRUN (0x0FU << ADC_SREXT_OVERRUN_Pos) ///< OVERRUN[7:4] ADC channel 12,14..15 data covered flag
#define ADC_SREXT_EOSMPIF_Pos (16)
#define ADC_SREXT_EOSMPIF (0x01U << ADC_SREXT_EOSMPIF_Pos) ///< End of sampling interrupt flag
#define ADC_SREXT_EOCIF_Pos (17)
#define ADC_SREXT_EOCIF (0x01U << ADC_SREXT_EOCIF_Pos) ///< End of conversion interrupt flag
#define ADC_SREXT_JEOSMPIF_Pos (18)
#define ADC_SREXT_JEOSMPIF (0x01U << ADC_SREXT_JEOSMPIF_Pos) /// Injected channel end of sampling interrupt flag
#define ADC_SREXT_JEOCIF_Pos (19)
#define ADC_SREXT_JEOCIF (0x03U << ADC_SREXT_JEOCIF_Pos) ///< Injected channel end of conversion interrupt flag
#define ADC_SREXT_JEOSIF_Pos (20)
#define ADC_SREXT_JEOSIF (0x03U << ADC_SREXT_JEOSIF_Pos) ///< Injected channel end of sequential conversion interrupt flag
#define ADC_SREXT_JBUSY_Pos (21)
#define ADC_SREXT_JBUSY (0x01U << ADC_SREXT_JBUSY_Pos) ///< Injection mode busy/idle
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_CHANY0 select Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC1_CHANY0_SEL0_Pos (0) ///< CHANY_SEL0 (Bit 0)
#define ADC1_CHANY0_SEL0 (0x0FU << ADC1_CHANY0_SEL0_Pos) ///< CHANY_SEL0 (Bitfield-Mask: 0x0f)
#define ADC1_CHANY0_SEL1_Pos (4) ///< CHANY_SEL1 (Bit 4)
#define ADC1_CHANY0_SEL1 (0x0FU << ADC1_CHANY0_SEL1_Pos) ///< CHANY_SEL1 (Bitfield-Mask: 0x0f)
#define ADC1_CHANY0_SEL2_Pos (8) ///< CHANY_SEL2 (Bit 8)
#define ADC1_CHANY0_SEL2 (0x0FU << ADC1_CHANY0_SEL2_Pos) ///< CHANY_SEL2 (Bitfield-Mask: 0x0f)
#define ADC1_CHANY0_SEL3_Pos (12) ///< CHANY_SEL3 (Bit 12)
#define ADC1_CHANY0_SEL3 (0x0FU << ADC1_CHANY0_SEL3_Pos) ///< CHANY_SEL3 (Bitfield-Mask: 0x0f)
#define ADC1_CHANY0_SEL4_Pos (16) ///< CHANY_SEL4 (Bit 16)
#define ADC1_CHANY0_SEL4 (0x0FU << ADC1_CHANY0_SEL4_Pos) ///< CHANY_SEL4 (Bitfield-Mask: 0x0f)
#define ADC1_CHANY0_SEL5_Pos (20) ///< CHANY_SEL5 (Bit 20)
#define ADC1_CHANY0_SEL5 (0x0FU << ADC1_CHANY0_SEL5_Pos) ///< CHANY_SEL5 (Bitfield-Mask: 0x0f)
#define ADC1_CHANY0_SEL6_Pos (24) ///< CHANY_SEL6 (Bit 24)
#define ADC1_CHANY0_SEL6 (0x0FU << ADC1_CHANY0_SEL6_Pos) ///< CHANY_SEL6 (Bitfield-Mask: 0x0f)
#define ADC1_CHANY0_SEL7_Pos (28) ///< CHANY_SEL7 (Bit 28)
#define ADC1_CHANY0_SEL7 (0x0FU << ADC1_CHANY0_SEL7_Pos) ///< CHANY_SEL7 (Bitfield-Mask: 0x0f)
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_CHANY1 select Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC1_CHANY1_SEL8_Pos (0) ///< CHANY_SEL8 (Bit 0)
#define ADC1_CHANY1_SEL8 (0x0FU << ADC1_CHANY1_SEL8_Pos) ///< CHANY_SEL8 (Bitfield-Mask: 0x0f)
#define ADC1_CHANY1_SEL9_Pos (4) ///< CHANY_SEL9 (Bit 4)
#define ADC1_CHANY1_SEL9 (0x0FU << ADC1_CHANY1_SEL9_Pos) ///< CHANY_SEL9 (Bitfield-Mask: 0x0f)
#define ADC1_CHANY1_SEL14_Pos (24) ///< CHANY_SEL14 (Bit 24)
#define ADC1_CHANY1_SEL14 (0x0FU << ADC1_CHANY1_SEL14_Pos) ///< CHANY_SEL14 (Bitfield-Mask: 0x0f)
#define ADC1_CHANY1_SEL15_Pos (28) ///< CHANY_SEL15 (Bit 28)
#define ADC1_CHANY1_SEL15 (0x0FU << ADC1_CHANY1_SEL15_Pos) ///< CHANY_SEL15 (Bitfield-Mask: 0x0f)
#define ADC1_CHANY1_SEL10_Pos (8) ///< CHANY_SEL10 (Bit 8)
#define ADC1_CHANY1_SEL10 (0x0FU << ADC1_CHANY1_SEL10_Pos) ///< CHANY_SEL10 (Bitfield-Mask: 0x0f)
#define ADC1_CHANY1_SEL11_Pos (12) ///< CHANY_SEL11 (Bit 12)
#define ADC1_CHANY1_SEL11 (0x0FU << ADC1_CHANY1_SEL11_Pos) ///< CHANY_SEL11 (Bitfield-Mask: 0x0f)
#define ADC1_CHANY1_SEL12_Pos (16) ///< CHANY_SEL12 (Bit 16)
#define ADC1_CHANY1_SEL12 (0x0FU << ADC1_CHANY1_SEL12_Pos) ///< CHANY_SEL12 (Bitfield-Mask: 0x0f)
#define ADC1_CHANY1_SEL13_Pos (20) ///< CHANY_SEL13 (Bit 20)
#define ADC1_CHANY1_SEL13 (0x0FU << ADC1_CHANY1_SEL13_Pos) ///< CHANY_SEL13 (Bitfield-Mask: 0x0f)
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_CHANY config number Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC1_CHANY_CFG_NUM_Max (16) ///< CHANY_CFG_NUM Max Value is 16
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_CHANY mode enable Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC1_CHANY_CR_MDEN_Pos (0) ///< CHANY_MDEN (Bit 0)
#define ADC1_CHANY_CR_MDEN (0x01U << ADC1_CHANY_CR_MDEN_Pos) ///< CHANY_MDEN (Bitfield-Mask: 0x01)
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_ANY_CR mode enable Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_ANY_CR_JTRGEDGE_Pos (16) ///< Injection mode triggers edge selection
#define ADC_ANY_CR_JTRGEDGE_R_F (0x00U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Triggered along both rising and falling edges
#define ADC_ANY_CR_JTRGEDGE_F (0x01U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Drop edge trigger
#define ADC_ANY_CR_JTRGEDGE_R (0x02U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Rising edge trigger
#define ADC_ANY_CR_JTRGEDGE_S (0x03U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Shield trigger
#define ADC_ANY_CR_JTRGSHIFT_Pos (13) ///< Injection mode external trigger delay sampling
#define ADC_ANY_CR_JTRGSHIFT_0 (0x00U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 0 cycle
#define ADC_ANY_CR_JTRGSHIFT_4 (0x01U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 4 cycle
#define ADC_ANY_CR_JTRGSHIFT_16 (0x02U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 16 cycle
#define ADC_ANY_CR_JTRGSHIFT_32 (0x03U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 32 cycle
#define ADC_ANY_CR_JTRGSHIFT_64 (0x04U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 64 cycle
#define ADC_ANY_CR_JTRGSHIFT_128 (0x05U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 128 cycle
#define ADC_ANY_CR_JTRGSHIFT_256 (0x06U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 256 cycle
#define ADC_ANY_CR_JTRGSHIFT_512 (0x07U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 512 cycle
#define ADC_ANY_CR_JTRGSEL_Pos (8) ///< External event select for injected group
#define ADC_ANY_CR_JTRGSEL (0x07U << ADC_ANY_CR_JTRGSEL_Pos)
#define ADC_ANY_CR_JTRGSEL_TIM1_TRGO (0x00U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM1 TRGO
#define ADC_ANY_CR_JTRGSEL_TIM1_CC4 (0x01U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM1 CC4
#define ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5 (0x02U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM1 CC4 and CC5
#define ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1 (0x03U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM2 CC1 and TIM4 CC1
#define ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4 (0x04U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM3 CC4 and TIM5 CC4
#define ADC_ANY_CR_JTRGSEL_TIM8_CC4 (0x05U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM8 CC4
#define ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5 (0x06U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM8 CC4 and CC5
#define ADC_ANY_CR_JTRGSEL_EXTI12 (0x07U << ADC_ANY_CR_JTRGSEL_Pos) ///< EXTI12
#define ADC_ANY_CR_JTRGEN_Pos (7)
#define ADC_ANY_CR_JTRGEN (0x01U << ADC_ANY_CR_JTRGEN_Pos) ///< External trigger conversion mode for injected channels
#define ADC_ANY_CR_JADST_Pos (6)
#define ADC_ANY_CR_JADST (0x01U << ADC_ANY_CR_JADST_Pos) ///< Start conversion of injected channels
#define ADC_ANY_CR_JAUTO_Pos (5)
#define ADC_ANY_CR_JAUTO (0x01U << ADC_ANY_CR_JAUTO_Pos) ///<Automatic Injected group conversion
#define ADC_ANY_CR_JEOSIE_Pos (4)
#define ADC_ANY_CR_JEOSIE (0x01U << ADC_ANY_CR_JEOSIE_Pos) ///< Interrupt enable the end of sequence conversion for injected channel
#define ADC_ANY_CR_JEOCIE_Pos (3)
#define ADC_ANY_CR_JEOCIE (0x01U << ADC_ANY_CR_JEOCIE_Pos) ///< Interrupt enable the end of conversion for injected channel
#define ADC_ANY_CR_JEOSMPIE_Pos (2)
#define ADC_ANY_CR_JEOSMPIE (0x01U << ADC_ANY_CR_JEOSMPIE_Pos) ///< Interrupt enable the end of sequence conversion for injected channel
#define ADC_ANY_CR_JCEN_Pos (1)
#define ADC_ANY_CR_JCEN (0x01U << ADC_ANY_CR_JCEN_Pos) ///< Injected channel enable
#define ADC_ANY_CR_CHANY_MDEN_Pos (0)
#define ADC_ANY_CR_CHANY_MDEN (0x01U << ADC_ANY_CR_CHANY_MDEN_Pos) ///< Enable bits for any channel configuration mode:
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_SMPR1 mode enable Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_SMPR_SAMCTL_Pos (0) ///< Injection mode external trigger delay sampling off_set Position
#define ADC_SMPR_SAMCTL_Msk (0x0FU << ADC_SMPR_SAMCTL_Pos) ///< Injection mode external trigger delay sampling mask for Value
#define ADC_SMPR_SAMCTL_2_5 (0x00U << ADC_SMPR_SAMCTL_Pos) ///< 2.5 cycle
#define ADC_SMPR_SAMCTL_8_5 (0x01U << ADC_SMPR_SAMCTL_Pos) ///< 8.5 cycle
#define ADC_SMPR_SAMCTL_14_5 (0x02U << ADC_SMPR_SAMCTL_Pos) ///< 14.5 cycle
#define ADC_SMPR_SAMCTL_29_5 (0x03U << ADC_SMPR_SAMCTL_Pos) ///< 29.5 cycle
#define ADC_SMPR_SAMCTL_42_5 (0x04U << ADC_SMPR_SAMCTL_Pos) ///< 42.5 cycle
#define ADC_SMPR_SAMCTL_56_5 (0x05U << ADC_SMPR_SAMCTL_Pos) ///< 56.5 cycle
#define ADC_SMPR_SAMCTL_72_5 (0x06U << ADC_SMPR_SAMCTL_Pos) ///< 72.5 cycle
#define ADC_SMPR_SAMCTL_240_5 (0x07U << ADC_SMPR_SAMCTL_Pos) ///< 240.5 cycle
#define ADC_SMPR_SAMCTL_3_5 (0x08U << ADC_SMPR_SAMCTL_Pos) ///< 3.5 cycle
#define ADC_SMPR_SAMCTL_4_5 (0x09U << ADC_SMPR_SAMCTL_Pos) ///< 4.5 cycle
#define ADC_SMPR_SAMCTL_5_5 (0x0AU << ADC_SMPR_SAMCTL_Pos) ///< 5.5 cycle
#define ADC_SMPR_SAMCTL_6_5 (0x0BU << ADC_SMPR_SAMCTL_Pos) ///< 6.5 cycle
#define ADC_SMPR_SAMCTL_7_5 (0x0CU << ADC_SMPR_SAMCTL_Pos) ///< 7.5 cycle
#define ADC_SMPR1_SAMCTL7_Pos (28) ///< Injection mode external trigger delay sampling
#define ADC_SMPR1_SAMCTL7_Msk (0x0FU << ADC_SMPR1_SAMCTL7_Pos) ///< Injection mode external trigger delay sampling mask for Value
#define ADC_SMPR1_SAMCTL7_2_5 (0x00U << ADC_SMPR1_SAMCTL7_Pos) ///< 2.5 cycle
#define ADC_SMPR1_SAMCTL7_8_5 (0x01U << ADC_SMPR1_SAMCTL7_Pos) ///< 8.5 cycle
#define ADC_SMPR1_SAMCTL7_14_5 (0x02U << ADC_SMPR1_SAMCTL7_Pos) ///< 14.5 cycle
#define ADC_SMPR1_SAMCTL7_29_5 (0x03U << ADC_SMPR1_SAMCTL7_Pos) ///< 29.5 cycle
#define ADC_SMPR1_SAMCTL7_42_5 (0x04U << ADC_SMPR1_SAMCTL7_Pos) ///< 42.5 cycle
#define ADC_SMPR1_SAMCTL7_56_5 (0x05U << ADC_SMPR1_SAMCTL7_Pos) ///< 56.5 cycle
#define ADC_SMPR1_SAMCTL7_72_5 (0x06U << ADC_SMPR1_SAMCTL7_Pos) ///< 72.5 cycle
#define ADC_SMPR1_SAMCTL7_240_5 (0x07U << ADC_SMPR1_SAMCTL7_Pos) ///< 240.5 cycle
#define ADC_SMPR1_SAMCTL7_3_5 (0x08U << ADC_SMPR1_SAMCTL7_Pos) ///< 3.5 cycle
#define ADC_SMPR1_SAMCTL7_4_5 (0x09U << ADC_SMPR1_SAMCTL7_Pos) ///< 4.5 cycle
#define ADC_SMPR1_SAMCTL7_5_5 (0x0AU << ADC_SMPR1_SAMCTL7_Pos) ///< 5.5 cycle
#define ADC_SMPR1_SAMCTL7_6_5 (0x0BU << ADC_SMPR1_SAMCTL7_Pos) ///< 6.5 cycle
#define ADC_SMPR1_SAMCTL7_7_5 (0x0CU << ADC_SMPR1_SAMCTL7_Pos) ///< 7.5 cycle
#define ADC_SMPR1_SAMCTL6_Pos (24) ///< Injection mode external trigger delay sampling
#define ADC_SMPR1_SAMCTL6_2_5 (0x00U << ADC_SMPR1_SAMCTL6_Pos) ///< 2.5 cycle
#define ADC_SMPR1_SAMCTL6_8_5 (0x01U << ADC_SMPR1_SAMCTL6_Pos) ///< 8.5 cycle
#define ADC_SMPR1_SAMCTL6_14_5 (0x02U << ADC_SMPR1_SAMCTL6_Pos) ///< 14.5 cycle
#define ADC_SMPR1_SAMCTL6_29_5 (0x03U << ADC_SMPR1_SAMCTL6_Pos) ///< 29.5 cycle
#define ADC_SMPR1_SAMCTL6_42_5 (0x04U << ADC_SMPR1_SAMCTL6_Pos) ///< 42.5 cycle
#define ADC_SMPR1_SAMCTL6_56_5 (0x05U << ADC_SMPR1_SAMCTL6_Pos) ///< 56.5 cycle
#define ADC_SMPR1_SAMCTL6_72_5 (0x06U << ADC_SMPR1_SAMCTL6_Pos) ///< 72.5 cycle
#define ADC_SMPR1_SAMCTL6_240_5 (0x07U << ADC_SMPR1_SAMCTL6_Pos) ///< 240.5 cycle
#define ADC_SMPR1_SAMCTL6_3_5 (0x08U << ADC_SMPR1_SAMCTL6_Pos) ///< 3.5 cycle
#define ADC_SMPR1_SAMCTL6_4_5 (0x09U << ADC_SMPR1_SAMCTL6_Pos) ///< 4.5 cycle
#define ADC_SMPR1_SAMCTL6_5_5 (0x0AU << ADC_SMPR1_SAMCTL6_Pos) ///< 5.5 cycle
#define ADC_SMPR1_SAMCTL6_6_5 (0x0BU << ADC_SMPR1_SAMCTL6_Pos) ///< 6.5 cycle
#define ADC_SMPR1_SAMCTL6_7_5 (0x0CU << ADC_SMPR1_SAMCTL6_Pos) ///< 7.5 cycle
#define ADC_SMPR1_SAMCTL5_Pos (20) ///< Injection mode external trigger delay sampling
#define ADC_SMPR1_SAMCTL5_2_5 (0x00U << ADC_SMPR1_SAMCTL5_Pos) ///< 2.5 cycle
#define ADC_SMPR1_SAMCTL5_8_5 (0x01U << ADC_SMPR1_SAMCTL5_Pos) ///< 8.5 cycle
#define ADC_SMPR1_SAMCTL5_14_5 (0x02U << ADC_SMPR1_SAMCTL5_Pos) ///< 14.5 cycle
#define ADC_SMPR1_SAMCTL5_29_5 (0x03U << ADC_SMPR1_SAMCTL5_Pos) ///< 29.5 cycle
#define ADC_SMPR1_SAMCTL5_42_5 (0x04U << ADC_SMPR1_SAMCTL5_Pos) ///< 42.5 cycle
#define ADC_SMPR1_SAMCTL5_56_5 (0x05U << ADC_SMPR1_SAMCTL5_Pos) ///< 56.5 cycle
#define ADC_SMPR1_SAMCTL5_72_5 (0x06U << ADC_SMPR1_SAMCTL5_Pos) ///< 72.5 cycle
#define ADC_SMPR1_SAMCTL5_240_5 (0x07U << ADC_SMPR1_SAMCTL5_Pos) ///< 240.5 cycle
#define ADC_SMPR1_SAMCTL5_3_5 (0x08U << ADC_SMPR1_SAMCTL5_Pos) ///< 3.5 cycle
#define ADC_SMPR1_SAMCTL5_4_5 (0x09U << ADC_SMPR1_SAMCTL5_Pos) ///< 4.5 cycle
#define ADC_SMPR1_SAMCTL5_5_5 (0x0AU << ADC_SMPR1_SAMCTL5_Pos) ///< 5.5 cycle
#define ADC_SMPR1_SAMCTL5_6_5 (0x0BU << ADC_SMPR1_SAMCTL5_Pos) ///< 6.5 cycle
#define ADC_SMPR1_SAMCTL5_7_5 (0x0CU << ADC_SMPR1_SAMCTL5_Pos) ///< 7.5 cycle
#define ADC_SMPR1_SAMCTL4_Pos (16) ///< Injection mode external trigger delay sampling
#define ADC_SMPR1_SAMCTL4_2_5 (0x00U << ADC_SMPR1_SAMCTL4_Pos) ///< 2.5 cycle
#define ADC_SMPR1_SAMCTL4_8_5 (0x01U << ADC_SMPR1_SAMCTL4_Pos) ///< 8.5 cycle
#define ADC_SMPR1_SAMCTL4_14_5 (0x02U << ADC_SMPR1_SAMCTL4_Pos) ///< 14.5 cycle
#define ADC_SMPR1_SAMCTL4_29_5 (0x03U << ADC_SMPR1_SAMCTL4_Pos) ///< 29.5 cycle
#define ADC_SMPR1_SAMCTL4_42_5 (0x04U << ADC_SMPR1_SAMCTL4_Pos) ///< 42.5 cycle
#define ADC_SMPR1_SAMCTL4_56_5 (0x05U << ADC_SMPR1_SAMCTL4_Pos) ///< 56.5 cycle
#define ADC_SMPR1_SAMCTL4_72_5 (0x06U << ADC_SMPR1_SAMCTL4_Pos) ///< 72.5 cycle
#define ADC_SMPR1_SAMCTL4_240_5 (0x07U << ADC_SMPR1_SAMCTL4_Pos) ///< 240.5 cycle
#define ADC_SMPR1_SAMCTL4_3_5 (0x08U << ADC_SMPR1_SAMCTL4_Pos) ///< 3.5 cycle
#define ADC_SMPR1_SAMCTL4_4_5 (0x09U << ADC_SMPR1_SAMCTL4_Pos) ///< 4.5 cycle
#define ADC_SMPR1_SAMCTL4_5_5 (0x0AU << ADC_SMPR1_SAMCTL4_Pos) ///< 5.5 cycle
#define ADC_SMPR1_SAMCTL4_6_5 (0x0BU << ADC_SMPR1_SAMCTL4_Pos) ///< 6.5 cycle
#define ADC_SMPR1_SAMCTL4_7_5 (0x0CU << ADC_SMPR1_SAMCTL4_Pos) ///< 7.5 cycle
#define ADC_SMPR1_SAMCTL3_Pos (12) ///< Injection mode external trigger delay sampling
#define ADC_SMPR1_SAMCTL3_2_5 (0x00U << ADC_SMPR1_SAMCTL3_Pos) ///< 2.5 cycle
#define ADC_SMPR1_SAMCTL3_8_5 (0x01U << ADC_SMPR1_SAMCTL3_Pos) ///< 8.5 cycle
#define ADC_SMPR1_SAMCTL3_14_5 (0x02U << ADC_SMPR1_SAMCTL3_Pos) ///< 14.5 cycle
#define ADC_SMPR1_SAMCTL3_29_5 (0x03U << ADC_SMPR1_SAMCTL3_Pos) ///< 29.5 cycle
#define ADC_SMPR1_SAMCTL3_42_5 (0x04U << ADC_SMPR1_SAMCTL3_Pos) ///< 42.5 cycle
#define ADC_SMPR1_SAMCTL3_56_5 (0x05U << ADC_SMPR1_SAMCTL3_Pos) ///< 56.5 cycle
#define ADC_SMPR1_SAMCTL3_72_5 (0x06U << ADC_SMPR1_SAMCTL3_Pos) ///< 72.5 cycle
#define ADC_SMPR1_SAMCTL3_240_5 (0x07U << ADC_SMPR1_SAMCTL3_Pos) ///< 240.5 cycle
#define ADC_SMPR1_SAMCTL3_3_5 (0x08U << ADC_SMPR1_SAMCTL3_Pos) ///< 3.5 cycle
#define ADC_SMPR1_SAMCTL3_4_5 (0x09U << ADC_SMPR1_SAMCTL3_Pos) ///< 4.5 cycle
#define ADC_SMPR1_SAMCTL3_5_5 (0x0AU << ADC_SMPR1_SAMCTL3_Pos) ///< 5.5 cycle
#define ADC_SMPR1_SAMCTL3_6_5 (0x0BU << ADC_SMPR1_SAMCTL3_Pos) ///< 6.5 cycle
#define ADC_SMPR1_SAMCTL3_7_5 (0x0CU << ADC_SMPR1_SAMCTL3_Pos) ///< 7.5 cycle
#define ADC_SMPR1_SAMCTL2_Pos (8) ///< Injection mode external trigger delay sampling
#define ADC_SMPR1_SAMCTL2_2_5 (0x00U << ADC_SMPR1_SAMCTL2_Pos) ///< 2.5 cycle
#define ADC_SMPR1_SAMCTL2_8_5 (0x01U << ADC_SMPR1_SAMCTL2_Pos) ///< 8.5 cycle
#define ADC_SMPR1_SAMCTL2_14_5 (0x02U << ADC_SMPR1_SAMCTL2_Pos) ///< 14.5 cycle
#define ADC_SMPR1_SAMCTL2_29_5 (0x03U << ADC_SMPR1_SAMCTL2_Pos) ///< 29.5 cycle
#define ADC_SMPR1_SAMCTL2_42_5 (0x04U << ADC_SMPR1_SAMCTL2_Pos) ///< 42.5 cycle
#define ADC_SMPR1_SAMCTL2_56_5 (0x05U << ADC_SMPR1_SAMCTL2_Pos) ///< 56.5 cycle
#define ADC_SMPR1_SAMCTL2_72_5 (0x06U << ADC_SMPR1_SAMCTL2_Pos) ///< 72.5 cycle
#define ADC_SMPR1_SAMCTL2_240_5 (0x07U << ADC_SMPR1_SAMCTL2_Pos) ///< 240.5 cycle
#define ADC_SMPR1_SAMCTL2_3_5 (0x08U << ADC_SMPR1_SAMCTL2_Pos) ///< 3.5 cycle
#define ADC_SMPR1_SAMCTL2_4_5 (0x09U << ADC_SMPR1_SAMCTL2_Pos) ///< 4.5 cycle
#define ADC_SMPR1_SAMCTL2_5_5 (0x0AU << ADC_SMPR1_SAMCTL2_Pos) ///< 5.5 cycle
#define ADC_SMPR1_SAMCTL2_6_5 (0x0BU << ADC_SMPR1_SAMCTL2_Pos) ///< 6.5 cycle
#define ADC_SMPR1_SAMCTL2_7_5 (0x0CU << ADC_SMPR1_SAMCTL2_Pos) ///< 7.5 cycle
#define ADC_SMPR1_SAMCTL1_Pos (4) ///< Injection mode external trigger delay sampling
#define ADC_SMPR1_SAMCTL1_2_5 (0x00U << ADC_SMPR1_SAMCTL1_Pos) ///< 2.5 cycle
#define ADC_SMPR1_SAMCTL1_8_5 (0x01U << ADC_SMPR1_SAMCTL1_Pos) ///< 8.5 cycle
#define ADC_SMPR1_SAMCTL1_14_5 (0x02U << ADC_SMPR1_SAMCTL1_Pos) ///< 14.5 cycle
#define ADC_SMPR1_SAMCTL1_29_5 (0x03U << ADC_SMPR1_SAMCTL1_Pos) ///< 29.5 cycle
#define ADC_SMPR1_SAMCTL1_42_5 (0x04U << ADC_SMPR1_SAMCTL1_Pos) ///< 42.5 cycle
#define ADC_SMPR1_SAMCTL1_56_5 (0x05U << ADC_SMPR1_SAMCTL1_Pos) ///< 56.5 cycle
#define ADC_SMPR1_SAMCTL1_72_5 (0x06U << ADC_SMPR1_SAMCTL1_Pos) ///< 72.5 cycle
#define ADC_SMPR1_SAMCTL1_240_5 (0x07U << ADC_SMPR1_SAMCTL1_Pos) ///< 240.5 cycle
#define ADC_SMPR1_SAMCTL1_3_5 (0x08U << ADC_SMPR1_SAMCTL1_Pos) ///< 3.5 cycle
#define ADC_SMPR1_SAMCTL1_4_5 (0x09U << ADC_SMPR1_SAMCTL1_Pos) ///< 4.5 cycle
#define ADC_SMPR1_SAMCTL1_5_5 (0x0AU << ADC_SMPR1_SAMCTL1_Pos) ///< 5.5 cycle
#define ADC_SMPR1_SAMCTL1_6_5 (0x0BU << ADC_SMPR1_SAMCTL1_Pos) ///< 6.5 cycle
#define ADC_SMPR1_SAMCTL1_7_5 (0x0CU << ADC_SMPR1_SAMCTL1_Pos) ///< 7.5 cycle
#define ADC_SMPR1_SAMCTL0_Pos (0) ///< Injection mode external trigger delay sampling
#define ADC_SMPR1_SAMCTL0_2_5 (0x00U << ADC_SMPR1_SAMCTL0_Pos) ///< 2.5 cycle
#define ADC_SMPR1_SAMCTL0_8_5 (0x01U << ADC_SMPR1_SAMCTL0_Pos) ///< 8.5 cycle
#define ADC_SMPR1_SAMCTL0_14_5 (0x02U << ADC_SMPR1_SAMCTL0_Pos) ///< 14.5 cycle
#define ADC_SMPR1_SAMCTL0_29_5 (0x03U << ADC_SMPR1_SAMCTL0_Pos) ///< 29.5 cycle
#define ADC_SMPR1_SAMCTL0_42_5 (0x04U << ADC_SMPR1_SAMCTL0_Pos) ///< 42.5 cycle
#define ADC_SMPR1_SAMCTL0_56_5 (0x05U << ADC_SMPR1_SAMCTL0_Pos) ///< 56.5 cycle
#define ADC_SMPR1_SAMCTL0_72_5 (0x06U << ADC_SMPR1_SAMCTL0_Pos) ///< 72.5 cycle
#define ADC_SMPR1_SAMCTL0_240_5 (0x07U << ADC_SMPR1_SAMCTL0_Pos) ///< 240.5 cycle
#define ADC_SMPR1_SAMCTL0_3_5 (0x08U << ADC_SMPR1_SAMCTL0_Pos) ///< 3.5 cycle
#define ADC_SMPR1_SAMCTL0_4_5 (0x09U << ADC_SMPR1_SAMCTL0_Pos) ///< 4.5 cycle
#define ADC_SMPR1_SAMCTL0_5_5 (0x0AU << ADC_SMPR1_SAMCTL0_Pos) ///< 5.5 cycle
#define ADC_SMPR1_SAMCTL0_6_5 (0x0BU << ADC_SMPR1_SAMCTL0_Pos) ///< 6.5 cycle
#define ADC_SMPR1_SAMCTL0_7_5 (0x0CU << ADC_SMPR1_SAMCTL0_Pos) ///< 7.5 cycle
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_SMPR2 mode enable Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_SMPR2_SAMCTL15_Pos (28) ///< Injection mode external trigger delay sampling
#define ADC_SMPR2_SAMCTL15_2_5 (0x00U << ADC_SMPR2_SAMCTL15_Pos) ///< 2.5 cycle
#define ADC_SMPR2_SAMCTL15_8_5 (0x01U << ADC_SMPR2_SAMCTL15_Pos) ///< 8.5 cycle
#define ADC_SMPR2_SAMCTL15_14_5 (0x02U << ADC_SMPR2_SAMCTL15_Pos) ///< 14.5 cycle
#define ADC_SMPR2_SAMCTL15_29_5 (0x03U << ADC_SMPR2_SAMCTL15_Pos) ///< 29.5 cycle
#define ADC_SMPR2_SAMCTL15_42_5 (0x04U << ADC_SMPR2_SAMCTL15_Pos) ///< 42.5 cycle
#define ADC_SMPR2_SAMCTL15_56_5 (0x05U << ADC_SMPR2_SAMCTL15_Pos) ///< 56.5 cycle
#define ADC_SMPR2_SAMCTL15_72_5 (0x06U << ADC_SMPR2_SAMCTL15_Pos) ///< 72.5 cycle
#define ADC_SMPR2_SAMCTL15_240_5 (0x07U << ADC_SMPR2_SAMCTL15_Pos) ///< 240.5 cycle
#define ADC_SMPR2_SAMCTL15_3_5 (0x08U << ADC_SMPR2_SAMCTL15_Pos) ///< 3.5 cycle
#define ADC_SMPR2_SAMCTL15_4_5 (0x09U << ADC_SMPR2_SAMCTL15_Pos) ///< 4.5 cycle
#define ADC_SMPR2_SAMCTL15_5_5 (0x0AU << ADC_SMPR2_SAMCTL15_Pos) ///< 5.5 cycle
#define ADC_SMPR2_SAMCTL15_6_5 (0x0BU << ADC_SMPR2_SAMCTL15_Pos) ///< 6.5 cycle
#define ADC_SMPR2_SAMCTL15_7_5 (0x0CU << ADC_SMPR2_SAMCTL15_Pos) ///< 7.5 cycle
#define ADC_SMPR2_SAMCTL14_Pos (24) ///< Injection mode external trigger delay sampling
#define ADC_SMPR2_SAMCTL14_2_5 (0x00U << ADC_SMPR2_SAMCTL14_Pos) ///< 2.5 cycle
#define ADC_SMPR2_SAMCTL14_8_5 (0x01U << ADC_SMPR2_SAMCTL14_Pos) ///< 8.5 cycle
#define ADC_SMPR2_SAMCTL14_14_5 (0x02U << ADC_SMPR2_SAMCTL14_Pos) ///< 14.5 cycle
#define ADC_SMPR2_SAMCTL14_29_5 (0x03U << ADC_SMPR2_SAMCTL14_Pos) ///< 29.5 cycle
#define ADC_SMPR2_SAMCTL14_42_5 (0x04U << ADC_SMPR2_SAMCTL14_Pos) ///< 42.5 cycle
#define ADC_SMPR2_SAMCTL14_56_5 (0x05U << ADC_SMPR2_SAMCTL14_Pos) ///< 56.5 cycle
#define ADC_SMPR2_SAMCTL14_72_5 (0x06U << ADC_SMPR2_SAMCTL14_Pos) ///< 72.5 cycle
#define ADC_SMPR2_SAMCTL14_240_5 (0x07U << ADC_SMPR2_SAMCTL14_Pos) ///< 240.5 cycle
#define ADC_SMPR2_SAMCTL14_3_5 (0x08U << ADC_SMPR2_SAMCTL14_Pos) ///< 3.5 cycle
#define ADC_SMPR2_SAMCTL14_4_5 (0x09U << ADC_SMPR2_SAMCTL14_Pos) ///< 4.5 cycle
#define ADC_SMPR2_SAMCTL14_5_5 (0x0AU << ADC_SMPR2_SAMCTL14_Pos) ///< 5.5 cycle
#define ADC_SMPR2_SAMCTL14_6_5 (0x0BU << ADC_SMPR2_SAMCTL14_Pos) ///< 6.5 cycle
#define ADC_SMPR2_SAMCTL14_7_5 (0x0CU << ADC_SMPR2_SAMCTL14_Pos) ///< 7.5 cycle
#define ADC_SMPR2_SAMCTL13_Pos (20) ///< Injection mode external trigger delay sampling
#define ADC_SMPR2_SAMCTL13_2_5 (0x00U << ADC_SMPR2_SAMCTL13_Pos) ///< 2.5 cycle
#define ADC_SMPR2_SAMCTL13_8_5 (0x01U << ADC_SMPR2_SAMCTL13_Pos) ///< 8.5 cycle
#define ADC_SMPR2_SAMCTL13_14_5 (0x02U << ADC_SMPR2_SAMCTL13_Pos) ///< 14.5 cycle
#define ADC_SMPR2_SAMCTL13_29_5 (0x03U << ADC_SMPR2_SAMCTL13_Pos) ///< 29.5 cycle
#define ADC_SMPR2_SAMCTL13_42_5 (0x04U << ADC_SMPR2_SAMCTL13_Pos) ///< 42.5 cycle
#define ADC_SMPR2_SAMCTL13_56_5 (0x05U << ADC_SMPR2_SAMCTL13_Pos) ///< 56.5 cycle
#define ADC_SMPR2_SAMCTL13_72_5 (0x06U << ADC_SMPR2_SAMCTL13_Pos) ///< 72.5 cycle
#define ADC_SMPR2_SAMCTL13_240_5 (0x07U << ADC_SMPR2_SAMCTL13_Pos) ///< 240.5 cycle
#define ADC_SMPR2_SAMCTL13_3_5 (0x08U << ADC_SMPR2_SAMCTL13_Pos) ///< 3.5 cycle
#define ADC_SMPR2_SAMCTL13_4_5 (0x09U << ADC_SMPR2_SAMCTL13_Pos) ///< 4.5 cycle
#define ADC_SMPR2_SAMCTL13_5_5 (0x0AU << ADC_SMPR2_SAMCTL13_Pos) ///< 5.5 cycle
#define ADC_SMPR2_SAMCTL13_6_5 (0x0BU << ADC_SMPR2_SAMCTL13_Pos) ///< 6.5 cycle
#define ADC_SMPR2_SAMCTL13_7_5 (0x0CU << ADC_SMPR2_SAMCTL13_Pos) ///< 7.5 cycle
#define ADC_SMPR2_SAMCTL12_Pos (16) ///< Injection mode external trigger delay sampling
#define ADC_SMPR2_SAMCTL12_2_5 (0x00U << ADC_SMPR2_SAMCTL12_Pos) ///< 2.5 cycle
#define ADC_SMPR2_SAMCTL12_8_5 (0x01U << ADC_SMPR2_SAMCTL12_Pos) ///< 8.5 cycle
#define ADC_SMPR2_SAMCTL12_14_5 (0x02U << ADC_SMPR2_SAMCTL12_Pos) ///< 14.5 cycle
#define ADC_SMPR2_SAMCTL12_29_5 (0x03U << ADC_SMPR2_SAMCTL12_Pos) ///< 29.5 cycle
#define ADC_SMPR2_SAMCTL12_42_5 (0x04U << ADC_SMPR2_SAMCTL12_Pos) ///< 42.5 cycle
#define ADC_SMPR2_SAMCTL12_56_5 (0x05U << ADC_SMPR2_SAMCTL12_Pos) ///< 56.5 cycle
#define ADC_SMPR2_SAMCTL12_72_5 (0x06U << ADC_SMPR2_SAMCTL12_Pos) ///< 72.5 cycle
#define ADC_SMPR2_SAMCTL12_240_5 (0x07U << ADC_SMPR2_SAMCTL12_Pos) ///< 240.5 cycle
#define ADC_SMPR2_SAMCTL12_3_5 (0x08U << ADC_SMPR2_SAMCTL12_Pos) ///< 3.5 cycle
#define ADC_SMPR2_SAMCTL12_4_5 (0x09U << ADC_SMPR2_SAMCTL12_Pos) ///< 4.5 cycle
#define ADC_SMPR2_SAMCTL12_5_5 (0x0AU << ADC_SMPR2_SAMCTL12_Pos) ///< 5.5 cycle
#define ADC_SMPR2_SAMCTL12_6_5 (0x0BU << ADC_SMPR2_SAMCTL12_Pos) ///< 6.5 cycle
#define ADC_SMPR2_SAMCTL12_7_5 (0x0CU << ADC_SMPR2_SAMCTL12_Pos) ///< 7.5 cycle
#define ADC_SMPR2_SAMCTL11_Pos (12) ///< Injection mode external trigger delay sampling
#define ADC_SMPR2_SAMCTL11_2_5 (0x00U << ADC_SMPR2_SAMCTL11_Pos) ///< 2.5 cycle
#define ADC_SMPR2_SAMCTL11_8_5 (0x01U << ADC_SMPR2_SAMCTL11_Pos) ///< 8.5 cycle
#define ADC_SMPR2_SAMCTL11_14_5 (0x02U << ADC_SMPR2_SAMCTL11_Pos) ///< 14.5 cycle
#define ADC_SMPR2_SAMCTL11_29_5 (0x03U << ADC_SMPR2_SAMCTL11_Pos) ///< 29.5 cycle
#define ADC_SMPR2_SAMCTL11_42_5 (0x04U << ADC_SMPR2_SAMCTL11_Pos) ///< 42.5 cycle
#define ADC_SMPR2_SAMCTL11_56_5 (0x05U << ADC_SMPR2_SAMCTL11_Pos) ///< 56.5 cycle
#define ADC_SMPR2_SAMCTL11_72_5 (0x06U << ADC_SMPR2_SAMCTL11_Pos) ///< 72.5 cycle
#define ADC_SMPR2_SAMCTL11_240_5 (0x07U << ADC_SMPR2_SAMCTL11_Pos) ///< 240.5 cycle
#define ADC_SMPR2_SAMCTL11_3_5 (0x08U << ADC_SMPR2_SAMCTL11_Pos) ///< 3.5 cycle
#define ADC_SMPR2_SAMCTL11_4_5 (0x09U << ADC_SMPR2_SAMCTL11_Pos) ///< 4.5 cycle
#define ADC_SMPR2_SAMCTL11_5_5 (0x0AU << ADC_SMPR2_SAMCTL11_Pos) ///< 5.5 cycle
#define ADC_SMPR2_SAMCTL11_6_5 (0x0BU << ADC_SMPR2_SAMCTL11_Pos) ///< 6.5 cycle
#define ADC_SMPR2_SAMCTL11_7_5 (0x0CU << ADC_SMPR2_SAMCTL11_Pos) ///< 7.5 cycle
#define ADC_SMPR2_SAMCTL10_Pos (8) ///< Injection mode external trigger delay sampling
#define ADC_SMPR2_SAMCTL10_2_5 (0x00U << ADC_SMPR2_SAMCTL10_Pos) ///< 2.5 cycle
#define ADC_SMPR2_SAMCTL10_8_5 (0x01U << ADC_SMPR2_SAMCTL10_Pos) ///< 8.5 cycle
#define ADC_SMPR2_SAMCTL10_14_5 (0x02U << ADC_SMPR2_SAMCTL10_Pos) ///< 14.5 cycle
#define ADC_SMPR2_SAMCTL10_29_5 (0x03U << ADC_SMPR2_SAMCTL10_Pos) ///< 29.5 cycle
#define ADC_SMPR2_SAMCTL10_42_5 (0x04U << ADC_SMPR2_SAMCTL10_Pos) ///< 42.5 cycle
#define ADC_SMPR2_SAMCTL10_56_5 (0x05U << ADC_SMPR2_SAMCTL10_Pos) ///< 56.5 cycle
#define ADC_SMPR2_SAMCTL10_72_5 (0x06U << ADC_SMPR2_SAMCTL10_Pos) ///< 72.5 cycle
#define ADC_SMPR2_SAMCTL10_240_5 (0x07U << ADC_SMPR2_SAMCTL10_Pos) ///< 240.5 cycle
#define ADC_SMPR2_SAMCTL10_3_5 (0x08U << ADC_SMPR2_SAMCTL10_Pos) ///< 3.5 cycle
#define ADC_SMPR2_SAMCTL10_4_5 (0x09U << ADC_SMPR2_SAMCTL10_Pos) ///< 4.5 cycle
#define ADC_SMPR2_SAMCTL10_5_5 (0x0AU << ADC_SMPR2_SAMCTL10_Pos) ///< 5.5 cycle
#define ADC_SMPR2_SAMCTL10_6_5 (0x0BU << ADC_SMPR2_SAMCTL10_Pos) ///< 6.5 cycle
#define ADC_SMPR2_SAMCTL10_7_5 (0x0CU << ADC_SMPR2_SAMCTL10_Pos) ///< 7.5 cycle
#define ADC_SMPR2_SAMCTL9_Pos (4) ///< Injection mode external trigger delay sampling
#define ADC_SMPR2_SAMCTL9_2_5 (0x00U << ADC_SMPR2_SAMCTL9_Pos) ///< 2.5 cycle
#define ADC_SMPR2_SAMCTL9_8_5 (0x01U << ADC_SMPR2_SAMCTL9_Pos) ///< 8.5 cycle
#define ADC_SMPR2_SAMCTL9_14_5 (0x02U << ADC_SMPR2_SAMCTL9_Pos) ///< 14.5 cycle
#define ADC_SMPR2_SAMCTL9_29_5 (0x03U << ADC_SMPR2_SAMCTL9_Pos) ///< 29.5 cycle
#define ADC_SMPR2_SAMCTL9_42_5 (0x04U << ADC_SMPR2_SAMCTL9_Pos) ///< 42.5 cycle
#define ADC_SMPR2_SAMCTL9_56_5 (0x05U << ADC_SMPR2_SAMCTL9_Pos) ///< 56.5 cycle
#define ADC_SMPR2_SAMCTL9_72_5 (0x06U << ADC_SMPR2_SAMCTL9_Pos) ///< 72.5 cycle
#define ADC_SMPR2_SAMCTL9_240_5 (0x07U << ADC_SMPR2_SAMCTL9_Pos) ///< 240.5 cycle
#define ADC_SMPR2_SAMCTL9_3_5 (0x08U << ADC_SMPR2_SAMCTL9_Pos) ///< 3.5 cycle
#define ADC_SMPR2_SAMCTL9_4_5 (0x09U << ADC_SMPR2_SAMCTL9_Pos) ///< 4.5 cycle
#define ADC_SMPR2_SAMCTL9_5_5 (0x0AU << ADC_SMPR2_SAMCTL9_Pos) ///< 5.5 cycle
#define ADC_SMPR2_SAMCTL9_6_5 (0x0BU << ADC_SMPR2_SAMCTL9_Pos) ///< 6.5 cycle
#define ADC_SMPR2_SAMCTL9_7_5 (0x0CU << ADC_SMPR2_SAMCTL9_Pos) ///< 7.5 cycle
#define ADC_SMPR2_SAMCTL8_Pos (0) ///< Injection mode external trigger delay sampling
#define ADC_SMPR2_SAMCTL8_2_5 (0x00U << ADC_SMPR2_SAMCTL8_Pos) ///< 2.5 cycle
#define ADC_SMPR2_SAMCTL8_8_5 (0x01U << ADC_SMPR2_SAMCTL8_Pos) ///< 8.5 cycle
#define ADC_SMPR2_SAMCTL8_14_5 (0x02U << ADC_SMPR2_SAMCTL8_Pos) ///< 14.5 cycle
#define ADC_SMPR2_SAMCTL8_29_5 (0x03U << ADC_SMPR2_SAMCTL8_Pos) ///< 29.5 cycle
#define ADC_SMPR2_SAMCTL8_42_5 (0x04U << ADC_SMPR2_SAMCTL8_Pos) ///< 42.5 cycle
#define ADC_SMPR2_SAMCTL8_56_5 (0x05U << ADC_SMPR2_SAMCTL8_Pos) ///< 56.5 cycle
#define ADC_SMPR2_SAMCTL8_72_5 (0x06U << ADC_SMPR2_SAMCTL8_Pos) ///< 72.5 cycle
#define ADC_SMPR2_SAMCTL8_240_5 (0x07U << ADC_SMPR2_SAMCTL8_Pos) ///< 240.5 cycle
#define ADC_SMPR2_SAMCTL8_3_5 (0x08U << ADC_SMPR2_SAMCTL8_Pos) ///< 3.5 cycle
#define ADC_SMPR2_SAMCTL8_4_5 (0x09U << ADC_SMPR2_SAMCTL8_Pos) ///< 4.5 cycle
#define ADC_SMPR2_SAMCTL8_5_5 (0x0AU << ADC_SMPR2_SAMCTL8_Pos) ///< 5.5 cycle
#define ADC_SMPR2_SAMCTL8_6_5 (0x0BU << ADC_SMPR2_SAMCTL8_Pos) ///< 6.5 cycle
#define ADC_SMPR2_SAMCTL8_7_5 (0x0CU << ADC_SMPR2_SAMCTL8_Pos) ///< 7.5 cycle
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_JOFR0 mode enable Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_JOFR0_JOFR (0xFFFU) ///< Compensates for the A/D conversion results of the injected channel 0
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_JOFR1 mode enable Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_JOFR1_JOFR (0xFFFU) ///< Compensates for the A/D conversion results of the injected channel 1
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_JOFR2 mode enable Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_JOFR2_JOFR (0xFFFU) ///< Compensates for the A/D conversion results of the injected channel 2
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_JOFR3 mode enable Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_JOFR3_JOFR (0xFFFU) ///< Compensates for the A/D conversion results of the injected channel 3
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_JSQR mode enable Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_JSQR_JSQ0_Pos (0) ///< 1st conversion in injected sequence
#define ADC_JSQR_JSQ0_0 (0x01U << ADC_JSQR_JSQ0_Pos) ///< Bit 0
#define ADC_JSQR_JSQ0_1 (0x02U << ADC_JSQR_JSQ0_Pos) ///< Bit 1
#define ADC_JSQR_JSQ0_2 (0x04U << ADC_JSQR_JSQ0_Pos) ///< Bit 2
#define ADC_JSQR_JSQ0_3 (0x08U << ADC_JSQR_JSQ0_Pos) ///< Bit 3
#define ADC_JSQR_JSQ0_4 (0x10U << ADC_JSQR_JSQ0_Pos) ///< Bit 4
#define ADC_JSQR_JSQ1_Pos (5 ) ///< 2st conversion in injected sequence
#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) ///< Bit 0
#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) ///< Bit 1
#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) ///< Bit 2
#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) ///< Bit 3
#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) ///< Bit 4
#define ADC_JSQR_JSQ2_Pos (10) ///< 3st conversion in injected sequence
#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) ///< Bit 0
#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) ///< Bit 1
#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) ///< Bit 2
#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) ///< Bit 3
#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) ///< Bit 4
#define ADC_JSQR_JSQ3_Pos (15) ///< 4st conversion in injected sequence
#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) ///< Bit 0
#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) ///< Bit 1
#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) ///< Bit 2
#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) ///< Bit 3
#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) ///< Bit 4
#define ADC_JSQR_JL_Pos (20) ///< Injected Sequence length
#define ADC_JSQR_JL_0 (0x01U << ADC_JSQR_JL_Pos) ///< Bit 0
#define ADC_JSQR_JL_1 (0x02U << ADC_JSQR_JL_Pos) ///< Bit 1
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_JDATA mode enable Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_JDATA_JVALID_Pos (22)
#define ADC_JDATA_JVALID (0x01U << ADC_JDATA_JVALID_Pos) ///< Valid flag
#define ADC_JDATA_JOVERRUN_Pos (21)
#define ADC_JDATA_JOVERRUN (0x01U << ADC_JDATA_JOVERRUN_Pos) ///< Overrun flag
#define ADC_JDATA_JCHANNELSEL_Pos (16)
#define ADC_JDATA_JCHANNELSEL (0xFFU << ADC_JDATA_JCHANNELSEL_Pos) ///< Channel selection
#define ADC_JDATA_JDATA_Pos (0)
#define ADC_JDATA_JDATA (0xFFFFU << ADC_JSQR_JSQ0_Pos) ///< Transfer data
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_JDR0 mode enable Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_JDR0_JVALID_Pos (22)
#define ADC_JDR0_JVALID (0x01U << ADC_JDATA_JVALID_Pos) ///< Valid flag
#define ADC_JDR0_JOVERRUN_Pos (21)
#define ADC_JDR0_JOVERRUN (0x01U << ADC_JDATA_JOVERRUN_Pos) ///< Overrun flag
#define ADC_JDR0_JDATA_Pos (0)
#define ADC_JDR0_JDATA (0xFFFFU << ADC_JSQR_JSQ0_Pos) ///< Transfer data
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_JDR1 mode enable Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_JDR1_JVALID_Pos (22)
#define ADC_JDR1_JVALID (0x01U << ADC_JDATA_JVALID_Pos) ///< Valid flag
#define ADC_JDR1_JOVERRUN_Pos (21)
#define ADC_JDR1_JOVERRUN (0x01U << ADC_JDATA_JOVERRUN_Pos) ///< Overrun flag
#define ADC_JDR1_JDATA_Pos (0)
#define ADC_JDR1_JDATA (0xFFFFU << ADC_JSQR_JSQ0_Pos) ///< Transfer data
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_JDR2 mode enable Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_JDR2_JVALID_Pos (22)
#define ADC_JDR2_JVALID (0x01U << ADC_JDATA_JVALID_Pos) ///< Valid flag
#define ADC_JDR2_JOVERRUN_Pos (21)
#define ADC_JDR2_JOVERRUN (0x01U << ADC_JDATA_JOVERRUN_Pos) ///< Overrun flag
#define ADC_JDR2_JDATA_Pos (0)
#define ADC_JDR2_JDATA (0xFFFFU << ADC_JSQR_JSQ0_Pos) ///< Transfer data
////////////////////////////////////////////////////////////////////////////////
/// @brief ADC_JDR3 mode enable Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ADC_JDR3_JVALID_Pos (22)
#define ADC_JDR3_JVALID (0x01U << ADC_JDATA_JVALID_Pos) ///< Valid flag
#define ADC_JDR3_JOVERRUN_Pos (21)
#define ADC_JDR3_JOVERRUN (0x01U << ADC_JDATA_JOVERRUN_Pos) ///< Overrun flag
#define ADC_JDR3_JDATA_Pos (0)
#define ADC_JDR3_JDATA (0xFFFFU << ADC_JSQR_JSQ0_Pos) ///< Transfer data
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_bkp.h
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_bkp.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_BKP_H
#define __REG_BKP_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief BKP Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define BKP_BASE (APB1PERIPH_BASE + 0x2840) ///< Base Address: 0x40002840
////////////////////////////////////////////////////////////////////////////////
/// @brief BKP Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
#define BKP_NUMBER 20
typedef struct {
__IO u32 RTCCR; ///< RTC clock calibration register, offset: 0x00
__IO u32 CR; ///< BKP control register, offset: 0x04
__IO u32 CSR; ///< BKP control/status register, offset: 0x08
__IO u32 RESERVED0; ///< Reserved, offset: 0x0C
__IO u32 DR1; ///< BKP data register 1, offset: 0x10
__IO u32 DR2; ///< BKP data register 2, offset: 0x14
__IO u32 DR3; ///< BKP data register 3, offset: 0x18
__IO u32 DR4; ///< BKP data register 4, offset: 0x1C
__IO u32 DR5; ///< BKP data register 5, offset: 0x20
__IO u32 DR6; ///< BKP data register 6, offset: 0x24
__IO u32 DR7; ///< BKP data register 7, offset: 0x28
__IO u32 DR8; ///< BKP data register 8, offset: 0x2C
__IO u32 DR9; ///< BKP data register 9, offset: 0x30
__IO u32 DR10; ///< BKP data register 10 offset: 0x34
__IO u32 DR11; ///< BKP data register 11, offset: 0x38
__IO u32 DR12; ///< BKP data register 12, offset: 0x3C
__IO u32 DR13; ///< BKP data register 13, offset: 0x40
__IO u32 DR14; ///< BKP data register 14, offset: 0x44
__IO u32 DR15; ///< BKP data register 15, offset: 0x48
__IO u32 DR16; ///< BKP data register 16, offset: 0x4C
__IO u32 DR17; ///< BKP data register 17, offset: 0x50
__IO u32 DR18; ///< BKP data register 18, offset: 0x54
__IO u32 DR19; ///< BKP data register 19, offset: 0x58
__IO u32 DR20; ///< BKP data register 20, offset: 0x5C
} BKP_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief BKP type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define BKP ((BKP_TypeDef*) BKP_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief BKP_DRn Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define BKP_DR_DATA_Pos (0)
#define BKP_DR_DATA (0xFFFFU << BKP_DR_DATA) ///< Backup data
////////////////////////////////////////////////////////////////////////////////
/// @brief BKP_RTCCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define BKP_RTCCR_CAL_Pos (0)
#define BKP_RTCCR_CAL (0x7FU << BKP_RTCCR_CAL_Pos) ///< Calibration value
#define BKP_RTCCR_CCO_Pos (7)
#define BKP_RTCCR_CCO (0x01U << BKP_RTCCR_CCO_Pos) ///< Calibration Clock Output
#define BKP_RTCCR_ASOE_Pos (8)
#define BKP_RTCCR_ASOE (0x01U << BKP_RTCCR_ASOE_Pos) ///< Alarm or Second Output Enable
#define BKP_RTCCR_ASOS_Pos (9)
#define BKP_RTCCR_ASOS (0x01U << BKP_RTCCR_ASOS_Pos) ///< Alarm or Second Output Selection
////////////////////////////////////////////////////////////////////////////////
/// @brief BKP_CR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define BKP_CR_TPE_Pos (0)
#define BKP_CR_TPE (0x01U << BKP_CR_TPE_Pos) ///< TAMPER pin enable
#define BKP_CR_TPAL_Pos (1)
#define BKP_CR_TPAL (0x01U << BKP_CR_TPAL_Pos) ///< TAMPER pin active level
////////////////////////////////////////////////////////////////////////////////
/// @brief BKP_CSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define BKP_CSR_CTE_Pos (0)
#define BKP_CSR_CTE (0x01U << BKP_CSR_CTE_Pos) ///< Clear Tamper event
#define BKP_CSR_CTI_Pos (1)
#define BKP_CSR_CTI (0x01U << BKP_CSR_CTI_Pos) ///< Clear Tamper Interrupt
#define BKP_CSR_TPIE_Pos (2)
#define BKP_CSR_TPIE (0x01U << BKP_CSR_TPIE_Pos) ///< TAMPER Pin interrupt enable
#define BKP_CSR_TEF_Pos (8)
#define BKP_CSR_TEF (0x01U << BKP_CSR_TEF_Pos) ///< Tamper Event Flag
#define BKP_CSR_TIF_Pos (9)
#define BKP_CSR_TIF (0x01U << BKP_CSR_TIF_Pos) ///< Tamper Interrupt Flag
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_can.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_CAN_H
#define __REG_CAN_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) ///< Base Address: 0x40006400
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN basic
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 CR; ///< Control register, offset: 0x00
__IO u32 CMR; ///< Command register, offset: 0x04
__IO u32 SR; ///< <Status register, offset: 0x08
__IO u32 IR; ///< Interrupt register, offset: 0x0c
__IO u32 ACR; ///< Acceptance Code register, offset: 0x10
__IO u32 AMR; ///< Acceptance Mask register, offset: 0x14
__IO u32 BTR0; ///< Bus Timing register 0, offset: 0x18
__IO u32 BTR1; ///< Bus Timing register 1, offset: 0x1C
__IO u32 RESERVED0;
__IO u32 RESERVED1;
__IO u32 TXID0; ///< Send ID register 0, offset: 0x28
__IO u32 TXID1; ///< Send ID register 1, offset: 0x2c
__IO u32 TXDR0; ///< Send Data register 0, offset: 0x30
__IO u32 TXDR1; ///< Send Data register 1, offset: 0x34
__IO u32 TXDR2; ///< Send Data register 2, offset: 0x38
__IO u32 TXDR3; ///< Send Data register 3, offset: 0x3c
__IO u32 TXDR4; ///< Send Data register 4, offset: 0x40
__IO u32 TXDR5; ///< Send Data register 5, offset: 0x44
__IO u32 TXDR6; ///< Send Data register 6, offset: 0x48
__IO u32 TXDR7; ///< Send Data register 7, offset: 0x4c
__IO u32 RXID0; ///< Mode register, offset: 0x50
__IO u32 RXID1; ///< Mode register, offset: 0x54
__IO u32 RXDR0; ///< Mode register, offset: 0x58
__IO u32 RXDR1; ///< Mode register, offset: 0x5C
__IO u32 RXDR2; ///< Mode register, offset: 0x60
__IO u32 RXDR3; ///< Mode register, offset: 0x64
__IO u32 RXDR4; ///< Mode register, offset: 0x68
__IO u32 RXDR5; ///< Mode register, offset: 0x6c
__IO u32 RXDR6; ///< Mode register, offset: 0x70
__IO u32 RXDR7; ///< Mode register, offset: 0x74
__IO u32 RESERVED2;
__IO u32 CDR; ///< Clock Divider register, offset: 0x7c
} CAN_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN Peli
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 MOD; ///< Mode register, offset: 0x00
__IO u32 CMR; ///< Command register, offset: 0x04
__IO u32 SR; ///< Status register, offset: 0x08
__IO u32 IR; ///< Interrupt Enable register, offset: 0x0c
__IO u32 IER; ///< Mode register, offset: 0x10
__IO u32 RESERVED0;
__IO u32 BTR0; ///< Bus Timing register 0, offset: 0x18
__IO u32 BTR1; ///< Bus Timing register 1, offset: 0x1C
__IO u32 RESERVED1;
__IO u32 RESERVED2;
__IO u32 RESERVED3;
__IO u32 ALC; ///< Arbitration Lost Capture register, offset: 0x2c
__IO u32 ECC; ///< Error Code Capture register, offset: 0x30
__IO u32 EWLR; ///< Error Warning Limit register, offset: 0x34
__IO u32 RXERR; ///< RX Error Counter register, offset: 0x38
__IO u32 TXERR; ///< TX Error Counter register, offset: 0x3c
__IO u32 FF; ///< Frame Format register, offset: 0x40
__IO u32 ID0; ///< ID register 0, offset: 0x44
__IO u32 ID1; ///< ID register 1, offset: 0x48
__IO u32 DATA0; ///< Data register 0, offset: 0x4c
__IO u32 DATA1; ///< Data register 1, offset: 0x50
__IO u32 DATA2; ///< Data register 2, offset: 0x54
__IO u32 DATA3; ///< Data register 3, offset: 0x58
__IO u32 DATA4; ///< Data register 4, offset: 0x5c
__IO u32 DATA5; ///< Data register 5, offset: 0x60
__IO u32 DATA6; ///< Data register 6, offset: 0x64
__IO u32 DATA7; ///< Data register 7, offset: 0x68
__IO u32 DATA8; ///< Data register 8, offset: 0x6c
__IO u32 DATA9; ///< Data register 9, offset: 0x70
__IO u32 RMC; ///< RMC register, offset: 0x74
__IO u32 RBSA; ///< RBSA register, offset: 0x78
__IO u32 CDR; ///< Clock Divider register offset: 0x7c
} CAN_Peli_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN type pointer Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 ACR0;
__IO u32 ACR1;
__IO u32 ACR2;
__IO u32 ACR3;
__IO u32 AMR0;
__IO u32 AMR1;
__IO u32 AMR2;
__IO u32 AMR3;
} CAN_FLT_GROUP;
typedef struct {
CAN_FLT_GROUP GROUP0; //Address offset: 0x40
u32 RESERVED[8]; //Address offset: 0x60
__IO u32 AFM0; //Address offset: 0x80
__IO u32 AFM1; //Address offset: 0x84
__IO u32 AFM2; //Address offset: 0x88
__IO u32 FGA0; //Address offset: 0x8C
__IO u32 FGA1; //Address offset: 0x90
__IO u32 FGA2; //Address offset: 0x94
CAN_FLT_GROUP GROUP1; //Address offset: 0x98
CAN_FLT_GROUP GROUP2; //Address offset: 0xB8
CAN_FLT_GROUP GROUP3; //Address offset: 0xD8
CAN_FLT_GROUP GROUP4; //Address offset: 0xF8
CAN_FLT_GROUP GROUP5; //Address offset: 0x118
CAN_FLT_GROUP GROUP6; //Address offset: 0x138
CAN_FLT_GROUP GROUP7; //Address offset: 0x158
CAN_FLT_GROUP GROUP8; //Address offset: 0x178
CAN_FLT_GROUP GROUP9; //Address offset: 0x198
CAN_FLT_GROUP GROUP10; //Address offset: 0x1B8
CAN_FLT_GROUP GROUP11; //Address offset: 0x1D8
CAN_FLT_GROUP GROUP12; //Address offset: 0x1F8
CAN_FLT_GROUP GROUP13; //Address offset: 0x218
CAN_FLT_GROUP GROUP14; //Address offset: 0x238
CAN_FLT_GROUP GROUP15; //Address offset: 0x258
CAN_FLT_GROUP GROUP16; //Address offset: 0x278
CAN_FLT_GROUP GROUP17; //Address offset: 0x298
CAN_FLT_GROUP GROUP18; //Address offset: 0x2B8
CAN_FLT_GROUP GROUP19; //Address offset: 0x2D8
} CAN_Peli_FLT_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define CAN1 ((CAN_TypeDef*) CAN1_BASE)
#define CAN1_PELI ((CAN_Peli_TypeDef*) CAN1_BASE)
#define CAN_Peli_FLT ((CAN_Peli_FLT_TypeDef*)(CAN1_BASE + 0x40))
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN basic
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_CR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_CR_RR_Pos (0)
#define CAN_CR_RR (0x01U << CAN_CR_RR_Pos) ///< CAN reset request
#define CAN_CR_RIE_Pos (1)
#define CAN_CR_RIE (0x01U << CAN_CR_RIE_Pos) ///< CAN receive interrupt enable
#define CAN_CR_TIE_Pos (2)
#define CAN_CR_TIE (0x01U << CAN_CR_TIE_Pos) ///< CAN transmit interrupt enable
#define CAN_CR_EIE_Pos (3)
#define CAN_CR_EIE (0x01U << CAN_CR_EIE_Pos) ///< CAN error interrupt enable
#define CAN_CR_OIE_Pos (4)
#define CAN_CR_OIE (0x01U << CAN_CR_OIE_Pos) ///< CAN overflow interrupt enable
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_CMR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_CMR_TR_Pos (0)
#define CAN_CMR_TR (0x01U << CAN_CMR_TR_Pos ) ///< CAN transmission request
#define CAN_CMR_AT_Pos (1)
#define CAN_CMR_AT (0x01U << CAN_CMR_AT_Pos ) ///< CAN abort transmission
#define CAN_CMR_RRB_Pos (2)
#define CAN_CMR_RRB (0x01U << CAN_CMR_RRB_Pos) ///< CAN release receive buffer
#define CAN_CMR_CDO_Pos (3)
#define CAN_CMR_CDO (0x01U << CAN_CMR_CDO_Pos) ///< CAN clear data overrun
#define CAN_CMR_GTS_Pos (4)
#define CAN_CMR_GTS (0x01U << CAN_CMR_GTS_Pos) ///< CAN go to sleep
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_SR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_SR_RBS_Pos (0)
#define CAN_SR_RBS (0x01U << CAN_SR_RBS_Pos) ///< CAN receive buffer status
#define CAN_SR_DOS_Pos (1)
#define CAN_SR_DOS (0x01U << CAN_SR_DOS_Pos) ///< CAN data overrun status
#define CAN_SR_TBS_Pos (2)
#define CAN_SR_TBS (0x01U << CAN_SR_TBS_Pos) ///< CAN transmit buffer status
#define CAN_SR_TCS_Pos (3)
#define CAN_SR_TCS (0x01U << CAN_SR_TCS_Pos) ///< CAN transmission complete status
#define CAN_SR_RS_Pos (4)
#define CAN_SR_RS (0x01U << CAN_SR_RS_Pos) ///< CAN receive status
#define CAN_SR_TS_Pos (5)
#define CAN_SR_TS (0x01U << CAN_SR_TS_Pos) ///< CAN transmit status
#define CAN_SR_ES_Pos (6)
#define CAN_SR_ES (0x01U << CAN_SR_ES_Pos) ///< CAN error status
#define CAN_SR_BS_Pos (7)
#define CAN_SR_BS (0x01U << CAN_SR_BS_Pos) ///< CAN bus status
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_ACR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_ACR_AC (0xFFU << 0) ///< CAN acceptance code
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_AMR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_AMR_AM_Pos (0)
#define CAN_AMR_AM (0xFFU << CAN_AMR_AM_Pos) ///< CAN acceptance mask
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_BTR0 register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_BTR0_BRP_Pos (0)
#define CAN_BTR0_BRP (0x003FU << CAN_BTR0_BRP_Pos) ///< CAN baud rate prescaler
#define CAN_BTR0_SJW_Pos (6)
#define CAN_BTR0_SJW (0x03U << CAN_BTR0_SJW_Pos) ///< CAN synchronization jump width
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_BTR1 register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_BTR1_TESG1_Pos (0)
#define CAN_BTR1_TESG1 (0x000FU << CAN_BTR1_TESG1_Pos) ///< CAN Time segment 1
#define CAN_BTR1_TESG2_Pos (4)
#define CAN_BTR1_TESG2 (0x07U << CAN_BTR1_TESG2_Pos) ///< CAN Time segment 2
#define CAN_BTR1_SAM_Pos (7)
#define CAN_BTR1_SAM (0x01U << CAN_BTR1_SAM_Pos) ///< CAN sampling
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_TXID0 register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_TXID0_ID_3_Pos (0)
#define CAN_TXID0_ID_3 (0x01U << CAN_TXID0_ID_3_Pos) ///< CAN identifier byte 3
#define CAN_TXID0_ID_4_Pos (1)
#define CAN_TXID0_ID_4 (0x01U << CAN_TXID0_ID_4_Pos) ///< CAN identifier byte 4
#define CAN_TXID0_ID_5_Pos (2)
#define CAN_TXID0_ID_5 (0x01U << CAN_TXID0_ID_5_Pos) ///< CAN identifier byte 5
#define CAN_TXID0_ID_6_Pos (3)
#define CAN_TXID0_ID_6 (0x01U << CAN_TXID0_ID_6_Pos) ///< CAN identifier byte 6
#define CAN_TXID0_ID_7_Pos (4)
#define CAN_TXID0_ID_7 (0x01U << CAN_TXID0_ID_7_Pos) ///< CAN identifier byte 7
#define CAN_TXID0_ID_8_Pos (5)
#define CAN_TXID0_ID_8 (0x01U << CAN_TXID0_ID_8_Pos) ///< CAN identifier byte 8
#define CAN_TXID0_ID_9_Pos (6)
#define CAN_TXID0_ID_9 (0x01U << CAN_TXID0_ID_9_Pos) ///< CAN identifier byte 9
#define CAN_TXID0_ID_10_Pos (7)
#define CAN_TXID0_ID_10 (0x01U << CAN_TXID0_ID_10_Pos) ///< CAN identifier byte 10
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_TXID1 register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_TXID1_DLC0_Pos (0)
#define CAN_TXID1_DLC0 (0x01U << CAN_TXID1_DLC0_Pos) ///< CAN data length code 0 ~ 8
#define CAN_TXID1_DLC1_Pos (1)
#define CAN_TXID1_DLC1 (0x01U << CAN_TXID1_DLC1_Pos) ///< CAN data length code 0 ~ 8
#define CAN_TXID1_DLC2_Pos (2)
#define CAN_TXID1_DLC2 (0x01U << CAN_TXID1_DLC2_Pos) ///< CAN data length code 0 ~ 8
#define CAN_TXID1_DLC3_Pos (3)
#define CAN_TXID1_DLC3 (0x01U << CAN_TXID1_DLC3_Pos) ///< CAN data length code 0 ~ 8
#define CAN_TXID1_RTR_Pos (4)
#define CAN_TXID1_RTR (0x01U << CAN_TXID1_RTR_Pos ) ///< CAN remote transmission request
#define CAN_TXID1_ID_0_Pos (5)
#define CAN_TXID1_ID_0 (0x01U << CAN_TXID1_ID_0_Pos) ///< CAN identifier byte 0
#define CAN_TXID1_ID_1_Pos (6)
#define CAN_TXID1_ID_1 (0x01U << CAN_TXID1_ID_1_Pos) ///< CAN identifier byte 1
#define CAN_TXID1_ID_2_Pos (7)
#define CAN_TXID1_ID_2 (0x01U << CAN_TXID1_ID_2_Pos) ///< CAN identifier byte 2
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_TXDRn register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_TXDRn (0x00FFU) // (n = 0..7) ///< CAN send data
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_CDR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_CDR_MODE_Pos (7)
#define CAN_CDR_MODE (0x01U << CAN_CDR_MODE_Pos) ///< CAN mode
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN Peli
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_MOD register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_MOD_RM_Pos (0)
#define CAN_MOD_RM (0x01U << CAN_MOD_RM_Pos) ///< CAN reset mode
#define CAN_MOD_LOM_Pos (1)
#define CAN_MOD_LOM (0x01U << CAN_MOD_LOM_Pos) ///< CAN listen only mode
#define CAN_MOD_STM_Pos (2)
#define CAN_MOD_STM (0x01U << CAN_MOD_STM_Pos) ///< CAN self test mode
#define CAN_MOD_AFM_Pos (3)
#define CAN_MOD_AFM (0x01U << CAN_MOD_AFM_Pos) ///< CAN acceptance filter mode
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_CMR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_CMR_TR_Pos (0)
#define CAN_CMR_TR (0x01U << CAN_CMR_TR_Pos ) ///< CAN transmission request
#define CAN_CMR_AT_Pos (1)
#define CAN_CMR_AT (0x01U << CAN_CMR_AT_Pos ) ///< CAN abort transmission
#define CAN_CMR_RRB_Pos (2)
#define CAN_CMR_RRB (0x01U << CAN_CMR_RRB_Pos) ///< CAN release receive buffer
#define CAN_CMR_CDO_Pos (3)
#define CAN_CMR_CDO (0x01U << CAN_CMR_CDO_Pos) ///< CAN clear data overrun
#define CAN_CMR_SRR_Pos (4)
#define CAN_CMR_SRR (0x01U << CAN_CMR_SRR_Pos) ///< CAN self reset request
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_SR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_SR_RBS_Pos (0)
#define CAN_SR_RBS (0x01U << CAN_SR_RBS_Pos) ///< CAN receive buffer status
#define CAN_SR_DOS_Pos (1)
#define CAN_SR_DOS (0x01U << CAN_SR_DOS_Pos) ///< CAN data overrun status
#define CAN_SR_TBS_Pos (2)
#define CAN_SR_TBS (0x01U << CAN_SR_TBS_Pos) ///< CAN transmit buffer status
#define CAN_SR_TCS_Pos (3)
#define CAN_SR_TCS (0x01U << CAN_SR_TCS_Pos) ///< CAN transmission complete status
#define CAN_SR_RS_Pos (4)
#define CAN_SR_RS (0x01U << CAN_SR_RS_Pos) ///< CAN receive status
#define CAN_SR_TS_Pos (5)
#define CAN_SR_TS (0x01U << CAN_SR_TS_Pos) ///< CAN transmit status
#define CAN_SR_ES_Pos (6)
#define CAN_SR_ES (0x01U << CAN_SR_ES_Pos) ///< CAN error status
#define CAN_SR_BS_Pos (7)
#define CAN_SR_BS (0x01U << CAN_SR_BS_Pos) ///< CAN bus status
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_IR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_IR_RI_Pos (0)
#define CAN_IR_RI (0x01U << CAN_IR_RI_Pos) ///< CAN receive interrupt
#define CAN_IR_TI_Pos (1)
#define CAN_IR_TI (0x01U << CAN_IR_TI_Pos) ///< CAN transmit interrupt
#define CAN_IR_EI_Pos (2)
#define CAN_IR_EI (0x01U << CAN_IR_EI_Pos) ///< CAN error interrupt
#define CAN_IR_DOI_Pos (3)
#define CAN_IR_DOI (0x01U << CAN_IR_DOI_Pos) ///< CAN data overrun interrupt
#define CAN_IR_EPI_Pos (5)
#define CAN_IR_EPI (0x01U << CAN_IR_EPI_Pos) ///< CAN error passive interrupt
#define CAN_IR_ALI_Pos (6)
#define CAN_IR_ALI (0x01U << CAN_IR_ALI_Pos) ///< CAN arbitration lost interrupt
#define CAN_IR_BEI_Pos (7)
#define CAN_IR_BEI (0x01U << CAN_IR_BEI_Pos) ///< CAN bus error interrupt
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_IR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_IER_RIE_Pos (0)
#define CAN_IER_RIE (0x01U << CAN_IER_RIE_Pos) ///< CAN receive interrupt enable
#define CAN_IER_TIE_Pos (1)
#define CAN_IER_TIE (0x01U << CAN_IER_TIE_Pos) ///< CAN transmit interrupt enable
#define CAN_IER_EIE_Pos (2)
#define CAN_IER_EIE (0x01U << CAN_IER_EIE_Pos) ///< CAN error interrupt enable
#define CAN_IER_DOIE_Pos (3)
#define CAN_IER_DOIE (0x01U << CAN_IER_DOIE_Pos) ///< CAN data overrun interrupt enable
#define CAN_IER_EPIE_Pos (5)
#define CAN_IER_EPIE (0x01U << CAN_IER_EPI_Pos) ///< CAN error passive interrupt enable
#define CAN_IER_ALIE_Pos (6)
#define CAN_IER_ALIE (0x01U << CAN_IER_ALIE_Pos) ///< CAN arbitration lost interrupt enable
#define CAN_IER_BEIE_Pos (7)
#define CAN_IER_BEIE (0x01U << CAN_IER_BEIE_Pos) ///< CAN bus error interrupt enable
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_ACRn register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_ACRn_AC_Pos (0)
#define CAN_ACRn_AC (0xFFU << CAN_ACRn_AC_Pos) ///< CAN acceptance code
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_AMRn register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_AMRn_AM_Pos (0)
#define CAN_AMRn_AM (0xFFU << CAN_AMRn_AM_Pos) ///< CAN acceptance mask
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_BTR0 register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_BTR0_BRP_Pos (0)
#define CAN_BTR0_BRP (0x003FU << CAN_BTR0_BRP_Pos) ///< CAN baud rate prescaler
#define CAN_BTR0_SJW_Pos (6)
#define CAN_BTR0_SJW (0x03U << CAN_BTR0_SJW_Pos) ///< CAN synchronization jump width
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_ALC register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_ALC_BITNO_Pos (0)
#define CAN_ALC_BITNO (0x001FU << CAN_ALC_BITNO_Pos) ///< CAN bit number
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_ECC register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_ECC_SEG_Pos (0)
#define CAN_ECC_SEG (0x001FU <<CAN_ECC_SEG_Pos) ///< CAN error code capture
#define CAN_ECC_DIR_Pos (5)
#define CAN_ECC_DIR (0x01U << CAN_ECC_DIR_Pos) ///< CAN direction
#define CAN_ECC_ERRC_Pos (6)
#define CAN_ECC_ERRC (0x03U << CAN_ECC_ERRC_Pos) ///< CAN error code
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_EWLR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_EWLR_EWL_Pos (0)
#define CAN_EWLR_EWL (0x00FFU << CAN_EWLR_EWL_Pos) ///< CAN programmable error warning limit
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_RXERR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_RXERR_RXERR_Pos (0)
#define CAN_RXERR_RXERR (0x00FFU << CAN_RXERR_RXERR_Pos) ///< CAN RX error counter register
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_TXERR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_TXERR_TXERR_Pos (0)
#define CAN_TXERR_TXERR (0x00FFU << CAN_TXERR_TXERR_Pos) ///< CAN TX error counter register
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_FF register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_FF_DLC_0_Pos (0)
#define CAN_FF_DLC_0 (0x01U << CAN_FF_DLC_0_Pos) ///< CAN data length code bit
#define CAN_FF_DLC_1_Pos (1)
#define CAN_FF_DLC_1 (0x01U << CAN_FF_DLC_1_Pos) ///< CAN data length code bit
#define CAN_FF_DLC_2_Pos (2)
#define CAN_FF_DLC_2 (0x01U << CAN_FF_DLC_2_Pos) ///< CAN data length code bit
#define CAN_FF_DLC_3_Pos (3)
#define CAN_FF_DLC_3 (0x01U << CAN_FF_DLC_3_Pos) ///< CAN data length code bit
#define CAN_FF_RTR_Pos (6)
#define CAN_FF_RTR (0x01U << CAN_FF_RTR_Pos) ///< CAN remote transmission request
#define CAN_FF_FF_Pos (7)
#define CAN_FF_FF (0x01U << CAN_FF_FF_Pos) ///< CAN frame format
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_TXID0 register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_TXID0_ID_21_Pos (0)
#define CAN_TXID0_ID_21 (0x01U << CAN_TXID0_ID_21_Pos) ///< CAN identifier bit 21
#define CAN_TXID0_ID_22_Pos (1)
#define CAN_TXID0_ID_22 (0x01U << CAN_TXID0_ID_22_Pos) ///< CAN identifier bit 22
#define CAN_TXID0_ID_23_Pos (2)
#define CAN_TXID0_ID_23 (0x01U << CAN_TXID0_ID_23_Pos) ///< CAN identifier bit 23
#define CAN_TXID0_ID_24_Pos (3)
#define CAN_TXID0_ID_24 (0x01U << CAN_TXID0_ID_24_Pos) ///< CAN identifier bit 24
#define CAN_TXID0_ID_25_Pos (4)
#define CAN_TXID0_ID_25 (0x01U << CAN_TXID0_ID_25_Pos) ///< CAN identifier bit 25
#define CAN_TXID0_ID_26_Pos (5)
#define CAN_TXID0_ID_26 (0x01U << CAN_TXID0_ID_26_Pos) ///< CAN identifier bit 26
#define CAN_TXID0_ID_27_Pos (6)
#define CAN_TXID0_ID_27 (0x01U << CAN_TXID0_ID_27_Pos) ///< CAN identifier bit 27
#define CAN_TXID0_ID_28_Pos (7)
#define CAN_TXID0_ID_28 (0x01U << CAN_TXID0_ID_28_Pos) ///< CAN identifier bit 28
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_TXID1 register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_TXID1_ID_13_Pos (0)
#define CAN_TXID1_ID_13 (0x01U << CAN_TXID1_ID_13_Pos) ///< CAN identifier bit 13
#define CAN_TXID1_ID_14_Pos (1)
#define CAN_TXID1_ID_14 (0x01U << CAN_TXID1_ID_14_Pos) ///< CAN identifier bit 14
#define CAN_TXID1_ID_15_Pos (2)
#define CAN_TXID1_ID_15 (0x01U << CAN_TXID1_ID_15_Pos) ///< CAN identifier bit 15
#define CAN_TXID1_ID_16_Pos (3)
#define CAN_TXID1_ID_16 (0x01U << CAN_TXID1_ID_16_Pos) ///< CAN identifier bit 16
#define CAN_TXID1_ID_17_Pos (4)
#define CAN_TXID1_ID_17 (0x01U << CAN_TXID1_ID_17_Pos) ///< CAN identifier bit 17
#define CAN_TXID1_ID_18_Pos (5)
#define CAN_TXID1_ID_18 (0x01U << CAN_TXID1_ID_18_Pos) ///< CAN identifier bit 18
#define CAN_TXID1_ID_19_Pos (6)
#define CAN_TXID1_ID_19 (0x01U << CAN_TXID1_ID_19_Pos) ///< CAN identifier bit 19
#define CAN_TXID1_ID_20_Pos (7)
#define CAN_TXID1_ID_20 (0x01U << CAN_TXID1_ID_20_Pos) ///< CAN identifier bit 20
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_TXDATAn register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_TXDATAn_Pos (0)
#define CAN_TXDATAn (0x00FFU << CAN_TXDATAn_Pos) ///< CAN transmit data n
////////////////////////////////////////////////////////////////////////////////
/// @brief CAN_CDR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define CAN_CDR_MODE_Pos (7)
#define CAN_CDR_MODE (0x01U << CAN_CDR_MODE_Pos) ///< CAN mode
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_common.h
+643
View File
@@ -0,0 +1,643 @@
////////////////////////////////////////////////////////////////////////////////
/// @file reg_common.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_COMMON_H
#define __REG_COMMON_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
#ifndef HSE_STARTUP_TIMEOUT
#define HSE_STARTUP_TIMEOUT (0x0500U) ///< Time out for HSE start up.
#endif
#ifdef CUSTOM_HSE_VAL
#ifndef HSE_VALUE
#define HSE_VALUE (12000000U) ///< Value of the External oscillator in Hz.
#endif
#else
#ifndef HSE_VALUE
#define HSE_VALUE (8000000U) ///< Value of the External oscillator in Hz.
#endif
#endif
#define HSI_VALUE_PLL_ON (8000000U) ///< Value of the Internal oscillator in Hz.
#define HSI_DIV6 (8000000U) ///< Value of the Internal oscillator in Hz.
// Value of the Internal oscillator in Hz.
#define LSI_VALUE (40000U) ///< Value of the Internal oscillator in Hz.
#ifndef HSI_VALUE
#define HSI_VALUE (8000000U) ///< Value of the Internal oscillator in Hz.
#endif
#define __MPU_PRESENT (0) ///< Cortex-M3 does not provide a MPU present or not
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS (4) ///< Cortex-M3 uses 4 Bits for the Priority Levels
//#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#define __Vendor_SysTickConfig (0) ///< Set to 1 if different SysTick Config is used
////////////////////////////////////////////////////////////////////////////////
/// @brief MM32 MCU Interrupt Handle
////////////////////////////////////////////////////////////////////////////////
typedef enum IRQn {
NonMaskableInt_IRQn = -14, ///< 2 Non Maskable Interrupt
MemoryManagement_IRQn = -12, ///< 4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn = -11, ///< 5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn = -10, ///< 6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn = -5, ///< 11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn = -4, ///< 12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn = -2, ///< 14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn = -1, ///< 15 Cortex-M3 System Tick Interrupt
WWDG_IWDG_IRQn = 0, ///< Watchdog interrupt
WWDG_IRQn = 0, ///< Watchdog interrupt
PVD_IRQn = 1, ///< (PVD) Interrupt
TAMPER_IRQn = 2, ///< Intrusion detection interrupted
RTC_IRQn = 3, ///< Real-time clock (RTC) global interrupt
FLASH_IRQn = 4, ///< Flash global interrupt
RCC_CRS_IRQn = 5, ///< RCC and CRS global interrupt
EXTI0_IRQn = 6, ///< EXTI line 0 interrupt
EXTI1_IRQn = 7, ///< EXTI line 1 interrupt
EXTI2_IRQn = 8, ///< EXTI line 2 interrupt
EXTI3_IRQn = 9, ///< EXTI line 3 interrupted
EXTI4_IRQn = 10, ///< EXTI line 4 interrupt
DMA1_Channel1_IRQn = 11, ///< DMA1 channel 1 global interrupt
DMA1_Channel2_IRQn = 12, ///< DMA1 channel 2 global interrupt
DMA1_Channel3_IRQn = 13, ///< DMA1 channel 3 global interrupt
DMA1_Channel4_IRQn = 14, ///< DMA1 channel 4 global interrupt
DMA1_Channel5_IRQn = 15, ///< DMA1 channel 5 global interrupt
DMA1_Channel6_IRQn = 16, ///< DMA1 channel 6 global interrupt
DMA1_Channel7_IRQn = 17, ///< DMA1 channel 7 global interrupt
ADC1_IRQn = 18, ///< ADC1 global interrupt
ADC1_2_IRQn = 18, ///< ADC1&ADC2 global interrupt
ADC2_IRQn = 18, ///< ADC2 global interrupt
FlashCache_IRQn = 19, ///< FlashCache outage
CAN1_RX_IRQn = 21, ///< CAN1 receive interrupt
CAN_IRQn = 21, ///< CAN interrupt
EXTI9_5_IRQn = 23, ///< EXTI line [9: 5] interrupted
TIM1_BRK_IRQn = 24, ///< TIM1 disconnect interrupt
TIM1_UP_IRQn = 25, ///< TIM1 update interrupt
IM1_TRG_COM_IRQn = 26, ///< TIM1 trigger and communication interrupt
TIM1_CC_IRQn = 27, ///< TIM1 capture compare interrupt
TIM2_IRQn = 28, ///< TIM2 global interrupt
TIM3_IRQn = 29, ///< TIM3 global interrupt
TIM4_IRQn = 30, ///< TIM4 global interrupt
I2C1_IRQn = 31, ///< I2C1 global interrupt
I2C2_IRQn = 33, ///< I2C2 global interrupt
SPI1_IRQn = 35, ///< SPI1 global interrupt
SPI2_IRQn = 36, ///< SPI2 global interrupt
UART1_IRQn = 37, ///< UART1 global interrupt
UART2_IRQn = 38, ///< UART2 global interrupt
UART3_IRQn = 39, ///< UART3 global interrupt
EXTI15_10_IRQn = 40, ///< EXTI line [15: 10] interrupted
RTCAlarm_IRQn = 41, ///< RTC alarm connected to EXTI interrupted
USB_WKUP_IRQn = 42, ///< Wake-up interrupt from USB connected to EXTI
TIM8_BRK_IRQn = 43, ///< TIM8 brake interruption
TIM8_UP_IRQn = 44, ///< TIM8 update interrupt
TIM8_TRG_COM_IRQn = 45, ///< TIM8 trigger, communication interrupt
TIM8_CC_IRQn = 46, ///< TIM8 capture compare interrupt
ADC3_IRQn = 47, ///< ADC3 global interrupt
SDIO_IRQn = 49, ///< SDIO global interrupt
TIM5_IRQn = 50, ///< TIM5 global interrupt
SPI3_IRQn = 51, ///< SPI3 global interrupt
UART4_IRQn = 52, ///< UART4 global interrupt
UART5_IRQn = 53, ///< UART5 global interrupt
TIM6_IRQn = 54, ///< TIM6 global interrupt
TIM7_IRQn = 55, ///< TIM7 global interrupt
DMA2_Channel1_IRQn = 56, ///< DMA2 channel 1 global interrupt
DMA2_Channel2_IRQn = 57, ///< DMA2 channel 2 global interrupt
DMA2_Channel3_IRQn = 58, ///< DMA2 channel 3 global interrupt
DMA2_Channel4_IRQn = 59, ///< DMA2 channel 4 global interrupt
DMA2_Channel5_IRQn = 60, ///< DMA2 channel 5 global interrupt
ETHERNET_MAC_IRQn = 61, ///< ETHERNET global interrupt
COMP1_2_IRQn = 64, ///< Comparator 1/2 interrupt connected to EXTI
USB_FS_IRQn = 67, ///< USB FS global interrupt
UART6_IRQn = 71, ///< UART6 global interrupt
UART7_IRQn = 82, ///< UART7 global interrupt
UART8_IRQn = 83, ///< UART8 global interrupt
} IRQn_Type;
#include <core_cm3.h>
#define PERIPH_BASE (0x40000000U) ///< Peripheral base address in the alias region
#define EEPROM_BASE (0x08100000U) ///< EEPROM base address in the alias region
#define SRAM_BITBAND_BASE (0x22000000U) ///< Peripheral base address in the bit-band region
#define PERIPH_BITBAND_BASE (0x42000000U) ///< SRAM base address in the bit-band region
#define APB1PERIPH_BASE (PERIPH_BASE + 0x00000000)
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
#define AHB3PERIPH_BASE (PERIPH_BASE + 0x20000000)
////////////////////////////////////////////////////////////////////////////////
/// @brief UID type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define UID_BASE (0x1FFFF7E0U) ///< Unique device ID register base address
///////////////////////////////////////////////////////////////////////////////
/// @brief Nested Vectored Interrupt Controller
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// @brief NVIC_ISER Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define NVIC_ISER_SETENA (0xFFFFFFFFU) ///< Interrupt set enable bits
#define NVIC_ISER_SETENA_0 (0x00000001U) ///< bit 0
#define NVIC_ISER_SETENA_1 (0x00000002U) ///< bit 1
#define NVIC_ISER_SETENA_2 (0x00000004U) ///< bit 2
#define NVIC_ISER_SETENA_3 (0x00000008U) ///< bit 3
#define NVIC_ISER_SETENA_4 (0x00000010U) ///< bit 4
#define NVIC_ISER_SETENA_5 (0x00000020U) ///< bit 5
#define NVIC_ISER_SETENA_6 (0x00000040U) ///< bit 6
#define NVIC_ISER_SETENA_7 (0x00000080U) ///< bit 7
#define NVIC_ISER_SETENA_8 (0x00000100U) ///< bit 8
#define NVIC_ISER_SETENA_9 (0x00000200U) ///< bit 9
#define NVIC_ISER_SETENA_10 (0x00000400U) ///< bit 10
#define NVIC_ISER_SETENA_11 (0x00000800U) ///< bit 11
#define NVIC_ISER_SETENA_12 (0x00001000U) ///< bit 12
#define NVIC_ISER_SETENA_13 (0x00002000U) ///< bit 13
#define NVIC_ISER_SETENA_14 (0x00004000U) ///< bit 14
#define NVIC_ISER_SETENA_15 (0x00008000U) ///< bit 15
#define NVIC_ISER_SETENA_16 (0x00010000U) ///< bit 16
#define NVIC_ISER_SETENA_17 (0x00020000U) ///< bit 17
#define NVIC_ISER_SETENA_18 (0x00040000U) ///< bit 18
#define NVIC_ISER_SETENA_19 (0x00080000U) ///< bit 19
#define NVIC_ISER_SETENA_20 (0x00100000U) ///< bit 20
#define NVIC_ISER_SETENA_21 (0x00200000U) ///< bit 21
#define NVIC_ISER_SETENA_22 (0x00400000U) ///< bit 22
#define NVIC_ISER_SETENA_23 (0x00800000U) ///< bit 23
#define NVIC_ISER_SETENA_24 (0x01000000U) ///< bit 24
#define NVIC_ISER_SETENA_25 (0x02000000U) ///< bit 25
#define NVIC_ISER_SETENA_26 (0x04000000U) ///< bit 26
#define NVIC_ISER_SETENA_27 (0x08000000U) ///< bit 27
#define NVIC_ISER_SETENA_28 (0x10000000U) ///< bit 28
#define NVIC_ISER_SETENA_29 (0x20000000U) ///< bit 29
#define NVIC_ISER_SETENA_30 (0x40000000U) ///< bit 30
#define NVIC_ISER_SETENA_31 (0x80000000U) ///< bit 31
////////////////////////////////////////////////////////////////////////////////
/// @brief NVIC_ICER Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define NVIC_ICER_CLRENA (0xFFFFFFFFU) ///< Interrupt clear-enable bits
#define NVIC_ICER_CLRENA_0 (0x00000001U) ///< bit 0
#define NVIC_ICER_CLRENA_1 (0x00000002U) ///< bit 1
#define NVIC_ICER_CLRENA_2 (0x00000004U) ///< bit 2
#define NVIC_ICER_CLRENA_3 (0x00000008U) ///< bit 3
#define NVIC_ICER_CLRENA_4 (0x00000010U) ///< bit 4
#define NVIC_ICER_CLRENA_5 (0x00000020U) ///< bit 5
#define NVIC_ICER_CLRENA_6 (0x00000040U) ///< bit 6
#define NVIC_ICER_CLRENA_7 (0x00000080U) ///< bit 7
#define NVIC_ICER_CLRENA_8 (0x00000100U) ///< bit 8
#define NVIC_ICER_CLRENA_9 (0x00000200U) ///< bit 9
#define NVIC_ICER_CLRENA_10 (0x00000400U) ///< bit 10
#define NVIC_ICER_CLRENA_11 (0x00000800U) ///< bit 11
#define NVIC_ICER_CLRENA_12 (0x00001000U) ///< bit 12
#define NVIC_ICER_CLRENA_13 (0x00002000U) ///< bit 13
#define NVIC_ICER_CLRENA_14 (0x00004000U) ///< bit 14
#define NVIC_ICER_CLRENA_15 (0x00008000U) ///< bit 15
#define NVIC_ICER_CLRENA_16 (0x00010000U) ///< bit 16
#define NVIC_ICER_CLRENA_17 (0x00020000U) ///< bit 17
#define NVIC_ICER_CLRENA_18 (0x00040000U) ///< bit 18
#define NVIC_ICER_CLRENA_19 (0x00080000U) ///< bit 19
#define NVIC_ICER_CLRENA_20 (0x00100000U) ///< bit 20
#define NVIC_ICER_CLRENA_21 (0x00200000U) ///< bit 21
#define NVIC_ICER_CLRENA_22 (0x00400000U) ///< bit 22
#define NVIC_ICER_CLRENA_23 (0x00800000U) ///< bit 23
#define NVIC_ICER_CLRENA_24 (0x01000000U) ///< bit 24
#define NVIC_ICER_CLRENA_25 (0x02000000U) ///< bit 25
#define NVIC_ICER_CLRENA_26 (0x04000000U) ///< bit 26
#define NVIC_ICER_CLRENA_27 (0x08000000U) ///< bit 27
#define NVIC_ICER_CLRENA_28 (0x10000000U) ///< bit 28
#define NVIC_ICER_CLRENA_29 (0x20000000U) ///< bit 29
#define NVIC_ICER_CLRENA_30 (0x40000000U) ///< bit 30
#define NVIC_ICER_CLRENA_31 (0x80000000U) ///< bit 31
////////////////////////////////////////////////////////////////////////////////
/// @brief NVIC_ISPR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define NVIC_ISPR_SETPEND (0xFFFFFFFFU) ///< Interrupt set-pending bits
#define NVIC_ISPR_SETPEND_0 (0x00000001U) ///< bit 0
#define NVIC_ISPR_SETPEND_1 (0x00000002U) ///< bit 1
#define NVIC_ISPR_SETPEND_2 (0x00000004U) ///< bit 2
#define NVIC_ISPR_SETPEND_3 (0x00000008U) ///< bit 3
#define NVIC_ISPR_SETPEND_4 (0x00000010U) ///< bit 4
#define NVIC_ISPR_SETPEND_5 (0x00000020U) ///< bit 5
#define NVIC_ISPR_SETPEND_6 (0x00000040U) ///< bit 6
#define NVIC_ISPR_SETPEND_7 (0x00000080U) ///< bit 7
#define NVIC_ISPR_SETPEND_8 (0x00000100U) ///< bit 8
#define NVIC_ISPR_SETPEND_9 (0x00000200U) ///< bit 9
#define NVIC_ISPR_SETPEND_10 (0x00000400U) ///< bit 10
#define NVIC_ISPR_SETPEND_11 (0x00000800U) ///< bit 11
#define NVIC_ISPR_SETPEND_12 (0x00001000U) ///< bit 12
#define NVIC_ISPR_SETPEND_13 (0x00002000U) ///< bit 13
#define NVIC_ISPR_SETPEND_14 (0x00004000U) ///< bit 14
#define NVIC_ISPR_SETPEND_15 (0x00008000U) ///< bit 15
#define NVIC_ISPR_SETPEND_16 (0x00010000U) ///< bit 16
#define NVIC_ISPR_SETPEND_17 (0x00020000U) ///< bit 17
#define NVIC_ISPR_SETPEND_18 (0x00040000U) ///< bit 18
#define NVIC_ISPR_SETPEND_19 (0x00080000U) ///< bit 19
#define NVIC_ISPR_SETPEND_20 (0x00100000U) ///< bit 20
#define NVIC_ISPR_SETPEND_21 (0x00200000U) ///< bit 21
#define NVIC_ISPR_SETPEND_22 (0x00400000U) ///< bit 22
#define NVIC_ISPR_SETPEND_23 (0x00800000U) ///< bit 23
#define NVIC_ISPR_SETPEND_24 (0x01000000U) ///< bit 24
#define NVIC_ISPR_SETPEND_25 (0x02000000U) ///< bit 25
#define NVIC_ISPR_SETPEND_26 (0x04000000U) ///< bit 26
#define NVIC_ISPR_SETPEND_27 (0x08000000U) ///< bit 27
#define NVIC_ISPR_SETPEND_28 (0x10000000U) ///< bit 28
#define NVIC_ISPR_SETPEND_29 (0x20000000U) ///< bit 29
#define NVIC_ISPR_SETPEND_30 (0x40000000U) ///< bit 30
#define NVIC_ISPR_SETPEND_31 (0x80000000U) ///< bit 31
////////////////////////////////////////////////////////////////////////////////
/// @brief NVIC_ICPR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define NVIC_ICPR_CLRPEND (0xFFFFFFFFU) ///< Interrupt clear-pending bits
#define NVIC_ICPR_CLRPEND_0 (0x00000001U) ///< bit 0
#define NVIC_ICPR_CLRPEND_1 (0x00000002U) ///< bit 1
#define NVIC_ICPR_CLRPEND_2 (0x00000004U) ///< bit 2
#define NVIC_ICPR_CLRPEND_3 (0x00000008U) ///< bit 3
#define NVIC_ICPR_CLRPEND_4 (0x00000010U) ///< bit 4
#define NVIC_ICPR_CLRPEND_5 (0x00000020U) ///< bit 5
#define NVIC_ICPR_CLRPEND_6 (0x00000040U) ///< bit 6
#define NVIC_ICPR_CLRPEND_7 (0x00000080U) ///< bit 7
#define NVIC_ICPR_CLRPEND_8 (0x00000100U) ///< bit 8
#define NVIC_ICPR_CLRPEND_9 (0x00000200U) ///< bit 9
#define NVIC_ICPR_CLRPEND_10 (0x00000400U) ///< bit 10
#define NVIC_ICPR_CLRPEND_11 (0x00000800U) ///< bit 11
#define NVIC_ICPR_CLRPEND_12 (0x00001000U) ///< bit 12
#define NVIC_ICPR_CLRPEND_13 (0x00002000U) ///< bit 13
#define NVIC_ICPR_CLRPEND_14 (0x00004000U) ///< bit 14
#define NVIC_ICPR_CLRPEND_15 (0x00008000U) ///< bit 15
#define NVIC_ICPR_CLRPEND_16 (0x00010000U) ///< bit 16
#define NVIC_ICPR_CLRPEND_17 (0x00020000U) ///< bit 17
#define NVIC_ICPR_CLRPEND_18 (0x00040000U) ///< bit 18
#define NVIC_ICPR_CLRPEND_19 (0x00080000U) ///< bit 19
#define NVIC_ICPR_CLRPEND_20 (0x00100000U) ///< bit 20
#define NVIC_ICPR_CLRPEND_21 (0x00200000U) ///< bit 21
#define NVIC_ICPR_CLRPEND_22 (0x00400000U) ///< bit 22
#define NVIC_ICPR_CLRPEND_23 (0x00800000U) ///< bit 23
#define NVIC_ICPR_CLRPEND_24 (0x01000000U) ///< bit 24
#define NVIC_ICPR_CLRPEND_25 (0x02000000U) ///< bit 25
#define NVIC_ICPR_CLRPEND_26 (0x04000000U) ///< bit 26
#define NVIC_ICPR_CLRPEND_27 (0x08000000U) ///< bit 27
#define NVIC_ICPR_CLRPEND_28 (0x10000000U) ///< bit 28
#define NVIC_ICPR_CLRPEND_29 (0x20000000U) ///< bit 29
#define NVIC_ICPR_CLRPEND_30 (0x40000000U) ///< bit 30
#define NVIC_ICPR_CLRPEND_31 (0x80000000U) ///< bit 31
////////////////////////////////////////////////////////////////////////////////
/// @brief NVIC_IABR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define NVIC_IABR_ACTIVE (0xFFFFFFFFU) ///< Interrupt active flags
#define NVIC_IABR_ACTIVE_0 (0x00000001U) ///< bit 0
#define NVIC_IABR_ACTIVE_1 (0x00000002U) ///< bit 1
#define NVIC_IABR_ACTIVE_2 (0x00000004U) ///< bit 2
#define NVIC_IABR_ACTIVE_3 (0x00000008U) ///< bit 3
#define NVIC_IABR_ACTIVE_4 (0x00000010U) ///< bit 4
#define NVIC_IABR_ACTIVE_5 (0x00000020U) ///< bit 5
#define NVIC_IABR_ACTIVE_6 (0x00000040U) ///< bit 6
#define NVIC_IABR_ACTIVE_7 (0x00000080U) ///< bit 7
#define NVIC_IABR_ACTIVE_8 (0x00000100U) ///< bit 8
#define NVIC_IABR_ACTIVE_9 (0x00000200U) ///< bit 9
#define NVIC_IABR_ACTIVE_10 (0x00000400U) ///< bit 10
#define NVIC_IABR_ACTIVE_11 (0x00000800U) ///< bit 11
#define NVIC_IABR_ACTIVE_12 (0x00001000U) ///< bit 12
#define NVIC_IABR_ACTIVE_13 (0x00002000U) ///< bit 13
#define NVIC_IABR_ACTIVE_14 (0x00004000U) ///< bit 14
#define NVIC_IABR_ACTIVE_15 (0x00008000U) ///< bit 15
#define NVIC_IABR_ACTIVE_16 (0x00010000U) ///< bit 16
#define NVIC_IABR_ACTIVE_17 (0x00020000U) ///< bit 17
#define NVIC_IABR_ACTIVE_18 (0x00040000U) ///< bit 18
#define NVIC_IABR_ACTIVE_19 (0x00080000U) ///< bit 19
#define NVIC_IABR_ACTIVE_20 (0x00100000U) ///< bit 20
#define NVIC_IABR_ACTIVE_21 (0x00200000U) ///< bit 21
#define NVIC_IABR_ACTIVE_22 (0x00400000U) ///< bit 22
#define NVIC_IABR_ACTIVE_23 (0x00800000U) ///< bit 23
#define NVIC_IABR_ACTIVE_24 (0x01000000U) ///< bit 24
#define NVIC_IABR_ACTIVE_25 (0x02000000U) ///< bit 25
#define NVIC_IABR_ACTIVE_26 (0x04000000U) ///< bit 26
#define NVIC_IABR_ACTIVE_27 (0x08000000U) ///< bit 27
#define NVIC_IABR_ACTIVE_28 (0x10000000U) ///< bit 28
#define NVIC_IABR_ACTIVE_29 (0x20000000U) ///< bit 29
#define NVIC_IABR_ACTIVE_30 (0x40000000U) ///< bit 30
#define NVIC_IABR_ACTIVE_31 (0x80000000U) ///< bit 31
////////////////////////////////////////////////////////////////////////////////
/// @brief NVIC_PRI0 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define NVIC_IPR0_PRI_0 (0x000000FFU) ///< Priority of interrupt 0
#define NVIC_IPR0_PRI_1 (0x0000FF00U) ///< Priority of interrupt 1
#define NVIC_IPR0_PRI_2 (0x00FF0000U) ///< Priority of interrupt 2
#define NVIC_IPR0_PRI_3 (0xFF000000U) ///< Priority of interrupt 3
////////////////////////////////////////////////////////////////////////////////
/// @brief NVIC_PRI1 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define NVIC_IPR1_PRI_4 (0x000000FFU) ///< Priority of interrupt 4
#define NVIC_IPR1_PRI_5 (0x0000FF00U) ///< Priority of interrupt 5
#define NVIC_IPR1_PRI_6 (0x00FF0000U) ///< Priority of interrupt 6
#define NVIC_IPR1_PRI_7 (0xFF000000U) ///< Priority of interrupt 7
////////////////////////////////////////////////////////////////////////////////
/// @brief NVIC_PRI2 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define NVIC_IPR2_PRI_8 (0x000000FFU) ///< Priority of interrupt 8
#define NVIC_IPR2_PRI_9 (0x0000FF00U) ///< Priority of interrupt 9
#define NVIC_IPR2_PRI_10 (0x00FF0000U) ///< Priority of interrupt 10
#define NVIC_IPR2_PRI_11 (0xFF000000U) ///< Priority of interrupt 11
////////////////////////////////////////////////////////////////////////////////
/// @brief NVIC_PRI3 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define NVIC_IPR3_PRI_12 (0x000000FFU) ///< Priority of interrupt 12
#define NVIC_IPR3_PRI_13 (0x0000FF00U) ///< Priority of interrupt 13
#define NVIC_IPR3_PRI_14 (0x00FF0000U) ///< Priority of interrupt 14
#define NVIC_IPR3_PRI_15 (0xFF000000U) ///< Priority of interrupt 15
////////////////////////////////////////////////////////////////////////////////
/// @brief NVIC_PRI4 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define NVIC_IPR4_PRI_16 (0x000000FFU) ///< Priority of interrupt 16
#define NVIC_IPR4_PRI_17 (0x0000FF00U) ///< Priority of interrupt 17
#define NVIC_IPR4_PRI_18 (0x00FF0000U) ///< Priority of interrupt 18
#define NVIC_IPR4_PRI_19 (0xFF000000U) ///< Priority of interrupt 19
////////////////////////////////////////////////////////////////////////////////
/// @brief NVIC_PRI5 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define NVIC_IPR5_PRI_20 (0x000000FFU) ///< Priority of interrupt 20
#define NVIC_IPR5_PRI_21 (0x0000FF00U) ///< Priority of interrupt 21
#define NVIC_IPR5_PRI_22 (0x00FF0000U) ///< Priority of interrupt 22
#define NVIC_IPR5_PRI_23 (0xFF000000U) ///< Priority of interrupt 23
////////////////////////////////////////////////////////////////////////////////
/// @brief NVIC_PRI6 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define NVIC_IPR6_PRI_24 (0x000000FFU) ///< Priority of interrupt 24
#define NVIC_IPR6_PRI_25 (0x0000FF00U) ///< Priority of interrupt 25
#define NVIC_IPR6_PRI_26 (0x00FF0000U) ///< Priority of interrupt 26
#define NVIC_IPR6_PRI_27 (0xFF000000U) ///< Priority of interrupt 27
////////////////////////////////////////////////////////////////////////////////
/// @brief NVIC_PRI7 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define NVIC_IPR7_PRI_28 (0x000000FFU) ///< Priority of interrupt 28
#define NVIC_IPR7_PRI_29 (0x0000FF00U) ///< Priority of interrupt 29
#define NVIC_IPR7_PRI_30 (0x00FF0000U) ///< Priority of interrupt 30
#define NVIC_IPR7_PRI_31 (0xFF000000U) ///< Priority of interrupt 31
////////////////////////////////////////////////////////////////////////////////
/// @brief NVIC_PRI8 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define NVIC_IPR7_PRI_32 (0x000000FFU) ///< Priority of interrupt 32
#define NVIC_IPR7_PRI_33 (0x0000FF00U) ///< Priority of interrupt 33
#define NVIC_IPR7_PRI_34 (0x00FF0000U) ///< Priority of interrupt 34
#define NVIC_IPR7_PRI_35 (0xFF000000U) ///< Priority of interrupt 35
////////////////////////////////////////////////////////////////////////////////
/// @brief NVIC_PRI9 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define NVIC_IPR7_PRI_36 (0x000000FFU) ///< Priority of interrupt 36
#define NVIC_IPR7_PRI_37 (0x0000FF00U) ///< Priority of interrupt 37
#define NVIC_IPR7_PRI_38 (0x00FF0000U) ///< Priority of interrupt 38
#define NVIC_IPR7_PRI_39 (0xFF000000U) ///< Priority of interrupt 39
////////////////////////////////////////////////////////////////////////////////
/// @brief NVIC_PRI10 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define NVIC_IPR7_PRI_40 (0x000000FFU) ///< Priority of interrupt 40
#define NVIC_IPR7_PRI_41 (0x0000FF00U) ///< Priority of interrupt 41
#define NVIC_IPR7_PRI_42 (0x00FF0000U) ///< Priority of interrupt 42
#define NVIC_IPR7_PRI_43 (0xFF000000U) ///< Priority of interrupt 43
////////////////////////////////////////////////////////////////////////////////
/// @brief NVIC_PRI11 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define NVIC_IPR7_PRI_44 (0x000000FFU) ///< Priority of interrupt 44
#define NVIC_IPR7_PRI_45 (0x0000FF00U) ///< Priority of interrupt 45
#define NVIC_IPR7_PRI_46 (0x00FF0000U) ///< Priority of interrupt 46
#define NVIC_IPR7_PRI_47 (0xFF000000U) ///< Priority of interrupt 47
////////////////////////////////////////////////////////////////////////////////
/// @brief SCB_CPUID Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SCB_CPUID_REVISION (0x0000000FU) ///< Implementation defined revision number
#define SCB_CPUID_PARTNO (0x0000FFF0U) ///< Number of processor within family
#define SCB_CPUID_Constant (0x000F0000U) ///< Reads as 0x0F
#define SCB_CPUID_VARIANT (0x00F00000U) ///< Implementation defined variant number
#define SCB_CPUID_IMPLEMENTER (0xFF000000U) ///< Implementer code. ARM is 0x41
////////////////////////////////////////////////////////////////////////////////
/// @brief SCB_ICSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SCB_ICSR_VECTACTIVE (0x000001FFU) ///< Active ISR number field
#define SCB_ICSR_RETTOBASE (0x00000800U) ///< All active exceptions minus the IPSR_current_exception yields the empty set
#define SCB_ICSR_VECTPENDING (0x003FF000U) ///< Pending ISR number field
#define SCB_ICSR_ISRPENDING (0x00400000U) ///< Interrupt pending flag
#define SCB_ICSR_ISRPREEMPT (0x00800000U) ///< It indicates that a pending interrupt becomes active in the next running cycle
#define SCB_ICSR_PENDSTCLR (0x02000000U) ///< Clear pending SysTick bit
#define SCB_ICSR_PENDSTSET (0x04000000U) ///< Set pending SysTick bit
#define SCB_ICSR_PENDSVCLR (0x08000000U) ///< Clear pending pendSV bit
#define SCB_ICSR_PENDSVSET (0x10000000U) ///< Set pending pendSV bit
#define SCB_ICSR_NMIPENDSET (0x80000000U) ///< Set pending NMI bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SCB_VTOR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SCB_VTOR_TBLOFF (0x1FFFFF80U) ///< Vector table base offset field
#define SCB_VTOR_TBLBASE (0x20000000U) ///< Table base in code(0) or RAM(1)
////////////////////////////////////////////////////////////////////////////////
/// @brief SCB_AIRCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SCB_AIRCR_VECTRESET (0x00000001U) ///< System Reset bit
#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) ///< Clear active vector bit
#define SCB_AIRCR_SYSRESETREQ (0x00000004U) ///< Requests chip control logic to generate a reset
#define SCB_AIRCR_PRIGROUP (0x00000700U) ///< PRIGROUP[2:0] bits (Priority group)
#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) ///< Bit 0
#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) ///< Bit 1
#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) ///< Bit 2
#define SCB_AIRCR_PRIGROUP0 (0x00000000U) ///< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority)
#define SCB_AIRCR_PRIGROUP1 (0x00000100U) ///< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority)
#define SCB_AIRCR_PRIGROUP2 (0x00000200U) ///< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority)
#define SCB_AIRCR_PRIGROUP3 (0x00000300U) ///< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority)
#define SCB_AIRCR_PRIGROUP4 (0x00000400U) ///< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority)
#define SCB_AIRCR_PRIGROUP5 (0x00000500U) ///< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority)
#define SCB_AIRCR_PRIGROUP6 (0x00000600U) ///< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority)
#define SCB_AIRCR_PRIGROUP7 (0x00000700U) ///< Priority group=7 (no pre-emption priority, 8 bits of subpriority)
#define SCB_AIRCR_ENDIANESS (0x00008000U) ///< Data endianness bit
#define SCB_AIRCR_VECTKEY (0xFFFF0000U) ///< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT)
////////////////////////////////////////////////////////////////////////////////
/// @brief SCB_SCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SCB_SCR_SLEEPONEXIT (0x02U) ///< Sleep on exit bit
#define SCB_SCR_SLEEPDEEP (0x04U) ///< Sleep deep bit
#define SCB_SCR_SEVONPEND (0x10U) ///< Wake up from WFE
////////////////////////////////////////////////////////////////////////////////
/// @brief SCB_CCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SCB_CCR_NONBASETHRDENA (0x0001U) ///< Thread mode can be entered from any level in Handler mode by controlled return value
#define SCB_CCR_USERSETMPEND (0x0002U) ///< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception
#define SCB_CCR_UNALIGN_TRP (0x0008U) ///< Trap for unaligned access
#define SCB_CCR_DIV_0_TRP (0x0010U) ///< Trap on Divide by 0
#define SCB_CCR_BFHFNMIGN (0x0100U) ///< Handlers running at priority -1 and -2
#define SCB_CCR_STKALIGN (0x0200U) ///< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned
////////////////////////////////////////////////////////////////////////////////
/// @brief SCB_SHPR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SCB_SHPR_PRI_N (0x000000FFU) ///< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor
#define SCB_SHPR_PRI_N1 (0x0000FF00U) ///< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved
#define SCB_SHPR_PRI_N2 (0x00FF0000U) ///< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV
#define SCB_SHPR_PRI_N3 (0xFF000000U) ///< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick
////////////////////////////////////////////////////////////////////////////////
/// @brief SCB_SHCSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SCB_SHCSR_MEMFAULTACT (0x00000001U) ///< MemManage is active
#define SCB_SHCSR_BUSFAULTACT (0x00000002U) ///< BusFault is active
#define SCB_SHCSR_USGFAULTACT (0x00000008U) ///< UsageFault is active
#define SCB_SHCSR_SVCALLACT (0x00000080U) ///< SVCall is active
#define SCB_SHCSR_MONITORACT (0x00000100U) ///< Monitor is active
#define SCB_SHCSR_PENDSVACT (0x00000400U) ///< PendSV is active
#define SCB_SHCSR_SYSTICKACT (0x00000800U) ///< SysTick is active
#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) ///< Usage Fault is pended
#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) ///< MemManage is pended
#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) ///< Bus Fault is pended
#define SCB_SHCSR_SVCALLPENDED (0x00008000U) ///< SVCall is pended
#define SCB_SHCSR_MEMFAULTENA (0x00010000U) ///< MemManage enable
#define SCB_SHCSR_BUSFAULTENA (0x00020000U) ///< Bus Fault enable
#define SCB_SHCSR_USGFAULTENA (0x00040000U) ///< UsageFault enable
////////////////////////////////////////////////////////////////////////////////
/// @brief SCB_CFSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
///< MFSR
#define SCB_CFSR_IACCVIOL (0x00000001U) ///< Instruction access violation
#define SCB_CFSR_DACCVIOL (0x00000002U) ///< Data access violation
#define SCB_CFSR_MUNSTKERR (0x00000008U) ///< Unstacking error
#define SCB_CFSR_MSTKERR (0x00000010U) ///< Stacking error
#define SCB_CFSR_MMARVALID (0x00000080U) ///< Memory Manage Address Register address valid flag
///< BFSR
#define SCB_CFSR_IBUSERR (0x00000100U) ///< Instruction bus error flag
#define SCB_CFSR_PRECISERR (0x00000200U) ///< Precise data bus error
#define SCB_CFSR_IMPRECISERR (0x00000400U) ///< Imprecise data bus error
#define SCB_CFSR_UNSTKERR (0x00000800U) ///< Unstacking error
#define SCB_CFSR_STKERR (0x00001000U) ///< Stacking error
#define SCB_CFSR_BFARVALID (0x00008000U) ///< Bus Fault Address Register address valid flag
///< UFSR
#define SCB_CFSR_UNDEFINSTR (0x00010000U) ///< The processor attempt to excecute an undefined instruction
#define SCB_CFSR_INVSTATE (0x00020000U) ///< Invalid combination of EPSR and instruction
#define SCB_CFSR_INVPC (0x00040000U) ///< Attempt to load EXC_RETURN into pc illegally
#define SCB_CFSR_NOCP (0x00080000U) ///< Attempt to use a coprocessor instruction
#define SCB_CFSR_UNALIGNED (0x01000000U) ///< Fault occurs when there is an attempt to make an unaligned memory access
#define SCB_CFSR_DIVBYZERO (0x02000000U) ///< Fault occurs when SDIV or DIV instruction is used with a divisor of 0
////////////////////////////////////////////////////////////////////////////////
/// @brief SCB_HFSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SCB_HFSR_VECTTBL (0x00000002U) ///< Fault occures because of vector table read on exception processing
#define SCB_HFSR_FORCED (0x40000000U) ///< Hard Fault activated when a configurable Fault was received and cannot activate
#define SCB_HFSR_DEBUGEVT (0x80000000U) ///< Fault related to debug
////////////////////////////////////////////////////////////////////////////////
/// @brief SCB_DFSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SCB_DFSR_HALTED (0x01U) ///< Halt request flag
#define SCB_DFSR_BKPT (0x02U) ///< BKPT flag
#define SCB_DFSR_DWTTRAP (0x04U) ///< Data Watchpoint and Trace (DWT) flag
#define SCB_DFSR_VCATCH (0x08U) ///< Vector catch flag
#define SCB_DFSR_EXTERNAL (0x10U) ///< External debug request flag
////////////////////////////////////////////////////////////////////////////////
/// @brief SCB_MMFAR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SCB_MMFAR_ADDRESS (0xFFFFFFFFU) ///< Mem Manage fault address field
////////////////////////////////////////////////////////////////////////////////
/// @brief SCB_BFAR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SCB_BFAR_ADDRESS (0xFFFFFFFFU) ///< Bus fault address field
////////////////////////////////////////////////////////////////////////////////
/// @brief SCB_AFSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SCB_AFSR_IMPDEF (0xFFFFFFFFU) ///< Implementation defined
#endif
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h
+228
View File
@@ -0,0 +1,228 @@
////////////////////////////////////////////////////////////////////////////////
/// @file reg_comp.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_COMP_H
#define __REG_COMP_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief COMP Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define COMP_BASE (APB2PERIPH_BASE + 0x4000) ///< Base Address: 0x40014000
////////////////////////////////////////////////////////////////////////////////
/// @brief Comparators Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 RESERVED1; ///< offset: 0x00
__IO u32 RESERVED2; ///< offset: 0x04
__IO u32 RESERVED3; ///< offset: 0x08
union {
__IO u32 CSR1; ///< COMP1 Control Status Register offset: 0x0C
__IO u32 COMP1_CSR;
};
union {
__IO u32 CSR2; ///< COMP2 Control Status Register offset: 0x10
__IO u32 COMP2_CSR;
};
__IO u32 RESERVED4; ///< offset: 0x14
union {
__IO u32 CRV; ///< COMP external reference voltage register offset: 0x18
__IO u32 COMP_CRV;
};
union {
__IO u32 POLL1; ///< COMP1 polling register offset: 0x1C
__IO u32 COMP1_POLL;
};
union {
__IO u32 POLL2; ///< COMP2 polling register offset: 0x20
__IO u32 COMP2_POLL;
};
} COMP_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief COMP type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define COMP ((COMP_TypeDef*) COMP_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief COMP_CSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define COMP_CSR_EN_Pos (0)
#define COMP_CSR_EN (0x01U << COMP_CSR_EN_Pos) ///< Comparator enable
#define COMP_CSR_MODE_Pos (2)
#define COMP_CSR_MODE (0x03U << COMP_CSR_MODE_Pos) ///< Comparator mode
#define COMP_CSR_MODE_LOWESTPOWER (0x00U << COMP_CSR_MODE_Pos) ///< Comparator lowest power mode
#define COMP_CSR_MODE_LOWPOWER (0x01U << COMP_CSR_MODE_Pos) ///< Comparator low power mode
#define COMP_CSR_MODE_MEDIUMRATE (0x02U << COMP_CSR_MODE_Pos) ///< Comparator medium rate mode
#define COMP_CSR_MODE_HIGHRATE (0x03U << COMP_CSR_MODE_Pos) ///< Comparator high rate mode
#define COMP_CSR_INM_Pos (4)
#define COMP_CSR_INM (0x03U << COMP_CSR_INM_Pos) ///< Comparator inverting input selection
#define COMP_CSR_INM_0 (0x00U << COMP_CSR_INM_Pos) ///< INM0 as COMP inverting input
#define COMP_CSR_INM_1 (0x01U << COMP_CSR_INM_Pos) ///< INM1 as COMP inverting input
#define COMP_CSR_INM_2 (0x02U << COMP_CSR_INM_Pos) ///< INM2 as COMP inverting input
#define COMP_CSR_INM_3 (0x03U << COMP_CSR_INM_Pos) ///< INM3 as COMP inverting input
#define COMP_CSR_INP_Pos (7)
#define COMP_CSR_INP (0x03U << COMP_CSR_INP_Pos) ///< Comparator non-inverting input selection
#define COMP_CSR_INP_INP0 (0x00U << COMP_CSR_INP_Pos) ///< INP0 as COMP non-inverting input
#define COMP_CSR_INP_INP1 (0x01U << COMP_CSR_INP_Pos) ///< INP1 as COMP non-inverting input
#define COMP_CSR_INP_INP2 (0x02U << COMP_CSR_INP_Pos) ///< INP2 as COMP non-inverting input
#define COMP_CSR_INP_INP3 (0x03U << COMP_CSR_INP_Pos) ///< INP3 as COMP non-inverting input
#define COMP_CSR_OUT_Pos (10)
#define COMP_CSR_OUT (0x0FU << COMP_CSR_OUT_Pos) ///< Comparator output selection
#define COMP_CSR_OUT_TIM1_BRAKE (0x02U << COMP_CSR_OUT_Pos) ///< Timer1 brake input
#define COMP_CSR_OUT_TIM8_BRAKE (0x03U << COMP_CSR_OUT_Pos) ///< Timer8 brake input
#define COMP_CSR_OUT_TIM1_OCREFCLR (0x06U << COMP_CSR_OUT_Pos) ///< Timer1 ocrefclear input
#define COMP_CSR_OUT_TIM1_CAPTURE1 (0x07U << COMP_CSR_OUT_Pos) ///< Timer1 input capture 1
#define COMP_CSR_OUT_TIM2_CAPTURE4 (0x08U << COMP_CSR_OUT_Pos) ///< Timer2 input capture 4
#define COMP_CSR_OUT_TIM2_OCREFCLR (0x09U << COMP_CSR_OUT_Pos) ///< Timer2 ocrefclear input
#define COMP_CSR_OUT_TIM3_CAPTURE1 (0x0AU << COMP_CSR_OUT_Pos) ///< Timer3 input capture 1
#define COMP_CSR_OUT_TIM3_OCREFCLR (0x0BU << COMP_CSR_OUT_Pos) ///< Timer3 ocrefclear input
#define COMP_CSR_OUT_TIM8_OCREFCLR (0x0FU << COMP_CSR_OUT_Pos) ///< Timer8 ocrefclear input
#define COMP_CSR_POL_Pos (15)
#define COMP_CSR_POL (0x01U << COMP_CSR_POL_Pos) ///< Comparator output polarity
#define COMP_CSR_HYST_Pos (16)
#define COMP_CSR_HYST (0x03U << COMP_CSR_HYST_Pos) ///< Comparator hysteresis
#define COMP_CSR_HYST_0 (0x00U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 0mV
#define COMP_CSR_HYST_15 (0x01U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 15mV
#define COMP_CSR_HYST_30 (0x02U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 30mV
#define COMP_CSR_HYST_90 (0x03U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 90mV
#define COMP_CSR_OFLT_Pos (18)
#define COMP_CSR_OFLT (0x07U << COMP_CSR_OFLT_Pos) ///< Comparator output filter
#define COMP_CSR_OFLT_0 (0x00U << COMP_CSR_OFLT_Pos) ///< 0 clock cycle
#define COMP_CSR_OFLT_1 (0x01U << COMP_CSR_OFLT_Pos) ///< 2 clock cycle
#define COMP_CSR_OFLT_2 (0x02U << COMP_CSR_OFLT_Pos) ///< 4 clock cycle
#define COMP_CSR_OFLT_3 (0x03U << COMP_CSR_OFLT_Pos) ///< 8 clock cycle
#define COMP_CSR_OFLT_4 (0x04U << COMP_CSR_OFLT_Pos) ///< 16 clock cycle
#define COMP_CSR_OFLT_5 (0x05U << COMP_CSR_OFLT_Pos) ///< 32 clock cycle
#define COMP_CSR_OFLT_6 (0x06U << COMP_CSR_OFLT_Pos) ///< 64 clock cycle
#define COMP_CSR_OFLT_7 (0x07U << COMP_CSR_OFLT_Pos) ///< 128 clock cycle
#define COMP_CSR_STA_Pos (30)
#define COMP_CSR_STA (0x01U << COMP_CSR_STA_Pos) ///< Comparator output status
#define COMP_CSR_LOCK_Pos (31)
#define COMP_CSR_LOCK (0x01U << COMP_CSR_LOCK_Pos) ///< Comparator lock
////////////////////////////////////////////////////////////////////////////////
/// @brief COMP_CRV Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define COMP_CRV_Pos (0)
#define COMP_CRV_MASK (0x0FU << COMP_CRV_Pos) ///< Comparator external reference voltage select
#define COMP_CRV_1_20 (0x00U << COMP_CRV_Pos) ///< Comparator external reference voltage select
#define COMP_CRV_2_20 (0x01U << COMP_CRV_Pos) ///< Comparator external reference voltage select
#define COMP_CRV_3_20 (0x02U << COMP_CRV_Pos) ///< Comparator external reference voltage select
#define COMP_CRV_4_20 (0x03U << COMP_CRV_Pos) ///< Comparator external reference voltage select
#define COMP_CRV_5_20 (0x04U << COMP_CRV_Pos) ///< Comparator external reference voltage select
#define COMP_CRV_6_20 (0x05U << COMP_CRV_Pos) ///< Comparator external reference voltage select
#define COMP_CRV_7_20 (0x06U << COMP_CRV_Pos) ///< Comparator external reference voltage select
#define COMP_CRV_8_20 (0x07U << COMP_CRV_Pos) ///< Comparator external reference voltage select
#define COMP_CRV_9_20 (0x08U << COMP_CRV_Pos) ///< Comparator external reference voltage select
#define COMP_CRV_10_20 (0x09U << COMP_CRV_Pos) ///< Comparator external reference voltage select
#define COMP_CRV_11_20 (0x0AU << COMP_CRV_Pos) ///< Comparator external reference voltage select
#define COMP_CRV_12_20 (0x0BU << COMP_CRV_Pos) ///< Comparator external reference voltage select
#define COMP_CRV_13_20 (0x0CU << COMP_CRV_Pos) ///< Comparator external reference voltage select
#define COMP_CRV_14_20 (0x0DU << COMP_CRV_Pos) ///< Comparator external reference voltage select
#define COMP_CRV_15_20 (0x0EU << COMP_CRV_Pos) ///< Comparator external reference voltage select
#define COMP_CRV_16_20 (0x0FU << COMP_CRV_Pos) ///< Comparator external reference voltage select
#define COMP_CRV_EN_Pos (4)
#define COMP_CRV_EN (0x01U << COMP_CRV_EN_Pos) ///< Comparator external reference voltage enable
#define COMP_CRV_EN_DISABLE (0x00U << COMP_CRV_EN_Pos) ///< Disable comparator external reference voltage
#define COMP_CRV_EN_ENABLE (0x01U << COMP_CRV_EN_Pos) ///< Enable comparator external reference voltage
#define COMP_CRV_SRC_Pos (5)
#define COMP_CRV_SRC (0x01U << COMP_CRV_SRC_Pos) ///< Comparator external reference voltage source select
#define COMP_CRV_SRC_VREF (0x00U << COMP_CRV_SRC_Pos) ///< Select VREF
#define COMP_CRV_SRC_AVDD (0x01U << COMP_CRV_SRC_Pos) ///< Select AVDD
////////////////////////////////////////////////////////////////////////////////
/// @brief COMP_POL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define COMP_POLL_EN_Pos (0)
#define COMP_POLL_EN (0x01U << COMP_POLL_EN_Pos) ///< Comparator polling enable
#define COMP_POLL_EN_DISABLE (0x00U << COMP_POLL_EN_Pos) ///< Disable comparator polling mode
#define COMP_POLL_EN_ENABLE (0x01U << COMP_POLL_EN_Pos) ///< Enable comparator polling mode
#define COMP_POLL_CH_Pos (1)
#define COMP_POLL_CH (0x01U << COMP_POLL_CH_Pos) ///< Comparator polling channel
#define COMP_POLL_CH_1_2 (0x00U << COMP_POLL_CH_Pos) ///< Polling channel 1/2
#define COMP_POLL_CH_1_2_3 (0x01U << COMP_POLL_CH_Pos) ///< Polling channel 1/2/3
#define COMP_POLL_FIXN_Pos (2)
#define COMP_POLL_FIXN (0x01U << COMP_POLL_FIXN_Pos) ///< Polling inverting input fix
#define COMP_POLL_FIXN_NOTFIXED (0x00U << COMP_POLL_FIXN_Pos) ///< Polling channel inverting input is not fixed
#define COMP_POLL_FIXN_FIXED (0x01U << COMP_POLL_FIXN_Pos) ///< Polling channel inverting input fixed
#define COMP_POLL_PERIOD_Pos (4)
#define COMP_POLL_PERIOD (0x07U << COMP_POLL_PERIOD_Pos) ///< polling wait cycle
#define COMP_POLL_PERIOD_1 (0x00U << COMP_POLL_PERIOD_Pos) ///< 1 clock cycle
#define COMP_POLL_PERIOD_2 (0x01U << COMP_POLL_PERIOD_Pos) ///< 2 clock cycle
#define COMP_POLL_PERIOD_4 (0x02U << COMP_POLL_PERIOD_Pos) ///< 4 clock cycle
#define COMP_POLL_PERIOD_8 (0x03U << COMP_POLL_PERIOD_Pos) ///< 8 clock cycle
#define COMP_POLL_PERIOD_16 (0x04U << COMP_POLL_PERIOD_Pos) ///< 16 clock cycle
#define COMP_POLL_PERIOD_32 (0x05U << COMP_POLL_PERIOD_Pos) ///< 32 clock cycle
#define COMP_POLL_PERIOD_64 (0x06U << COMP_POLL_PERIOD_Pos) ///< 64 clock cycle
#define COMP_POLL_PERIOD_128 (0x07U << COMP_POLL_PERIOD_Pos) ///< 128 clock cycle
#define COMP_POLL_POUT_Pos (8)
#define COMP_POLL_POUT (0x07U << COMP_POLL_POUT_Pos) ///< Polling output
#define COMP_POLL_POUT_Low (0x00U << COMP_POLL_POUT_Pos) ///< Non-inverting input is lower than inverting input
#define COMP_POLL_POUT_High (0x01U << COMP_POLL_POUT_Pos) ///< Non-inverting input is higher than inverting input
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_crc.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_CRC_H
#define __REG_CRC_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief CRC Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define CRC_BASE (AHBPERIPH_BASE + 0x3000) ///< Base Address: 0x40023000
////////////////////////////////////////////////////////////////////////////////
/// @brief CRC Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 DR; ///< CRC data register, offset: 0x00
__IO u32 IDR; ///< CRC independent data register, offset: 0x04
__IO u32 CR; ///< CRC control register, offset: 0x08
__IO u32 MIR; ///< Middle data register, offset: 0x08
} CRC_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief CRC type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define CRC ((CRC_TypeDef*) CRC_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief CRC_DR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define CRC_DR_DATA_Pos (0)
#define CRC_DR_DATA (0xFFFFFFFFU << CRC_DR_DATA_Pos) ///< Data register bits
////////////////////////////////////////////////////////////////////////////////
/// @brief CRC_IDR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define CRC_IDR_DATA_Pos (0)
#define CRC_IDR_DATA (0xFFU << CRC_IDR_DATA_Pos) ///< General-purpose 8-bit data register bits
////////////////////////////////////////////////////////////////////////////////
/// @brief CRC_CTRL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define CRC_CR_RESET_Pos (0)
#define CRC_CR_RESET (0x01U << CRC_CR_RESET_Pos) ///< RESET bit
////////////////////////////////////////////////////////////////////////////////
/// @brief CRC_MIR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define CRC_MIR_Pos (0)
#define CRC_MIR (0xFFFFFFFFU << CRC_MIR_Pos) ///< Middle data register
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_crs.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_CRS_H
#define __REG_CRS_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief CRS Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define CRS_BASE (APB1PERIPH_BASE + 0x6C00) ///< Base Address: 0x40006C00
////////////////////////////////////////////////////////////////////////////////
/// @brief CRS Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 CR; ///< Control Register offset: 0x00
__IO u32 CFGR; ///< Configuration Register offset: 0x04
__IO u32 ISR; ///< Interrupt and Status Register offset: 0x08
__IO u32 ICR; ///< Interrupt Flag Clear Register offset: 0x0C
} CRS_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief CRS type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define CRS ((CRS_TypeDef*) CRS_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief CRS_CR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define CRS_CR_OKIE_Pos (0)
#define CRS_CR_OKIE (0x01U << CRS_CR_OKIE_Pos) ///< SYNC event OK interrupt enable
#define CRS_CR_WARNIE_Pos (1)
#define CRS_CR_WARNIE (0x01U << CRS_CR_WARNIE_Pos) ///< SYNC warning interrupt enable
#define CRS_CR_ERRIE_Pos (2)
#define CRS_CR_ERRIE (0x01U << CRS_CR_ERRIE_Pos) ///< Synchronization or trimming error interrupt enable
#define CRS_CR_EXPTIE_Pos (3)
#define CRS_CR_EXPTIE (0x01U << CRS_CR_EXPTIE_Pos) ///< Expected SYNC interrupt enable
#define CRS_CR_CNTEN_Pos (5)
#define CRS_CR_CNTEN (0x01U << CRS_CR_CNTEN_Pos) ///< Frequency error counter enable
#define CRS_CR_AUTOTRIMEN_Pos (6)
#define CRS_CR_AUTOTRIMEN (0x01U << CRS_CR_AUTOTRIMEN_Pos) ///< Automatic trimming enable
#define CRS_CR_SWSYNC_Pos (7)
#define CRS_CR_SWSYNC (0x01U << CRS_CR_SWSYNC_Pos) ///< Generate software SYNC event
#define CRS_CR_TRIM_Pos (8)
#define CRS_CR_TRIM (0x3FFU << CRS_CR_TRIM_Pos) ///< HSI 48 oscillator smooth trimming
////////////////////////////////////////////////////////////////////////////////
/// @brief CRS_CFGR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define CRS_CFGR_RELOAD_Pos (0)
#define CRS_CFGR_RELOAD (0xFFFFU << CRS_CFGR_RELOAD_Pos) ///< Counter reload value
#define CRS_CFGR_FELIM_Pos (16)
#define CRS_CFGR_FELIM (0xFFU << CRS_CFGR_FELIM_Pos) ///< Frequency error limit
#define CRS_CFGR_DIV_Pos (24)
#define CRS_CFGR_DIV (0x07U << CRS_CFGR_DIV_Pos) ///< SYNC divider
#define CRS_CFGR_SRC_Pos (28)
#define CRS_CFGR_SRC (0x03U << CRS_CFGR_SRC_Pos) ///< SYNC signal source selection
#define CRS_CFGR_SRC_MCO (0x00U << CRS_CFGR_SRC_Pos)
#define CRS_CFGR_SRC_USBSOF (0x02U << CRS_CFGR_SRC_Pos)
#define CRS_CFGR_POL_Pos (31)
#define CRS_CFGR_POL (0x01U << CRS_CFGR_POL_Pos) ///< SYNC polarity selection
////////////////////////////////////////////////////////////////////////////////
/// @brief CRS_ISR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define CRS_ISR_OKIF_Pos (0)
#define CRS_ISR_OKIF (0x01U << CRS_ISR_OKIF_Pos) ///< SYNC event OK flag
#define CRS_ISR_WARNIF_Pos (1)
#define CRS_ISR_WARNIF (0x01U << CRS_ISR_WARNIF_Pos) ///< SYNC warning flag
#define CRS_ISR_ERRIF_Pos (2)
#define CRS_ISR_ERRIF (0x01U << CRS_ISR_ERRIF_Pos) ///< Error flag
#define CRS_ISR_EXPTIF_Pos (3)
#define CRS_ISR_EXPTIF (0x01U << CRS_ISR_EXPTIF_Pos) ///< Expected SYNC flag
#define CRS_ISR_ERR_Pos (8)
#define CRS_ISR_ERR (0x01U << CRS_ISR_ERR_Pos) ///< SYNC error
#define CRS_ISR_MISS_Pos (9)
#define CRS_ISR_MISS (0x01U << CRS_ISR_MISS_Pos) ///< SYNC missed
#define CRS_ISR_OVERFLOW_Pos (10)
#define CRS_ISR_OVERFLOW (0x01U << CRS_ISR_OVERFLOW_Pos) ///< Trimming overflow or underflow
#define CRS_ISR_FEDIR_Pos (15)
#define CRS_ISR_FEDIR (0x01U << CRS_ISR_FEDIR_Pos) ///< Frequency error direction
#define CRS_ISR_FECAP_Pos (16)
#define CRS_ISR_FECAP (0xFFFFU << CRS_ISR_FECAP_Pos) ///< Frequency error capture
////////////////////////////////////////////////////////////////////////////////
/// @brief CRS_ICR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define CRS_ICR_OK_Pos (0)
#define CRS_ICR_OK (0x01U << CRS_ICR_OK_Pos) ///< SYNC event OK clear flag
#define CRS_ICR_WARN_Pos (1)
#define CRS_ICR_WARN (0x01U << CRS_ICR_WARN_Pos) ///< SYNC warning clear flag
#define CRS_ICR_ERR_Pos (2)
#define CRS_ICR_ERR (0x01U << CRS_ICR_ERR_Pos) ///< Error clear flag
#define CRS_ICR_EXPT_Pos (3)
#define CRS_ICR_EXPT (0x01U << CRS_ICR_EXPT_Pos) ///< Expected SYNC clear flag
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_dac.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_DAC_H
#define __REG_DAC_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief DAC Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define DAC_BASE (APB1PERIPH_BASE + 0x7400) ///< Base Address: 0x40007400
////////////////////////////////////////////////////////////////////////////////
/// @brief Digital to analog converter register
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 CR; ///< DAC control register, offset: 0x00
__IO u32 SWTRIGR; ///< DAC software trigger register, offset: 0x04
__IO u32 DHR12R1; ///< Channel 1 12-bit right align data register, offset: 0x08
__IO u32 DHR12L1; ///< Channel 1 12-bit left align data register, offset: 0x0C
__IO u32 DHR8R1; ///< Channel 1 8-bit right align data register, offset: 0x10
__IO u32 DHR12R2; ///< Channel 2 12-bit right align data register, offset: 0x14
__IO u32 DHR12L2; ///< Channel 2 12-bit left align data register, offset: 0x18
__IO u32 DHR8R2; ///< Channel 2 8-bit right align data register, offset: 0x1C
__IO u32 DHR12RD; ///< Dual channel 12-bit right align data register,offset: 0x20
__IO u32 DHR12LD; ///< Dual channel 12-bit left align data register, offset: 0x24
__IO u32 DHR8RD; ///< Dual channel 8-bit right align data register, offset: 0x28
__IO u32 DOR1; ///< Channel 1 output register, offset: 0x2C
__IO u32 DOR2; ///< Channel 2 output register, offset: 0x30
} DAC_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief DAC type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define DAC ((DAC_TypeDef*) DAC_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief DAC_CR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DAC_CR_EN1_Pos (0)
#define DAC_CR_EN1 (0x01U << DAC_CR_EN1_Pos) ///< DAC channel1 enable
#define DAC_CR_BOFF1_Pos (1)
#define DAC_CR_BOFF1 (0x01U << DAC_CR_BOFF1_Pos) ///< DAC channel1 output buffer disable
#define DAC_CR_TEN1_Pos (2)
#define DAC_CR_TEN1 (0x01U << DAC_CR_TEN1_Pos) ///< DAC channel1 Trigger enable
#define DAC_CR_TSEL1_Pos (3)
#define DAC_CR_TSEL1 (0x07U << DAC_CR_TSEL1_Pos) ///< TSEL1[2:0] (DAC channel1 Trigger selection)
#define DAC_CR_TSEL1_TIM1_TRIG (0x00U << DAC_CR_TSEL1_Pos) ///< TIM1_TRIG trigger
#define DAC_CR_TSEL1_TIM3_TRIG (0x01U << DAC_CR_TSEL1_Pos) ///< TIM3_TRIG trigger
#define DAC_CR_TSEL1_TIM2_TRIG (0x04U << DAC_CR_TSEL1_Pos) ///< TIM2_TRIG trigger
#define DAC_CR_TSEL1_TIM4_TRIG (0x05U << DAC_CR_TSEL1_Pos) ///< TIM4_TRIG trigger
#define DAC_CR_TSEL1_EXTI9 (0x06U << DAC_CR_TSEL1_Pos) ///< External interrupt line 9 trigger
#define DAC_CR_TSEL1_SOFTWARE (0x07U << DAC_CR_TSEL1_Pos) ///< Software trigger
#define DAC_CR_WAVE1_Pos (6)
#define DAC_CR_WAVE1 (0x03U << DAC_CR_WAVE1_Pos) ///< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
#define DAC_CR_WAVE1_NONE (0x00U << DAC_CR_WAVE1_Pos) ///< Turn off waveform generation
#define DAC_CR_WAVE1_NOISE (0x01U << DAC_CR_WAVE1_Pos) ///< Noise waveform generation
#define DAC_CR_WAVE1_TRIANGLE (0x02U << DAC_CR_WAVE1_Pos) ///< Triangle wave generation
#define DAC_CR_MAMP1_Pos (8)
#define DAC_CR_MAMP1 (0x0FU << DAC_CR_MAMP1_Pos) ///< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
#define DAC_CR_MAMP1_1 (0x00U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 1
#define DAC_CR_MAMP1_3 (0x01U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 3
#define DAC_CR_MAMP1_7 (0x02U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 7
#define DAC_CR_MAMP1_15 (0x03U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 15
#define DAC_CR_MAMP1_31 (0x04U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 31
#define DAC_CR_MAMP1_63 (0x05U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 63
#define DAC_CR_MAMP1_127 (0x06U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 127
#define DAC_CR_MAMP1_255 (0x07U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 255
#define DAC_CR_MAMP1_511 (0x08U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 511
#define DAC_CR_MAMP1_1023 (0x09U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 1023
#define DAC_CR_MAMP1_2047 (0x0AU << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 2047
#define DAC_CR_MAMP1_4095 (0x0BU << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 4095
#define DAC_CR_DMAEN1_Pos (12)
#define DAC_CR_DMAEN1 (0x01U << DAC_CR_DMAEN1_Pos) ///< DAC channel1 DMA enable
#define DAC_CR_EN2_Pos (16)
#define DAC_CR_EN2 (0x01U << DAC_CR_EN2_Pos) ///< DAC channel2 enable
#define DAC_CR_BOFF2_Pos (17)
#define DAC_CR_BOFF2 (0x01U << DAC_CR_BOFF2_Pos) ///< DAC channel2 output buffer disable
#define DAC_CR_TEN2_Pos (18)
#define DAC_CR_TEN2 (0x01U << DAC_CR_TEN2_Pos) ///< DAC channel2 Trigger enable
#define DAC_CR_TSEL2_Pos (19)
#define DAC_CR_TSEL2 (0x07U << DAC_CR_TSEL2_Pos) ///< TSEL1[2:0] (DAC channel1 Trigger selection)
#define DAC_CR_TSEL2_TIM1_TRIG (0x00U << DAC_CR_TSEL2_Pos) ///< TIM1_TRIG trigger
#define DAC_CR_TSEL2_TIM3_TRIG (0x01U << DAC_CR_TSEL2_Pos) ///< TIM3_TRIG trigger
#define DAC_CR_TSEL2_TIM2_TRIG (0x04U << DAC_CR_TSEL2_Pos) ///< TIM2_TRIG trigger
#define DAC_CR_TSEL2_TIM4_TRIG (0x05U << DAC_CR_TSEL2_Pos) ///< TIM4_TRIG trigger
#define DAC_CR_TSEL2_EXTI9 (0x06U << DAC_CR_TSEL2_Pos) ///< External interrupt line 9 trigger
#define DAC_CR_TSEL2_SOFTWARE (0x07U << DAC_CR_TSEL2_Pos) ///< Software trigger
#define DAC_CR_WAVE2_Pos (22)
#define DAC_CR_WAVE2 (0x03U << DAC_CR_WAVE2_Pos) ///< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
#define DAC_CR_WAVE2_NONE (0x00U << DAC_CR_WAVE2_Pos) ///< Turn off waveform generation
#define DAC_CR_WAVE2_NOISE (0x01U << DAC_CR_WAVE2_Pos) ///< Noise waveform generation
#define DAC_CR_WAVE2_TRIANGLE (0x02U << DAC_CR_WAVE2_Pos) ///< Triangle wave generation
#define DAC_CR_MAMP2_Pos (24)
#define DAC_CR_MAMP2 (0x0FU << DAC_CR_MAMP2_Pos) ///< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
#define DAC_CR_MAMP2_1 (0x00U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 1
#define DAC_CR_MAMP2_3 (0x01U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 3
#define DAC_CR_MAMP2_7 (0x02U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 7
#define DAC_CR_MAMP2_15 (0x03U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 15
#define DAC_CR_MAMP2_31 (0x04U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 31
#define DAC_CR_MAMP2_63 (0x05U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 63
#define DAC_CR_MAMP2_127 (0x06U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 127
#define DAC_CR_MAMP2_255 (0x07U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 255
#define DAC_CR_MAMP2_511 (0x08U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 511
#define DAC_CR_MAMP2_1023 (0x09U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 1023
#define DAC_CR_MAMP2_2047 (0x0AU << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 2047
#define DAC_CR_MAMP2_4095 (0x0BU << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 4095
#define DAC_CR_DMAEN2_Pos (28)
#define DAC_CR_DMAEN2 (0x01U << DAC_CR_DMAEN2_Pos) ///< DAC channel2 DMA enabled
////////////////////////////////////////////////////////////////////////////////
/// @brief DAC_SWTRIGR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DAC_SWTRIGR_SWTRIG1_Pos (0)
#define DAC_SWTRIGR_SWTRIG1 (0x01U << DAC_SWTRIGR_SWTRIG1_Pos) ///< DAC channel1 software trigger
#define DAC_SWTRIGR_SWTRIG2_Pos (1)
#define DAC_SWTRIGR_SWTRIG2 (0x01U << DAC_SWTRIGR_SWTRIG2_Pos) ///< DAC channel2 software trigger
#define DAC_SWTRIGR_DACPRE_Pos (8)
#define DAC_SWTRIGR_DACPRE (0x7FU << DAC_SWTRIGR_DACPRE_Pos) ///< DAC prescale
////////////////////////////////////////////////////////////////////////////////
/// @brief DAC_DHR12R1 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DAC_DHR12R1_DACC1DHR_Pos (0)
#define DAC_DHR12R1_DACC1DHR (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) ///< DAC channel1 12-bit Right align data
////////////////////////////////////////////////////////////////////////////////
/// @brief DAC_DHR12L1 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DAC_DHR12L1_DACC1DHR_Pos (4)
#define DAC_DHR12L1_DACC1DHR (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) ///< DAC channel1 12-bit Left align data
////////////////////////////////////////////////////////////////////////////////
/// @brief DAC_DHR8R1 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DAC_DHR8R1_DACC1DHR_Pos (0)
#define DAC_DHR8R1_DACC1DHR (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) ///< DAC channel1 8-bit Right align data
////////////////////////////////////////////////////////////////////////////////
/// @brief DAC_DHR12R2 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DAC_DHR12R2_DACC2DHR_Pos (0)
#define DAC_DHR12R2_DACC2DHR (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) ///< DAC channel2 12-bit Right align data
////////////////////////////////////////////////////////////////////////////////
/// @brief DAC_DHR12L2 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DAC_DHR12L2_DACC2DHR_Pos (4)
#define DAC_DHR12L2_DACC2DHR (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) ///< DAC channel2 12-bit Left align data
////////////////////////////////////////////////////////////////////////////////
/// @brief DAC_DHR8R2 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DAC_DHR8R2_DACC2DHR_Pos (0)
#define DAC_DHR8R2_DACC2DHR (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) ///< DAC channel2 8-bit Right align data
////////////////////////////////////////////////////////////////////////////////
/// @brief DAC_DHR12RD Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DAC_DHR12RD_DACC1DHR_Pos (0)
#define DAC_DHR12RD_DACC1DHR (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) ///< DAC channel1 12-bit Right align data
#define DAC_DHR12RD_DACC2DHR_Pos (16)
#define DAC_DHR12RD_DACC2DHR (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) ///< DAC channel2 12-bit Right align data
////////////////////////////////////////////////////////////////////////////////
/// @brief DAC_DHR12LD Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DAC_DHR12LD_DACC1DHR_Pos (4)
#define DAC_DHR12LD_DACC1DHR (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) ///< DAC channel1 12-bit Right align data
#define DAC_DHR12LD_DACC2DHR_Pos (20)
#define DAC_DHR12LD_DACC2DHR (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) ///< DAC channel2 12-bit Right align data
////////////////////////////////////////////////////////////////////////////////
/// @brief DAC_DHR8RD Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DAC_DHR8RD_DACC1DHR_Pos (0)
#define DAC_DHR8RD_DACC1DHR (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) ///< DAC channel1 8-bit Right align data
#define DAC_DHR8RD_DACC2DHR_Pos (8)
#define DAC_DHR8RD_DACC2DHR (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) ///< DAC channel2 8-bit Right align data
////////////////////////////////////////////////////////////////////////////////
/// @brief DAC_DOR1 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DAC_DOR1_DACC1DOR_Pos (0)
#define DAC_DOR1_DACC1DOR (0xFFFU << DAC_DOR1_DACC1DOR_Pos) ///< DAC channel1 data output
////////////////////////////////////////////////////////////////////////////////
/// @brief DAC_DOR2 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DAC_DOR2_DACC2DOR_Pos (0)
#define DAC_DOR2_DACC2DOR (0xFFFU << DAC_DOR2_DACC2DOR_Pos) ///< DAC channel2 data output #endif
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_dbg.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_DBG_H
#define __REG_DBG_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief DBG Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define DBG_BASE (0x40007080UL) ///< Base Address: 0x40007080
////////////////////////////////////////////////////////////////////////////////
/// @brief DEBUG Registers Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 IDCODE; ///< Code ID offset: 0x00
__IO u32 CR; ///< Control Register offset: 0x04
} DBGMCU_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief DBGMCU type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define DBGMCU ((DBGMCU_TypeDef*) DBG_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief DBGMCU_IDCODE Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DBGMCU_IDCODE_DEV_ID_Pos (0)
#define DBGMCU_IDCODE_DEV_ID (0xFFFFFFFFU << DBGMCU_IDCODE_DEV_ID_Pos) ///< Device identifier
////////////////////////////////////////////////////////////////////////////////
/// @brief DBGMCU_CR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DBGMCU_CR_SLEEP_Pos (0)
#define DBGMCU_CR_SLEEP (0x01U << DBGMCU_CR_SLEEP_Pos) ///< Debug Sleep mode
#define DBGMCU_CR_STOP_Pos (1)
#define DBGMCU_CR_STOP (0x01U << DBGMCU_CR_STOP_Pos) ///< Debug Stop mode
#define DBGMCU_CR_STANDBY_Pos (2)
#define DBGMCU_CR_STANDBY (0x01U << DBGMCU_CR_STANDBY_Pos) ///< Debug Standby mode
#define DBGMCU_CR_TRACE_IOEN_Pos (5)
#define DBGMCU_CR_TRACE_IOEN (0x01U << DBGMCU_CR_TRACE_IOEN_Pos) ///< Trace pin assignment
#define DBGMCU_CR_TRACE_MODE_Pos (6)
#define DBGMCU_CR_TRACE_MODE_Msk (0x03U << DBGMCU_CR_TRACE_MODE_Pos) ///< TRACE_MODE[1:0] bits (Trace Pin Assignment Control)
#define DBGMCU_CR_TRACE_MODE_0 (0x01U << DBGMCU_CR_TRACE_MODE_Pos) ///< Bit 0
#define DBGMCU_CR_TRACE_MODE_1 (0x02U << DBGMCU_CR_TRACE_MODE_Pos) ///< Bit 1
#define DBGMCU_CR_TRACE_MODE_ASYNC (0x00U << DBGMCU_CR_TRACE_MODE_Pos) ///< Tracking pin uses asynchronous mode
#define DBGMCU_CR_TRACE_MODE_SYNC1 (0x01U << DBGMCU_CR_TRACE_MODE_Pos) ///< The trace pin uses synchronous mode, and the data length is 1
#define DBGMCU_CR_TRACE_MODE_SYNC2 (0x02U << DBGMCU_CR_TRACE_MODE_Pos) ///< The trace pin uses synchronous mode, and the data length is 2
#define DBGMCU_CR_IWDG_STOP_Pos (8)
#define DBGMCU_CR_IWDG_STOP (0x01U << DBGMCU_CR_IWDG_STOP_Pos) ///< Debug independent watchdog stopped when core is halted
#define DBGMCU_CR_WWDG_STOP_Pos (9)
#define DBGMCU_CR_WWDG_STOP (0x01U << DBGMCU_CR_WWDG_STOP_Pos) ///< Debug window watchdog stopped when core is halted
#define DBGMCU_CR_TIM_STOP_Pos (10)
#define DBGMCU_CR_TIM1_STOP (0x01U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM1 counter stopped when core is halted
#define DBGMCU_CR_TIM2_STOP (0x02U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM2 counter stopped when core is halted
#define DBGMCU_CR_TIM3_STOP (0x04U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM3 counter stopped when core is halted
#define DBGMCU_CR_TIM4_STOP (0x08U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM4 counter stopped when core is halted
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_dma.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_DMA_H
#define __REG_DMA_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief DMA Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) ///< Base Address: 0x40020000
#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) ///< Base Address: 0x40020008
#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) ///< Base Address: 0x4002001C
#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) ///< Base Address: 0x40020030
#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) ///< Base Address: 0x40020044
#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) ///< Base Address: 0x40020058
#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) ///< Base Address: 0x4002006C
#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) ///< Base Address: 0x40020080
#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) ///< Base Address: 0x40020400
#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) ///< Base Address: 0x40020408
#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) ///< Base Address: 0x4002041C
#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) ///< Base Address: 0x40020430
#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) ///< Base Address: 0x40020444
#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) ///< Base Address: 0x40020458
////////////////////////////////////////////////////////////////////////////////
/// @brief DMA Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 CCR; ///< DMA channel x configuration register offset: 0x00
__IO u32 CNDTR; ///< DMA channel x number of data register offset: 0x04
__IO u32 CPAR; ///< DMA channel x peripheral address register offset: 0x08
__IO u32 CMAR; ///< DMA channel x memory address register offset: 0x0C
} DMA_Channel_TypeDef;
typedef struct {
__IO u32 ISR; ///< Interrupt Status Register offset: 0x00
__IO u32 IFCR; ///< Interrupt Flag Clear Register offset: 0x04
__IO u32 CCRx; ///< Channel X configures registers offset: 0x08
__IO u32 CNDTRx; ///< Channel X transfer quantity register offset: 0x0C
__IO u32 CPARx; ///< Channel X peripheral address register offset: 0x10
__IO u32 CMARx; ///< Channel X memory address register offset: 0x14
} DMA_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief DMA type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define DMA1 ((DMA_TypeDef*) DMA1_BASE)
#define DMA1_ch1 ((DMA_Channel_TypeDef*) DMA1_Channel1_BASE)
#define DMA1_ch2 ((DMA_Channel_TypeDef*) DMA1_Channel2_BASE)
#define DMA1_ch3 ((DMA_Channel_TypeDef*) DMA1_Channel3_BASE)
#define DMA1_ch4 ((DMA_Channel_TypeDef*) DMA1_Channel4_BASE)
#define DMA1_ch5 ((DMA_Channel_TypeDef*) DMA1_Channel5_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef*) DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef*) DMA1_Channel2_BASE)
#define DMA1_Channel3 ((DMA_Channel_TypeDef*) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef*) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef*) DMA1_Channel5_BASE)
#define DMA1_ch6 ((DMA_Channel_TypeDef*) DMA1_Channel6_BASE)
#define DMA1_ch7 ((DMA_Channel_TypeDef*) DMA1_Channel7_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef*) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef*) DMA1_Channel7_BASE)
#define DMA2 ((DMA_TypeDef*) DMA2_BASE)
#define DMA2_ch1 ((DMA_Channel_TypeDef*) DMA2_Channel1_BASE)
#define DMA2_ch2 ((DMA_Channel_TypeDef*) DMA2_Channel2_BASE)
#define DMA2_ch3 ((DMA_Channel_TypeDef*) DMA2_Channel3_BASE)
#define DMA2_ch4 ((DMA_Channel_TypeDef*) DMA2_Channel4_BASE)
#define DMA2_ch5 ((DMA_Channel_TypeDef*) DMA2_Channel5_BASE)
#define DMA2_Channel1 ((DMA_Channel_TypeDef*) DMA2_Channel1_BASE)
#define DMA2_Channel2 ((DMA_Channel_TypeDef*) DMA2_Channel2_BASE)
#define DMA2_Channel3 ((DMA_Channel_TypeDef*) DMA2_Channel3_BASE)
#define DMA2_Channel4 ((DMA_Channel_TypeDef*) DMA2_Channel4_BASE)
#define DMA2_Channel5 ((DMA_Channel_TypeDef*) DMA2_Channel5_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief DMA_ISR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DMA_ISR_GIF1_Pos (0)
#define DMA_ISR_GIF1 (0x01U << DMA_ISR_GIF1_Pos) ///< Channel 1 Global interrupt flag
#define DMA_ISR_TCIF1_Pos (1)
#define DMA_ISR_TCIF1 (0x01U << DMA_ISR_TCIF1_Pos) ///< Channel 1 Transfer Complete flag
#define DMA_ISR_HTIF1_Pos (2)
#define DMA_ISR_HTIF1 (0x01U << DMA_ISR_HTIF1_Pos) ///< Channel 1 Half Transfer flag
#define DMA_ISR_TEIF1_Pos (3)
#define DMA_ISR_TEIF1 (0x01U << DMA_ISR_TEIF1_Pos) ///< Channel 1 Transfer Error flag
#define DMA_ISR_GIF2_Pos (4)
#define DMA_ISR_GIF2 (0x01U << DMA_ISR_GIF2_Pos) ///< Channel 2 Global interrupt flag
#define DMA_ISR_TCIF2_Pos (5)
#define DMA_ISR_TCIF2 (0x01U << DMA_ISR_TCIF2_Pos) ///< Channel 2 Transfer Complete flag
#define DMA_ISR_HTIF2_Pos (6)
#define DMA_ISR_HTIF2 (0x01U << DMA_ISR_HTIF2_Pos) ///< Channel 2 Half Transfer flag
#define DMA_ISR_TEIF2_Pos (7)
#define DMA_ISR_TEIF2 (0x01U << DMA_ISR_TEIF2_Pos) ///< Channel 2 Transfer Error flag
#define DMA_ISR_GIF3_Pos (8)
#define DMA_ISR_GIF3 (0x01U << DMA_ISR_GIF3_Pos) ///< Channel 3 Global interrupt flag
#define DMA_ISR_TCIF3_Pos (9)
#define DMA_ISR_TCIF3 (0x01U << DMA_ISR_TCIF3_Pos) ///< Channel 3 Transfer Complete flag
#define DMA_ISR_HTIF3_Pos (10)
#define DMA_ISR_HTIF3 (0x01U << DMA_ISR_HTIF3_Pos) ///< Channel 3 Half Transfer flag
#define DMA_ISR_TEIF3_Pos (11)
#define DMA_ISR_TEIF3 (0x01U << DMA_ISR_TEIF3_Pos) ///< Channel 3 Transfer Error flag
#define DMA_ISR_GIF4_Pos (12)
#define DMA_ISR_GIF4 (0x01U << DMA_ISR_GIF4_Pos) ///< Channel 4 Global interrupt flag
#define DMA_ISR_TCIF4_Pos (13)
#define DMA_ISR_TCIF4 (0x01U << DMA_ISR_TCIF4_Pos) ///< Channel 4 Transfer Complete flag
#define DMA_ISR_HTIF4_Pos (14)
#define DMA_ISR_HTIF4 (0x01U << DMA_ISR_HTIF4_Pos) ///< Channel 4 Half Transfer flag
#define DMA_ISR_TEIF4_Pos (15)
#define DMA_ISR_TEIF4 (0x01U << DMA_ISR_TEIF4_Pos) ///< Channel 4 Transfer Error flag
#define DMA_ISR_GIF5_Pos (16)
#define DMA_ISR_GIF5 (0x01U << DMA_ISR_GIF5_Pos) ///< Channel 5 Global interrupt flag
#define DMA_ISR_TCIF5_Pos (17)
#define DMA_ISR_TCIF5 (0x01U << DMA_ISR_TCIF5_Pos) ///< Channel 5 Transfer Complete flag
#define DMA_ISR_HTIF5_Pos (18)
#define DMA_ISR_HTIF5 (0x01U << DMA_ISR_HTIF5_Pos) ///< Channel 5 Half Transfer flag
#define DMA_ISR_TEIF5_Pos (19)
#define DMA_ISR_TEIF5 (0x01U << DMA_ISR_TEIF5_Pos) ///< Channel 5 Transfer Error flag
#define DMA_ISR_GIF6_Pos (20)
#define DMA_ISR_GIF6 (0x01U << DMA_ISR_GIF6_Pos) ///< Channel 6 Global interrupt flag
#define DMA_ISR_TCIF6_Pos (21)
#define DMA_ISR_TCIF6 (0x01U << DMA_ISR_TCIF6_Pos) ///< Channel 6 Transfer Complete flag
#define DMA_ISR_HTIF6_Pos (22)
#define DMA_ISR_HTIF6 (0x01U << DMA_ISR_HTIF6_Pos) ///< Channel 6 Half Transfer flag
#define DMA_ISR_TEIF6_Pos (23)
#define DMA_ISR_TEIF6 (0x01U << DMA_ISR_TEIF6_Pos) ///< Channel 6 Transfer Error flag
#define DMA_ISR_GIF7_Pos (24)
#define DMA_ISR_GIF7 (0x01U << DMA_ISR_GIF7_Pos) ///< Channel 7 Global interrupt flag
#define DMA_ISR_TCIF7_Pos (25)
#define DMA_ISR_TCIF7 (0x01U << DMA_ISR_TCIF7_Pos) ///< Channel 7 Transfer Complete flag
#define DMA_ISR_HTIF7_Pos (26)
#define DMA_ISR_HTIF7 (0x01U << DMA_ISR_HTIF7_Pos) ///< Channel 7 Half Transfer flag
#define DMA_ISR_TEIF7_Pos (27)
#define DMA_ISR_TEIF7 (0x01U << DMA_ISR_TEIF7_Pos) ///< Channel 7 Transfer Error flag
////////////////////////////////////////////////////////////////////////////////
/// @brief DMA_IFCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DMA_IFCR_CGIF1_Pos (0)
#define DMA_IFCR_CGIF1 (0x01U << DMA_IFCR_CGIF1_Pos) ///< Channel 1 Global interrupt clearr
#define DMA_IFCR_CTCIF1_Pos (1)
#define DMA_IFCR_CTCIF1 (0x01U << DMA_IFCR_CTCIF1_Pos) ///< Channel 1 Transfer Complete clear
#define DMA_IFCR_CHTIF1_Pos (2)
#define DMA_IFCR_CHTIF1 (0x01U << DMA_IFCR_CHTIF1_Pos) ///< Channel 1 Half Transfer clear
#define DMA_IFCR_CTEIF1_Pos (3)
#define DMA_IFCR_CTEIF1 (0x01U << DMA_IFCR_CTEIF1_Pos) ///< Channel 1 Transfer Error clear
#define DMA_IFCR_CGIF2_Pos (4)
#define DMA_IFCR_CGIF2 (0x01U << DMA_IFCR_CGIF2_Pos) ///< Channel 2 Global interrupt clear
#define DMA_IFCR_CTCIF2_Pos (5)
#define DMA_IFCR_CTCIF2 (0x01U << DMA_IFCR_CTCIF2_Pos) ///< Channel 2 Transfer Complete clear
#define DMA_IFCR_CHTIF2_Pos (6)
#define DMA_IFCR_CHTIF2 (0x01U << DMA_IFCR_CHTIF2_Pos) ///< Channel 2 Half Transfer clear
#define DMA_IFCR_CTEIF2_Pos (7)
#define DMA_IFCR_CTEIF2 (0x01U << DMA_IFCR_CTEIF2_Pos) ///< Channel 2 Transfer Error clear
#define DMA_IFCR_CGIF3_Pos (8)
#define DMA_IFCR_CGIF3 (0x01U << DMA_IFCR_CGIF3_Pos) ///< Channel 3 Global interrupt clear
#define DMA_IFCR_CTCIF3_Pos (9)
#define DMA_IFCR_CTCIF3 (0x01U << DMA_IFCR_CTCIF3_Pos) ///< Channel 3 Transfer Complete clear
#define DMA_IFCR_CHTIF3_Pos (10)
#define DMA_IFCR_CHTIF3 (0x01U << DMA_IFCR_CHTIF3_Pos) ///< Channel 3 Half Transfer clear
#define DMA_IFCR_CTEIF3_Pos (11)
#define DMA_IFCR_CTEIF3 (0x01U << DMA_IFCR_CTEIF3_Pos) ///< Channel 3 Transfer Error clear
#define DMA_IFCR_CGIF4_Pos (12)
#define DMA_IFCR_CGIF4 (0x01U << DMA_IFCR_CGIF4_Pos) ///< Channel 4 Global interrupt clear
#define DMA_IFCR_CTCIF4_Pos (13)
#define DMA_IFCR_CTCIF4 (0x01U << DMA_IFCR_CTCIF4_Pos) ///< Channel 4 Transfer Complete clear
#define DMA_IFCR_CHTIF4_Pos (14)
#define DMA_IFCR_CHTIF4 (0x01U << DMA_IFCR_CHTIF4_Pos) ///< Channel 4 Half Transfer clear
#define DMA_IFCR_CTEIF4_Pos (15)
#define DMA_IFCR_CTEIF4 (0x01U << DMA_IFCR_CTEIF4_Pos) ///< Channel 4 Transfer Error clear
#define DMA_IFCR_CGIF5_Pos (16)
#define DMA_IFCR_CGIF5 (0x01U << DMA_IFCR_CGIF5_Pos) ///< Channel 5 Global interrupt clear
#define DMA_IFCR_CTCIF5_Pos (17)
#define DMA_IFCR_CTCIF5 (0x01U << DMA_IFCR_CTCIF5_Pos) ///< Channel 5 Transfer Complete clear
#define DMA_IFCR_CHTIF5_Pos (18)
#define DMA_IFCR_CHTIF5 (0x01U << DMA_IFCR_CHTIF5_Pos) ///< Channel 5 Half Transfer clear
#define DMA_IFCR_CTEIF5_Pos (19)
#define DMA_IFCR_CTEIF5 (0x01U << DMA_IFCR_CTEIF5_Pos) ///< Channel 5 Transfer Error clear
#define DMA_IFCR_CGIF6_Pos (20)
#define DMA_IFCR_CGIF6 (0x01U << DMA_IFCR_CGIF6_Pos) ///< Channel 6 Global interrupt clear
#define DMA_IFCR_CTCIF6_Pos (21)
#define DMA_IFCR_CTCIF6 (0x01U << DMA_IFCR_CTCIF6_Pos) ///< Channel 6 Transfer Complete clear
#define DMA_IFCR_CHTIF6_Pos (22)
#define DMA_IFCR_CHTIF6 (0x01U << DMA_IFCR_CHTIF6_Pos) ///< Channel 6 Half Transfer clear
#define DMA_IFCR_CTEIF6_Pos (23)
#define DMA_IFCR_CTEIF6 (0x01U << DMA_IFCR_CTEIF6_Pos) ///< Channel 6 Transfer Error clear
#define DMA_IFCR_CGIF7_Pos (24)
#define DMA_IFCR_CGIF7 (0x01U << DMA_IFCR_CGIF7_Pos) ///< Channel 7 Global interrupt clear
#define DMA_IFCR_CTCIF7_Pos (25)
#define DMA_IFCR_CTCIF7 (0x01U << DMA_IFCR_CTCIF7_Pos) ///< Channel 7 Transfer Complete clear
#define DMA_IFCR_CHTIF7_Pos (26)
#define DMA_IFCR_CHTIF7 (0x01U << DMA_IFCR_CHTIF7_Pos) ///< Channel 7 Half Transfer clear
#define DMA_IFCR_CTEIF7_Pos (27)
#define DMA_IFCR_CTEIF7 (0x01U << DMA_IFCR_CTEIF7_Pos) ///< Channel 7 Transfer Error clear
////////////////////////////////////////////////////////////////////////////////
/// @brief DMA_CCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DMA_CCR_EN_Pos (0)
#define DMA_CCR_EN (0x01U << DMA_CCR_EN_Pos) ///< Channel enabl
#define DMA_CCR_TCIE_Pos (1)
#define DMA_CCR_TCIE (0x01U << DMA_CCR_TCIE_Pos) ///< Transfer complete interrupt enable
#define DMA_CCR_HTIE_Pos (2)
#define DMA_CCR_HTIE (0x01U << DMA_CCR_HTIE_Pos) ///< Half Transfer interrupt enable
#define DMA_CCR_TEIE_Pos (3)
#define DMA_CCR_TEIE (0x01U << DMA_CCR_TEIE_Pos) ///< Transfer error interrupt enable
#define DMA_CCR_DIR_Pos (4)
#define DMA_CCR_DIR (0x01U << DMA_CCR_DIR_Pos) ///< Data transfer direction
#define DMA_CCR_CIRC_Pos (5)
#define DMA_CCR_CIRC (0x01U << DMA_CCR_CIRC_Pos) ///< Circular mode
#define DMA_CCR_PINC_Pos (6)
#define DMA_CCR_PINC (0x01U << DMA_CCR_PINC_Pos) ///< Peripheral increment mode
#define DMA_CCR_MINC_Pos (7)
#define DMA_CCR_MINC (0x01U << DMA_CCR_MINC_Pos) ///< Memory increment mode
#define DMA_CCR_PSIZE_Pos (8)
#define DMA_CCR_PSIZE (0x03U << DMA_CCR_PSIZE_Pos) ///< PSIZE[1:0] bits (Peripheral size)
#define DMA_CCR_PSIZE_0 (0x01U << DMA_CCR_PSIZE_Pos) ///< Bit0
#define DMA_CCR_PSIZE_1 (0x02U << DMA_CCR_PSIZE_Pos) ///< Bit1
#define DMA_CCR_PSIZE_BYTE (0x00U << DMA_CCR_PSIZE_Pos) ///< DMA Peripheral Data Size Byte
#define DMA_CCR_PSIZE_HALFWORD (0x01U << DMA_CCR_PSIZE_Pos) ///< DMA Peripheral Data Size HalfWord
#define DMA_CCR_PSIZE_WORD (0x02U << DMA_CCR_PSIZE_Pos) ///< DMA Peripheral Data Size Word
#define DMA_CCR_MSIZE_Pos (10)
#define DMA_CCR_MSIZE (0x03U << DMA_CCR_MSIZE_Pos) ///< MSIZE[1:0] bits (Memory size)
#define DMA_CCR_MSIZE_0 (0x01U << DMA_CCR_MSIZE_Pos) ///< Bit0
#define DMA_CCR_MSIZE_1 (0x02U << DMA_CCR_MSIZE_Pos) ///< Bit1
#define DMA_CCR_MSIZE_BYTE (0x00U << DMA_CCR_MSIZE_Pos) ///< DMA Memory Data Size Byte
#define DMA_CCR_MSIZE_HALFWORD (0x01U << DMA_CCR_MSIZE_Pos) ///< DMA Memory Data Size HalfWord
#define DMA_CCR_MSIZE_WORD (0x02U << DMA_CCR_MSIZE_Pos) ///< DMA Memory Data Size Word
#define DMA_CCR_PL_Pos (12)
#define DMA_CCR_PL (0x03U << DMA_CCR_PL_Pos) ///< PL[1:0] bits(Channel Priority level)
#define DMA_CCR_PL_0 (0x01U << DMA_CCR_PL_Pos) ///< Bit0
#define DMA_CCR_PL_1 (0x02U << DMA_CCR_PL_Pos) ///< Bit1
#define DMA_CCR_PL_Low (0x00U << DMA_CCR_PL_Pos) ///< DMA Priority Low
#define DMA_CCR_PL_Medium (0x01U << DMA_CCR_PL_Pos) ///< DMA Priority Medium
#define DMA_CCR_PL_High (0x02U << DMA_CCR_PL_Pos) ///< DMA Priority High
#define DMA_CCR_PL_VeryHigh (0x03U << DMA_CCR_PL_Pos) ///< DMA Priority VeryHigh
#define DMA_CCR_M2M_Pos (14)
#define DMA_CCR_M2M (0x01U << DMA_CCR_M2M_Pos) ///< Memory to memory mode
#define DMA_CCR_ARE_Pos (15)
#define DMA_CCR_ARE (0x01U << DMA_CCR_ARE_Pos) ///< Auto-Reload Enable bit
////////////////////////////////////////////////////////////////////////////////
/// @brief DMA_CNDTR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DMA_CNDTR_NDT_Pos (0)
#define DMA_CNDTR_NDT (0xFFFFU << DMA_CNDTR_NDT_Pos) ///< Number of data to Transfer
////////////////////////////////////////////////////////////////////////////////
/// @brief DMA_CPAR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DMA_CPAR_PA_Pos (0)
#define DMA_CPAR_PA (0xFFFFFFFFU << DMA_CPAR_PA_Pos) ///< Peripheral Address
////////////////////////////////////////////////////////////////////////////////
/// @brief DMA_CMAR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define DMA_CMAR_MA_Pos (0)
#define DMA_CMAR_MA (0xFFFFFFFFU << DMA_CMAR_MA_Pos) ///< Peripheral Address
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h
+730
View File
@@ -0,0 +1,730 @@
////////////////////////////////////////////////////////////////////////////////
/// @file reg_iwdg.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_ETH_H
#define __REG_ETH_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#include "reg_common.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief IWDG Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_BASE (AHBPERIPH_BASE + 0x8000) ///< Base Address: 0x40028000
#define ETH ((ETH_TypeDef*) ETH_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 MACCR; ///< configuration register offset 0x0000
__IO u32 MACFFR; ///< frame filter register offset 0x0004
__IO u32 MACHTHR; ///< Hash list high register offset 0x0008
__IO u32 MACHTLR; ///< Hash list low register offset 0x000C
__IO u32 MACMIIAR; ///< MII address register offset 0x0010
__IO u32 MACMIIDR; ///< MII data register offset 0x0014
__IO u32 MACFCR; ///< flow control register offset 0x0018
__IO u32 MACVLANTR; ///< VLAN label register offset 0x001C
__IO u32 RESERVEDX0020[2]; /// 0x0020 ~ 0x0024
__IO u32 MACRWUFFR; /// 0x0028
__IO u32 MACPMTCSR; /// 0x002C
__IO u32 RESERVEDX0030[4]; /// 0x0030 ~ 0x003C
__IO u32 MACA0HR; ///< address 0 high register offset 0x0040
__IO u32 MACA0LR; ///< address 0 low register offset 0x0044
__IO u32 MACA1HR; ///< address 1 high register offset 0x0048
__IO u32 MACA1LR; ///< address 1 low register offset 0x004C
__IO u32 MACA2HR; ///< address 2 high register offset 0x0050
__IO u32 MACA2LR; ///< address 2 low register offset 0x0054
__IO u32 MACA3HR; ///< address 3 high register offset 0x0058
__IO u32 MACA3LR; ///< address 3 low register offset 0x005C
__IO u32 MACA4HR; ///< address 4 high register offset 0x0060
__IO u32 MACA4LR; ///< address 4 low register offset 0x0064
__IO u32 MACA5HR; ///< address 5 high register offset 0x0068
__IO u32 MACA5LR; ///< address 5 low register offset 0x006C
__IO u32 MACA6HR; ///< address 6 high register offset 0x0070
__IO u32 MACA6LR; ///< address 6 low register offset 0x0074
__IO u32 MACA7HR; ///< address 7 high register offset 0x0078
__IO u32 MACA7LR; ///< address 7 low register offset 0x007C
__IO u32 MACA8HR; ///< address 8 high register offset 0x0080
__IO u32 MACA8LR; ///< address 8 low register offset 0x0084
__IO u32 MACA9HR; ///< address 9 high register offset 0x0088
__IO u32 MACA9LR; ///< address 9 low register offset 0x008C
__IO u32 MACA10HR; ///< address 10 high register offset 0x0090
__IO u32 MACA10LR; ///< address 10 low register offset 0x0094
__IO u32 MACA11HR; ///< address 11 high register offset 0x0098
__IO u32 MACA11LR; ///< address 11 low register offset 0x009C
__IO u32 MACA12HR; ///< address 12 high register offset 0x00A0
__IO u32 MACA12LR; ///< address 12 low register offset 0x00A4
__IO u32 MACA13HR; ///< address 13 high register offset 0x00A8
__IO u32 MACA13LR; ///< address 13 low register offset 0x00AC
__IO u32 MACA14HR; ///< address 14 high register offset 0x00B0
__IO u32 MACA14LR; ///< address 14 low register offset 0x00B4
__IO u32 MACA15HR; ///< address 15 high register offset 0x00B8
__IO u32 MACA15LR; ///< address 15 low register offset 0x00BC
__IO u32 MACANCR; ///< Automatic negotiation control register offset 0x00C0
__IO u32 MACANSR; ///< Automatic negotiation of the status register offset 0x00C4
__IO u32 MACANAR; ///< Automatic negotiation of broadcast registers offset 0x00C8
__IO u32 MACANLPAR; ///< Automatic negotiation of link partner capability register offset 0x00CC
__IO u32 MACANER; ///< Automatic negotiation of extension registers offset 0x00D0
__IO u32 MACTBIER; ///< Ten - place interface extension register offset 0x00D4
__IO u32 MACMIISR; ///< MII status register offset 0x00D8
__IO u32 RESERVEDX00DC[9]; ///< offset 0x00DC ~ 0x00FC
__IO u32 MMCCR; ///< MMC controls registers offset 0x0100
__IO u32 MMCRIR; ///< The MMC receives the interrupt register offset 0x0104
__IO u32 MMCTIR; ///< The MMC sends the interrupt register offset 0x0108
__IO u32 MMCRIMR; ///< The MMC receives the interrupt mask register offset 0x010C
__IO u32 MMCTIMR; ///< MMC sends interrupt masking registers offset 0x0110
__IO u32 RESERVEDX0114[14]; ///< offset 0x0114 ~ 0x0148
__IO u32 MMCTGFSCCR; ///< A good frame counter register that MMC sends after a single conflict offset 0x014C
__IO u32 MMCTGFMSCCR; ///< A good frame counter register that MMC sends after multiple collisions offset 0x0150
__IO u32 RESERVEDX0154[5]; ///< offset 0x0154 ~ 0x0164
__IO u32 MMCTGFCR; ///< Good frame counter register sent by MMC offset 0x0168
__IO u32 RESERVEDX016C[10]; ///< offset 0x016C ~ 0x0190
__IO u32 MMCRFCECR; ///< Ethernet MMC with CRC error counter register receives frame register offset 0x0194
__IO u32 MMCRFAECR; ///< Ethernet MMC receives frames with alignment error counter registers offset 0x0198
__IO u32 RESERVEDX019C[10]; ///< offset 0x019C ~ 0x01C0
__IO u32 MMCRGUFCR; ///< Good unicast frame counter register received by MMC offset 0x01C4
__IO u32 RESERVEDx01C8[910]; ///< offset 0x01C8 ~ 0x0FFC
__IO u32 DMABMR; ///< Bus mode register offset 0x1000
__IO u32 DMATPDR; ///< DMA sends the polling request register offset 0x1004
__IO u32 DMARPDR; ///< DMA receives the polling request register offset 0x1008
__IO u32 DMARDLAR; ///< DMA receives a list of descriptor addresses offset 0x100C
__IO u32 DMATDLAR; ///< DMA sends the descriptor list address offset 0x1010
__IO u32 DMASR; ///< DMA status register offset 0x1014
__IO u32 DMAOMR; ///< DMA working mode register offset 0x1018
__IO u32 DMAIER; ///< DMA interrupt enablement register offset 0x101C
__IO u32 DMAMFBOCR; ///< DMA lost frames and cache overflow counter registers offset 0x1020
__IO u32 DMARSWTR; /// 0x1024
__IO u32 RESERVEDX1028[8]; /// 0x1028 ~ 0x1044
__IO u32 DMACHTDR; /// 0x1048
__IO u32 DMACHRDR; /// 0x104C
__IO u32 DMACHTBAR; ///< DMA is currently sending the cache address register offset 0x1050
__IO u32 DMACHRBAR; ///< DMA currently receives the cache address register offset 0x1054
} ETH_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACCR_WD_Pos (23)
#define ETH_MACCR_WD (0x01U << ETH_MACCR_WD_Pos) ///< Watchdog disable
#define ETH_MACCR_JD_Pos (22)
#define ETH_MACCR_JD (0x01U << ETH_MACCR_JD_Pos) ///< Jabber disable
#define ETH_MACCR_FBE_Pos (21)
#define ETH_MACCR_FBE (0x01U << ETH_MACCR_FBE_Pos) ///< Frame Burst Enable
#define ETH_MACCR_JE_Pos (20)
#define ETH_MACCR_JE (0x01U << ETH_MACCR_JE_Pos) ///< Jumbo Frame Enable
#define ETH_MACCR_IFG_Pos (17) ///< Inter-frame gap
#define ETH_MACCR_IFG_96Bit (0x00U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 96Bit
#define ETH_MACCR_IFG_88Bit (0x01U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 88Bit
#define ETH_MACCR_IFG_80Bit (0x02U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 80Bit
#define ETH_MACCR_IFG_72Bit (0x03U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 72Bit
#define ETH_MACCR_IFG_64Bit (0x04U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 64Bit
#define ETH_MACCR_IFG_56Bit (0x05U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 56Bit
#define ETH_MACCR_IFG_48Bit (0x06U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 48Bit
#define ETH_MACCR_IFG_40Bit (0x07U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 40Bit
#define ETH_MACCR_FES_Pos (14)
#define ETH_MACCR_FES (0x01U << ETH_MACCR_FES_Pos) ///< Fast ethernet speed
#define ETH_MACCR_ROD_Pos (13)
#define ETH_MACCR_ROD (0x01U << ETH_MACCR_ROD_Pos) ///< Receive own disable
#define ETH_MACCR_LM_Pos (12)
#define ETH_MACCR_LM (0x01U << ETH_MACCR_LM_Pos) ///< loopback mode
#define ETH_MACCR_DM_Pos (11)
#define ETH_MACCR_DM (0x01U << ETH_MACCR_DM_Pos) ///< Duplex mode
#define ETH_MACCR_IPCO_Pos (10)
#define ETH_MACCR_IPCO (0x01U << ETH_MACCR_IPCO_Pos) ///< IP Checksum offload
#define ETH_MACCR_RD_Pos (9)
#define ETH_MACCR_RD (0x01U << ETH_MACCR_RD_Pos) ///< Retry disable
#define ETH_MACCR_APCS_Pos (8)
#define ETH_MACCR_APCS (0x01U << ETH_MACCR_APCS_Pos) ///< Automatic Pad/CRC stripping
#define ETH_MACCR_BL_Pos (5) ///< Back-off limit: random integer number (r) of slot time delays before rescheduling a transmission attempt during retries after a collision: 0 =< r <2^k
#define ETH_MACCR_BL_10 (0x00U << ETH_MACCR_BL_Pos) ///< k = min (n, 10)
#define ETH_MACCR_BL_8 (0x01U << ETH_MACCR_BL_Pos) ///< k = min (n, 8)
#define ETH_MACCR_BL_4 (0x02U << ETH_MACCR_BL_Pos) ///< k = min (n, 4)
#define ETH_MACCR_BL_1 (0x03U << ETH_MACCR_BL_Pos) ///< k = min (n, 1)
#define ETH_MACCR_DC_Pos (4)
#define ETH_MACCR_DC (0x01U << ETH_MACCR_DC_Pos) ///< Defferal check
#define ETH_MACCR_TE_Pos (3)
#define ETH_MACCR_TE (0x01U << ETH_MACCR_TE_Pos) ///< Transmitter enable
#define ETH_MACCR_RE_Pos (2)
#define ETH_MACCR_RE (0x01U << ETH_MACCR_RE_Pos) ///< Receiver enable
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACFFR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACFFR_RA_Pos (31)
#define ETH_MACFFR_RA (0x01U << ETH_MACFFR_RA_Pos) ///< Receive all
#define ETH_MACFFR_SAF_Pos (9)
#define ETH_MACFFR_SAF (0x01U << ETH_MACFFR_SAF_Pos) ///< Source address filter enable
#define ETH_MACFFR_SAIF_Pos (8)
#define ETH_MACFFR_SAIF (0x01U << ETH_MACFFR_SAIF_Pos) ///< SA inverse filtering
#define ETH_MACFFR_PCF_Pos (6)
#define ETH_MACFFR_PCF (0x03U << ETH_MACFFR_PCF_Pos) ///< Pass control frames: 3 cases
#define ETH_MACFFR_PCF_BlockAll (0x01U << ETH_MACFFR_PCF_Pos) ///< MAC filters all control frames from reaching the application
#define ETH_MACFFR_PCF_ForwardAll (0x02U << ETH_MACFFR_PCF_Pos) ///< MAC forwards all control frames to application even if they fail the Address Filter
#define ETH_MACFFR_PCF_ForwardPassedAddrFilter (0x03U << ETH_MACFFR_PCF_Pos) ///< MAC forwards control frames that pass the Address Filter.
#define ETH_MACFFR_BFD_Pos (5)
#define ETH_MACFFR_BFD (0x01U << ETH_MACFFR_BFD_Pos) ///< Broadcast frame disable
#define ETH_MACFFR_PAM_Pos (4)
#define ETH_MACFFR_PAM (0x01U << ETH_MACFFR_PAM_Pos) ///< Pass all mutlicast
#define ETH_MACFFR_DAIF_Pos (3)
#define ETH_MACFFR_DAIF (0x01U << ETH_MACFFR_DAIF_Pos) ///< DA Inverse filtering
#define ETH_MACFFR_HM_Pos (2)
#define ETH_MACFFR_HM (0x01U << ETH_MACFFR_HM_Pos) ///< Hash multicast
#define ETH_MACFFR_HU_Pos (1)
#define ETH_MACFFR_HU (0x01U << ETH_MACFFR_HU_Pos) ///< Hash unicast
#define ETH_MACFFR_PM_Pos (0)
#define ETH_MACFFR_PM (0x01U << ETH_MACFFR_PM_Pos) ///< Promiscuous mode
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACHTHR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACHTHR_HTH (0xFFFFFFFFU) ///< Hash table high
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACHTLR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACHTLR_HTL (0xFFFFFFFFU) ///< Hash table low
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACMIIAR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACMIIAR_PA_Pos (11)
#define ETH_MACMIIAR_PA (0x1FU << ETH_MACMIIAR_PA_Pos) ///< Physical layer address
#define ETH_MACMIIAR_MR_Pos (6)
#define ETH_MACMIIAR_MR (0x1FU << ETH_MACMIIAR_MR_Pos) ///< MII register in the selected PHY
#define ETH_MACMIIAR_CR_Pos (2)
#define ETH_MACMIIAR_CR (0x07U << ETH_MACMIIAR_CR_Pos) ///< CR clock range: 6 cases
#define ETH_MACMIIAR_CR_Div42 (0x00U << ETH_MACMIIAR_CR_Pos) ///< HCLK:60-100 MHz; MDC clock= HCLK/42
#define ETH_MACMIIAR_CR_Div62 (0x01U << ETH_MACMIIAR_CR_Pos) ///< HCLK:100-150 MHz; MDC clock= HCLK/62
#define ETH_MACMIIAR_CR_Div16 (0x02U << ETH_MACMIIAR_CR_Pos) ///< HCLK:20-35 MHz; MDC clock= HCLK/16
#define ETH_MACMIIAR_CR_Div26 (0x03U << ETH_MACMIIAR_CR_Pos) ///< HCLK:35-60 MHz; MDC clock= HCLK/26
#define ETH_MACMIIAR_CR_Div102 (0x04U << ETH_MACMIIAR_CR_Pos) ///< HCLK:150-168 MHz; MDC clock= HCLK/102
#define ETH_MACMIIAR_MW_Pos (1)
#define ETH_MACMIIAR_MW (0x01U << ETH_MACMIIAR_MW_Pos) ///< MII write
#define ETH_MACMIIAR_MB_Pos (0)
#define ETH_MACMIIAR_MB (0x01U << ETH_MACMIIAR_MB_Pos) ///< MII busy
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACMIIDR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACMIIDR_MD (0x0000FFFFU) ///< MII data: read/write data from/to PHY
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACFCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACFCR_PT_Pos (16)
#define ETH_MACFCR_PT ((u32)0xFFFF << ETH_MACFCR_PT_Pos) ///< Pause time
#define ETH_MACFCR_PLT_Pos (4)
#define ETH_MACFCR_PLT (0x03U << ETH_MACFCR_PLT_Pos) ///< Pause low threshold: 4 cases
#define ETH_MACFCR_PLT_Minus4 (0x00U << ETH_MACFCR_PLT_Pos) ///< Pause time minus 4 slot times
#define ETH_MACFCR_PLT_Minus28 (0x01U << ETH_MACFCR_PLT_Pos) ///< Pause time minus 28 slot times
#define ETH_MACFCR_PLT_Minus144 (0x02U << ETH_MACFCR_PLT_Pos) ///< Pause time minus 144 slot times
#define ETH_MACFCR_PLT_Minus256 (0x03U << ETH_MACFCR_PLT_Pos) ///< Pause time minus 256 slot times
#define ETH_MACFCR_UPFD_Pos (3)
#define ETH_MACFCR_UPFD (0x01U << ETH_MACFCR_UPFD_Pos) ///< Unicast pause frame detect
#define ETH_MACFCR_RFCE_Pos (2)
#define ETH_MACFCR_RFCE (0x01U << ETH_MACFCR_RFCE_Pos) ///< Receive flow control enable
#define ETH_MACFCR_TFCE_Pos (1)
#define ETH_MACFCR_TFCE (0x01U << ETH_MACFCR_TFCE_Pos) ///< Transmit flow control enable
#define ETH_MACFCR_FCBBPA_Pos (0)
#define ETH_MACFCR_FCBBPA (0x01U << ETH_MACFCR_FCBBPA_Pos) ///< Flow control busy/backpressure activate
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACVLANTR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACVLANTR_VLANTI (0x0000FFFFU) ///< VLAN tag identifier (for receive frames)
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACRWUFFR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACRWUFFR_D (0xFFFFFFFFU) ///< Wake-up frame filter register data
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACPMTCSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACPMTCSR_WFFRPR_Pos (31) ///< Wake-Up Frame Filter Register Pointer Reset
#define ETH_MACPMTCSR_WFFRPR (0x01U << ETH_MACPMTCSR_WFFRPR_Pos) ///< Wake-Up Frame Filter Register Pointer Reset
#define ETH_MACPMTCSR_GU_Pos (9)
#define ETH_MACPMTCSR_GU (0x01U << ETH_MACPMTCSR_GU_Pos) ///< Global Unicast
#define ETH_MACPMTCSR_WFR_Pos (6)
#define ETH_MACPMTCSR_WFR (0x01U << ETH_MACPMTCSR_WFR_Pos) ///< Wake-Up Frame Received
#define ETH_MACPMTCSR_MPR_Pos (5)
#define ETH_MACPMTCSR_MPR (0x01U << ETH_MACPMTCSR_MPR_Pos) ///< Magic Packet Received
#define ETH_MACPMTCSR_WFE_Pos (2)
#define ETH_MACPMTCSR_WFE (0x01U << ETH_MACPMTCSR_WFE_Pos) ///< Wake-Up Frame Enable
#define ETH_MACPMTCSR_MPE_Pos (1)
#define ETH_MACPMTCSR_MPE (0x01U << ETH_MACPMTCSR_MPE_Pos) ///< Magic Packet Enable
#define ETH_MACPMTCSR_PD_Pos (0)
#define ETH_MACPMTCSR_PD (0x01U << ETH_MACPMTCSR_PD_Pos) ///< Power Down
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACA0HR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACA0HR_MACA0H ((u32)0x0000FFFF) ///< MAC address0 high
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACA0LR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACA0LR_MACA0L ((u32)0xFFFFFFFF) ///< MAC address0 low
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACA1HR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACA1HR_AE_Pos (31)
#define ETH_MACA1HR_AE (0x01U << ETH_MACA1HR_AE_Pos) ///< Address enable
#define ETH_MACA1HR_SA_Pos (30)
#define ETH_MACA1HR_SA (0x01U << ETH_MACA1HR_SA_Pos) ///< Source address
#define ETH_MACA1HR_MBC_Pos (24)
#define ETH_MACA1HR_MBC (0x3FU << ETH_MACA1HR_MBC_Pos) ///< Mask byte control: bits to mask for comparison of the MAC Address bytes
#define ETH_MACA1HR_MBC_HBits15_8 (0x20U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address high reg bits [15:8]
#define ETH_MACA1HR_MBC_HBits7_0 (0x10U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address high reg bits [7:0]
#define ETH_MACA1HR_MBC_LBits31_24 (0x08U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address low reg bits [31:24]
#define ETH_MACA1HR_MBC_LBits23_16 (0x04U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address low reg bits [23:16]
#define ETH_MACA1HR_MBC_LBits15_8 (0x02U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address low reg bits [15:8]
#define ETH_MACA1HR_MBC_LBits7_0 (0x00U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address low reg bits [7:0]
#define ETH_MACA1HR_MACA1H_Pos (0)
#define ETH_MACA1HR_MACA1H (0x0000FFFFU << ETH_MACA1HR_MACA1H_Pos) ///< MAC address1 high
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACA1LR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACA1LR_MACA1L (0xFFFFFFFFU) ///< MAC address1 low
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACA2HR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACA2HR_AE_Pos (31)
#define ETH_MACA2HR_AE (0x01U << ETH_MACA2HR_AE_Pos) ///< Address enable
#define ETH_MACA2HR_SA_Pos (30)
#define ETH_MACA2HR_SA (0x01U << ETH_MACA2HR_SA_Pos) ///< Source address
#define ETH_MACA2HR_MBC_Pos (24)
#define ETH_MACA2HR_MBC (0x3FU << ETH_MACA2HR_MBC_Pos) ///< Mask byte control: bits to mask for comparison of the MAC Address bytes
#define ETH_MACA2HR_MBC_HBits15_8 (0x20U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address high reg bits [15:8]
#define ETH_MACA2HR_MBC_HBits7_0 (0x10U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address high reg bits [7:0]
#define ETH_MACA2HR_MBC_LBits31_24 (0x08U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address low reg bits [31:24]
#define ETH_MACA2HR_MBC_LBits23_16 (0x04U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address low reg bits [23:16]
#define ETH_MACA2HR_MBC_LBits15_8 (0x02U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address low reg bits [15:8]
#define ETH_MACA2HR_MBC_LBits7_0 (0x00U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address low reg bits [7:0]
#define ETH_MACA2HR_MACA2H_Pos (0)
#define ETH_MACA2HR_MACA2H (0x0000FFFFU << ETH_MACA2HR_MACA2H_Pos) ///< MAC address2 high
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACA2LR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACA2LR_MACA2L (0xFFFFFFFFU) ///< MAC address2 low
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACANCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACANCR_LR_Pos (17)
#define ETH_MACANCR_LR (0x01U << ETH_MACANCR_LR_Pos) ///< Lock to Reference
#define ETH_MACANCR_ECD_Pos (16)
#define ETH_MACANCR_ECD (0x01U << ETH_MACANCR_ECD_Pos) ///< Enable Comma Detect
#define ETH_MACANCR_ELE_Pos (14)
#define ETH_MACANCR_ELE (0x01U << ETH_MACANCR_ELE_Pos) ///< External Loopback Enable
#define ETH_MACANCR_ANE_Pos (12)
#define ETH_MACANCR_ANE (0x01U << ETH_MACANCR_ANE_Pos) ///< Auto-Negotiation Enable
#define ETH_MACANCR_RAN_Pos (9)
#define ETH_MACANCR_RAN (0x01U << ETH_MACANCR_RAN_Pos) ///< Restart Auto-Negotiation
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACANSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACANSR_ES_Pos (8)
#define ETH_MACANSR_ES (0x01U << ETH_MACANSR_ES_Pos) ///< Extended Status
#define ETH_MACANSR_ANC_Pos (5)
#define ETH_MACANSR_ANC (0x01U << ETH_MACANSR_ANC_Pos) ///< Auto-Negotiation Complete
#define ETH_MACANSR_ANA_Pos (3)
#define ETH_MACANSR_ANA (0x01U << ETH_MACANSR_ANA_Pos) ///< Auto-Negotiation Ability
#define ETH_MACANSR_LS_Pos (2)
#define ETH_MACANSR_LS (0x01U << ETH_MACANSR_LS_Pos) ///< Link Status
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACANAR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACANAR_NP_Pos (15)
#define ETH_MACANAR_NP (0x01U << ETH_MACANAR_NP_Pos) ///< Next Page Support
#define ETH_MACANAR_RFE_Pos (12)
#define ETH_MACANAR_RFE (0x01U << ETH_MACANAR_RFE_Pos) ///< Remote Fault Encoding
#define ETH_MACANAR_PSE_Pos (7)
#define ETH_MACANAR_PSE (0x01U << ETH_MACANAR_PSE_Pos) ///< Pause Encoding
#define ETH_MACANAR_HD_Pos (6)
#define ETH_MACANAR_HD (0x01U << ETH_MACANAR_HD_Pos) ///< support Half-Duplex
#define ETH_MACANAR_FD_Pos (5)
#define ETH_MACANAR_FD (0x01U << ETH_MACANAR_FD_Pos) ///< support Full-Durplex
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACANLPAR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACANLPAR_NP_Pos (15)
#define ETH_MACANLPAR_NP (0x01U << ETH_MACANLPAR_NP_Pos) ///< Next Page Support
#define ETH_MACANLPAR_ACK_Pos (14)
#define ETH_MACANLPAR_ACK (0x01U << ETH_MACANLPAR_ACK_Pos) ///< Acknowledge
#define ETH_MACANLPAR_RFE_Pos (12)
#define ETH_MACANLPAR_RFE (0x01U << ETH_MACANLPAR_RFE_Pos) ///< Remote Fault Encoding
#define ETH_MACANLPAR_PSE_Pos (7)
#define ETH_MACANLPAR_PSE (0x01U << ETH_MACANLPAR_PSE_Pos) ///< Pause Encoding
#define ETH_MACANLPAR_HD_Pos (6)
#define ETH_MACANLPAR_HD (0x01U << ETH_MACANLPAR_HD_Pos) ///< support Half-Duplex
#define ETH_MACANLPAR_FD_Pos (5)
#define ETH_MACANLPAR_FD (0x01U << ETH_MACANLPAR_FD_Pos) ///< support Full-Durplex
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACANER Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACANER_NPA_Pos (2)
#define ETH_MACANER_NPA (0x01U << ETH_MACANER_NPA_Pos) ///< Next Page Ability
#define ETH_MACANER_NPR_Pos (1)
#define ETH_MACANER_NPR (0x01U << ETH_MACANER_NPR_Pos) ///< New Page Received
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACTBIER Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACTBIER_GFD_Pos (15)
#define ETH_MACTBIER_GFD (0x01U << ETH_MACTBIER_GFD_Pos) ///< 1000BASE-X Full-Duplex Capable
#define ETH_MACTBIER_GHD_Pos (14)
#define ETH_MACTBIER_GHD (0x01U << ETH_MACTBIER_GHD_Pos) ///< 1000BASE-X Half-Duplex Capable
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MACMIISR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MACMIISR_LS_Pos (3)
#define ETH_MACMIISR_LS (0x01U << ETH_MACMIISR_LS_Pos) ///< Link Status
#define ETH_MACMIISR_LSP_Pos (1)
#define ETH_MACMIISR_LSP_2_5 (0x00U << ETH_MACMIISR_LSP_Pos) ///< Link Speed 2.5 MHz
#define ETH_MACMIISR_LSP_25 (0x01U << ETH_MACMIISR_LSP_Pos) ///< Link Speed 25 MHz
#define ETH_MACMIISR_LSP_125 (0x02U << ETH_MACMIISR_LSP_Pos) ///< Link Speed 125 MHz
#define ETH_MACMIISR_LM_Pos (0)
#define ETH_MACMIISR_LM (0x01U << ETH_MACMIISR_LM_Pos) ///< Link Mode : Full-Duplex Capable
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MMCCR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MMCCR_MCFHP ((u32)0x00000020) ///< MMC counter Full-Half preset
#define ETH_MMCCR_MCP ((u32)0x00000010) ///< MMC counter preset
#define ETH_MMCCR_MCF ((u32)0x00000008) ///< MMC Counter Freeze
#define ETH_MMCCR_ROR_Pos (2)
#define ETH_MMCCR_ROR (0x01U << ETH_MMCCR_ROR_Pos) ///< Reset on Read
#define ETH_MMCCR_CSR_Pos (1)
#define ETH_MMCCR_CSR (0x01U << ETH_MMCCR_CSR_Pos) ///< Counter Stop Rollover
#define ETH_MMCCR_CR_Pos (0)
#define ETH_MMCCR_CR (0x01U << ETH_MMCCR_CR_Pos) ///< Counters Reset
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MMCRIR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MMCRIR_RGUF_Pos (17)
#define ETH_MMCRIR_RGUFS (0x01U << ETH_MMCRIR_RGUF_Pos) ///< Set when Rx good unicast frames counter reaches half the maximum value
#define ETH_MMCRIR_RFAES_Pos (6)
#define ETH_MMCRIR_RFAES (0x01U << ETH_MMCRIR_RFAES_Pos) ///< Set when Rx alignment error counter reaches half the maximum value
#define ETH_MMCRIR_RFCES_Pos (5)
#define ETH_MMCRIR_RFCES (0x01U << ETH_MMCRIR_RFCES_Pos) ///< Set when Rx crc error counter reaches half the maximum value
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MMCTIR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MMCTIR_TGFS_Pos (21)
#define ETH_MMCTIR_TGFS (0x01U << ETH_MMCTIR_TGFS_Pos) ///< Set when Tx good frame count counter reaches half the maximum value
#define ETH_MMCTIR_TGFMSCS_Pos (15)
#define ETH_MMCTIR_TGFMSCS (0x01U << ETH_MMCTIR_TGFMSCS_Pos) ///< Set when Tx good multi col counter reaches half the maximum value
#define ETH_MMCTIR_TGFSCS_Pos (14)
#define ETH_MMCTIR_TGFSCS (0x01U << ETH_MMCTIR_TGFSCS_Pos) ///< Set when Tx good single col counter reaches half the maximum value
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MMCRIMR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MMCRIMR_RGUFM_Pos (17)
#define ETH_MMCRIMR_RGUFM (0x01U << ETH_MMCRIMR_RGUFM_Pos) ///< Mask the interrupt when Rx good unicast frames counter reaches half the maximum value
#define ETH_MMCRIMR_RFAEM_Pos (6)
#define ETH_MMCRIMR_RFAEM (0x01U << ETH_MMCRIMR_RFAEM_Pos) ///< Mask the interrupt when when Rx alignment error counter reaches half the maximum value
#define ETH_MMCRIMR_RFCEM_Pos (5)
#define ETH_MMCRIMR_RFCEM (0x01U << ETH_MMCRIMR_RFCEM_Pos) ///< Mask the interrupt when Rx crc error counter reaches half the maximum value
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MMCTIMR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MMCTIMR_TGFM_Pos (21)
#define ETH_MMCTIMR_TGFM (0x01U << ETH_MMCTIMR_TGFM_Pos) ///< Mask the interrupt when Tx good frame count counter reaches half the maximum value
#define ETH_MMCTIMR_TGFMSCM_Pos (15)
#define ETH_MMCTIMR_TGFMSCM (0x01U << ETH_MMCTIMR_TGFMSCM_Pos) ///< Mask the interrupt when Tx good multi col counter reaches half the maximum value
#define ETH_MMCTIMR_TGFSCM_Pos (14)
#define ETH_MMCTIMR_TGFSCM (0x01U << ETH_MMCTIMR_TGFSCM_Pos) ///< Mask the interrupt when Tx good single col counter reaches half the maximum value
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MMCTGFSCCR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MMCTGFSCCR_TGFSCC (0xFFFFFFFFU) ///< Number of successfully transmitted frames after a single collision in Half-duplex mode.
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MMCTGFMSCCR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MMCTGFMSCCR_TGFMSCC (0xFFFFFFFFU) ///< Number of successfully transmitted frames after more than a single collision in Half-duplex mode.
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MMCTGFCR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MMCTGFCR_TGFC (0xFFFFFFFFU) ///< Number of good frames transmitted.
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MMCRFCECR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MMCRFCECR_RFCEC (0xFFFFFFFFU) ///< Number of frames received with CRC error.
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MMCRFAECR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MMCRFAECR_RFAEC (0xFFFFFFFFU) ///< Number of frames received with alignment (dribble) error
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_MMCRGUFCR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_MMCRGUFCR_RGUFC (0xFFFFFFFFU) ///< Number of good unicast frames received.
/// @brief ETH_DMABMR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_DMABMR_FB_Pos (16)
#define ETH_DMABMR_FB (0x01U << ETH_DMABMR_FB_Pos) ///< Fixed Burst
#define ETH_DMABMR_RTPR_Pos (14)
#define ETH_DMABMR_RTPR (0x03U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio
#define ETH_DMABMR_RTPR_1_1 (0x00U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio
#define ETH_DMABMR_RTPR_2_1 (0x01U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio
#define ETH_DMABMR_RTPR_3_1 (0x02U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio
#define ETH_DMABMR_RTPR_4_1 (0x03U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio
#define ETH_DMABMR_PBL_Pos (8)
#define ETH_DMABMR_PBL (0x3FU<< ETH_DMABMR_PBL_Pos) //< Programmable burst length
#define ETH_DMABMR_PBL_1Beat (0x01U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1
#define ETH_DMABMR_PBL_2Beat (0x02U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2
#define ETH_DMABMR_PBL_4Beat (0x04U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4
#define ETH_DMABMR_PBL_8Beat (0x08U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8
#define ETH_DMABMR_PBL_16Beat (0x10U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16
#define ETH_DMABMR_PBL_32Beat (0x20U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32
#define ETH_DMABMR_PBL_4xPBL_4Beat (0x10001U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4
#define ETH_DMABMR_PBL_4xPBL_8Beat (0x10002U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8
#define ETH_DMABMR_PBL_4xPBL_16Beat (0x10004U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16
#define ETH_DMABMR_PBL_4xPBL_32Beat (0x10008U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32
#define ETH_DMABMR_PBL_4xPBL_64Beat (0x10010U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64
#define ETH_DMABMR_PBL_4xPBL_128Beat (0x10020U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128
#define ETH_DMABMR_DSL_Pos (2)
#define ETH_DMABMR_DSL (0x01U << ETH_DMABMR_DSL_Pos) ///< Descriptor Skip Length
#define ETH_DMABMR_DA_Pos (1)
#define ETH_DMABMR_DA (0x1FU << ETH_DMABMR_DA_Pos) ///< DMA arbitration scheme
#define ETH_DMABMR_SR_Pos (0)
#define ETH_DMABMR_SR (0x01U << ETH_DMABMR_SR_Pos) ///< Software reset
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_DMATPDR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_DMATPDR_TPD (0xFFFFFFFFU) ///< Transmit poll demand
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_DMARPDR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_DMARPDR_RPD (0xFFFFFFFFU) ///< Receive poll demand
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_DMARDLAR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_DMARDLAR_SRL (0xFFFFFFFFU) ///< Start of receive list
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_DMATDLAR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_DMATDLAR_STL (0xFFFFFFFFU) ///< Start of transmit list
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_DMASR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_DMASR_PMTS_Pos (28)
#define ETH_DMASR_PMTS (0x01U << ETH_DMASR_PMTS_Pos) ///< PMT status
#define ETH_DMASR_MMCS_Pos (27)
#define ETH_DMASR_MMCS (0x01U << ETH_DMASR_MMCS_Pos) ///< MMC status
#define ETH_DMASR_LIS_Pos (26)
#define ETH_DMASR_LIS (0x01U << ETH_DMASR_LIS_Pos) ///< GMAC Line interface Status
#define ETH_DMASR_EBS_Pos (23)
#define ETH_DMASR_EBS (0x07U << ETH_DMASR_EBS_Pos) ///< Error bits status
#define ETH_DMASR_EBS_DescAccess (0x04U << ETH_DMASR_EBS_Pos) ///< Error bits 0-data buffer, 1-desc. access
#define ETH_DMASR_EBS_ReadTransf (0x02U << ETH_DMASR_EBS_Pos) ///< Error bits 0-write trnsf, 1-read transfr
#define ETH_DMASR_EBS_DataTransfTx (0x01U << ETH_DMASR_EBS_Pos) ///< Error bits 0-Rx DMA, 1-Tx DMA
#define ETH_DMASR_TPS_Pos (20)
#define ETH_DMASR_TPS (0x007U << ETH_DMASR_TPS_Pos) ///< Transmit process state
#define ETH_DMASR_TPS_Stopped (0x000U << ETH_DMASR_TPS_Pos) ///< Stopped - Reset or Stop Tx Command issued
#define ETH_DMASR_TPS_Fetching (0x001U << ETH_DMASR_TPS_Pos) ///< Running - fetching the Tx descriptor
#define ETH_DMASR_TPS_Waiting (0x002U << ETH_DMASR_TPS_Pos) ///< Running - waiting for status
#define ETH_DMASR_TPS_Reading (0x003U << ETH_DMASR_TPS_Pos) ///< Running - reading the data from host memory
#define ETH_DMASR_TPS_Suspended (0x006U << ETH_DMASR_TPS_Pos) ///< Suspended - Tx Descriptor unavailabe
#define ETH_DMASR_TPS_Closing (0x007U << ETH_DMASR_TPS_Pos) ///< Running - closing Rx descriptor
#define ETH_DMASR_RPS_Pos (17)
#define ETH_DMASR_RPS (0x07U << ETH_DMASR_RPS_Pos) ///< Receive process state
#define ETH_DMASR_RPS_Stopped (0x00U << ETH_DMASR_RPS_Pos) ///< Stopped - Reset or Stop Rx Command issued
#define ETH_DMASR_RPS_Fetching (0x01U << ETH_DMASR_RPS_Pos) ///< Running - fetching the Rx descriptor
#define ETH_DMASR_RPS_Waiting (0x03U << ETH_DMASR_RPS_Pos) ///< Running - waiting for packet
#define ETH_DMASR_RPS_Suspended (0x04U << ETH_DMASR_RPS_Pos) ///< Suspended - Rx Descriptor unavailable
#define ETH_DMASR_RPS_Closing (0x05U << ETH_DMASR_RPS_Pos) ///< Running - closing descriptor
#define ETH_DMASR_RPS_Queuing (0x07U << ETH_DMASR_RPS_Pos) ///< Running - queuing the recieve frame into host memory
#define ETH_DMASR_NIS_Pos (16)
#define ETH_DMASR_NIS (0x01U << ETH_DMASR_NIS_Pos ) ///< Normal interrupt summary
#define ETH_DMASR_AIS_Pos (15)
#define ETH_DMASR_AIS (0x01U << ETH_DMASR_AIS_Pos ) ///< Abnormal interrupt summary
#define ETH_DMASR_ERS_Pos (14)
#define ETH_DMASR_ERS (0x01U << ETH_DMASR_ERS_Pos ) ///< Early receive status
#define ETH_DMASR_FBES_Pos (13)
#define ETH_DMASR_FBES (0x01U << ETH_DMASR_FBES_Pos) ///< Fatal bus error status
#define ETH_DMASR_ETS_Pos (10)
#define ETH_DMASR_ETS (0x01U << ETH_DMASR_ETS_Pos ) ///< Early transmit status
#define ETH_DMASR_RWTS_Pos (9)
#define ETH_DMASR_RWTS (0x01U << ETH_DMASR_RWTS_Pos) ///< Receive watchdog timeout status
#define ETH_DMASR_RPSS_Pos (8)
#define ETH_DMASR_RPSS (0x01U << ETH_DMASR_RPSS_Pos) ///< Receive process stopped status
#define ETH_DMASR_RBUS_Pos (7)
#define ETH_DMASR_RBUS (0x01U << ETH_DMASR_RBUS_Pos) ///< Receive buffer unavailable status
#define ETH_DMASR_RS_Pos (6)
#define ETH_DMASR_RS (0x01U << ETH_DMASR_RS_Pos ) ///< Receive status
#define ETH_DMASR_TUS_Pos (5)
#define ETH_DMASR_TUS (0x01U << ETH_DMASR_TUS_Pos ) ///< Transmit underflow status
#define ETH_DMASR_ROS_Pos (4)
#define ETH_DMASR_ROS (0x01U << ETH_DMASR_ROS_Pos ) ///< Receive overflow status
#define ETH_DMASR_TJTS_Pos (3)
#define ETH_DMASR_TJTS (0x01U << ETH_DMASR_TJTS_Pos) ///< Transmit jabber timeout status
#define ETH_DMASR_TBUS_Pos (2)
#define ETH_DMASR_TBUS (0x01U << ETH_DMASR_TBUS_Pos) ///< Transmit buffer unavailable status
#define ETH_DMASR_TPSS_Pos (1)
#define ETH_DMASR_TPSS (0x01U << ETH_DMASR_TPSS_Pos) ///< Transmit process stopped status
#define ETH_DMASR_TS_Pos (0)
#define ETH_DMASR_TS (0x01U << ETH_DMASR_TS_Pos ) ///< Transmit status
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_DMAOMR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_DMAOMR_TSF_Pos (21)
#define ETH_DMAOMR_TSF (0x01U << ETH_DMAOMR_TSF_Pos) ///< Transmit store and forward
#define ETH_DMAOMR_FTF_Pos (20)
#define ETH_DMAOMR_FTF (0x01U << ETH_DMAOMR_FTF_Pos) ///< Flush transmit FIFO
#define ETH_DMAOMR_TTC_Pos (14)
#define ETH_DMAOMR_TTC (0x07U << ETH_DMAOMR_TTC_Pos) ///< Transmit threshold control
#define ETH_DMAOMR_TTC_64Bytes (0x00U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 64 Bytes
#define ETH_DMAOMR_TTC_128Bytes (0x01U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 128 Bytes
#define ETH_DMAOMR_TTC_192Bytes (0x02U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 192 Bytes
#define ETH_DMAOMR_TTC_256Bytes (0x03U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 256 Bytes
#define ETH_DMAOMR_TTC_40Bytes (0x04U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 40 Bytes
#define ETH_DMAOMR_TTC_32Bytes (0x05U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 32 Bytes
#define ETH_DMAOMR_TTC_24Bytes (0x06U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 24 Bytes
#define ETH_DMAOMR_TTC_16Bytes (0x07U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 16 Bytes
#define ETH_DMAOMR_ST_Pos (13)
#define ETH_DMAOMR_ST (0x01U << ETH_DMAOMR_ST_Pos ) ///< Start/stop transmission command
#define ETH_DMAOMR_RFD_Pos (11)
#define ETH_DMAOMR_RFD1 (0x00U << ETH_DMAOMR_RFD_Pos ) ///< Threshold for failure flow control 1 byte
#define ETH_DMAOMR_RFD2 (0x01U << ETH_DMAOMR_RFD_Pos ) ///< Threshold for failure flow control 2 byte
#define ETH_DMAOMR_RFD3 (0x02U << ETH_DMAOMR_RFD_Pos ) ///< Threshold for failure flow control 3 byte
#define ETH_DMAOMR_RFD4 (0x03U << ETH_DMAOMR_RFD_Pos ) ///< Threshold for failure flow control 4 byte
#define ETH_DMAOMR_RFA_Pos (9)
#define ETH_DMAOMR_RFA1 (0x00U << ETH_DMAOMR_RFA_Pos ) ///< Activate the threshold for flow control 1 byte
#define ETH_DMAOMR_RFA2 (0x01U << ETH_DMAOMR_RFA_Pos ) ///< Activate the threshold for flow control 2 byte
#define ETH_DMAOMR_RFA3 (0x02U << ETH_DMAOMR_RFA_Pos ) ///< Activate the threshold for flow control 3 byte
#define ETH_DMAOMR_RFA4 (0x03U << ETH_DMAOMR_RFA_Pos ) ///< Activate the threshold for flow control 4 byte
#define ETH_DMAOMR_EFC_Pos (8)
#define ETH_DMAOMR_EFC (0x01U << ETH_DMAOMR_EFC_Pos ) ///< Enable HW Flow Control
#define ETH_DMAOMR_FEF_Pos (7)
#define ETH_DMAOMR_FEF (0x01U << ETH_DMAOMR_FEF_Pos ) ///< Forward error frames
#define ETH_DMAOMR_FUGF_Pos (6)
#define ETH_DMAOMR_FUGF (0x01U << ETH_DMAOMR_FUGF_Pos) ///< Forward undersized good frames
#define ETH_DMAOMR_RTC_Pos (3)
#define ETH_DMAOMR_RTC (0x03U << ETH_DMAOMR_RTC_Pos) ///< receive threshold control
#define ETH_DMAOMR_RTC_64Bytes (0x00U << ETH_DMAOMR_RTC_Pos) ///< threshold level of the MTL Receive FIFO is 64 Bytes
#define ETH_DMAOMR_RTC_32Bytes (0x01U << ETH_DMAOMR_RTC_Pos) ///< threshold level of the MTL Receive FIFO is 32 Bytes
#define ETH_DMAOMR_RTC_96Bytes (0x02U << ETH_DMAOMR_RTC_Pos) ///< threshold level of the MTL Receive FIFO is 96 Bytes
#define ETH_DMAOMR_RTC_128Bytes (0x03U << ETH_DMAOMR_RTC_Pos) ///< threshold level of the MTL Receive FIFO is 128 Bytes
#define ETH_DMAOMR_OSF_Pos (2)
#define ETH_DMAOMR_OSF (0x01U << ETH_DMAOMR_OSF_Pos) ///< operate on second frame
#define ETH_DMAOMR_SR_Pos (1)
#define ETH_DMAOMR_SR (0x01U << ETH_DMAOMR_SR_Pos ) ///< Start/stop receive
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_DMAIER Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_DMAIER_NISE_Pos (16)
#define ETH_DMAIER_NISE (0x01U << ETH_DMAIER_NISE_Pos ) ///< Normal interrupt summary enable
#define ETH_DMAIER_AISE_Pos (15)
#define ETH_DMAIER_AISE (0x01U << ETH_DMAIER_AISE_Pos ) ///< Abnormal interrupt summary enable
#define ETH_DMAIER_ERIE_Pos (14)
#define ETH_DMAIER_ERIE (0x01U << ETH_DMAIER_ERIE_Pos ) ///< Early receive interrupt enable
#define ETH_DMAIER_FBEIE_Pos (13)
#define ETH_DMAIER_FBEIE (0x01U << ETH_DMAIER_FBEIE_Pos) ///< Fatal bus error interrupt enable
#define ETH_DMAIER_ETIE_Pos (10)
#define ETH_DMAIER_ETIE (0x01U << ETH_DMAIER_ETIE_Pos ) ///< Early transmit interrupt enable
#define ETH_DMAIER_RWTIE_Pos (9)
#define ETH_DMAIER_RWTIE (0x01U << ETH_DMAIER_RWTIE_Pos) ///< Receive watchdog timeout interrupt enable
#define ETH_DMAIER_RPSIE_Pos (8)
#define ETH_DMAIER_RPSIE (0x01U << ETH_DMAIER_RPSIE_Pos) ///< Receive process stopped interrupt enable
#define ETH_DMAIER_RBUIE_Pos (7)
#define ETH_DMAIER_RBUIE (0x01U << ETH_DMAIER_RBUIE_Pos) ///< Receive buffer unavailable interrupt enable
#define ETH_DMAIER_RIE_Pos (6)
#define ETH_DMAIER_RIE (0x01U << ETH_DMAIER_RIE_Pos ) ///< Receive interrupt enable
#define ETH_DMAIER_TUIE_Pos (5)
#define ETH_DMAIER_TUIE (0x01U << ETH_DMAIER_TUIE_Pos ) ///< Transmit Underflow interrupt enable
#define ETH_DMAIER_ROIE_Pos (4)
#define ETH_DMAIER_ROIE (0x01U << ETH_DMAIER_ROIE_Pos ) ///< Receive Overflow interrupt enable
#define ETH_DMAIER_TJTIE_Pos (3)
#define ETH_DMAIER_TJTIE (0x01U << ETH_DMAIER_TJTIE_Pos) ///< Transmit jabber timeout interrupt enable
#define ETH_DMAIER_TBUIE_Pos (2)
#define ETH_DMAIER_TBUIE (0x01U << ETH_DMAIER_TBUIE_Pos) ///< Transmit buffer unavailable interrupt enable
#define ETH_DMAIER_TPSIE_Pos (1)
#define ETH_DMAIER_TPSIE (0x01U << ETH_DMAIER_TPSIE_Pos) ///< Transmit process stopped interrupt enable
#define ETH_DMAIER_TIE_Pos (0)
#define ETH_DMAIER_TIE (0x01U << ETH_DMAIER_TIE_Pos ) ///< Transmit interrupt enable
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_DMAMFBOCR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_DMAMFBOCR_OFOC_Pos (28)
#define ETH_DMAMFBOCR_OFOC (0x01U << ETH_DMAMFBOCR_OFOC_Pos) ///< Overflow bit for FIFO overflow counter
#define ETH_DMAMFBOCR_MFA_Pos (17)
#define ETH_DMAMFBOCR_MFA (0x7FFU << ETH_DMAMFBOCR_MFA_Pos ) ///< Number of frames missed by the application
#define ETH_DMAMFBOCR_OMFC_Pos (16)
#define ETH_DMAMFBOCR_OMFC (0x01U << ETH_DMAMFBOCR_OMFC_Pos) ///< Overflow bit for missed frame counter
#define ETH_DMAMFBOCR_MFC_Pos (0)
#define ETH_DMAMFBOCR_MFC (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos ) ///< Number of frames missed by the controller
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_DMACHTDR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_DMACHTDR_HTDAP (0xFFFFFFFFU) ///< Host transmit descriptor address pointer
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_DMACHRDR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_DMACHRDR_HRDAP (0xFFFFFFFFU) ///< Host receive descriptor address pointer
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_DMACHTBAR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_DMACHTBAR_HTBAP (0xFFFFFFFFU) ///< Host transmit buffer address pointer
////////////////////////////////////////////////////////////////////////////////
/// @brief ETH_DMACHRBAR Registers bits definition
////////////////////////////////////////////////////////////////////////////////
#define ETH_DMACHRBAR_HRBAP (0xFFFFFFFFU) ///< Host receive buffer address pointer
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h
+544
View File
@@ -0,0 +1,544 @@
////////////////////////////////////////////////////////////////////////////////
/// @file reg_exti.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_EXTI_H
#define __REG_EXTI_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief EXTI Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define EXTI_BASE (APB2PERIPH_BASE + 0x0000) ///< Base Address: 0x40010000
////////////////////////////////////////////////////////////////////////////////
/// @brief EXTI Registers Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 CFGR; ///< configuration register, offset: 0x00
u32 Reserved; ///< Reserved offset: 0x04
__IO u32 CR[4]; ///< External interrupt configuration register, offset: 0x08 - 0x14
__IO u32 CFGR2; ///< configuration register offset: 0x18
__IO u32 PDETCSR; ///< Power detection configuration status register offset: 0x1C
__IO u32 VOSDLY; ///< VOS delay time offset: 0x20
u32 Reserved1[0x100 - 0x09]; ///< Reserved space
__IO u32 IMR; ///< Interrupt Mask Register offset: 0x00 + 0x400
__IO u32 EMR; ///< Event Mask Register offset: 0x04 + 0x400
__IO u32 RTSR; ///< Rising Trigger Status Register offset: 0x08 + 0x400
__IO u32 FTSR; ///< Falling Trigger Status Register offset: 0x0C + 0x400
__IO u32 SWIER; ///< Software Interrupt Enable Register offset: 0x10 + 0x400
__IO u32 PR; ///< Pending Register offset: 0x14 + 0x400
} EXTI_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief EXTI type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define EXTI ((EXTI_TypeDef*) EXTI_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief EXTI_CFGR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define EXTI_CFGR_MEMMODE_Pos (0)
#define EXTI_CFGR_MEMMODE (0x03U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config
#define EXTI_CFGR_MEMMODE_0 (0x01U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Bit 0
#define EXTI_CFGR_MEMMODE_1 (0x02U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Bit 1
#define EXTI_CFGR_FLASH_MEMORY (0x00U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Mode 0
#define EXTI_CFGR_SYSTEM_MEMORY (0x01U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Mode 1
#define EXTI_CFGR_SRAM_MEMORY (0x03U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Mode 3
#define EXTI_CFGR_FC_SYNCEN_Pos (27)
#define EXTI_CFGR_FC_SYNCEN (0x01U << EXTI_CFGR_FC_SYNCEN_Pos) ///< FSMC synchronization enable
#define EXTI_CFGR_FC_ODATAEN_Pos (28)
#define EXTI_CFGR_FC_ODATAEN (0x01U << EXTI_CFGR_FC_ODATAEN_Pos) ///< FSMC Only used as data pin
#define EXTI_CFGR_MODESEL_Pos (29) ///< FSMC mode selection
#define EXTI_CFGR_MODESEL0 (0x00U << EXTI_CFGR_MODESEL0_Pos) ///< Compatible with 8080 protocol interface
#define EXTI_CFGR_MODESEL1 (0x01U << EXTI_CFGR_MODESEL1_Pos) ///< Compatible with NOR FLASH protocol interface
////////////////////////////////////////////////////////////////////////////////
/// @brief EXTI_CR1 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define EXTI_CR1_EXTI0_Pos (0)
#define EXTI_CR1_EXTI0 (0x0FU << EXTI_CR1_EXTI0_Pos) ///< EXTI 0 configuration
#define EXTI_CR1_EXTI0_PA (0x00U << EXTI_CR1_EXTI0_Pos) ///< PA[0] pin
#define EXTI_CR1_EXTI0_PB (0x01U << EXTI_CR1_EXTI0_Pos) ///< PB[0] pin
#define EXTI_CR1_EXTI0_PC (0x02U << EXTI_CR1_EXTI0_Pos) ///< PC[0] pin
#define EXTI_CR1_EXTI0_PD (0x03U << EXTI_CR1_EXTI0_Pos) ///< PD[0] pin
#define EXTI_CR1_EXTI1_Pos (4)
#define EXTI_CR1_EXTI1 (0x0FU << EXTI_CR1_EXTI1_Pos) ///< EXTI 1 configuration
#define EXTI_CR1_EXTI1_PA (0x00U << EXTI_CR1_EXTI1_Pos) ///< PA[1] pin
#define EXTI_CR1_EXTI1_PB (0x01U << EXTI_CR1_EXTI1_Pos) ///< PB[1] pin
#define EXTI_CR1_EXTI1_PC (0x02U << EXTI_CR1_EXTI1_Pos) ///< PC[1] pin
#define EXTI_CR1_EXTI1_PD (0x03U << EXTI_CR1_EXTI1_Pos) ///< PD[1] pin
#define EXTI_CR1_EXTI2_Pos (8)
#define EXTI_CR1_EXTI2 (0x0FU << EXTI_CR1_EXTI2_Pos) ///< EXTI 2 configuration
#define EXTI_CR1_EXTI2_PA (0x00U << EXTI_CR1_EXTI2_Pos) ///< PA[2] pin
#define EXTI_CR1_EXTI2_PB (0x01U << EXTI_CR1_EXTI2_Pos) ///< PB[2] pin
#define EXTI_CR1_EXTI2_PC (0x02U << EXTI_CR1_EXTI2_Pos) ///< PC[2] pin
#define EXTI_CR1_EXTI2_PD (0x03U << EXTI_CR1_EXTI2_Pos) ///< PD[2] pin
#define EXTI_CR1_EXTI3_Pos (12)
#define EXTI_CR1_EXTI3 (0x0FU << EXTI_CR1_EXTI3_Pos) ///< EXTI 3 configuration
#define EXTI_CR1_EXTI3_PA (0x00U << EXTI_CR1_EXTI3_Pos) ///< PA[3] pin
#define EXTI_CR1_EXTI3_PB (0x01U << EXTI_CR1_EXTI3_Pos) ///< PB[3] pin
#define EXTI_CR1_EXTI3_PC (0x02U << EXTI_CR1_EXTI3_Pos) ///< PC[3] pin
#define EXTI_CR1_EXTI3_PD (0x03U << EXTI_CR1_EXTI3_Pos) ///< PD[3] pin
////////////////////////////////////////////////////////////////////////////////
/// @brief EXTI_CR2 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define EXTI_CR2_EXTI4_Pos (0)
#define EXTI_CR2_EXTI4 (0x0FU << EXTI_CR2_EXTI4_Pos) ///< EXTI 4 configuration
#define EXTI_CR2_EXTI4_PA (0x00U << EXTI_CR2_EXTI4_Pos) ///< PA[4] pin
#define EXTI_CR2_EXTI4_PB (0x01U << EXTI_CR2_EXTI4_Pos) ///< PB[4] pin
#define EXTI_CR2_EXTI4_PC (0x02U << EXTI_CR2_EXTI4_Pos) ///< PC[4] pin
#define EXTI_CR2_EXTI4_PD (0x03U << EXTI_CR2_EXTI4_Pos) ///< PD[4] pin
#define EXTI_CR2_EXTI5_Pos (4)
#define EXTI_CR2_EXTI5 (0x0FU << EXTI_CR2_EXTI5_Pos) ///< EXTI 5 configuration
#define EXTI_CR2_EXTI5_PA (0x00U << EXTI_CR2_EXTI5_Pos) ///< PA[5] pin
#define EXTI_CR2_EXTI5_PB (0x01U << EXTI_CR2_EXTI5_Pos) ///< PB[5] pin
#define EXTI_CR2_EXTI5_PC (0x02U << EXTI_CR2_EXTI5_Pos) ///< PC[5] pin
#define EXTI_CR2_EXTI5_PD (0x03U << EXTI_CR2_EXTI5_Pos) ///< PD[5] pin
#define EXTI_CR2_EXTI6_Pos (8)
#define EXTI_CR2_EXTI6 (0x0FU << EXTI_CR2_EXTI6_Pos) ///< EXTI 6 configuration
#define EXTI_CR2_EXTI6_PA (0x00U << EXTI_CR2_EXTI6_Pos) ///< PA[6] pin
#define EXTI_CR2_EXTI6_PB (0x01U << EXTI_CR2_EXTI6_Pos) ///< PB[6] pin
#define EXTI_CR2_EXTI6_PC (0x02U << EXTI_CR2_EXTI6_Pos) ///< PC[6] pin
#define EXTI_CR2_EXTI6_PD (0x03U << EXTI_CR2_EXTI6_Pos) ///< PD[6] pin
#define EXTI_CR2_EXTI7_Pos (12)
#define EXTI_CR2_EXTI7 (0x0FU << EXTI_CR2_EXTI7_Pos) ///< EXTI 7 configuration
#define EXTI_CR2_EXTI7_PA (0x00U << EXTI_CR2_EXTI7_Pos) ///< PA[7] pin
#define EXTI_CR2_EXTI7_PB (0x01U << EXTI_CR2_EXTI7_Pos) ///< PB[7] pin
#define EXTI_CR2_EXTI7_PC (0x02U << EXTI_CR2_EXTI7_Pos) ///< PC[7] pin
#define EXTI_CR2_EXTI7_PD (0x03U << EXTI_CR2_EXTI7_Pos) ///< PD[7] pin
////////////////////////////////////////////////////////////////////////////////
/// @brief EXTI_CR3 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define EXTI_CR3_EXTI8_Pos (0)
#define EXTI_CR3_EXTI8 (0x0FU << EXTI_CR3_EXTI8_Pos) ///< EXTI 8 configuration
#define EXTI_CR3_EXTI8_PA (0x00U << EXTI_CR3_EXTI8_Pos) ///< PA[8] pin
#define EXTI_CR3_EXTI8_PB (0x01U << EXTI_CR3_EXTI8_Pos) ///< PB[8] pin
#define EXTI_CR3_EXTI8_PC (0x02U << EXTI_CR3_EXTI8_Pos) ///< PC[8] pin
#define EXTI_CR3_EXTI8_PD (0x03U << EXTI_CR3_EXTI8_Pos) ///< PD[8] pin
#define EXTI_CR3_EXTI9_Pos (4)
#define EXTI_CR3_EXTI9 (0x0FU << EXTI_CR3_EXTI9_Pos) ///< EXTI 9 configuration
#define EXTI_CR3_EXTI9_PA (0x00U << EXTI_CR3_EXTI9_Pos) ///< PA[9] pin
#define EXTI_CR3_EXTI9_PB (0x01U << EXTI_CR3_EXTI9_Pos) ///< PB[9] pin
#define EXTI_CR3_EXTI9_PC (0x02U << EXTI_CR3_EXTI9_Pos) ///< PC[9] pin
#define EXTI_CR3_EXTI9_PD (0x03U << EXTI_CR3_EXTI9_Pos) ///< PD[9] pin
#define EXTI_CR3_EXTI10_Pos (8)
#define EXTI_CR3_EXTI10 (0x0FU << EXTI_CR3_EXTI10_Pos) ///< EXTI 10 configuration
#define EXTI_CR3_EXTI10_PA (0x00U << EXTI_CR3_EXTI10_Pos) ///< PA[10] pin
#define EXTI_CR3_EXTI10_PB (0x01U << EXTI_CR3_EXTI10_Pos) ///< PB[10] pin
#define EXTI_CR3_EXTI10_PC (0x02U << EXTI_CR3_EXTI10_Pos) ///< PC[10] pin
#define EXTI_CR3_EXTI10_PD (0x03U << EXTI_CR3_EXTI10_Pos) ///< PD[10] pin
#define EXTI_CR3_EXTI11_Pos (12)
#define EXTI_CR3_EXTI11 (0x0FU << EXTI_CR3_EXTI11_Pos) ///< EXTI 11 configuration
#define EXTI_CR3_EXTI11_PA (0x00U << EXTI_CR3_EXTI11_Pos) ///< PA[11] pin
#define EXTI_CR3_EXTI11_PB (0x01U << EXTI_CR3_EXTI11_Pos) ///< PB[11] pin
#define EXTI_CR3_EXTI11_PC (0x02U << EXTI_CR3_EXTI11_Pos) ///< PC[11] pin
#define EXTI_CR3_EXTI11_PD (0x03U << EXTI_CR3_EXTI11_Pos) ///< PD[11] pin
////////////////////////////////////////////////////////////////////////////////
/// @brief EXTI_CR4 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define EXTI_CR4_EXTI12_Pos (0)
#define EXTI_CR4_EXTI12 (0x0FU << EXTI_CR4_EXTI12_Pos) ///< EXTI 12 configuration
#define EXTI_CR4_EXTI12_PA (0x00U << EXTI_CR4_EXTI12_Pos) ///< PA[12] pin
#define EXTI_CR4_EXTI12_PB (0x01U << EXTI_CR4_EXTI12_Pos) ///< PB[12] pin
#define EXTI_CR4_EXTI12_PC (0x02U << EXTI_CR4_EXTI12_Pos) ///< PC[12] pin
#define EXTI_CR4_EXTI12_PD (0x03U << EXTI_CR4_EXTI12_Pos) ///< PD[12] pin
#define EXTI_CR4_EXTI13_Pos (4)
#define EXTI_CR4_EXTI13 (0x0FU << EXTI_CR4_EXTI13_Pos) ///< EXTI 13 configuration
#define EXTI_CR4_EXTI13_PA (0x00U << EXTI_CR4_EXTI13_Pos) ///< PA[13] pin
#define EXTI_CR4_EXTI13_PB (0x01U << EXTI_CR4_EXTI13_Pos) ///< PB[13] pin
#define EXTI_CR4_EXTI13_PC (0x02U << EXTI_CR4_EXTI13_Pos) ///< PC[13] pin
#define EXTI_CR4_EXTI13_PD (0x03U << EXTI_CR4_EXTI13_Pos) ///< PD[13] pin
#define EXTI_CR4_EXTI14_Pos (8)
#define EXTI_CR4_EXTI14 (0x0FU << EXTI_CR4_EXTI14_Pos) ///< EXTI 14 configuration
#define EXTI_CR4_EXTI14_PA (0x00U << EXTI_CR4_EXTI14_Pos) ///< PA[14] pin
#define EXTI_CR4_EXTI14_PB (0x01U << EXTI_CR4_EXTI14_Pos) ///< PB[14] pin
#define EXTI_CR4_EXTI14_PC (0x02U << EXTI_CR4_EXTI14_Pos) ///< PC[14] pin
#define EXTI_CR4_EXTI14_PD (0x03U << EXTI_CR4_EXTI14_Pos) ///< PD[14] pin
#define EXTI_CR4_EXTI15_Pos (12)
#define EXTI_CR4_EXTI15 (0x0FU << EXTI_CR4_EXTI15_Pos) ///< EXTI 15 configuration
#define EXTI_CR4_EXTI15_PA (0x00U << EXTI_CR4_EXTI15_Pos) ///< PA[15] pin
#define EXTI_CR4_EXTI15_PB (0x01U << EXTI_CR4_EXTI15_Pos) ///< PB[15] pin
#define EXTI_CR4_EXTI15_PC (0x02U << EXTI_CR4_EXTI15_Pos) ///< PC[15] pin
#define EXTI_CR4_EXTI15_PD (0x03U << EXTI_CR4_EXTI15_Pos) ///< PD[15] pin
////////////////////////////////////////////////////////////////////////////////
/// @brief EXTI_CFGR2 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define EXTI_CFGR2_I2C1_Pos (16)
#define EXTI_CFGR2_I2C1_OD (0x00U << EXTI_CFGR2_I2C1_Pos) ///< Select open drain mode
#define EXTI_CFGR2_I2C1_PP (0x01U << EXTI_CFGR2_I2C1_Pos) ///< Select Push-pull mode
#define EXTI_CFGR2_I2C2_Pos (17)
#define EXTI_CFGR2_I2C2_OD (0x00U << EXTI_CFGR2_I2C2_Pos) ///< Select open drain mode
#define EXTI_CFGR2_I2C2_PP (0x01U << EXTI_CFGR2_I2C2_Pos) ///< Select Push-pull mode
#define EXTI_CFGR2_ETPHY_Pos (20)
#define EXTI_CFGR2_ETPHY_MII (0x00U << EXTI_CFGR2_ETPHY_Pos) ///< Select MII port
#define EXTI_CFGR2_ETPHY_RMII (0x01U << EXTI_CFGR2_ETPHY_Pos) ///< Select RMII port
#define EXTI_CFGR2_MAC_SPD_Pos (20)
#define EXTI_CFGR2_MAC_SPD_10 (0x00U << EXTI_CFGR2_ETPHY_Pos) ///< Select MAC_SPD 10 Mbps
#define EXTI_CFGR2_MAC_SPD_100 (0x01U << EXTI_CFGR2_ETPHY_Pos) ///< Select MAC_SPD 100 Mbps
////////////////////////////////////////////////////////////////////////////////
/// @brief EXTI_PDETCSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define EXTI_PDETCSR_PVDE_Pos (0)
#define EXTI_PDETCSR_PVDE (0x01U << EXTI_PDETCSR_PVDE_Pos) ///< PVD Enable
#define EXTI_PDETCSR_PLS_Pos (1)
#define EXTI_PDETCSR_PLS_1_7 (0x00U << EXTI_PDETCSR_PLS_Pos) ///< PVD 1.7mV
#define EXTI_PDETCSR_PLS_2_0 (0x01U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.0mV
#define EXTI_PDETCSR_PLS_2_3 (0x02U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.3mV
#define EXTI_PDETCSR_PLS_2_6 (0x03U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.6mV
#define EXTI_PDETCSR_PLS_2_9 (0x04U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.9mV
#define EXTI_PDETCSR_PLS_3_2 (0x05U << EXTI_PDETCSR_PLS_Pos) ///< PVD 3.2mV
#define EXTI_PDETCSR_PLS_3_5 (0x06U << EXTI_PDETCSR_PLS_Pos) ///< PVD 3.5mV
#define EXTI_PDETCSR_PLS_3_8 (0x07U << EXTI_PDETCSR_PLS_Pos) ///< PVD 3.8mV
#define EXTI_PDETCSR_PLS_4_1 (0x08U << EXTI_PDETCSR_PLS_Pos) ///< PVD 4.1mV
#define EXTI_PDETCSR_PLS_4_4 (0x09U << EXTI_PDETCSR_PLS_Pos) ///< PVD 4.4mV
#define EXTI_PDETCSR_PLS_4_7 (0x0AU << EXTI_PDETCSR_PLS_Pos) ///< PVD 4.7mV
#define EXTI_PDETCSR_PVDO_Pos (5)
#define EXTI_PDETCSR_PVDO (0x01U << EXTI_PDETCSR_PVDO_Pos) ///< PVD Output state
#define EXTI_PDETCSR_VDTO_Pos (6)
#define EXTI_PDETCSR_VDTO (0x01U << EXTI_PDETCSR_VDTO_Pos) ///< VDTO Output state
#define EXTI_PDETCSR_VDTE_Pos (8)
#define EXTI_PDETCSR_VDTE (0x01U << EXTI_PDETCSR_VDTE_Pos) ///< VDT Enable
#define EXTI_PDETCSR_VDTLS_Pos (9)
#define EXTI_PDETCSR_VDTLS0 (0x00U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 0.9V
#define EXTI_PDETCSR_VDTLS1 (0x01U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 1.0V
#define EXTI_PDETCSR_VDTLS2 (0x02U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 1.1V
#define EXTI_PDETCSR_VDTLS3 (0x03U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 1.2V
#define EXTI_PDETCSR_VBATDIV3_Pos (11)
#define EXTI_PDETCSR_VBATDIV3 (0x01U << EXTI_PDETCSR_VBATDIV3_Pos) ///< PVD Enable
////////////////////////////////////////////////////////////////////////////////
/// @brief EXTI_VOSDLY Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define EXTI_EXTI_VOSDLY (0x3FFU) ///< VOS delay time
////////////////////////////////////////////////////////////////////////////////
/// @brief EXTI_IMR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define EXTI_IMR_0_Pos (0)
#define EXTI_IMR_0 (0x01U << EXTI_IMR_0_Pos) ///< Interrupt Mask on line 0
#define EXTI_IMR_1_Pos (1)
#define EXTI_IMR_1 (0x01U << EXTI_IMR_1_Pos) ///< Interrupt Mask on line 1
#define EXTI_IMR_2_Pos (2)
#define EXTI_IMR_2 (0x01U << EXTI_IMR_2_Pos) ///< Interrupt Mask on line 2
#define EXTI_IMR_3_Pos (3)
#define EXTI_IMR_3 (0x01U << EXTI_IMR_3_Pos) ///< Interrupt Mask on line 3
#define EXTI_IMR_4_Pos (4)
#define EXTI_IMR_4 (0x01U << EXTI_IMR_4_Pos) ///< Interrupt Mask on line 4
#define EXTI_IMR_5_Pos (5)
#define EXTI_IMR_5 (0x01U << EXTI_IMR_5_Pos) ///< Interrupt Mask on line 5
#define EXTI_IMR_6_Pos (6)
#define EXTI_IMR_6 (0x01U << EXTI_IMR_6_Pos) ///< Interrupt Mask on line 6
#define EXTI_IMR_7_Pos (7)
#define EXTI_IMR_7 (0x01U << EXTI_IMR_7_Pos) ///< Interrupt Mask on line 7
#define EXTI_IMR_8_Pos (8)
#define EXTI_IMR_8 (0x01U << EXTI_IMR_8_Pos) ///< Interrupt Mask on line 8
#define EXTI_IMR_9_Pos (9)
#define EXTI_IMR_9 (0x01U << EXTI_IMR_9_Pos) ///< Interrupt Mask on line 9
#define EXTI_IMR_10_Pos (10)
#define EXTI_IMR_10 (0x01U << EXTI_IMR_10_Pos) ///< Interrupt Mask on line 10
#define EXTI_IMR_11_Pos (11)
#define EXTI_IMR_11 (0x01U << EXTI_IMR_11_Pos) ///< Interrupt Mask on line 11
#define EXTI_IMR_12_Pos (12)
#define EXTI_IMR_12 (0x01U << EXTI_IMR_12_Pos) ///< Interrupt Mask on line 12
#define EXTI_IMR_13_Pos (13)
#define EXTI_IMR_13 (0x01U << EXTI_IMR_13_Pos) ///< Interrupt Mask on line 13
#define EXTI_IMR_14_Pos (14)
#define EXTI_IMR_14 (0x01U << EXTI_IMR_14_Pos) ///< Interrupt Mask on line 14
#define EXTI_IMR_15_Pos (15)
#define EXTI_IMR_15 (0x01U << EXTI_IMR_15_Pos) ///< Interrupt Mask on line 15
#define EXTI_IMR_16_Pos (16)
#define EXTI_IMR_16 (0x01U << EXTI_IMR_16_Pos) ///< Interrupt Mask on line 16
////////////////////////////////////////////////////////////////////////////////
/// @brief EXTI_EMR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define EXTI_EMR_0_Pos (0)
#define EXTI_EMR_0 (0x01U << EXTI_EMR_0_Pos) ///< Event Mask on line 0
#define EXTI_EMR_1_Pos (1)
#define EXTI_EMR_1 (0x01U << EXTI_EMR_1_Pos) ///< Event Mask on line 1
#define EXTI_EMR_2_Pos (2)
#define EXTI_EMR_2 (0x01U << EXTI_EMR_2_Pos) ///< Event Mask on line 2
#define EXTI_EMR_3_Pos (3)
#define EXTI_EMR_3 (0x01U << EXTI_EMR_3_Pos) ///< Event Mask on line 3
#define EXTI_EMR_4_Pos (4)
#define EXTI_EMR_4 (0x01U << EXTI_EMR_4_Pos) ///< Event Mask on line 4
#define EXTI_EMR_5_Pos (5)
#define EXTI_EMR_5 (0x01U << EXTI_EMR_5_Pos) ///< Event Mask on line 5
#define EXTI_EMR_6_Pos (6)
#define EXTI_EMR_6 (0x01U << EXTI_EMR_6_Pos) ///< Event Mask on line 6
#define EXTI_EMR_7_Pos (7)
#define EXTI_EMR_7 (0x01U << EXTI_EMR_7_Pos) ///< Event Mask on line 7
#define EXTI_EMR_8_Pos (8)
#define EXTI_EMR_8 (0x01U << EXTI_EMR_8_Pos) ///< Event Mask on line 8
#define EXTI_EMR_9_Pos (9)
#define EXTI_EMR_9 (0x01U << EXTI_EMR_9_Pos) ///< Event Mask on line 9
#define EXTI_EMR_10_Pos (10)
#define EXTI_EMR_10 (0x01U << EXTI_EMR_10_Pos) ///< Event Mask on line 10
#define EXTI_EMR_11_Pos (11)
#define EXTI_EMR_11 (0x01U << EXTI_EMR_11_Pos) ///< Event Mask on line 11
#define EXTI_EMR_12_Pos (12)
#define EXTI_EMR_12 (0x01U << EXTI_EMR_12_Pos) ///< Event Mask on line 12
#define EXTI_EMR_13_Pos (13)
#define EXTI_EMR_13 (0x01U << EXTI_EMR_13_Pos) ///< Event Mask on line 13
#define EXTI_EMR_14_Pos (14)
#define EXTI_EMR_14 (0x01U << EXTI_EMR_14_Pos) ///< Event Mask on line 14
#define EXTI_EMR_15_Pos (15)
#define EXTI_EMR_15 (0x01U << EXTI_EMR_15_Pos) ///< Event Mask on line 15
#define EXTI_EMR_16_Pos (16)
#define EXTI_EMR_16 (0x01U << EXTI_EMR_16_Pos) ///< Event Mask on line 16
////////////////////////////////////////////////////////////////////////////////
/// @brief EXTI_RTSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define EXTI_RTSR_0_Pos (0)
#define EXTI_RTSR_0 (0x01U << EXTI_RTSR_0_Pos) ///< Rising trigger event configuration bit of line 0
#define EXTI_RTSR_1_Pos (1)
#define EXTI_RTSR_1 (0x01U << EXTI_RTSR_1_Pos) ///< Rising trigger event configuration bit of line 1
#define EXTI_RTSR_2_Pos (2)
#define EXTI_RTSR_2 (0x01U << EXTI_RTSR_2_Pos) ///< Rising trigger event configuration bit of line 2
#define EXTI_RTSR_3_Pos (3)
#define EXTI_RTSR_3 (0x01U << EXTI_RTSR_3_Pos) ///< Rising trigger event configuration bit of line 3
#define EXTI_RTSR_4_Pos (4)
#define EXTI_RTSR_4 (0x01U << EXTI_RTSR_4_Pos) ///< Rising trigger event configuration bit of line 4
#define EXTI_RTSR_5_Pos (5)
#define EXTI_RTSR_5 (0x01U << EXTI_RTSR_5_Pos) ///< Rising trigger event configuration bit of line 5
#define EXTI_RTSR_6_Pos (6)
#define EXTI_RTSR_6 (0x01U << EXTI_RTSR_6_Pos) ///< Rising trigger event configuration bit of line 6
#define EXTI_RTSR_7_Pos (7)
#define EXTI_RTSR_7 (0x01U << EXTI_RTSR_7_Pos) ///< Rising trigger event configuration bit of line 7
#define EXTI_RTSR_8_Pos (8)
#define EXTI_RTSR_8 (0x01U << EXTI_RTSR_8_Pos) ///< Rising trigger event configuration bit of line 8
#define EXTI_RTSR_9_Pos (9)
#define EXTI_RTSR_9 (0x01U << EXTI_RTSR_9_Pos) ///< Rising trigger event configuration bit of line 9
#define EXTI_RTSR_10_Pos (10)
#define EXTI_RTSR_10 (0x01U << EXTI_RTSR_10_Pos) ///< Rising trigger event configuration bit of line 10
#define EXTI_RTSR_11_Pos (11)
#define EXTI_RTSR_11 (0x01U << EXTI_RTSR_11_Pos) ///< Rising trigger event configuration bit of line 11
#define EXTI_RTSR_12_Pos (12)
#define EXTI_RTSR_12 (0x01U << EXTI_RTSR_12_Pos) ///< Rising trigger event configuration bit of line 12
#define EXTI_RTSR_13_Pos (13)
#define EXTI_RTSR_13 (0x01U << EXTI_RTSR_13_Pos) ///< Rising trigger event configuration bit of line 13
#define EXTI_RTSR_14_Pos (14)
#define EXTI_RTSR_14 (0x01U << EXTI_RTSR_14_Pos) ///< Rising trigger event configuration bit of line 14
#define EXTI_RTSR_15_Pos (15)
#define EXTI_RTSR_15 (0x01U << EXTI_RTSR_15_Pos) ///< Rising trigger event configuration bit of line 15
#define EXTI_RTSR_16_Pos (16)
#define EXTI_RTSR_16 (0x01U << EXTI_RTSR_16_Pos) ///< Rising trigger event configuration bit of line 16
////////////////////////////////////////////////////////////////////////////////
/// @brief EXTI_FTSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define EXTI_FTSR_0_Pos (0)
#define EXTI_FTSR_0 (0x01U << EXTI_FTSR_0_Pos) ///< Falling trigger event configuration bit of line 0
#define EXTI_FTSR_1_Pos (1)
#define EXTI_FTSR_1 (0x01U << EXTI_FTSR_1_Pos) ///< Falling trigger event configuration bit of line 1
#define EXTI_FTSR_2_Pos (2)
#define EXTI_FTSR_2 (0x01U << EXTI_FTSR_2_Pos) ///< Falling trigger event configuration bit of line 2
#define EXTI_FTSR_3_Pos (3)
#define EXTI_FTSR_3 (0x01U << EXTI_FTSR_3_Pos) ///< Falling trigger event configuration bit of line 3
#define EXTI_FTSR_4_Pos (4)
#define EXTI_FTSR_4 (0x01U << EXTI_FTSR_4_Pos) ///< Falling trigger event configuration bit of line 4
#define EXTI_FTSR_5_Pos (5)
#define EXTI_FTSR_5 (0x01U << EXTI_FTSR_5_Pos) ///< Falling trigger event configuration bit of line 5
#define EXTI_FTSR_6_Pos (6)
#define EXTI_FTSR_6 (0x01U << EXTI_FTSR_6_Pos) ///< Falling trigger event configuration bit of line 6
#define EXTI_FTSR_7_Pos (7)
#define EXTI_FTSR_7 (0x01U << EXTI_FTSR_7_Pos) ///< Falling trigger event configuration bit of line 7
#define EXTI_FTSR_8_Pos (8)
#define EXTI_FTSR_8 (0x01U << EXTI_FTSR_8_Pos) ///< Falling trigger event configuration bit of line 8
#define EXTI_FTSR_9_Pos (9)
#define EXTI_FTSR_9 (0x01U << EXTI_FTSR_9_Pos) ///< Falling trigger event configuration bit of line 9
#define EXTI_FTSR_10_Pos (10)
#define EXTI_FTSR_10 (0x01U << EXTI_FTSR_10_Pos) ///< Falling trigger event configuration bit of line 10
#define EXTI_FTSR_11_Pos (11)
#define EXTI_FTSR_11 (0x01U << EXTI_FTSR_11_Pos) ///< Falling trigger event configuration bit of line 11
#define EXTI_FTSR_12_Pos (12)
#define EXTI_FTSR_12 (0x01U << EXTI_FTSR_12_Pos) ///< Falling trigger event configuration bit of line 12
#define EXTI_FTSR_13_Pos (13)
#define EXTI_FTSR_13 (0x01U << EXTI_FTSR_13_Pos) ///< Falling trigger event configuration bit of line 13
#define EXTI_FTSR_14_Pos (14)
#define EXTI_FTSR_14 (0x01U << EXTI_FTSR_14_Pos) ///< Falling trigger event configuration bit of line 14
#define EXTI_FTSR_15_Pos (15)
#define EXTI_FTSR_15 (0x01U << EXTI_FTSR_15_Pos) ///< Falling trigger event configuration bit of line 15
#define EXTI_FTSR_16_Pos (16)
#define EXTI_FTSR_16 (0x01U << EXTI_FTSR_16_Pos) ///< Falling trigger event configuration bit of line 16
////////////////////////////////////////////////////////////////////////////////
/// @brief EXTI_SWIER Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define EXTI_SWIER_0_Pos (0)
#define EXTI_SWIER_0 (0x01U << EXTI_SWIER_0_Pos) ///< Software Interrupt on line 0
#define EXTI_SWIER_1_Pos (1)
#define EXTI_SWIER_1 (0x01U << EXTI_SWIER_1_Pos) ///< Software Interrupt on line 1
#define EXTI_SWIER_2_Pos (2)
#define EXTI_SWIER_2 (0x01U << EXTI_SWIER_2_Pos) ///< Software Interrupt on line 2
#define EXTI_SWIER_3_Pos (3)
#define EXTI_SWIER_3 (0x01U << EXTI_SWIER_3_Pos) ///< Software Interrupt on line 3
#define EXTI_SWIER_4_Pos (4)
#define EXTI_SWIER_4 (0x01U << EXTI_SWIER_4_Pos) ///< Software Interrupt on line 4
#define EXTI_SWIER_5_Pos (5)
#define EXTI_SWIER_5 (0x01U << EXTI_SWIER_5_Pos) ///< Software Interrupt on line 5
#define EXTI_SWIER_6_Pos (6)
#define EXTI_SWIER_6 (0x01U << EXTI_SWIER_6_Pos) ///< Software Interrupt on line 6
#define EXTI_SWIER_7_Pos (7)
#define EXTI_SWIER_7 (0x01U << EXTI_SWIER_7_Pos) ///< Software Interrupt on line 7
#define EXTI_SWIER_8_Pos (8)
#define EXTI_SWIER_8 (0x01U << EXTI_SWIER_8_Pos) ///< Software Interrupt on line 8
#define EXTI_SWIER_9_Pos (9)
#define EXTI_SWIER_9 (0x01U << EXTI_SWIER_9_Pos) ///< Software Interrupt on line 9
#define EXTI_SWIER_10_Pos (10)
#define EXTI_SWIER_10 (0x01U << EXTI_SWIER_10_Pos) ///< Software Interrupt on line 10
#define EXTI_SWIER_11_Pos (11)
#define EXTI_SWIER_11 (0x01U << EXTI_SWIER_11_Pos) ///< Software Interrupt on line 11
#define EXTI_SWIER_12_Pos (12)
#define EXTI_SWIER_12 (0x01U << EXTI_SWIER_12_Pos) ///< Software Interrupt on line 12
#define EXTI_SWIER_13_Pos (13)
#define EXTI_SWIER_13 (0x01U << EXTI_SWIER_13_Pos) ///< Software Interrupt on line 13
#define EXTI_SWIER_14_Pos (14)
#define EXTI_SWIER_14 (0x01U << EXTI_SWIER_14_Pos) ///< Software Interrupt on line 14
#define EXTI_SWIER_15_Pos (15)
#define EXTI_SWIER_15 (0x01U << EXTI_SWIER_15_Pos) ///< Software Interrupt on line 15
#define EXTI_SWIER_16_Pos (16)
#define EXTI_SWIER_16 (0x01U << EXTI_SWIER_16_Pos) ///< Software Interrupt on line 16
////////////////////////////////////////////////////////////////////////////////
/// @brief EXTI_PR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define EXTI_PR_0_Pos (0)
#define EXTI_PR_0 (0x01U << EXTI_PR_0_Pos) ///< Pending bit 0
#define EXTI_PR_1_Pos (1)
#define EXTI_PR_1 (0x01U << EXTI_PR_1_Pos) ///< Pending bit 1
#define EXTI_PR_2_Pos (2)
#define EXTI_PR_2 (0x01U << EXTI_PR_2_Pos) ///< Pending bit 2
#define EXTI_PR_3_Pos (3)
#define EXTI_PR_3 (0x01U << EXTI_PR_3_Pos) ///< Pending bit 3
#define EXTI_PR_4_Pos (4)
#define EXTI_PR_4 (0x01U << EXTI_PR_4_Pos) ///< Pending bit 4
#define EXTI_PR_5_Pos (5)
#define EXTI_PR_5 (0x01U << EXTI_PR_5_Pos) ///< Pending bit 5
#define EXTI_PR_6_Pos (6)
#define EXTI_PR_6 (0x01U << EXTI_PR_6_Pos) ///< Pending bit 6
#define EXTI_PR_7_Pos (7)
#define EXTI_PR_7 (0x01U << EXTI_PR_7_Pos) ///< Pending bit 7
#define EXTI_PR_8_Pos (8)
#define EXTI_PR_8 (0x01U << EXTI_PR_8_Pos) ///< Pending bit 8
#define EXTI_PR_9_Pos (9)
#define EXTI_PR_9 (0x01U << EXTI_PR_9_Pos) ///< Pending bit 9
#define EXTI_PR_10_Pos (10)
#define EXTI_PR_10 (0x01U << EXTI_PR_10_Pos) ///< Pending bit 10
#define EXTI_PR_11_Pos (11)
#define EXTI_PR_11 (0x01U << EXTI_PR_11_Pos) ///< Pending bit 11
#define EXTI_PR_12_Pos (12)
#define EXTI_PR_12 (0x01U << EXTI_PR_12_Pos) ///< Pending bit 12
#define EXTI_PR_13_Pos (13)
#define EXTI_PR_13 (0x01U << EXTI_PR_13_Pos) ///< Pending bit 13
#define EXTI_PR_14_Pos (14)
#define EXTI_PR_14 (0x01U << EXTI_PR_14_Pos) ///< Pending bit 14
#define EXTI_PR_15_Pos (15)
#define EXTI_PR_15 (0x01U << EXTI_PR_15_Pos) ///< Pending bit 15
#define EXTI_PR_16_Pos (16)
#define EXTI_PR_16 (0x01U << EXTI_PR_16_Pos) ///< Pending bit 16
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h
+290
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_flash.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_FLASH_H
#define __REG_FLASH_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief MM32 MCU Memory/Peripherals mapping
////////////////////////////////////////////////////////////////////////////////
#define FLASH_BASE (0x08000000U) ///< FLASH base address in the alias region
#define SRAM_BASE (0x20000000U) ///< SRAM base address in the alias region
#define CACHE_BASE (APB2PERIPH_BASE + 0x6000) ///< Base Address: 0x40016000
////////////////////////////////////////////////////////////////////////////////
/// @brief FLASH Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define FLASH_REG_BASE (AHBPERIPH_BASE + 0x2000) ///< Base Address: 0x40022000
////////////////////////////////////////////////////////////////////////////////
/// @brief OPTB Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define OB_BASE (0x1FFFF800U) ///< Flash Option Bytes base address
#define PROTECT_BASE (0x1FFE0000U) ///< Flash Protect Bytes base address
////////////////////////////////////////////////////////////////////////////////
/// @brief FLASH Registers Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 ACR; ///< Access control Register offset: 0x00
__IO u32 KEYR; ///< Key Register offset: 0x04
__IO u32 OPTKEYR; ///< Option byte key Register offset: 0x08
__IO u32 SR; ///< State Register offset: 0x0C
__IO u32 CR; ///< Control Register offset: 0x10
__IO u32 AR; ///< Address Register offset: 0x14
__IO u32 RESERVED;
__IO u32 OBR; ///< Option bytes Register offset: 0x1C
__IO u32 WRPR; ///< Write protect Register offset: 0x20
} FLASH_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief OPT Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u16 RDP; ///< Read Protect, offset: 0x00
__IO u16 USER; ///< User option byte, offset: 0x02
__IO u16 Data0; ///< User data 0, offset: 0x04
__IO u16 Data1; ///< User data 1, offset: 0x06
__IO u16 WRP0; ///< Flash write protection option byte 0, offset: 0x08
__IO u16 WRP1; ///< Flash write protection option byte 1, offset: 0x0A
__IO u16 WRP2; ///< Flash write protection option byte 2, offset: 0x0C
__IO u16 WRP3; ///< Flash write protection option byte 3, offset: 0x0E
} OB_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief PROTECT BYTES Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u16 PROTECT_LEN0; ///< The length of Protect byte 0, offset: 0x00
__IO u16 PROTECT_ADDR0; ///< Data of Protect byte 0, offset: 0x02
__IO u16 PROTECT_LEN1; ///< The length of Protect byte 1, offset: 0x04
__IO u16 PROTECT_ADDR1; ///< Data of Protect byte 1, offset: 0x06
__IO u16 PROTECT_LEN2; ///< The length of Protect byte 2, offset: 0x08
__IO u16 PROTECT_ADDR2; ///< Data of Protect byte 2, offset: 0x0A
__IO u16 PROTECT_LEN3; ///< The length of Protect byte 3, offset: 0x0C
__IO u16 PROTECT_ADDR3; ///< Data of Protect byte 3, offset: 0x0E
} PROTECT_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief CACHE BYTES Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 CCR; ///< Configuration and control register offset: 0x00
__IO u32 SR; ///< Status register offset: 0x04
__IO u32 IMR; ///< Interrupt mask register offset: 0x08
__IO u32 ISR; ///< Interrupt status register offset: 0x0C
__IO u32 RESERVED0; ///< offset: 0x10
__IO u32 CSHR; ///< Hit Statistics Register offset: 0x14
__IO u32 CSMR; ///< Lost Statistics Register offset: 0x18
} CACHE_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief FLASH type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define FLASH ((FLASH_TypeDef*) FLASH_REG_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief OPTB type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define OB ((OB_TypeDef*) OB_BASE)
#define PROTECT ((PROTECT_TypeDef*) PROTECT_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief CACHE pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define CACHE ((CACHE_TypeDef*) CACHE_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief FLASH_ACR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define FLASH_ACR_LATENCY_Pos (0)
#define FLASH_ACR_LATENCY (0x07U << FLASH_ACR_LATENCY_Pos) ///< LATENCY[2:0] bits (Latency)
#define FLASH_ACR_LATENCY_0 (0x00U << FLASH_ACR_LATENCY_Pos) ///< 0 waiting state
#define FLASH_ACR_LATENCY_1 (0x01U << FLASH_ACR_LATENCY_Pos) ///< 1 waiting state
#define FLASH_ACR_LATENCY_2 (0x02U << FLASH_ACR_LATENCY_Pos) ///< 2 waiting state
#define FLASH_ACR_LATENCY_3 (0x03U << FLASH_ACR_LATENCY_Pos) ///< 3 waiting state
#define FLASH_ACR_HLFCYA_Pos (3)
#define FLASH_ACR_HLFCYA (0x01U << FLASH_ACR_HLFCYA_Pos) ///< Flash Half Cycle Access Enable
#define FLASH_ACR_PRFTBE_Pos (4)
#define FLASH_ACR_PRFTBE (0x01U << FLASH_ACR_PRFTBE_Pos) ///< Prefetch Buffer Enable
#define FLASH_ACR_PRFTBS_Pos (5)
#define FLASH_ACR_PRFTBS (0x01U << FLASH_ACR_PRFTBS_Pos) ///< Prefetch Buffer Status
////////////////////////////////////////////////////////////////////////////////
/// @brief FLASH_KEYR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define FLASH_KEYR_FKEY_Pos (0)
#define FLASH_KEYR_FKEY (0xFFFFFFFFU << FLASH_KEYR_FKEY_Pos) ///< FLASH Key
////////////////////////////////////////////////////////////////////////////////
/// @brief FLASH_OPTKEYR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define FLASH_OPTKEYR_OPTKEY_Pos (0)
#define FLASH_OPTKEYR_OPTKEY (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEY_Pos) ///< Option Byte Key
////////////////////////////////////////////////////////////////////////////////
/// @brief FLASH_SR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define FLASH_SR_BUSY_Pos (0)
#define FLASH_SR_BUSY (0x01U << FLASH_SR_BUSY_Pos) ///< Busy
#define FLASH_SR_PGERR_Pos (2)
#define FLASH_SR_PGERR (0x01U << FLASH_SR_PGERR_Pos) ///< Programming Error
#define FLASH_SR_WRPRTERR_Pos (4)
#define FLASH_SR_WRPRTERR (0x01U << FLASH_SR_WRPRTERR_Pos) ///< Write Protection Error
#define FLASH_SR_EOP_Pos (5)
#define FLASH_SR_EOP (0x01U << FLASH_SR_EOP_Pos) ///< End of operation
////////////////////////////////////////////////////////////////////////////////
/// @brief FLASH_CR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define FLASH_CR_PG_Pos (0)
#define FLASH_CR_PG (0x01U << FLASH_CR_PG_Pos) ///< Programming
#define FLASH_CR_PER_Pos (1)
#define FLASH_CR_PER (0x01U << FLASH_CR_PER_Pos) ///< Page Erase
#define FLASH_CR_MER_Pos (2)
#define FLASH_CR_MER (0x01U << FLASH_CR_MER_Pos) ///< Mass Erase
#define FLASH_CR_OPTPG_Pos (4)
#define FLASH_CR_OPTPG (0x01U << FLASH_CR_OPTPG_Pos) ///< Option Byte Programming
#define FLASH_CR_OPTER_Pos (5)
#define FLASH_CR_OPTER (0x01U << FLASH_CR_OPTER_Pos) ///< Option Byte Erase
#define FLASH_CR_STRT_Pos (6)
#define FLASH_CR_STRT (0x01U << FLASH_CR_STRT_Pos) ///< Start
#define FLASH_CR_LOCK_Pos (7)
#define FLASH_CR_LOCK (0x01U << FLASH_CR_LOCK_Pos) ///< Lock
#define FLASH_CR_OPTWRE_Pos (9)
#define FLASH_CR_OPTWRE (0x01U << FLASH_CR_OPTWRE_Pos) ///< Option Bytes Write Enable
#define FLASH_CR_ERRIE_Pos (10)
#define FLASH_CR_ERRIE (0x01U << FLASH_CR_ERRIE_Pos) ///< Error Interrupt Enable
#define FLASH_CR_EOPIE_Pos (12)
#define FLASH_CR_EOPIE (0x01U << FLASH_CR_EOPIE_Pos) ///< End of operation interrupt enable
////////////////////////////////////////////////////////////////////////////////
/// @brief FLASH_AR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define FLASH_AR_FAR_Pos (0)
#define FLASH_AR_FAR (0xFFFFFFFFU << FLASH_AR_FAR_Pos) ///< Flash Address
////////////////////////////////////////////////////////////////////////////////
/// @brief FLASH_OBR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define FLASH_OBR_OPTERR_Pos (0)
#define FLASH_OBR_OPTERR (0x01U << FLASH_OBR_OPTERR_Pos) ///< Option Byte Error
#define FLASH_OBR_RDPRT_Pos (1)
#define FLASH_OBR_RDPRT (0x01U << FLASH_OBR_RDPRT_Pos) ///< Read protection level status
#define FLASH_OBR_USER_Pos (2)
#define FLASH_OBR_USER (0xFFU << FLASH_OBR_USER_Pos) ///< User Option Bytes
#define FLASH_OBR_WDG_SW (0x01U << FLASH_OBR_USER_Pos) ///< WDG_SW
#define FLASH_OBR_RST_STOP (0x02U << FLASH_OBR_USER_Pos) ///< nRST_STOP
#define FLASH_OBR_RST_STDBY (0x04U << FLASH_OBR_USER_Pos) ///< nRST_STDBY
#define FLASH_OBR_Data0_Pos (10)
#define FLASH_OBR_Data0 (0xFFU << FLASH_OBR_Data0_Pos) ///< User data storage option byte
#define FLASH_OBR_Data1_Pos (18)
#define FLASH_OBR_Data1 (0xFFU << FLASH_OBR_Data1_Pos) ///< User data storage option byte
////////////////////////////////////////////////////////////////////////////////
/// @brief FLASH_WRPR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define FLASH_WRPR_WRP_Pos (0)
#define FLASH_WRPR_WRP (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) ///< Write Protect
////////////////////////////////////////////////////////////////////////////////
/// @brief CACHE_CCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define CACHE_CCR_EN_Pos (0)
#define CACHE_CCR_EN (0x01U << CACHE_CCR_EN_Pos) ///< Cache Enable
#define CACHE_CCR_INV_Pos (1)
#define CACHE_CCR_INV (0x01U << CACHE_CCR_INV_REQ_Pos) ///< Manually invalidate the request
#define CACHE_CCR_POW_Pos (2)
#define CACHE_CCR_POW (0x01U << CACHE_CCR_POW_REQ_Pos) ///< Manual SRAM power request
#define CACHE_CCR_MAN_POW_Pos (3)
#define CACHE_CCR_MAN_POW (0x01U << CACHE_CCR_MAN_POW_Pos) ///< Set manual or automatic SRAM power request
#define CACHE_CCR_MAN_INV_Pos (4)
#define CACHE_CCR_MAN_INV (0x01U << CACHE_CCR_MAN_INV_Pos) ///< Manually or automatically disable it
#define CACHE_CCR_PREFETCH_Pos (5)
#define CACHE_CCR_PREFETCH (0x01U << CACHE_CCR_PREFETCH_Pos) ///< Prefetch function
#define CACHE_CCR_STATISTIC_Pos (6)
#define CACHE_CCR_STATISTIC (0x01U << CACHE_CCR_STATISTIC_Pos) ///< Statistics enable
////////////////////////////////////////////////////////////////////////////////
/// @brief CACHE_SR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define CACHE_SR_CS_Pos (0)
#define CACHE_SR_CS0 (0x00U << CACHE_CCR_CS_Pos) ///< Cache is disabled
#define CACHE_SR_CS1 (0x01U << CACHE_CCR_CS_Pos) ///< Cache is being enabled
#define CACHE_SR_CS2 (0x02U << CACHE_CCR_CS_Pos) ///< Cache is enabled
#define CACHE_SR_CS3 (0x03U << CACHE_CCR_CS_Pos) ///< Cache is being disabled
#define CACHE_SR_INV_Pos (2)
#define CACHE_SR_INV (0x01U << CACHE_CCR_INV_REQ_Pos) ///< Invalidation status
#define CACHE_SR_POW_Pos (4)
#define CACHE_SR_POW (0x01U << CACHE_CCR_POW_REQ_Pos) ///< SRAM power response
////////////////////////////////////////////////////////////////////////////////
/// @brief CACHE_IMR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define CACHE_IMR_MAN_INV_Pos (0)
#define CACHE_IMR_MAN_INV (0x01U << CACHE_IMR_MAN_INV_Pos) ///< Mask the interrupt request of manual invalidation error
#define CACHE_IMR_POW_Pos (1)
#define CACHE_IMR_POW (0x01U << CACHE_IMR_POW_Pos) ///< Mask the interrupt request of power supply error
////////////////////////////////////////////////////////////////////////////////
/// @brief CACHE_ISR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define CACHE_ISR_MAN_INV_Pos (0)
#define CACHE_ISR_MAN_INV (0x01U << CACHE_ISR_MAN_INV_Pos) ///< Manual invalidation of error flags
#define CACHE_ISR_POW_Pos (1)
#define CACHE_ISR_POW (0x01U << CACHE_ISR_POW_Pos) ///< SRAM power error flags
////////////////////////////////////////////////////////////////////////////////
/// @brief CACHE_CSHR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define CACHE_CSHR (0xFFFFU ) ///< Cache Hits
////////////////////////////////////////////////////////////////////////////////
/// @brief CACHE_CSHR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define CACHE_CSMR (0xFFFFU ) ///< Cache Lost times
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_fsmc.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_FSMC_H
#define __REG_FSMC_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief FLASH Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define FSMC_BANK1_ADDR (0x60000000UL )
#define FSMC_BANK2_ADDR (0x60000000UL + 0x4000000 )
#define FSMC_BANK3_ADDR (0x60000000UL + 0x8000000 )
#define FSMC_BANK4_ADDR (0x60000000UL + 0xc000000 )
#define FSMC_BASE (0x60000000UL + 0x40000000) ///< Base Address: 0xA0000000
////////////////////////////////////////////////////////////////////////////////
/// @brief FSMC Registers Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 Reservedoffset0x00; ///< Reserved Register offset: 0x00
__IO u32 Reservedoffset0x04; ///< Reserved Register offset: 0x04
__IO u32 Reservedoffset0x08; ///< Reserved Register offset: 0x08
__IO u32 Reservedoffset0x0c; ///< Reserved Register offset: 0x0c
__IO u32 Reservedoffset0x10; ///< Reserved Register offset: 0x10
__IO u32 Reservedoffset0x14; ///< Reserved Register offset: 0x14
__IO u32 Reservedoffset0x18; ///< Reserved Register offset: 0x18
__IO u32 Reservedoffset0x1c; ///< Reserved Register offset: 0x1c
__IO u32 Reservedoffset0x20; ///< Reserved Register offset: 0x20
__IO u32 Reservedoffset0x24; ///< Reserved Register offset: 0x24
__IO u32 Reservedoffset0x28; ///< Reserved Register offset: 0x28
__IO u32 Reservedoffset0x2c; ///< Reserved Register offset: 0x2c
__IO u32 Reservedoffset0x30; ///< Reserved Register offset: 0x30
__IO u32 Reservedoffset0x34; ///< Reserved Register offset: 0x34
__IO u32 Reservedoffset0x38; ///< Reserved Register offset: 0x38
__IO u32 Reservedoffset0x3c; ///< Reserved Register offset: 0x3c
__IO u32 Reservedoffset0x40; ///< Reserved Register offset: 0x40
__IO u32 Reservedoffset0x44; ///< Reserved Register offset: 0x44
__IO u32 Reservedoffset0x48; ///< Reserved Register offset: 0x48
__IO u32 Reservedoffset0x4c; ///< Reserved Register offset: 0x4c
__IO u32 Reservedoffset0x50; ///< Reserved Register offset: 0x50
__IO u32 SMSKR; ///< SMSKR control Register offset: 0x54
__IO u32 Reservedoffset0x58; ///< Reserved Register offset: 0x58
__IO u32 Reservedoffset0x5c; ///< Reserved Register offset: 0x5c
__IO u32 Reservedoffset0x60; ///< Reserved Register offset: 0x60
__IO u32 Reservedoffset0x64; ///< Reserved Register offset: 0x64
__IO u32 Reservedoffset0x68; ///< Reserved Register offset: 0x68
__IO u32 Reservedoffset0x6c; ///< Reserved Register offset: 0x6c
__IO u32 Reservedoffset0x70; ///< Reserved Register offset: 0x70
__IO u32 Reservedoffset0x74; ///< Reserved Register offset: 0x74
__IO u32 Reservedoffset0x78; ///< Reserved Register offset: 0x78
__IO u32 Reservedoffset0x7c; ///< Reserved Register offset: 0x7c
__IO u32 Reservedoffset0x80; ///< Reserved Register offset: 0x80
__IO u32 Reservedoffset0x84; ///< Reserved Register offset: 0x84
__IO u32 Reservedoffset0x88; ///< Reserved Register offset: 0x88
__IO u32 Reservedoffset0x8c; ///< Reserved Register offset: 0x8c
__IO u32 Reservedoffset0x90; ///< Reserved Register offset: 0x90
__IO u32 SMTMGR_SET0; ///< SMTMGR_SET Register 0 offset: 0x94
__IO u32 SMTMGR_SET1; ///< SMTMGR_SET Register 1 offset: 0x98
__IO u32 SMTMGR_SET2; ///< SMTMGR_SET Register 2 offset: 0x9c
__IO u32 Reservedoffset0xA0; ///< Reserved Register offset: 0xa0
__IO u32 SMCTLR; ///< Reserved Register offset: 0xa4
__IO u32 Reservedoffset0xA8; ///< Reserved Register offset: 0xa8
__IO u32 Reservedoffset0xAC; ///< Reserved Register offset: 0xac
} FSMC_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief FSMC type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define FSMC ((FSMC_TypeDef*) FSMC_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief FSMC_SMSKR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define FSMC_SMSKR_REG_SELECT_Pos (8)
#define FSMC_SMSKR_REG_SELECT0 (0x00U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 0
#define FSMC_SMSKR_REG_SELECT1 (0x01U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 1
#define FSMC_SMSKR_REG_SELECT2 (0x02U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 2
#define FSMC_SMSKR_MEM_TYPE_Pos (5)
#define FSMC_SMSKR_MEM_TYPE0 (0x00U << FSMC_SMSKR_MEM_TYPE_Pos) ///< SDRAM
#define FSMC_SMSKR_MEM_TYPE1 (0x01U << FSMC_SMSKR_MEM_TYPE_Pos) ///< SRAM
#define FSMC_SMSKR_MEM_TYPE2 (0x02U << FSMC_SMSKR_MEM_TYPE_Pos) ///< FLASH
#define FSMC_SMSKR_MEM_SIZE_Pos (0)
#define FSMC_SMSKR_MEM_SIZE_64K (0x01U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 64KB
#define FSMC_SMSKR_MEM_SIZE_128K (0x02U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 128KB
#define FSMC_SMSKR_MEM_SIZE_256K (0x03U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 256KB
#define FSMC_SMSKR_MEM_SIZE_512K (0x04U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 512KB
#define FSMC_SMSKR_MEM_SIZE_1M (0x05U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 1MB
#define FSMC_SMSKR_MEM_SIZE_2M (0x06U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 2MB
#define FSMC_SMSKR_MEM_SIZE_4M (0x07U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 4MB
#define FSMC_SMSKR_MEM_SIZE_8M (0x08U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 8MB
#define FSMC_SMSKR_MEM_SIZE_16M (0x09U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 16MB
#define FSMC_SMSKR_MEM_SIZE_32M (0x10U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 32MB
#define FSMC_SMSKR_MEM_SIZE_64M (0x11U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 64MB
#define FSMC_SMSKR_MEM_SIZE_128M (0x12U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 128MB
#define FSMC_SMSKR_MEM_SIZE_256M (0x13U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 256MB
#define FSMC_SMSKR_MEM_SIZE_512M (0x14U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 512MB
#define FSMC_SMSKR_MEM_SIZE_1G (0x15U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 1GB
#define FSMC_SMSKR_MEM_SIZE_2G (0x16U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 2GB
#define FSMC_SMSKR_MEM_SIZE_4G (0x17U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 4GB
////////////////////////////////////////////////////////////////////////////////
/// @brief FSMC_SMTMGR_SET0/1/2 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define FSMC_SMTMGR_SET_SM_READ_PIPE_Pos (28)
#define FSMC_SMTMGR_SET_SM_READ_PIPE (0x03U << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) ///< The period of the latched read data
#define FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE_Pos (27)
#define FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE (0x01U << FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE_Pos) ///< Access low frequency synchronization devices
#define FSMC_SMTMGR_SET_READ_MODE_Pos (26)
#define FSMC_SMTMGR_SET_READ_MODE (0x01U << FSMC_SMTMGR_SET_READ_MODE_Pos) ///< The Hready_RESP signal is from an external DEVICE
#define FSMC_SMTMGR_SET_T_WP_Pos (10)
#define FSMC_SMTMGR_SET_T_WP (0x3FU << FSMC_SMTMGR_SET_T_WP_Pos) ///< Write pulse width 64 clock cycles
#define FSMC_SMTMGR_SET_T_WR_Pos (8)
#define FSMC_SMTMGR_SET_T_WR (0x03U << FSMC_SMTMGR_SET_T_WR_Pos) ///< Address/data retention time for write operations is 3 clock cycles
#define FSMC_SMTMGR_SET_T_AS_Pos (6)
#define FSMC_SMTMGR_SET_T_AS (0x03U << FSMC_SMTMGR_SET_T_AS_Pos) ///< The address establishment time of write operation is 3 clock cycles
#define FSMC_SMTMGR_SET_T_RC_Pos (0)
#define FSMC_SMTMGR_SET_T_RC (0x3FU << FSMC_SMTMGR_SET_T_RC_Pos) ///< Read operation cycle 64 clock cycles
////////////////////////////////////////////////////////////////////////////////
/// @brief FSMC_SMCTLR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos (13)
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos)
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 16 bits
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 32 bits
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 64 bits
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 128 bits
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 8 bits
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos (10)
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos)
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 16 bits
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 32 bits
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 64 bits
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 128 bits
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 8 bits
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos (7)
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos)
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 16 bits
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 32 bits
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 64 bits
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 128 bits
#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 8 bits
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif //__REG_FSMC_H
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h
+706
View File
@@ -0,0 +1,706 @@
////////////////////////////////////////////////////////////////////////////////
/// @file reg_gpio.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_GPIO_H
#define __REG_GPIO_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIOA_BASE (AHBPERIPH_BASE + 0x0020000) ///< Base Address: 0x40040000
#define GPIOB_BASE (AHBPERIPH_BASE + 0x0020400) ///< Base Address: 0x40040400
#define GPIOC_BASE (AHBPERIPH_BASE + 0x0020800) ///< Base Address: 0x40040800
#define GPIOD_BASE (AHBPERIPH_BASE + 0x0020C00) ///< Base Address: 0x40040C00
#define GPIOE_BASE (AHBPERIPH_BASE + 0x0021000) ///< Base Address: 0x40041000
#define GPIOF_BASE (AHBPERIPH_BASE + 0x0021400) ///< Base Address: 0x40041400
#define GPIOG_BASE (AHBPERIPH_BASE + 0x0021800) ///< Base Address: 0x40041800
#define GPIOH_BASE (AHBPERIPH_BASE + 0x0021C00) ///< Base Address: 0x40041C00
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO Registers Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 CRL; ///< Control Register Low, offset: 0x00
__IO u32 CRH; ///< Control Register High, offset: 0x04
__IO u32 IDR; ///< Input Data Register, offset: 0x08
__IO u32 ODR; ///< Output Data Register, offset: 0x0C
__IO u32 BSRR; ///< Bit Set or Reset Register, offset: 0x10
__IO u32 BRR; ///< Bit Reset Register, offset: 0x14
__IO u32 LCKR; ///< Lock Register, offset: 0x18
__IO u32 DCR; ///< Pin Output Open Drain Config Register, offset: 0x1C
__IO u32 AFRL; ///< Port Multiplexing Function Low Register, offset: 0x20
__IO u32 AFRH; ///< Port Multiplexing Function High Register, offset: 0x24
} GPIO_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIOA ((GPIO_TypeDef*) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef*) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef*) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef*) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef*) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef*) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef*) GPIOG_BASE)
#define GPIOH ((GPIO_TypeDef*) GPIOH_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO Common Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIO_CNF_MODE_AIN 0x00UL //0b0000, ///< Analog input
#define GPIO_CNF_MODE_FLOATING 0x04UL //0b0100, ///< Floating input
#define GPIO_CNF_MODE_INPUPD 0x08UL //0b1000, ///< Pull up and down input
#define GPIO_CNF_MODE_INRESEVED 0x0CUL //0b1100, ///< Reseved input mode
#define GPIO_CNF_MODE_OUT_PP 0x01UL //0b0001, ///< Universal push-pull output default
#define GPIO_CNF_MODE_OUT_OD 0x05UL //0b0101, ///< Universal open drain output default
#define GPIO_CNF_MODE_AF_PP 0x09UL //0b1001, ///< Multiplex push-pull output default
#define GPIO_CNF_MODE_AF_OD 0x0DUL //0b1101 ///< Multiplex open drain output default
#define GPIO_CNF_MODE_50MHZ_OUT_PP 0x01UL //0b0001, ///< Universal push-pull output 50MHZ
#define GPIO_CNF_MODE_50MHZ_OUT_OD 0x05UL //0b0101, ///< Universal open drain output 50MHZ
#define GPIO_CNF_MODE_50MHZ_AF_PP 0x09UL //0b1001, ///< Multiplex push-pull output 50MHZ
#define GPIO_CNF_MODE_50MHZ_AF_OD 0x0DUL //0b1101 ///< Multiplex open drain output 50MHZ
#define GPIO_CNF_MODE_20MHZ_OUT_PP 0x02UL //0b0010, ///< Universal push-pull output 20MHZ
#define GPIO_CNF_MODE_20MHZ_OUT_OD 0x06UL //0b0110, ///< Universal open drain output 20MHZ
#define GPIO_CNF_MODE_20MHZ_AF_PP 0x0AUL //0b1010, ///< Multiplex push-pull output 20MHZ
#define GPIO_CNF_MODE_20MHZ_AF_OD 0x0EUL //0b1110 ///< Multiplex open drain output 20MHZ
#define GPIO_CNF_MODE_10MHZ_OUT_PP 0x03UL //0b0011, ///< Universal push-pull output 10MHZ
#define GPIO_CNF_MODE_10MHZ_OUT_OD 0x07UL //0b0111, ///< Universal open drain output 10MHZ
#define GPIO_CNF_MODE_10MHZ_AF_PP 0x0BUL //0b1011, ///< Multiplex push-pull output 10MHZ
#define GPIO_CNF_MODE_10MHZ_AF_OD 0x0FUL //0b1111 ///< Multiplex open drain output 10MHZ
#define GPIO_CNF_MODE_MASK 0x0FUL //0b1111
#define GPIO_CRL_CNF_MODE_0_Pos (0) // ///< Analog input
#define GPIO_CRL_CNF_MODE_1_Pos (4) // ///< Floating input
#define GPIO_CRL_CNF_MODE_2_Pos (8) // ///< Pull up and down input
#define GPIO_CRL_CNF_MODE_3_Pos (12) // ///< Reseved input mode
#define GPIO_CRL_CNF_MODE_4_Pos (16) // ///< Universal push-pull output default
#define GPIO_CRL_CNF_MODE_5_Pos (20) // ///< Universal open drain output default
#define GPIO_CRL_CNF_MODE_6_Pos (24) // ///< Multiplex push-pull output default
#define GPIO_CRL_CNF_MODE_7_Pos (28) // ///< Multiplex open drain output default
#define GPIO_CRH_CNF_MODE_8_Pos (0) // ///< Universal push-pull output 50MHZ
#define GPIO_CRH_CNF_MODE_9_Pos (4) // ///< Universal open drain output 50MHZ
#define GPIO_CRH_CNF_MODE_10_Pos (8) // ///< Multiplex push-pull output 50MHZ
#define GPIO_CRH_CNF_MODE_11_Pos (12) // ///< Multiplex open drain output 50MHZ
#define GPIO_CRH_CNF_MODE_12_Pos (16) // ///< Universal push-pull output 20MHZ
#define GPIO_CRH_CNF_MODE_13_Pos (20) // ///< Universal open drain output 20MHZ
#define GPIO_CRH_CNF_MODE_14_Pos (24) // ///< Multiplex push-pull output 20MHZ
#define GPIO_CRH_CNF_MODE_15_Pos (28) // ///< Multiplex open drain output 20MHZ
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO_CRL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIO_CRL_MODE ((u32)0x33333333) ///< Port x mode bits
#define GPIO_CRL_MODE0_Pos (0)
#define GPIO_CRL_MODE0 (0x03U << GPIO_CRL_MODE0_Pos) ///< MODE0[1:0] bits (portx mode bits, pin 0)
#define GPIO_CRL_MODE0_0 (0x01U << GPIO_CRL_MODE0_Pos) ///< Bit 0
#define GPIO_CRL_MODE0_1 (0x02U << GPIO_CRL_MODE0_Pos) ///< Bit 1
#define GPIO_CRL_CNF0_Pos (2)
#define GPIO_CRL_CNF0 (0x03U << GPIO_CRL_CNF0_Pos) ///< CNF0[1:0] bits (portx configuration bits, pin 0)
#define GPIO_CRL_CNF0_0 (0x01U << GPIO_CRL_CNF0_Pos) ///< Bit 0
#define GPIO_CRL_CNF0_1 (0x02U << GPIO_CRL_CNF0_Pos) ///< Bit 1
#define GPIO_CRL_MODE1_Pos (4)
#define GPIO_CRL_MODE1 (0x03U << GPIO_CRL_MODE1_Pos) ///< MODE1[1:0] bits (portx mode bits, pin 1)
#define GPIO_CRL_MODE1_0 (0x01U << GPIO_CRL_MODE1_Pos) ///< Bit 0
#define GPIO_CRL_MODE1_1 (0x02U << GPIO_CRL_MODE1_Pos) ///< Bit 1
#define GPIO_CRL_CNF1_Pos (6)
#define GPIO_CRL_CNF1 (0x03U << GPIO_CRL_CNF1_Pos) ///< CNF1[1:0] bits (portx configuration bits, pin 1)
#define GPIO_CRL_CNF1_0 (0x01U << GPIO_CRL_CNF1_Pos) ///< Bit 0
#define GPIO_CRL_CNF1_1 (0x02U << GPIO_CRL_CNF1_Pos) ///< Bit 1
#define GPIO_CRL_MODE2_Pos (8)
#define GPIO_CRL_MODE2 (0x03U << GPIO_CRL_MODE2_Pos) ///< MODE2[1:0] bits (portx mode bits, pin 2)
#define GPIO_CRL_MODE2_0 (0x01U << GPIO_CRL_MODE2_Pos) ///< Bit 0
#define GPIO_CRL_MODE2_1 (0x02U << GPIO_CRL_MODE2_Pos) ///< Bit 1
#define GPIO_CRL_CNF2_Pos (10)
#define GPIO_CRL_CNF2 (0x03U << GPIO_CRL_CNF2_Pos) ///< CNF2[1:0] bits (portx configuration bits, pin 2)
#define GPIO_CRL_CNF2_0 (0x01U << GPIO_CRL_CNF2_Pos) ///< Bit 0
#define GPIO_CRL_CNF2_1 (0x02U << GPIO_CRL_CNF2_Pos) ///< Bit 1
#define GPIO_CRL_MODE3_Pos (12)
#define GPIO_CRL_MODE3 (0x03U << GPIO_CRL_MODE3_Pos) ///< MODE3[1:0] bits (portx mode bits, pin 3)
#define GPIO_CRL_MODE3_0 (0x01U << GPIO_CRL_MODE3_Pos) ///< Bit 0
#define GPIO_CRL_MODE3_1 (0x02U << GPIO_CRL_MODE3_Pos) ///< Bit 1
#define GPIO_CRL_CNF3_Pos (14)
#define GPIO_CRL_CNF3 (0x03U << GPIO_CRL_CNF3_Pos) ///< CNF3[1:0] bits (portx configuration bits, pin 3)
#define GPIO_CRL_CNF3_0 (0x01U << GPIO_CRL_CNF3_Pos) ///< Bit 0
#define GPIO_CRL_CNF3_1 (0x02U << GPIO_CRL_CNF3_Pos) ///< Bit 1
#define GPIO_CRL_MODE4_Pos (16)
#define GPIO_CRL_MODE4 (0x03U << GPIO_CRL_MODE4_Pos) ///< MODE4[1:0] bits (portx mode bits, pin 4)
#define GPIO_CRL_MODE4_0 (0x01U << GPIO_CRL_MODE4_Pos) ///< Bit 0
#define GPIO_CRL_MODE4_1 (0x02U << GPIO_CRL_MODE4_Pos) ///< Bit 1
#define GPIO_CRL_CNF4_Pos (18)
#define GPIO_CRL_CNF4 (0x03U << GPIO_CRL_CNF4_Pos) ///< CNF4[1:0] bits (portx configuration bits, pin 4)
#define GPIO_CRL_CNF4_0 (0x01U << GPIO_CRL_CNF4_Pos) ///< Bit 0
#define GPIO_CRL_CNF4_1 (0x02U << GPIO_CRL_CNF4_Pos) ///< Bit 1
#define GPIO_CRL_MODE5_Pos (20)
#define GPIO_CRL_MODE5 (0x03U << GPIO_CRL_MODE5_Pos) ///< MODE5[1:0] bits (portx mode bits, pin 5)
#define GPIO_CRL_MODE5_0 (0x01U << GPIO_CRL_MODE5_Pos) ///< Bit 0
#define GPIO_CRL_MODE5_1 (0x02U << GPIO_CRL_MODE5_Pos) ///< Bit 1
#define GPIO_CRL_CNF5_Pos (22)
#define GPIO_CRL_CNF5 (0x03U << GPIO_CRL_CNF5_Pos) ///< CNF5[1:0] bits (portx configuration bits, pin 5)
#define GPIO_CRL_CNF5_0 (0x01U << GPIO_CRL_CNF5_Pos) ///< Bit 0
#define GPIO_CRL_CNF5_1 (0x02U << GPIO_CRL_CNF5_Pos) ///< Bit 1
#define GPIO_CRL_MODE6_Pos (24)
#define GPIO_CRL_MODE6 (0x03U << GPIO_CRL_MODE6_Pos) ///< MODE6[1:0] bits (portx mode bits, pin 6)
#define GPIO_CRL_MODE6_0 (0x01U << GPIO_CRL_MODE6_Pos) ///< Bit 0
#define GPIO_CRL_MODE6_1 (0x02U << GPIO_CRL_MODE6_Pos) ///< Bit 1
#define GPIO_CRL_CNF6_Pos (26)
#define GPIO_CRL_CNF6 (0x03U << GPIO_CRL_CNF6_Pos) ///< CNF6[1:0] bits (portx configuration bits, pin 6)
#define GPIO_CRL_CNF6_0 (0x01U << GPIO_CRL_CNF6_Pos) ///< Bit 0
#define GPIO_CRL_CNF6_1 (0x02U << GPIO_CRL_CNF6_Pos) ///< Bit 1
#define GPIO_CRL_MODE7_Pos (28)
#define GPIO_CRL_MODE7 (0x03U << GPIO_CRL_MODE7_Pos) ///< MODE7[1:0] bits (portx mode bits, pin 7)
#define GPIO_CRL_MODE7_0 (0x01U << GPIO_CRL_MODE7_Pos) ///< Bit 0
#define GPIO_CRL_MODE7_1 (0x02U << GPIO_CRL_MODE7_Pos) ///< Bit 1
#define GPIO_CRL_CNF7_Pos (30)
#define GPIO_CRL_CNF7 (0x03U << GPIO_CRL_CNF7_Pos) ///< CNF7[1:0] bits (portx configuration bits, pin 7)
#define GPIO_CRL_CNF7_0 (0x01U << GPIO_CRL_CNF7_Pos) ///< Bit 0
#define GPIO_CRL_CNF7_1 (0x02U << GPIO_CRL_CNF7_Pos) ///< Bit 1
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO_CRH Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIO_CRH_MODE ((u32)0x33333333) ///< Port x mode bits
#define GPIO_CRH_MODE8_Pos (0)
#define GPIO_CRH_MODE8 (0x03U << GPIO_CRH_MODE8_Pos) ///< MODE8[1:0] bits (portx mode bits, pin 0)
#define GPIO_CRH_MODE8_0 (0x01U << GPIO_CRH_MODE8_Pos) ///< Bit 0
#define GPIO_CRH_MODE8_1 (0x02U << GPIO_CRH_MODE8_Pos) ///< Bit 1
#define GPIO_CRH_CNF8_Pos (2)
#define GPIO_CRH_CNF8 (0x03U << GPIO_CRH_CNF8_Pos) ///< CNF8[1:0] bits (portx configuration bits, pin 0)
#define GPIO_CRH_CNF8_0 (0x01U << GPIO_CRH_CNF8_Pos) ///< Bit 0
#define GPIO_CRH_CNF8_1 (0x02U << GPIO_CRH_CNF8_Pos) ///< Bit 1
#define GPIO_CRH_MODE9_Pos (4)
#define GPIO_CRH_MODE9 (0x03U << GPIO_CRH_MODE9_Pos) ///< MODE9[1:0] bits (portx mode bits, pin 1)
#define GPIO_CRH_MODE9_0 (0x01U << GPIO_CRH_MODE9_Pos) ///< Bit 0
#define GPIO_CRH_MODE9_1 (0x02U << GPIO_CRH_MODE9_Pos) ///< Bit 1
#define GPIO_CRH_CNF9_Pos (6)
#define GPIO_CRH_CNF9 (0x03U << GPIO_CRH_CNF9_Pos) ///< CNF9[1:0] bits (portx configuration bits, pin 1)
#define GPIO_CRH_CNF9_0 (0x01U << GPIO_CRH_CNF9_Pos) ///< Bit 0
#define GPIO_CRH_CNF9_1 (0x02U << GPIO_CRH_CNF9_Pos) ///< Bit 1
#define GPIO_CRH_MODE10_Pos (8)
#define GPIO_CRH_MODE10 (0x03U << GPIO_CRH_MODE10_Pos) ///< MODE10[1:0] bits (portx mode bits, pin 2)
#define GPIO_CRH_MODE10_0 (0x01U << GPIO_CRH_MODE10_Pos) ///< Bit 0
#define GPIO_CRH_MODE10_1 (0x02U << GPIO_CRH_MODE10_Pos) ///< Bit 1
#define GPIO_CRH_CNF10_Pos (10)
#define GPIO_CRH_CNF10 (0x03U << GPIO_CRH_CNF10_Pos) ///< CNF10[1:0] bits (portx configuration bits, pin 2)
#define GPIO_CRH_CNF10_0 (0x01U << GPIO_CRH_CNF10_Pos) ///< Bit 0
#define GPIO_CRH_CNF10_1 (0x02U << GPIO_CRH_CNF10_Pos) ///< Bit 1
#define GPIO_CRH_MODE11_Pos (12)
#define GPIO_CRH_MODE11 (0x03U << GPIO_CRH_MODE11_Pos) ///< MODE11[1:0] bits (portx mode bits, pin 3)
#define GPIO_CRH_MODE11_0 (0x01U << GPIO_CRH_MODE11_Pos) ///< Bit 0
#define GPIO_CRH_MODE11_1 (0x02U << GPIO_CRH_MODE11_Pos) ///< Bit 1
#define GPIO_CRH_CNF11_Pos (14)
#define GPIO_CRH_CNF11 (0x03U << GPIO_CRH_CNF11_Pos) ///< CNF11[1:0] bits (portx configuration bits, pin 3)
#define GPIO_CRH_CNF11_0 (0x01U << GPIO_CRH_CNF11_Pos) ///< Bit 0
#define GPIO_CRH_CNF11_1 (0x02U << GPIO_CRH_CNF11_Pos) ///< Bit 1
#define GPIO_CRH_MODE12_Pos (16)
#define GPIO_CRH_MODE12 (0x03U << GPIO_CRH_MODE12_Pos) ///< MODE12[1:0] bits (portx mode bits, pin 4)
#define GPIO_CRH_MODE12_0 (0x01U << GPIO_CRH_MODE12_Pos) ///< Bit 0
#define GPIO_CRH_MODE12_1 (0x02U << GPIO_CRH_MODE12_Pos) ///< Bit 1
#define GPIO_CRH_CNF12_Pos (18)
#define GPIO_CRH_CNF12 (0x03U << GPIO_CRH_CNF12_Pos) ///< CNF12[1:0] bits (portx configuration bits, pin 4)
#define GPIO_CRH_CNF12_0 (0x01U << GPIO_CRH_CNF12_Pos) ///< Bit 0
#define GPIO_CRH_CNF12_1 (0x02U << GPIO_CRH_CNF12_Pos) ///< Bit 1
#define GPIO_CRH_MODE13_Pos (20)
#define GPIO_CRH_MODE13 (0x03U << GPIO_CRH_MODE13_Pos) ///< MODE13[1:0] bits (portx mode bits, pin 5)
#define GPIO_CRH_MODE13_0 (0x01U << GPIO_CRH_MODE13_Pos) ///< Bit 0
#define GPIO_CRH_MODE13_1 (0x02U << GPIO_CRH_MODE13_Pos) ///< Bit 1
#define GPIO_CRH_CNF13_Pos (22)
#define GPIO_CRH_CNF13 (0x03U << GPIO_CRH_CNF13_Pos) ///< CNF13[1:0] bits (portx configuration bits, pin 5)
#define GPIO_CRH_CNF13_0 (0x01U << GPIO_CRH_CNF13_Pos) ///< Bit 0
#define GPIO_CRH_CNF13_1 (0x02U << GPIO_CRH_CNF13_Pos) ///< Bit 1
#define GPIO_CRH_MODE14_Pos (24)
#define GPIO_CRH_MODE14 (0x03U << GPIO_CRH_MODE14_Pos) ///< MODE14[1:0] bits (portx mode bits, pin 6)
#define GPIO_CRH_MODE14_0 (0x01U << GPIO_CRH_MODE14_Pos) ///< Bit 0
#define GPIO_CRH_MODE14_1 (0x02U << GPIO_CRH_MODE14_Pos) ///< Bit 1
#define GPIO_CRH_CNF14_Pos (26)
#define GPIO_CRH_CNF14 (0x03U << GPIO_CRH_CNF14_Pos) ///< CNF14[1:0] bits (portx configuration bits, pin 6)
#define GPIO_CRH_CNF14_0 (0x01U << GPIO_CRH_CNF14_Pos) ///< Bit 0
#define GPIO_CRH_CNF14_1 (0x02U << GPIO_CRH_CNF14_Pos) ///< Bit 1
#define GPIO_CRH_MODE15_Pos (28)
#define GPIO_CRH_MODE15 (0x03U << GPIO_CRH_MODE15_Pos) ///< MODE15[1:0] bits (portx mode bits, pin 7)
#define GPIO_CRH_MODE15_0 (0x01U << GPIO_CRH_MODE15_Pos) ///< Bit 0
#define GPIO_CRH_MODE15_1 (0x02U << GPIO_CRH_MODE15_Pos) ///< Bit 1
#define GPIO_CRH_CNF15_Pos (30)
#define GPIO_CRH_CNF15 (0x03U << GPIO_CRH_CNF15_Pos) ///< CNF15[1:0] bits (portx configuration bits, pin 7)
#define GPIO_CRH_CNF15_0 (0x01U << GPIO_CRH_CNF15_Pos) ///< Bit 0
#define GPIO_CRH_CNF15_1 (0x02U << GPIO_CRH_CNF15_Pos) ///< Bit 1
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO_IDR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIO_IDR_DATA_Pos (0)
#define GPIO_IDR_DATA (0xFFFFU << GPIO_IDR_DATA_Pos) ///< Port input data
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO_IDR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIO_IDR_IDR0_Pos (0)
#define GPIO_IDR_IDR0 (0x01U << GPIO_IDR_IDR0_Pos) ///< Portx Set bit 0
#define GPIO_IDR_IDR1_Pos (1)
#define GPIO_IDR_IDR1 (0x01U << GPIO_IDR_IDR1_Pos) ///< Portx Set bit 1
#define GPIO_IDR_IDR2_Pos (2)
#define GPIO_IDR_IDR2 (0x01U << GPIO_IDR_IDR2_Pos) ///< Portx Set bit 2
#define GPIO_IDR_IDR3_Pos (3)
#define GPIO_IDR_IDR3 (0x01U << GPIO_IDR_IDR3_Pos) ///< Portx Set bit 3
#define GPIO_IDR_IDR4_Pos (4)
#define GPIO_IDR_IDR4 (0x01U << GPIO_IDR_IDR4_Pos) ///< Portx Set bit 4
#define GPIO_IDR_IDR5_Pos (5)
#define GPIO_IDR_IDR5 (0x01U << GPIO_IDR_IDR5_Pos) ///< Portx Set bit 5
#define GPIO_IDR_IDR6_Pos (6)
#define GPIO_IDR_IDR6 (0x01U << GPIO_IDR_IDR6_Pos) ///< Portx Set bit 6
#define GPIO_IDR_IDR7_Pos (7)
#define GPIO_IDR_IDR7 (0x01U << GPIO_IDR_IDR7_Pos) ///< Portx Set bit 7
#define GPIO_IDR_IDR8_Pos (8)
#define GPIO_IDR_IDR8 (0x01U << GPIO_IDR_IDR8_Pos) ///< Portx Set bit 8
#define GPIO_IDR_IDR9_Pos (9)
#define GPIO_IDR_IDR9 (0x01U << GPIO_IDR_IDR9_Pos) ///< Portx Set bit 9
#define GPIO_IDR_IDR10_Pos (10)
#define GPIO_IDR_IDR10 (0x01U << GPIO_IDR_IDR10_Pos) ///< Portx Set bit 10
#define GPIO_IDR_IDR11_Pos (11)
#define GPIO_IDR_IDR11 (0x01U << GPIO_IDR_IDR11_Pos) ///< Portx Set bit 11
#define GPIO_IDR_IDR12_Pos (12)
#define GPIO_IDR_IDR12 (0x01U << GPIO_IDR_IDR12_Pos) ///< Portx Set bit 12
#define GPIO_IDR_IDR13_Pos (13)
#define GPIO_IDR_IDR13 (0x01U << GPIO_IDR_IDR13_Pos) ///< Portx Set bit 13
#define GPIO_IDR_IDR14_Pos (14)
#define GPIO_IDR_IDR14 (0x01U << GPIO_IDR_IDR14_Pos) ///< Portx Set bit 14
#define GPIO_IDR_IDR15_Pos (15)
#define GPIO_IDR_IDR15 (0x01U << GPIO_IDR_IDR15_Pos) ///< Portx Set bit 15
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO_ODR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIO_ODR_DATA_Pos (0)
#define GPIO_ODR_DATA (0xFFFF << GPIO_ODR_DATA_Pos) ///< Port output data
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO_ODR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIO_ODR_ODR0_Pos (0)
#define GPIO_ODR_ODR0 (0x01U << GPIO_ODR_ODR0_Pos) ///< Portx Set bit 0
#define GPIO_ODR_ODR1_Pos (1)
#define GPIO_ODR_ODR1 (0x01U << GPIO_ODR_ODR1_Pos) ///< Portx Set bit 1
#define GPIO_ODR_ODR2_Pos (2)
#define GPIO_ODR_ODR2 (0x01U << GPIO_ODR_ODR2_Pos) ///< Portx Set bit 2
#define GPIO_ODR_ODR3_Pos (3)
#define GPIO_ODR_ODR3 (0x01U << GPIO_ODR_ODR3_Pos) ///< Portx Set bit 3
#define GPIO_ODR_ODR4_Pos (4)
#define GPIO_ODR_ODR4 (0x01U << GPIO_ODR_ODR4_Pos) ///< Portx Set bit 4
#define GPIO_ODR_ODR5_Pos (5)
#define GPIO_ODR_ODR5 (0x01U << GPIO_ODR_ODR5_Pos) ///< Portx Set bit 5
#define GPIO_ODR_ODR6_Pos (6)
#define GPIO_ODR_ODR6 (0x01U << GPIO_ODR_ODR6_Pos) ///< Portx Set bit 6
#define GPIO_ODR_ODR7_Pos (7)
#define GPIO_ODR_ODR7 (0x01U << GPIO_ODR_ODR7_Pos) ///< Portx Set bit 7
#define GPIO_ODR_ODR8_Pos (8)
#define GPIO_ODR_ODR8 (0x01U << GPIO_ODR_ODR8_Pos) ///< Portx Set bit 8
#define GPIO_ODR_ODR9_Pos (9)
#define GPIO_ODR_ODR9 (0x01U << GPIO_ODR_ODR9_Pos) ///< Portx Set bit 9
#define GPIO_ODR_ODR10_Pos (10)
#define GPIO_ODR_ODR10 (0x01U << GPIO_ODR_ODR10_Pos) ///< Portx Set bit 10
#define GPIO_ODR_ODR11_Pos (11)
#define GPIO_ODR_ODR11 (0x01U << GPIO_ODR_ODR11_Pos) ///< Portx Set bit 11
#define GPIO_ODR_ODR12_Pos (12)
#define GPIO_ODR_ODR12 (0x01U << GPIO_ODR_ODR12_Pos) ///< Portx Set bit 12
#define GPIO_ODR_ODR13_Pos (13)
#define GPIO_ODR_ODR13 (0x01U << GPIO_ODR_ODR13_Pos) ///< Portx Set bit 13
#define GPIO_ODR_ODR14_Pos (14)
#define GPIO_ODR_ODR14 (0x01U << GPIO_ODR_ODR14_Pos) ///< Portx Set bit 14
#define GPIO_ODR_ODR15_Pos (15)
#define GPIO_ODR_ODR15 (0x01U << GPIO_ODR_ODR15_Pos) ///< Portx Set bit 15
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO_BRR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIO_BSRR_BS_Pos (0)
#define GPIO_BSRR_BS (0xFFFFU << GPIO_BSRR_BS_Pos) ///< Portx Reset
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO_BSRR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIO_BSRR_BS0_Pos (0)
#define GPIO_BSRR_BS0 (0x01U << GPIO_BSRR_BS0_Pos) ///< Portx Set bit 0
#define GPIO_BSRR_BS1_Pos (1)
#define GPIO_BSRR_BS1 (0x01U << GPIO_BSRR_BS1_Pos) ///< Portx Set bit 1
#define GPIO_BSRR_BS2_Pos (2)
#define GPIO_BSRR_BS2 (0x01U << GPIO_BSRR_BS2_Pos) ///< Portx Set bit 2
#define GPIO_BSRR_BS3_Pos (3)
#define GPIO_BSRR_BS3 (0x01U << GPIO_BSRR_BS3_Pos) ///< Portx Set bit 3
#define GPIO_BSRR_BS4_Pos (4)
#define GPIO_BSRR_BS4 (0x01U << GPIO_BSRR_BS4_Pos) ///< Portx Set bit 4
#define GPIO_BSRR_BS5_Pos (5)
#define GPIO_BSRR_BS5 (0x01U << GPIO_BSRR_BS5_Pos) ///< Portx Set bit 5
#define GPIO_BSRR_BS6_Pos (6)
#define GPIO_BSRR_BS6 (0x01U << GPIO_BSRR_BS6_Pos) ///< Portx Set bit 6
#define GPIO_BSRR_BS7_Pos (7)
#define GPIO_BSRR_BS7 (0x01U << GPIO_BSRR_BS7_Pos) ///< Portx Set bit 7
#define GPIO_BSRR_BS8_Pos (8)
#define GPIO_BSRR_BS8 (0x01U << GPIO_BSRR_BS8_Pos) ///< Portx Set bit 8
#define GPIO_BSRR_BS9_Pos (9)
#define GPIO_BSRR_BS9 (0x01U << GPIO_BSRR_BS9_Pos) ///< Portx Set bit 9
#define GPIO_BSRR_BS10_Pos (10)
#define GPIO_BSRR_BS10 (0x01U << GPIO_BSRR_BS10_Pos) ///< Portx Set bit 10
#define GPIO_BSRR_BS11_Pos (11)
#define GPIO_BSRR_BS11 (0x01U << GPIO_BSRR_BS11_Pos) ///< Portx Set bit 11
#define GPIO_BSRR_BS12_Pos (12)
#define GPIO_BSRR_BS12 (0x01U << GPIO_BSRR_BS12_Pos) ///< Portx Set bit 12
#define GPIO_BSRR_BS13_Pos (13)
#define GPIO_BSRR_BS13 (0x01U << GPIO_BSRR_BS13_Pos) ///< Portx Set bit 13
#define GPIO_BSRR_BS14_Pos (14)
#define GPIO_BSRR_BS14 (0x01U << GPIO_BSRR_BS14_Pos) ///< Portx Set bit 14
#define GPIO_BSRR_BS15_Pos (15)
#define GPIO_BSRR_BS15 (0x01U << GPIO_BSRR_BS15_Pos) ///< Portx Set bit 15
#define GPIO_BSRR_BR0_Pos (16)
#define GPIO_BSRR_BR0 (0x01U << GPIO_BSRR_BR0_Pos) ///< Portx Reset bit 0
#define GPIO_BSRR_BR1_Pos (17)
#define GPIO_BSRR_BR1 (0x01U << GPIO_BSRR_BR1_Pos) ///< Portx Reset bit 1
#define GPIO_BSRR_BR2_Pos (18)
#define GPIO_BSRR_BR2 (0x01U << GPIO_BSRR_BR2_Pos) ///< Portx Reset bit 2
#define GPIO_BSRR_BR3_Pos (19)
#define GPIO_BSRR_BR3 (0x01U << GPIO_BSRR_BR3_Pos) ///< Portx Reset bit 3
#define GPIO_BSRR_BR4_Pos (20)
#define GPIO_BSRR_BR4 (0x01U << GPIO_BSRR_BR4_Pos) ///< Portx Reset bit 4
#define GPIO_BSRR_BR5_Pos (21)
#define GPIO_BSRR_BR5 (0x01U << GPIO_BSRR_BR5_Pos) ///< Portx Reset bit 5
#define GPIO_BSRR_BR6_Pos (22)
#define GPIO_BSRR_BR6 (0x01U << GPIO_BSRR_BR6_Pos) ///< Portx Reset bit 6
#define GPIO_BSRR_BR7_Pos (23)
#define GPIO_BSRR_BR7 (0x01U << GPIO_BSRR_BR7_Pos) ///< Portx Reset bit 7
#define GPIO_BSRR_BR8_Pos (24)
#define GPIO_BSRR_BR8 (0x01U << GPIO_BSRR_BR8_Pos) ///< Portx Reset bit 8
#define GPIO_BSRR_BR9_Pos (25)
#define GPIO_BSRR_BR9 (0x01U << GPIO_BSRR_BR9_Pos) ///< Portx Reset bit 9
#define GPIO_BSRR_BR10_Pos (26)
#define GPIO_BSRR_BR10 (0x01U << GPIO_BSRR_BR10_Pos) ///< Portx Reset bit 10
#define GPIO_BSRR_BR11_Pos (27)
#define GPIO_BSRR_BR11 (0x01U << GPIO_BSRR_BR11_Pos) ///< Portx Reset bit 11
#define GPIO_BSRR_BR12_Pos (28)
#define GPIO_BSRR_BR12 (0x01U << GPIO_BSRR_BR12_Pos) ///< Portx Reset bit 12
#define GPIO_BSRR_BR13_Pos (29)
#define GPIO_BSRR_BR13 (0x01U << GPIO_BSRR_BR13_Pos) ///< Portx Reset bit 13
#define GPIO_BSRR_BR14_Pos (30)
#define GPIO_BSRR_BR14 (0x01U << GPIO_BSRR_BR14_Pos) ///< Portx Reset bit 14
#define GPIO_BSRR_BR15_Pos (31)
#define GPIO_BSRR_BR15 (0x01U << GPIO_BSRR_BR15_Pos) ///< Portx Reset bit 15
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO_BRR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIO_BRR_BR_Pos (0)
#define GPIO_BRR_BR (0xFFFFU << GPIO_BRR_BR_Pos) ///< Portx Reset
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO_BRR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIO_BRR_BR0_Pos (0)
#define GPIO_BRR_BR0 (0x01U << GPIO_BRR_BR0_Pos) ///< Portx Set bit 0
#define GPIO_BRR_BR1_Pos (1)
#define GPIO_BRR_BR1 (0x01U << GPIO_BRR_BR1_Pos) ///< Portx Set bit 1
#define GPIO_BRR_BR2_Pos (2)
#define GPIO_BRR_BR2 (0x01U << GPIO_BRR_BR2_Pos) ///< Portx Set bit 2
#define GPIO_BRR_BR3_Pos (3)
#define GPIO_BRR_BR3 (0x01U << GPIO_BRR_BR3_Pos) ///< Portx Set bit 3
#define GPIO_BRR_BR4_Pos (4)
#define GPIO_BRR_BR4 (0x01U << GPIO_BRR_BR4_Pos) ///< Portx Set bit 4
#define GPIO_BRR_BR5_Pos (5)
#define GPIO_BRR_BR5 (0x01U << GPIO_BRR_BR5_Pos) ///< Portx Set bit 5
#define GPIO_BRR_BR6_Pos (6)
#define GPIO_BRR_BR6 (0x01U << GPIO_BRR_BR6_Pos) ///< Portx Set bit 6
#define GPIO_BRR_BR7_Pos (7)
#define GPIO_BRR_BR7 (0x01U << GPIO_BRR_BR7_Pos) ///< Portx Set bit 7
#define GPIO_BRR_BR8_Pos (8)
#define GPIO_BRR_BR8 (0x01U << GPIO_BRR_BR8_Pos) ///< Portx Set bit 8
#define GPIO_BRR_BR9_Pos (9)
#define GPIO_BRR_BR9 (0x01U << GPIO_BRR_BR9_Pos) ///< Portx Set bit 9
#define GPIO_BRR_BR10_Pos (10)
#define GPIO_BRR_BR10 (0x01U << GPIO_BRR_BR10_Pos) ///< Portx Set bit 10
#define GPIO_BRR_BR11_Pos (11)
#define GPIO_BRR_BR11 (0x01U << GPIO_BRR_BR11_Pos) ///< Portx Set bit 11
#define GPIO_BRR_BR12_Pos (12)
#define GPIO_BRR_BR12 (0x01U << GPIO_BRR_BR12_Pos) ///< Portx Set bit 12
#define GPIO_BRR_BR13_Pos (13)
#define GPIO_BRR_BR13 (0x01U << GPIO_BRR_BR13_Pos) ///< Portx Set bit 13
#define GPIO_BRR_BR14_Pos (14)
#define GPIO_BRR_BR14 (0x01U << GPIO_BRR_BR14_Pos) ///< Portx Set bit 14
#define GPIO_BRR_BR15_Pos (15)
#define GPIO_BRR_BR15 (0x01U << GPIO_BRR_BR15_Pos) ///< Portx Set bit 15
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO_LCKR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIO_LCKR_LCK_Pos (0)
#define GPIO_LCKR_LCK (0xFFFFU << GPIO_LCKR_LCK_Pos) ///< Portx Lock
#define GPIO_LCKR_LCKK_Pos (16)
#define GPIO_LCKR_LCKK (0x01U << GPIO_LCKR_LCKK_Pos) ///< Lock key
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO_LCKR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIO_LCKR_LCK0_Pos (0)
#define GPIO_LCKR_LCK0 (0x01U << GPIO_LCKR_LCK0_Pos) ///< Portx Set bit 0
#define GPIO_LCKR_LCK1_Pos (1)
#define GPIO_LCKR_LCK1 (0x01U << GPIO_LCKR_LCK1_Pos) ///< Portx Set bit 1
#define GPIO_LCKR_LCK2_Pos (2)
#define GPIO_LCKR_LCK2 (0x01U << GPIO_LCKR_LCK2_Pos) ///< Portx Set bit 2
#define GPIO_LCKR_LCK3_Pos (3)
#define GPIO_LCKR_LCK3 (0x01U << GPIO_LCKR_LCK3_Pos) ///< Portx Set bit 3
#define GPIO_LCKR_LCK4_Pos (4)
#define GPIO_LCKR_LCK4 (0x01U << GPIO_LCKR_LCK4_Pos) ///< Portx Set bit 4
#define GPIO_LCKR_LCK5_Pos (5)
#define GPIO_LCKR_LCK5 (0x01U << GPIO_LCKR_LCK5_Pos) ///< Portx Set bit 5
#define GPIO_LCKR_LCK6_Pos (6)
#define GPIO_LCKR_LCK6 (0x01U << GPIO_LCKR_LCK6_Pos) ///< Portx Set bit 6
#define GPIO_LCKR_LCK7_Pos (7)
#define GPIO_LCKR_LCK7 (0x01U << GPIO_LCKR_LCK7_Pos) ///< Portx Set bit 7
#define GPIO_LCKR_LCK8_Pos (8)
#define GPIO_LCKR_LCK8 (0x01U << GPIO_LCKR_LCK8_Pos) ///< Portx Set bit 8
#define GPIO_LCKR_LCK9_Pos (9)
#define GPIO_LCKR_LCK9 (0x01U << GPIO_LCKR_LCK9_Pos) ///< Portx Set bit 9
#define GPIO_LCKR_LCK10_Pos (10)
#define GPIO_LCKR_LCK10 (0x01U << GPIO_LCKR_LCK10_Pos) ///< Portx Set bit 10
#define GPIO_LCKR_LCK11_Pos (11)
#define GPIO_LCKR_LCK11 (0x01U << GPIO_LCKR_LCK11_Pos) ///< Portx Set bit 11
#define GPIO_LCKR_LCK12_Pos (12)
#define GPIO_LCKR_LCK12 (0x01U << GPIO_LCKR_LCK12_Pos) ///< Portx Set bit 12
#define GPIO_LCKR_LCK13_Pos (13)
#define GPIO_LCKR_LCK13 (0x01U << GPIO_LCKR_LCK13_Pos) ///< Portx Set bit 13
#define GPIO_LCKR_LCK14_Pos (14)
#define GPIO_LCKR_LCK14 (0x01U << GPIO_LCKR_LCK14_Pos) ///< Portx Set bit 14
#define GPIO_LCKR_LCK15_Pos (15)
#define GPIO_LCKR_LCK15 (0x01U << GPIO_LCKR_LCK15_Pos) ///< Portx Set bit 15
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO_DCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIO_DCR_PX0_Pos (0)
#define GPIO_DCR_PX0 (0x03U << GPIO_DCR_PX0_Pos) ///< PX0[1:0] bits (pinx configuration bits, pin 0)
#define GPIO_DCR_PX0_MODE0 (0x00U << GPIO_DCR_PX0_Pos) ///< Mode = 0
#define GPIO_DCR_PX0_MODE1 (0x01U << GPIO_DCR_PX0_Pos) ///< Mode = 1
#define GPIO_DCR_PX0_MODE2 (0x02U << GPIO_DCR_PX0_Pos) ///< Mode = 2
#define GPIO_DCR_PX0_MODE3 (0x03U << GPIO_DCR_PX0_Pos) ///< Mode = 3
#define GPIO_DCR_PX1_Pos (2)
#define GPIO_DCR_PX1 (0x03U << GPIO_DCR_PX1_Pos) ///< PX1[1:0] bits (pinx configuration bits, pin 1)
#define GPIO_DCR_PX1_MODE0 (0x00U << GPIO_DCR_PX1_Pos) ///< Mode = 0
#define GPIO_DCR_PX1_MODE1 (0x01U << GPIO_DCR_PX1_Pos) ///< Mode = 1
#define GPIO_DCR_PX1_MODE2 (0x02U << GPIO_DCR_PX1_Pos) ///< Mode = 2
#define GPIO_DCR_PX1_MODE3 (0x03U << GPIO_DCR_PX1_Pos) ///< Mode = 3
#define GPIO_DCR_PX2_Pos (4)
#define GPIO_DCR_PX2 (0x03U << GPIO_DCR_PX2_Pos) ///< PX2[1:0] bits (pinx configuration bits, pin 2)
#define GPIO_DCR_PX2_MODE0 (0x00U << GPIO_DCR_PX2_Pos) ///< Mode = 0
#define GPIO_DCR_PX2_MODE1 (0x01U << GPIO_DCR_PX2_Pos) ///< Mode = 1
#define GPIO_DCR_PX2_MODE2 (0x02U << GPIO_DCR_PX2_Pos) ///< Mode = 2
#define GPIO_DCR_PX2_MODE3 (0x03U << GPIO_DCR_PX2_Pos) ///< Mode = 3
#define GPIO_DCR_PX3_Pos (6)
#define GPIO_DCR_PX3 (0x03U << GPIO_DCR_PX3_Pos) ///< PX3[1:0] bits (pinx configuration bits, pin 3)
#define GPIO_DCR_PX3_MODE0 (0x00U << GPIO_DCR_PX3_Pos) ///< Mode = 0
#define GPIO_DCR_PX3_MODE1 (0x01U << GPIO_DCR_PX3_Pos) ///< Mode = 1
#define GPIO_DCR_PX3_MODE2 (0x02U << GPIO_DCR_PX3_Pos) ///< Mode = 2
#define GPIO_DCR_PX3_MODE3 (0x03U << GPIO_DCR_PX3_Pos) ///< Mode = 3
#define GPIO_DCR_PX4_Pos (8)
#define GPIO_DCR_PX4 (0x03U << GPIO_DCR_PX4_Pos) ///< PX4[1:0] bits (pinx configuration bits, pin 4)
#define GPIO_DCR_PX4_MODE0 (0x00U << GPIO_DCR_PX4_Pos) ///< Mode = 0
#define GPIO_DCR_PX4_MODE1 (0x01U << GPIO_DCR_PX4_Pos) ///< Mode = 1
#define GPIO_DCR_PX4_MODE2 (0x02U << GPIO_DCR_PX4_Pos) ///< Mode = 2
#define GPIO_DCR_PX4_MODE3 (0x03U << GPIO_DCR_PX4_Pos) ///< Mode = 3
#define GPIO_DCR_PX5_Pos (10)
#define GPIO_DCR_PX5 (0x03U << GPIO_DCR_PX5_Pos) ///< PX5[1:0] bits (pinx configuration bits, pin 5)
#define GPIO_DCR_PX5_MODE0 (0x00U << GPIO_DCR_PX5_Pos) ///< Mode = 0
#define GPIO_DCR_PX5_MODE1 (0x01U << GPIO_DCR_PX5_Pos) ///< Mode = 1
#define GPIO_DCR_PX5_MODE2 (0x02U << GPIO_DCR_PX5_Pos) ///< Mode = 2
#define GPIO_DCR_PX5_MODE3 (0x03U << GPIO_DCR_PX5_Pos) ///< Mode = 3
#define GPIO_DCR_PX6_Pos (12)
#define GPIO_DCR_PX6 (0x03U << GPIO_DCR_PX6_Pos) ///< PX6[1:0] bits (pinx configuration bits, pin 6)
#define GPIO_DCR_PX6_MODE0 (0x00U << GPIO_DCR_PX6_Pos) ///< Mode = 0
#define GPIO_DCR_PX6_MODE1 (0x01U << GPIO_DCR_PX6_Pos) ///< Mode = 1
#define GPIO_DCR_PX6_MODE2 (0x02U << GPIO_DCR_PX6_Pos) ///< Mode = 2
#define GPIO_DCR_PX6_MODE3 (0x03U << GPIO_DCR_PX6_Pos) ///< Mode = 3
#define GPIO_DCR_PX7_Pos (14)
#define GPIO_DCR_PX7 (0x03U << GPIO_DCR_PX7_Pos) ///< PX7[1:0] bits (pinx configuration bits, pin 7)
#define GPIO_DCR_PX7_MODE0 (0x00U << GPIO_DCR_PX7_Pos) ///< Mode = 0
#define GPIO_DCR_PX7_MODE1 (0x01U << GPIO_DCR_PX7_Pos) ///< Mode = 1
#define GPIO_DCR_PX7_MODE2 (0x02U << GPIO_DCR_PX7_Pos) ///< Mode = 2
#define GPIO_DCR_PX7_MODE3 (0x03U << GPIO_DCR_PX7_Pos) ///< Mode = 3
#define GPIO_DCR_PX8_Pos (16)
#define GPIO_DCR_PX8 (0x03U << GPIO_DCR_PX8_Pos) ///< PX8[1:0] bits (pinx configuration bits, pin 8)
#define GPIO_DCR_PX8_MODE0 (0x00U << GPIO_DCR_PX8_Pos) ///< Mode = 0
#define GPIO_DCR_PX8_MODE1 (0x01U << GPIO_DCR_PX8_Pos) ///< Mode = 1
#define GPIO_DCR_PX8_MODE2 (0x02U << GPIO_DCR_PX8_Pos) ///< Mode = 2
#define GPIO_DCR_PX8_MODE3 (0x03U << GPIO_DCR_PX8_Pos) ///< Mode = 3
#define GPIO_DCR_PX9_Pos (18)
#define GPIO_DCR_PX9 (0x03U << GPIO_DCR_PX9_Pos) ///< PX9[1:0] bits (pinx configuration bits, pin 9)
#define GPIO_DCR_PX9_MODE0 (0x00U << GPIO_DCR_PX9_Pos) ///< Mode = 0
#define GPIO_DCR_PX9_MODE1 (0x01U << GPIO_DCR_PX9_Pos) ///< Mode = 1
#define GPIO_DCR_PX9_MODE2 (0x02U << GPIO_DCR_PX9_Pos) ///< Mode = 2
#define GPIO_DCR_PX9_MODE3 (0x03U << GPIO_DCR_PX9_Pos) ///< Mode = 3
#define GPIO_DCR_PX10_Pos (20)
#define GPIO_DCR_PX10 (0x03U << GPIO_DCR_PX10_Pos) ///< PX10[1:0] bits (pinx configuration bits, pin 10)
#define GPIO_DCR_PX10_MODE0 (0x00U << GPIO_DCR_PX10_Pos) ///< Mode = 0
#define GPIO_DCR_PX10_MODE1 (0x01U << GPIO_DCR_PX10_Pos) ///< Mode = 1
#define GPIO_DCR_PX10_MODE2 (0x02U << GPIO_DCR_PX10_Pos) ///< Mode = 2
#define GPIO_DCR_PX10_MODE3 (0x03U << GPIO_DCR_PX10_Pos) ///< Mode = 3
#define GPIO_DCR_PX11_Pos (22)
#define GPIO_DCR_PX11 (0x03U << GPIO_DCR_PX11_Pos) ///< PX11[1:0] bits (pinx configuration bits, pin 11)
#define GPIO_DCR_PX11_MODE0 (0x00U << GPIO_DCR_PX11_Pos) ///< Mode = 0
#define GPIO_DCR_PX11_MODE1 (0x01U << GPIO_DCR_PX11_Pos) ///< Mode = 1
#define GPIO_DCR_PX11_MODE2 (0x02U << GPIO_DCR_PX11_Pos) ///< Mode = 2
#define GPIO_DCR_PX11_MODE3 (0x03U << GPIO_DCR_PX11_Pos) ///< Mode = 3
#define GPIO_DCR_PX12_Pos (24)
#define GPIO_DCR_PX12 (0x03U << GPIO_DCR_PX12_Pos) ///< PX12[1:0] bits (pinx configuration bits, pin 12)
#define GPIO_DCR_PX12_MODE0 (0x00U << GPIO_DCR_PX12_Pos) ///< Mode = 0
#define GPIO_DCR_PX12_MODE1 (0x01U << GPIO_DCR_PX12_Pos) ///< Mode = 1
#define GPIO_DCR_PX12_MODE2 (0x02U << GPIO_DCR_PX12_Pos) ///< Mode = 2
#define GPIO_DCR_PX12_MODE3 (0x03U << GPIO_DCR_PX12_Pos) ///< Mode = 3
#define GPIO_DCR_PX13_Pos (26)
#define GPIO_DCR_PX13 (0x03U << GPIO_DCR_PX13_Pos) ///< PX13[1:0] bits (pinx configuration bits, pin 13)
#define GPIO_DCR_PX13_MODE0 (0x00U << GPIO_DCR_PX13_Pos) ///< Mode = 0
#define GPIO_DCR_PX13_MODE1 (0x01U << GPIO_DCR_PX13_Pos) ///< Mode = 1
#define GPIO_DCR_PX13_MODE2 (0x02U << GPIO_DCR_PX13_Pos) ///< Mode = 2
#define GPIO_DCR_PX13_MODE3 (0x03U << GPIO_DCR_PX13_Pos) ///< Mode = 3
#define GPIO_DCR_PX14_Pos (28)
#define GPIO_DCR_PX14 (0x03U << GPIO_DCR_PX14_Pos) ///< PX14[1:0] bits (pinx configuration bits, pin 14)
#define GPIO_DCR_PX14_MODE0 (0x00U << GPIO_DCR_PX14_Pos) ///< Mode = 0
#define GPIO_DCR_PX14_MODE1 (0x01U << GPIO_DCR_PX14_Pos) ///< Mode = 1
#define GPIO_DCR_PX14_MODE2 (0x02U << GPIO_DCR_PX14_Pos) ///< Mode = 2
#define GPIO_DCR_PX14_MODE3 (0x03U << GPIO_DCR_PX14_Pos) ///< Mode = 3
#define GPIO_DCR_PX15_Pos (30)
#define GPIO_DCR_PX15 (0x03U << GPIO_DCR_PX15_Pos) ///< PX15[1:0] bits (pinx configuration bits, pin 15)
#define GPIO_DCR_PX15_MODE0 (0x00U << GPIO_DCR_PX15_Pos) ///< Mode = 0
#define GPIO_DCR_PX15_MODE1 (0x01U << GPIO_DCR_PX15_Pos) ///< Mode = 1
#define GPIO_DCR_PX15_MODE2 (0x02U << GPIO_DCR_PX15_Pos) ///< Mode = 2
#define GPIO_DCR_PX15_MODE3 (0x03U << GPIO_DCR_PX15_Pos) ///< Mode = 3
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO_AFRL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIO_AFRL_AFR0_Pos (0)
#define GPIO_AFRL_AFR0 (0x0FU << GPIO_AFRL_AFR0_Pos) ///< Multiplexing function selection for bit 0 of portx
#define GPIO_AFRL_AFR1_Pos (4)
#define GPIO_AFRL_AFR1 (0x0FU << GPIO_AFRL_AFR1_Pos) ///< Multiplexing function selection for bit 1 of portx
#define GPIO_AFRL_AFR2_Pos (8)
#define GPIO_AFRL_AFR2 (0x0FU << GPIO_AFRL_AFR2_Pos) ///< Multiplexing function selection for bit 2 of portx
#define GPIO_AFRL_AFR3_Pos (12)
#define GPIO_AFRL_AFR3 (0x0FU << GPIO_AFRL_AFR3_Pos) ///< Multiplexing function selection for bit 3 of portx
#define GPIO_AFRL_AFR4_Pos (16)
#define GPIO_AFRL_AFR4 (0x0FU << GPIO_AFRL_AFR4_Pos) ///< Multiplexing function selection for bit 4 of portx
#define GPIO_AFRL_AFR5_Pos (20)
#define GPIO_AFRL_AFR5 (0x0FU << GPIO_AFRL_AFR5_Pos) ///< Multiplexing function selection for bit 5 of portx
#define GPIO_AFRL_AFR6_Pos (24)
#define GPIO_AFRL_AFR6 (0x0FU << GPIO_AFRL_AFR6_Pos) ///< Multiplexing function selection for bit 6 of portx
#define GPIO_AFRL_AFR7_Pos (28)
#define GPIO_AFRL_AFR7 (0x0FU << GPIO_AFRL_AFR7_Pos) ///< Multiplexing function selection for bit 7 of portx
////////////////////////////////////////////////////////////////////////////////
/// @brief GPIO_AFRH Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define GPIO_AFRH_AFR8_Pos (0)
#define GPIO_AFRH_AFR8 (0x0FU << GPIO_AFRH_AFR8_Pos) ///< Multiplexing function selection for bit 8 of portx
#define GPIO_AFRH_AFR9_Pos (4)
#define GPIO_AFRH_AFR9 (0x0FU << GPIO_AFRH_AFR9_Pos) ///< Multiplexing function selection for bit 9 of portx
#define GPIO_AFRH_AFR10_Pos (8)
#define GPIO_AFRH_AFR10 (0x0FU << GPIO_AFRH_AFR10_Pos) ///< Multiplexing function selection for bit 10 of portx
#define GPIO_AFRH_AFR11_Pos (12)
#define GPIO_AFRH_AFR11 (0x0FU << GPIO_AFRH_AFR11_Pos) ///< Multiplexing function selection for bit 11 of portx
#define GPIO_AFRH_AFR12_Pos (16)
#define GPIO_AFRH_AFR12 (0x0FU << GPIO_AFRH_AFR12_Pos) ///< Multiplexing function selection for bit 12 of portx
#define GPIO_AFRH_AFR13_Pos (20)
#define GPIO_AFRH_AFR13 (0x0FU << GPIO_AFRH_AFR13_Pos) ///< Multiplexing function selection for bit 13 of portx
#define GPIO_AFRH_AFR14_Pos (24)
#define GPIO_AFRH_AFR14 (0x0FU << GPIO_AFRH_AFR14_Pos) ///< Multiplexing function selection for bit 14 of portx
#define GPIO_AFRH_AFR15_Pos (28)
#define GPIO_AFRH_AFR15 (0x0FU << GPIO_AFRH_AFR15_Pos) ///< Multiplexing function selection for bit 15 of portx
#define GPIO_AF_MODEMASK (0x0FU) ///< Mode = 0
#define GPIO_AF_MODE0 (0x00U) ///< Mode = 0
#define GPIO_AF_MODE1 (0x01U) ///< Mode = 1
#define GPIO_AF_MODE2 (0x02U) ///< Mode = 2
#define GPIO_AF_MODE3 (0x03U) ///< Mode = 3
#define GPIO_AF_MODE4 (0x04U) ///< Mode = 4
#define GPIO_AF_MODE5 (0x05U) ///< Mode = 5
#define GPIO_AF_MODE6 (0x06U) ///< Mode = 6
#define GPIO_AF_MODE7 (0x07U) ///< Mode = 7
#define GPIO_AF_MODE8 (0x08U) ///< Mode = 8
#define GPIO_AF_MODE9 (0x09U) ///< Mode = 9
#define GPIO_AF_MODE10 (0x0AU) ///< Mode = 10
#define GPIO_AF_MODE11 (0x0BU) ///< Mode = 11
#define GPIO_AF_MODE12 (0x0CU) ///< Mode = 12
#define GPIO_AF_MODE13 (0x0DU) ///< Mode = 13
#define GPIO_AF_MODE14 (0x0EU) ///< Mode = 14
#define GPIO_AF_MODE15 (0x0FU) ///< Mode = 15
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h
+635
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@@ -0,0 +1,635 @@
////////////////////////////////////////////////////////////////////////////////
/// @file reg_i2c.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_I2C_H
#define __REG_I2C_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) ///< Base Address: 0x40005400
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) ///< Base Address: 0x40005800
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
#undef USENCOMBINEREGISTER
#undef USENNEWREGISTER
#undef USENOLDREGISTER
#define USENCOMBINEREGISTER
#ifdef USENCOMBINEREGISTER
typedef struct {
union {
__IO u32 CR; ///< Control Register offset: 0x00
__IO u32 IC_CON;
};
union {
__IO u32 TAR; ///< Target Address Register offset: 0x04
__IO u32 IC_TAR;
};
union {
__IO u32 SAR; ///< Slave Address Register offset: 0x08
__IO u32 IC_SAR;
};
__IO u32 IC_HS_MADDR_RESERVED; ///< Reserved Register offset: 0x0C
union {
__IO u32 DR; ///< Data Command Register offset: 0x10
__IO u32 IC_DATA_CMD;
};
union {
__IO u32 SSHR; ///< SCL High Period Count for Std. Speed Register offset: 0x14
__IO u32 IC_SS_SCL_HCNT;
};
union {
__IO u32 SSLR; ///< SCL Low Period Count for Std. Speed Register offset: 0x18
__IO u32 IC_SS_SCL_LCNT;
};
union {
__IO u32 FSHR; ///< SCL High Period Count for Fast Speed Register offset: 0x1C
__IO u32 IC_FS_SCL_HCNT;
};
union {
__IO u32 FSLR; ///< SCL Low Period Count for Fast Speed Register offset: 0x20
__IO u32 IC_FS_SCL_LCNT;
};
__IO u32 IC_HS_SCL_HCNT_RESERVED; ///< Reserved Register offset: 0x24
__IO u32 IC_HS_SCL_LCNT_RESERVED; ///< Reserved Register offset: 0x28
union {
__IO u32 ISR; ///< Interrupt Status Register offset: 0x2C
__IO u32 IC_INTR_STAT;
};
union {
__IO u32 IMR; ///< Interrupt Mask Register offset: 0x30
__IO u32 IC_INTR_MASK;
};
union {
__IO u32 RAWISR; ///< RAW Interrupt Status Register offset: 0x34
__IO u32 IC_RAW_INTR_STAT;
};
union {
__IO u32 RXTLR; ///< Receive FIFO Threshold Level Register offset: 0x38
__IO u32 IC_RX_TL;
};
union {
__IO u32 TXTLR; ///< Transmit FIFO Threshold Level Register offset: 0x3C
__IO u32 IC_TX_TL;
};
union {
__IO u32 ICR; ///< Clear All Interrupt Register offset: 0x40
__IO u32 IC_CLR_INTR;
};
union {
__IO u32 RX_UNDER; ///< Clear RX_UNDER Interrupt Register offset: 0x44
__IO u32 IC_CLR_RX_UNDER;
};
union {
__IO u32 RX_OVER; ///< Clear RX_OVER Interrupt Register offset: 0x48
__IO u32 IC_CLR_RX_OVER;
};
union {
__IO u32 TX_OVER; ///< Clear TX_OVER Interrupt Register offset: 0x4C
__IO u32 IC_CLR_TX_OVER;
};
union {
__IO u32 RD_REQ; ///< Clear RD_REQ Interrupt Register offset: 0x50
__IO u32 IC_CLR_RD_REQ;
};
union {
__IO u32 TX_ABRT; ///< Clear TX_ABRT Interrupt Register offset: 0x54
__IO u32 IC_CLR_TX_ABRT;
};
union {
__IO u32 RX_DONE; ///< Clear RX_DONE Interrupt Register offset: 0x58
__IO u32 IC_CLR_RX_DONE;
};
union {
__IO u32 ACTIV; ///< Clear ACTIVITY Interrupt Register offset: 0x5C
__IO u32 IC_CLR_ACTIVITY;
};
union {
__IO u32 STOP; ///< Clear STOP_DET Interrupt Register offset: 0x60
__IO u32 IC_CLR_STOP_DET;
};
union {
__IO u32 START; ///< Clear START_DET Interrupt Register offset: 0x64
__IO u32 IC_CLR_START_DET;
};
union {
__IO u32 GC; ///< Clear GEN_CALL Interrupt Register offset: 0x68
__IO u32 IC_CLR_GEN_CALL;
};
union {
__IO u32 ENR; ///< Enable Register offset: 0x6C
__IO u32 IC_ENABLE;
};
union {
__IO u32 SR; ///< Status Register offset: 0x70
__IO u32 IC_STATUS;
};
union {
__IO u32 TXFLR; ///< Transmit FIFO Level Register offset: 0x74
__IO u32 IC_TXFLR;
};
union {
__IO u32 RXFLR; ///< Receive FIFO Level Register offset: 0x78
__IO u32 IC_RXFLR;
};
union {
__IO u32 HOLD; ///< SDA Hold Time Register offset: 0x7C
__IO u32 IC_SDA_HOLD;
};
__IO u32 RESERVED28; ///IC_TX_ABRT_SOURCE_RESERVED;
__IO u32 RESERVED29; ///IC_SLV_DATA_NACK_ONLY_RESERVED;
union {
__IO u32 DMA; ///< DMA Control Register offset: 0x88
__IO u32 IC_DMA_CR;
};
__IO u32 RESERVED30; ///IC_DMA_TDLR_RESERVED;
__IO u32 RESERVED31; ///IC_DMA_RDLR_RESERVED;
union {
__IO u32 SETUP; ///< SDA Setup Time Register offset: 0x94
__IO u32 IC_SDA_SETUP;
};
union {
__IO u32 GCR; ///< ACK General Call Register offset: 0x98
__IO u32 IC_ACK_GENERAL_CALL;
};
__IO u32 RESERVED32a; ///_RESERVED; offset: 0x9C
__IO u32 RESERVED33; ///_RESERVED; offset: 0xA0
__IO u32 RESERVED34; ///_RESERVED; offset: 0xA4
__IO u32 RESERVED35; ///_RESERVED; offset: 0xA8
__IO u32 RESERVED36; ///_RESERVED; offset: 0xAC    
__IO u32 SLVMASK; ///<I2C Slave Mode Mask Register offset: 0xB0
__IO u32 SLVRCVADDR; ///<I2C Slave Mode Address Register offset: 0xB4
} I2C_TypeDef;
#endif
#ifdef USENNEWREGISTER
typedef struct {
__IO u32 CR; ///< Control Register offset: 0x00
__IO u32 TAR; ///< Target Address Register offset: 0x04
__IO u32 SAR; ///< Slave Address Register offset: 0x08
__IO u32 RESERVED3;
__IO u32 DR; ///< Data Command Register offset: 0x10
__IO u32 SSHR; ///< SCL High Period Count for Std. Speed Register offset: 0x14
__IO u32 SSLR; ///< SCL Low Period Count for Std. Speed Register offset: 0x18
__IO u32 FSHR; ///< SCL High Period Count for Fast Speed Register offset: 0x1C
__IO u32 FSLR; ///< SCL Low Period Count for Fast Speed Register offset: 0x20
__IO u32 RESERVED9;
__IO u32 RESERVED10;
__IO u32 ISR; ///< Interrupt Status Register offset: 0x2C
__IO u32 IMR; ///< Interrupt Mask Register offset: 0x30
__IO u32 RAWISR; ///< RAW Interrupt Status Register offset: 0x34
__IO u32 RXTLR; ///< Receive FIFO Threshold Level Register offset: 0x38
__IO u32 TXTLR; ///< Transmit FIFO Threshold Level Register offset: 0x3C
__IO u32 ICR; ///< Clear All Interrupt Register offset: 0x40
__IO u32 RX_UNDER; ///< Clear RX_UNDER Interrupt Register offset: 0x44
__IO u32 RX_OVER; ///< Clear RX_OVER Interrupt Register offset: 0x48
__IO u32 TX_OVER; ///< Clear TX_OVER Interrupt Register offset: 0x4C
__IO u32 RD_REQ; ///< Clear RD_REQ Interrupt Register offset: 0x50
__IO u32 TX_ABRT; ///< Clear TX_ABRT Interrupt Register offset: 0x54
__IO u32 RX_DONE; ///< Clear RX_DONE Interrupt Register offset: 0x58
__IO u32 ACTIV; ///< Clear ACTIVITY Interrupt Register offset: 0x5C
__IO u32 STOP; ///< Clear STOP_DET Interrupt Register offset: 0x60
__IO u32 START; ///< Clear START_DET Interrupt Register offset: 0x64
__IO u32 GC; ///< Clear GEN_CALL Interrupt Register offset: 0x68
__IO u32 ENR; ///< Enable Register offset: 0x6C
__IO u32 SR; ///< Status Register offset: 0x70
__IO u32 TXFLR; ///< Transmit FIFO Level Register offset: 0x74
__IO u32 RXFLR; ///< Receive FIFO Level Register offset: 0x78
__IO u32 HOLD; ///< SDA Hold Time Register offset: 0x7C
__IO u32 RESERVED28;
__IO u32 RESERVED29;
__IO u32 RESERVED30;
__IO u32 RESERVED30a;
__IO u32 SETUP; ///< SDA Setup Time Register offset: 0x94
__IO u32 GCR; ///< ACK General Call Register offset: 0x98
} I2C_TypeDef;
#endif
#ifdef USENOLDREGISTER
typedef struct {
__IO u32 IC_CON;
__IO u32 IC_TAR;
__IO u32 IC_SAR;
__IO u32 IC_HS_MADDR_RESERVED;
__IO u32 IC_DATA_CMD;
__IO u32 IC_SS_SCL_HCNT;
__IO u32 IC_SS_SCL_LCNT;
__IO u32 IC_FS_SCL_HCNT;
__IO u32 IC_FS_SCL_LCNT;
__IO u32 IC_HS_SCL_HCNT_RESERVED;
__IO u32 IC_HS_SCL_LCNT_RESERVED;
__IO u32 IC_INTR_STAT;
__IO u32 IC_INTR_MASK;
__IO u32 IC_RAW_INTR_STAT;
__IO u32 IC_RX_TL;
__IO u32 IC_TX_TL;
__IO u32 IC_CLR_INTR;
__IO u32 IC_CLR_RX_UNDER;
__IO u32 IC_CLR_RX_OVER;
__IO u32 IC_CLR_TX_OVER;
__IO u32 IC_CLR_RD_REQ;
__IO u32 IC_CLR_TX_ABRT;
__IO u32 IC_CLR_RX_DONE;
__IO u32 IC_CLR_ACTIVITY;
__IO u32 IC_CLR_STOP_DET;
__IO u32 IC_CLR_START_DET;
__IO u32 IC_CLR_GEN_CALL;
__IO u32 IC_ENABLE;
__IO u32 IC_STATUS;
__IO u32 IC_TXFLR;
__IO u32 IC_RXFLR;
__IO u32 IC_SDA_HOLD;
__IO u32 IC_TX_ABRT_SOURCE_RESERVED;
__IO u32 IC_SLV_DATA_NACK_ONLY_RESERVED;
__IO u32 IC_DMA_CR;
__IO u32 IC_DMA_TDLR_RESERVED;
__IO u32 IC_DMA_RDLR_RESERVED;
__IO u32 IC_SDA_SETUP;
__IO u32 IC_ACK_GENERAL_CALL;
} I2C_TypeDef;
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C1 ((I2C_TypeDef*)I2C1_BASE)
#define I2C2 ((I2C_TypeDef*)I2C2_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_CR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_CR_MASTER_Pos (0)
#define I2C_CR_MASTER (0x01U << I2C_CR_MASTER_Pos) ///< I2C master mode enable
#define I2C_CR_SPEED_Pos (1)
#define I2C_CR_SPEED (0x03U << I2C_CR_SPEED_Pos) ///< I2C speed mode
#define I2C_CR_STD (0x01U << I2C_CR_SPEED_Pos) ///< I2C standard speed mode
#define I2C_CR_FAST (0x02U << I2C_CR_SPEED_Pos) ///< I2C fast speed mode
#define I2C_CR_SLAVE10_Pos (3)
#define I2C_CR_SLAVE10 (0x01U << I2C_CR_SLAVE10_Pos) ///< I2C slave mode responds to 10-bit address
#define I2C_CR_MASTER10_Pos (4)
#define I2C_CR_MASTER10 (0x01U << I2C_CR_MASTER10_Pos) ///< I2C master mode responds to 10-bit address
#define I2C_CR_REPEN_Pos (5)
#define I2C_CR_REPEN (0x01U << I2C_CR_REPEN_Pos) ///< Enable send RESTART
#define I2C_CR_SLAVEDIS_Pos (6)
#define I2C_CR_SLAVEDIS (0x01U << I2C_CR_SLAVEDIS_Pos) ///< I2C slave mode disable
#define I2C_CR_STOPINT_Pos (7)
#define I2C_CR_STOPINT (0x01U << I2C_CR_STOPINT_Pos) ///< Generate STOP interrupt in slave mode
#define I2C_CR_EMPINT_Pos (8)
#define I2C_CR_EMPINT (0x01U << I2C_CR_EMPINT_Pos) ///< I2C TX_EMPTY interrupt
#define I2C_CR_STOP_Pos (9)
#define I2C_CR_STOP (0x01U << I2C_CR_STOP_Pos) ///< STOP signal enable
#define I2C_CR_RESTART_Pos (10)
#define I2C_CR_RESTART (0x01U << I2C_CR_RESTART_Pos) ///< RESTART signal enable
#define I2C_CR_SLV_TX_ABRT_DIS_Pos (11)
#define I2C_CR_SLV_TX_ABRT_DIS (0x01U << I2C_CR_SLV_TX_ABRT_DIS_Pos) ///< I2C as a slave
#define I2C_CR_PADSEL_Pos (12)
#define I2C_CR_PADSEL (0x01U << I2C_CR_PADSEL_Pos) ///< PAD mode select
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_TAR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_TAR_ADDR_Pos (0)
#define I2C_TAR_ADDR (0x03FFU << I2C_TAR_ADDR_Pos) ///< Target address for master mode
#define I2C_TAR_GC_Pos (10)
#define I2C_TAR_GC (0x01U << I2C_TAR_GC_Pos) ///< General Call or START byte
#define I2C_TAR_SPECIAL_Pos (11)
#define I2C_TAR_SPECIAL (0x01U << I2C_TAR_SPECIAL_Pos) ///< Special command enable like General Call or START byte
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_SAR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_SAR_ADDR_Pos (0)
#define I2C_SAR_ADDR (0x03FFU << I2C_SAR_ADDR_Pos) ///< Slave address
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_DR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_DR_DAT_Pos (0)
#define I2C_DR_DAT (0xFFU << I2C_DR_DAT_Pos) ///< The data to be transmitted or received
#define I2C_DR_CMD_Pos (8)
#define I2C_DR_CMD (0x01U << I2C_DR_CMD_Pos) ///< Read or write command
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_SSHR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_SSHR_CNT_Pos (0)
#define I2C_SSHR_CNT (0xFFFFU << I2C_SSHR_CNT_Pos) ///< SCL clock high period count for standard speed
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_SSLR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_SSLR_CNT_Pos (0)
#define I2C_SSLR_CNT (0xFFFFU << I2C_SSLR_CNT_Pos) ///< SCL clock low period count for standard speed
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_FSHR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_FSHR_CNT_Pos (0)
#define I2C_FSHR_CNT (0xFFFFU << I2C_FSHR_CNT_Pos) ///< SCL clock high period count for fast speed
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_FSLR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_FSLR_CNT_Pos (0)
#define I2C_FSLR_CNT (0xFFFFU << I2C_FSLR_CNT_Pos) ///< SCL clock low period count for fast speed
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_ISR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_ISR_RX_UNDER_Pos (0)
#define I2C_ISR_RX_UNDER (0x01U << I2C_ISR_RX_UNDER_Pos) ///< RX_UNDER interrupt status
#define I2C_ISR_RX_OVER_Pos (1)
#define I2C_ISR_RX_OVER (0x01U << I2C_ISR_RX_OVER_Pos) ///< RX_OVER interrupt status
#define I2C_ISR_RX_FULL_Pos (2)
#define I2C_ISR_RX_FULL (0x01U << I2C_ISR_RX_FULL_Pos) ///< RX_FULL interrupt status
#define I2C_ISR_TX_OVER_Pos (3)
#define I2C_ISR_TX_OVER (0x01U << I2C_ISR_TX_OVER_Pos) ///< TX_OVER interrupt status
#define I2C_ISR_TX_EMPTY_Pos (4)
#define I2C_ISR_TX_EMPTY (0x01U << I2C_ISR_TX_EMPTY_Pos) ///< TX_EMPTY interrupt status
#define I2C_ISR_RX_REQ_Pos (5)
#define I2C_ISR_RX_REQ (0x01U << I2C_ISR_RX_REQ_Pos) ///< RX_REQ interrupt status
#define I2C_ISR_TX_ABRT_Pos (6)
#define I2C_ISR_TX_ABRT (0x01U << I2C_ISR_TX_ABRT_Pos) ///< TX_ABRT interrupt status
#define I2C_ISR_RX_DONE_Pos (7)
#define I2C_ISR_RX_DONE (0x01U << I2C_ISR_RX_DONE_Pos) ///< RX_DONE interrupt status
#define I2C_ISR_ACTIV_Pos (8)
#define I2C_ISR_ACTIV (0x01U << I2C_ISR_ACTIV_Pos) ///< ACTIVITY interrupt status
#define I2C_ISR_STOP_Pos (9)
#define I2C_ISR_STOP (0x01U << I2C_ISR_STOP_Pos) ///< STOP_DET interrupt status
#define I2C_ISR_START_Pos (10)
#define I2C_ISR_START (0x01U << I2C_ISR_START_Pos) ///< START_DET interrupt status
#define I2C_ISR_GC_Pos (11)
#define I2C_ISR_GC (0x01U << I2C_ISR_GC_Pos) ///< GEN_CALL interrupt status
#define I2C_ISR_RESTART_Pos (12)
#define I2C_ISR_RESTART (0x01U << I2C_ISR_RESTART_Pos) ///< RESTART_DET interrupt status
#define I2C_ISR_HOLD_Pos (13)
#define I2C_ISR_HOLD (0x01U << I2C_ISR_HOLD_Pos) ///< MST_ON_HOLD interrupt status
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_IMR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_IMR_RX_UNDER_Pos (0)
#define I2C_IMR_RX_UNDER (0x01U << I2C_IMR_RX_UNDER_Pos) ///< RX_UNDER interrupt mask
#define I2C_IMR_RX_OVER_Pos (1)
#define I2C_IMR_RX_OVER (0x01U << I2C_IMR_RX_OVER_Pos) ///< RX_OVER interrupt mask
#define I2C_IMR_RX_FULL_Pos (2)
#define I2C_IMR_RX_FULL (0x01U << I2C_IMR_RX_FULL_Pos) ///< RX_FULL interrupt mask
#define I2C_IMR_TX_OVER_Pos (3)
#define I2C_IMR_TX_OVER (0x01U << I2C_IMR_TX_OVER_Pos) ///< TX_OVER interrupt mask
#define I2C_IMR_TX_EMPTY_Pos (4)
#define I2C_IMR_TX_EMPTY (0x01U << I2C_IMR_TX_EMPTY_Pos) ///< TX_EMPTY interrupt mask
#define I2C_IMR_RX_REQ_Pos (5)
#define I2C_IMR_RX_REQ (0x01U << I2C_IMR_RX_REQ_Pos) ///< RX_REQ interrupt mask
#define I2C_IMR_TX_ABRT_Pos (6)
#define I2C_IMR_TX_ABRT (0x01U << I2C_IMR_TX_ABRT_Pos) ///< TX_ABRT interrupt mask
#define I2C_IMR_RX_DONE_Pos (7)
#define I2C_IMR_RX_DONE (0x01U << I2C_IMR_RX_DONE_Pos) ///< RX_DONE interrupt mask
#define I2C_IMR_ACTIV_Pos (8)
#define I2C_IMR_ACTIV (0x01U << I2C_IMR_ACTIV_Pos) ///< ACTIVITY interrupt status
#define I2C_IMR_STOP_Pos (9)
#define I2C_IMR_STOP (0x01U << I2C_IMR_STOP_Pos) ///< STOP_DET interrupt status
#define I2C_IMR_START_Pos (10)
#define I2C_IMR_START (0x01U << I2C_IMR_START_Pos) ///< START_DET interrupt status
#define I2C_IMR_GC_Pos (11)
#define I2C_IMR_GC (0x01U << I2C_IMR_GC_Pos) ///< GEN_CALL interrupt status
#define I2C_IMR_RESTART_Pos (12)
#define I2C_IMR_RESTART (0x01U << I2C_IMR_RESTART_Pos) ///< RESTART_DET interrupt status
#define I2C_IMR_HOLD_Pos (13)
#define I2C_IMR_HOLD (0x01U << I2C_IMR_HOLD_Pos) ///< MST_ON_HOLD interrupt status
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_RAWISR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_RAWISR_RX_UNDER_Pos (0)
#define I2C_RAWISR_RX_UNDER (0x01U << I2C_RAWISR_RX_UNDER_Pos) ///< RX_UNDER raw interrupt status
#define I2C_RAWISR_RX_OVER_Pos (1)
#define I2C_RAWISR_RX_OVER (0x01U << I2C_RAWISR_RX_OVER_Pos) ///< RX_OVER raw interrupt status
#define I2C_RAWISR_RX_FULL_Pos (2)
#define I2C_RAWISR_RX_FULL (0x01U << I2C_RAWISR_RX_FULL_Pos) ///< RX_FULL raw interrupt status
#define I2C_RAWISR_TX_OVER_Pos (3)
#define I2C_RAWISR_TX_OVER (0x01U << I2C_RAWISR_TX_OVER_Pos) ///< TX_OVER raw interrupt status
#define I2C_RAWISR_TX_EMPTY_Pos (4)
#define I2C_RAWISR_TX_EMPTY (0x01U << I2C_RAWISR_TX_EMPTY_Pos) ///< TX_EMPTY raw interrupt status
#define I2C_RAWISR_RX_REQ_Pos (5)
#define I2C_RAWISR_RX_REQ (0x01U << I2C_RAWISR_RX_REQ_Pos) ///< RX_REQ raw interrupt status
#define I2C_RAWISR_TX_ABRT_Pos (6)
#define I2C_RAWISR_TX_ABRT (0x01U << I2C_RAWISR_TX_ABRT_Pos) ///< TX_ABRT raw interrupt status
#define I2C_RAWISR_RX_DONE_Pos (7)
#define I2C_RAWISR_RX_DONE (0x01U << I2C_RAWISR_RX_DONE_Pos) ///< RX_DONE raw interrupt status
#define I2C_RAWISR_ACTIV_Pos (8)
#define I2C_RAWISR_ACTIV (0x01U << I2C_RAWISR_ACTIV_Pos) ///< ACTIVITY interrupt status
#define I2C_RAWISR_STOP_Pos (9)
#define I2C_RAWISR_STOP (0x01U << I2C_RAWISR_STOP_Pos) ///< STOP_DET interrupt status
#define I2C_RAWISR_START_Pos (10)
#define I2C_RAWISR_START (0x01U << I2C_RAWISR_START_Pos) ///< START_DET interrupt status
#define I2C_RAWISR_GC_Pos (11)
#define I2C_RAWISR_GC (0x01U << I2C_RAWISR_GC_Pos) ///< GEN_CALL interrupt status
#define I2C_RAWISR_RESTART_Pos (12)
#define I2C_RAWISR_RESTART (0x01U << I2C_RAWISR_RESTART_Pos) ///< RESTART_DET interrupt status
#define I2C_RAWISR_HOLD_Pos (13)
#define I2C_RAWISR_HOLD (0x01U << I2C_RAWISR_HOLD_Pos) ///< MST_ON_HOLD interrupt status
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_RXTLR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_RXTLR_Pos (0)
#define I2C_RXTLR_TL (0xFFU << I2C_RXTLR_Pos) ///< Receive FIFO threshold level
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_TXTLR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_TXTLR_Pos (0)
#define I2C_TXTLR_TL (0xFFU << I2C_TXTLR_Pos) ///< Transmit FIFO threshold level
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_ICR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_ICR_Pos (0)
#define I2C_ICR (0x01U << I2C_ICR_Pos) ///< Read this register to clear the combined interrupt, all individual interrupts
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_RX_UNDER Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_RX_UNDER_Pos (0)
#define I2C_RX_UNDER (0x01U << I2C_RX_UNDER_Pos) ///< Read this register to clear the RX_UNDER interrupt of the I2C_RAW_INTR_STAT register
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_RX_OVER Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_RX_OVER_Pos (0)
#define I2C_RX_OVER (0x01U << I2C_RX_OVER_Pos) ///< Read this register to clear the RX_OVER interrupt of the I2C_RAW_INTR_STAT register
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_TX_OVER Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_TX_OVER_Pos (0)
#define I2C_TX_OVER (0x01U << I2C_TX_OVER_Pos) ///< Read this register to clear the TX_OVER interrupt of the I2C_RAW_INTR_STAT register
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_RD_REQ Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_RD_REQ_Pos (0)
#define I2C_RD_REQ (0x01U << I2C_RD_REQ_Pos) ///< Read this register to clear the RD_REQ interrupt of the I2C_RAW_INTR_STAT register
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_TX_ABRT Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_TX_ABRT_Pos (0)
#define I2C_TX_ABRT (0x01U << I2C_TX_ABRT_Pos) ///< Read this register to clear the TX_ABRT interrupt of the I2C_RAW_INTR_STAT register
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_RX_DONE Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_RX_DONE_Pos (0)
#define I2C_RX_DONE (0x01U << I2C_RX_DONE_Pos) ///< Read this register to clear the RX_DONE interrupt of the I2C_RAW_INTR_STAT register
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_ACTIV Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_ACTIV_Pos (0)
#define I2C_ACTIV (0x01U << I2C_ACTIV_Pos) ///< Read this register to clear the ACTIVITY interrupt of the I2C_RAW_INTR_STAT register
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_STOP Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_STOP_Pos (0)
#define I2C_STOP (0x01U << I2C_STOP_Pos) ///< Read this register to clear the STOP_DET interrupt of the I2C_RAW_INTR_STAT register
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_START Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_START_Pos (0)
#define I2C_START (0x01U << I2C_START_Pos) ///< Read this register to clear the START_DET interrupt of the I2C_RAW_INTR_STAT register
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_GC Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_GC_Pos (0)
#define I2C_GC (0x01U << I2C_GC_Pos) ///< Read this register to clear the GEN_CALL interrupt of the I2C_RAW_INTR_STAT register
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_ENR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_ENR_ENABLE_Pos (0)
#define I2C_ENR_ENABLE (0x01U << I2C_ENR_ENABLE_Pos) ///< I2C mode enable
#define I2C_ENR_ABORT_Pos (1)
#define I2C_ENR_ABORT (0x01U << I2C_ENR_ABORT_Pos) ///< I2C transfer abort
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_SR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_SR_ACTIV_Pos (0)
#define I2C_SR_ACTIV (0x01U << I2C_SR_ACTIV_Pos) ///< I2C activity status
#define I2C_SR_TFNF_Pos (1)
#define I2C_SR_TFNF (0x01U << I2C_SR_TFNF_Pos) ///< Transmit FIFO not full
#define I2C_SR_TFE_Pos (2)
#define I2C_SR_TFE (0x01U << I2C_SR_TFE_Pos) ///< Transmit FIFO completely empty
#define I2C_SR_RFNE_Pos (3)
#define I2C_SR_RFNE (0x01U << I2C_SR_RFNE_Pos) ///< Receive FIFO not empty
#define I2C_SR_RFF_Pos (4)
#define I2C_SR_RFF (0x01U << I2C_SR_RFF_Pos) ///< Receive FIFO completely full
#define I2C_SR_MST_ACTIV_Pos (5)
#define I2C_SR_MST_ACTIV (0x01U << I2C_SR_MST_ACTIV_Pos) ///< Master FSM activity status
#define I2C_SR_SLV_ACTIV_Pos (6)
#define I2C_SR_SLV_ACTIV (0x01U << I2C_SR_SLV_ACTIV_Pos) ///< Slave FSM activity status
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_TXFLR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_TXFLR_CNT_Pos (0)
#define I2C_TXFLR_CNT (0x03U << I2C_TXFLR_CNT_Pos) ///< Number of valid data in the transmit FIFO
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_RXFLR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_RXFLR_CNT_Pos (0)
#define I2C_RXFLR_CNT (0x03U << I2C_RXFLR_CNT_Pos) ///< Number of valid data in the receive FIFO
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_HOLD Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_HOLD_TXCNT_Pos (0)
#define I2C_HOLD_TXCNT (0xFFFFU << I2C_HOLD_TXCNT_Pos) ///< SDA hold time when I2C acts as a transmit
#define I2C_HOLD_RXCNT_Pos (16)
#define I2C_HOLD_RXCNT (0xFFU << I2C_HOLD_RXCNT_Pos) ///< SDA hold time when I2C acts as a receiver
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_DMA Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_DMA_RXEN_Pos (0)
#define I2C_DMA_RXEN (0x01U << I2C_DMA_RXEN_Pos) ///< Receive DMA enable
#define I2C_DMA_TXEN_Pos (1)
#define I2C_DMA_TXEN (0x01U << I2C_DMA_TXEN_Pos) ///< Transmit DMA enable
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_SETUP Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_SETUP_CNT_Pos (0)
#define I2C_SETUP_CNT (0xFFU << I2C_SETUP_CNT_Pos) ///< SDA setup
////////////////////////////////////////////////////////////////////////////////
/// @brief I2C_GCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2C_GCR_GC_Pos (0)
#define I2C_GCR_GC (0x01U << I2C_GCR_GC_Pos) ///< ACK general call
#define I2C_SLVMASK_Pos (0)
#define I2C_SLVMASK (0x3FFU <<I2C_SLVMASK_Pos)
#define I2C_SLVRCVADDR_Pos (0)
#define I2C_SLVRCVADDR (0x3FFU <<I2C_SLVRCVADDR_Pos)
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_iwdg.h
+125
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@@ -0,0 +1,125 @@
////////////////////////////////////////////////////////////////////////////////
/// @file reg_iwdg.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_IWDG_H
#define __REG_IWDG_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief IWDG Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) ///< Base Address: 0x40003000
////////////////////////////////////////////////////////////////////////////////
/// @brief IWDG Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 KR; ///< Key Register offset: 0x00
__IO u32 PR; ///< Prescaler Register offset: 0x04
__IO u32 RLR; ///< Reload Register offset: 0x08
__IO u32 SR; ///< Status Register offset: 0x0C
__IO u32 CR; ///< Control Register offset: 0x10
__IO u32 IGEN; ///< Interrupt Generator Register offset: 0x14
__IO u32 CNT; ///< Interrupt Generator count Register offset: 0x18
__IO u32 PS; ///< Prescaler count Register offset: 0x1C
} IWDG_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief IWDG type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define IWDG ((IWDG_TypeDef*) IWDG_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief IWDG_KR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define IWDG_KEYR_KEY_Pos (0)
#define IWDG_KEYR_KEY (0xFFFFU << IWDG_KEYR_KEY_Pos) ///< Key Value
////////////////////////////////////////////////////////////////////////////////
/// @brief IWDG_PR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define IWDG_PR_PRE_Pos (0)
#define IWDG_PR_PRE (0x07U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 4
#define IWDG_PR_PRE_DIV4 (0x00U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 4
#define IWDG_PR_PRE_DIV8 (0x01U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 8
#define IWDG_PR_PRE_DIV16 (0x02U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 16
#define IWDG_PR_PRE_DIV32 (0x03U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 32
#define IWDG_PR_PRE_DIV64 (0x04U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 64
#define IWDG_PR_PRE_DIV128 (0x05U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 128
#define IWDG_PR_PRE_DIV256 (0x06U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 256
////////////////////////////////////////////////////////////////////////////////
/// @brief IWDG_RLR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define IWDG_RLR_RL_Pos (0)
#define IWDG_RLR_RL (0x0FFFU << IWDG_RLR_RL_Pos) ///< Watchdog counter reload value
////////////////////////////////////////////////////////////////////////////////
/// @brief IWDG_SR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define IWDG_SR_PVU_Pos (0)
#define IWDG_SR_PVU (0x01U << IWDG_SR_PVU_Pos) ///< Watchdog prescaler value update
#define IWDG_SR_RVU_Pos (1)
#define IWDG_SR_RVU (0x01U << IWDG_SR_RVU_Pos) ///< Watchdog counter reload value update
#define IWDG_SR_IVU_Pos (2)
#define IWDG_SR_IVU (0x01U << IWDG_SR_IVU_Pos)
#define IWDG_SR_UPDATE_Pos (3)
#define IWDG_SR_UPDATE (0x01U << IWDG_SR_UPDATE_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief IWDG_CR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define IWDG_CR_IRQSEL_Pos (0)
#define IWDG_CR_IRQSEL (0x01U << IWDG_CR_IRQSEL_Pos) ///< IWDG overflow operation selection
#define IWDG_CR_IRQCLR_Pos (1)
#define IWDG_CR_IRQCLR (0x01U << IWDG_CR_IRQCLR_Pos) ///< IWDG interrupt clear
////////////////////////////////////////////////////////////////////////////////
/// @brief IWDG_IGRN Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define IWDG_IGEN_IGEN_Pos (0)
#define IWDG_IGEN_IGEN (0xFFFU << IWDG_CR_IRQSEL_Pos) ///< IWDG Interrupt Generate value
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h
+72
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_pwm.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_PWM_H
#define __REG_PWM_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief PWM Base Address Definition
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// @brief PWM Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_pwr.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_PWR_H
#define __REG_PWR_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief PWR Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define PWR_BASE (APB1PERIPH_BASE + 0x7000) ///< Base Address: 0x40007000
////////////////////////////////////////////////////////////////////////////////
/// @brief PWR Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
union {
__IO u32 CR; ///< Control register, offset: 0x00
__IO u32 CR1;
};
union {
__IO u32 CSR; ///< Control Status register offset: 0x04
__IO u32 CSR1;
};
__IO u32 CR2; ///< Control register 2 offset: 0x08
__IO u32 CR3; ///< Control register 3 offset: 0x0C
__IO u32 CR4; ///< Control register 4 offset: 0x10
__IO u32 CR5; ///< Control register 5 offset: 0x14
__IO u32 CR6; ///< Control register 6 offset: 0x18
__IO u32 SR; ///< Status register offset: 0x1C
__IO u32 SCR; ///< clear status register offset: 0x20
__IO u32 CFGR; ///< Configuration register offset: 0x24
} PWR_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief PWR type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define PWR ((PWR_TypeDef*) PWR_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief PWR_CR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define PWR_CR_LDPS_Pos (0)
#define PWR_CR_LDPS (0x01U << PWR_CR_LDPS_Pos) ///< Domain Write Protction
#define PWR_CR_PDDS_Pos (1)
#define PWR_CR_PDDS (0x01U << PWR_CR_PDDS_Pos) ///< Power Down Deepsleep
#define PWR_CR_CSBF_Pos (3)
#define PWR_CR_CSBF (0x01U << PWR_CR_CSBF_Pos) ///< Clear Standby Flag
#define PWR_CR_LPR_Pos (13)
#define PWR_CR_LPR (0x01U << PWR_CR_LPR_Pos) ///< Low power run
#define PWR_CR_VOS_Pos (14)
#define PWR_CR_VOS0 (0x00U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.80V
#define PWR_CR_VOS1 (0x01U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.70V
#define PWR_CR_VOS2 (0x02U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.60V
#define PWR_CR_VOS3 (0x03U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.55V
////////////////////////////////////////////////////////////////////////////////
/// @brief PWR_CSR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define PWR_CSR_SBF_Pos (1)
#define PWR_CSR_SBF (0x01U << PWR_CSR_SBF_Pos) ///< Standby Flag
#define PWR_CSR_VOSRDY_Pos (14)
#define PWR_CSR_VOSRDY (0x01U << PWR_CR_VOSRDY_Pos) ///< Voltage Modulator Output Selection Ready
////////////////////////////////////////////////////////////////////////////////
/// @brief PWR_CR2 register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define PWR_CR2_EWUP1_Pos (0)
#define PWR_CR2_EWUP1 (0x01U << PWR_CR2_EWUP1_Pos) ///< Enable WKUP1 wake-up pin
#define PWR_CR2_EWUP2_Pos (1)
#define PWR_CR2_EWUP2 (0x01U << PWR_CR2_EWUP2_Pos) ///< Enable WKUP2 wake-up pin
#define PWR_CR2_EWUP3_Pos (2)
#define PWR_CR2_EWUP3 (0x01U << PWR_CR2_EWUP3_Pos) ///< Enable WKUP3 wake-up pin
#define PWR_CR2_EWUP4_Pos (3)
#define PWR_CR2_EWUP4 (0x01U << PWR_CR2_EWUP4_Pos) ///< Enable WKUP4 wake-up pin
#define PWR_CR2_EWUP5_Pos (4)
#define PWR_CR2_EWUP5 (0x01U << PWR_CR2_EWUP5_Pos) ///< Enable WKUP5 wake-up pin
#define PWR_CR2_EWUP6_Pos (5)
#define PWR_CR2_EWUP6 (0x01U << PWR_CR2_EWUP6_Pos) ///< Enable WKUP6 wake-up pin
#define PWR_CR2_ENWU_Pos (15)
#define PWR_CR2_ENWU (0x01U << PWR_CR2_ENWU_Pos) ///< Enable wakeup module
////////////////////////////////////////////////////////////////////////////////
/// @brief PWR_CR3 register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define PWR_CR3_WP1_Pos (0)
#define PWR_CR3_WP1 (0x01U << PWR_CR3_WP1_Pos) ///< WKUP1 used for event polarity detection
#define PWR_CR3_WP2_Pos (1)
#define PWR_CR3_WP2 (0x01U << PWR_CR3_WP2_Pos) ///< WKUP2 used for event polarity detection
#define PWR_CR3_WP3_Pos (2)
#define PWR_CR3_WP3 (0x01U << PWR_CR3_WP3_Pos) ///< WKUP3 used for event polarity detection
#define PWR_CR3_WP4_Pos (3)
#define PWR_CR3_WP4 (0x01U << PWR_CR3_WP4_Pos) ///< WKUP4 used for event polarity detection
#define PWR_CR3_WP5_Pos (4)
#define PWR_CR3_WP5 (0x01U << PWR_CR3_WP5_Pos) ///< WKUP5 used for event polarity detection
#define PWR_CR3_WP6_Pos (5)
#define PWR_CR3_WP6 (0x01U << PWR_CR3_WP6_Pos) ///< WKUP6 used for event polarity detection
////////////////////////////////////////////////////////////////////////////////
/// @brief PWR_CR4 register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define PWR_CR4_FILTSEL0_Pos (0)
#define PWR_CR4_FILTSEL0 (0x01U << PWR_CR4_FILTSEL0_Pos) ///< selection wake-up source
#define PWR_CR4_FILTE0_Pos (2)
#define PWR_CR4_FILTE0 (0x01U << PWR_CR4_FILTE0_Pos) ///< enable Filter 0
#define PWR_CR4_FILTF0_Pos (4)
#define PWR_CR4_FILTF0 (0x01U << PWR_CR4_FILTF0_Pos) ///< Whether the wake source passes through filter 0
#define PWR_CR4_FILTCNT0_Pos (8)
#define PWR_CR4_FILTCNT0 (0xFFU << PWR_CR4_FILTCNT0_Pos) ///< Filter 0 counter
////////////////////////////////////////////////////////////////////////////////
/// @brief PWR_CR5 register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define PWR_CR5_FILTSEL1_Pos (0)
#define PWR_CR5_FILTSEL1 (0x01U << PWR_CR5_FILTSEL1_Pos) ///< selection wake-up source
#define PWR_CR5_FILTE1_Pos (2)
#define PWR_CR5_FILTE1 (0x01U << PWR_CR5_FILTE1_Pos) ///< enable Filter 1
#define PWR_CR5_FILTF1_Pos (4)
#define PWR_CR5_FILTF1 (0x01U << PWR_CR5_FILTF1_Pos) ///< Whether the wake source passes through filter 1
#define PWR_CR5_FILTCNT1_Pos (8)
#define PWR_CR5_FILTCNT1 (0xFFU << PWR_CR5_FILTCNT1_Pos) ///< Filter 1 counter
////////////////////////////////////////////////////////////////////////////////
/// @brief PWR_CR6 register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define PWR_CR6_STDBY_FS_W_Pos (0)
#define PWR_CR6_STDBY_FS_W1 (0x00U << PWR_CR6_STDBY_FS_W_Pos) ///< 1 LSI cycle wake
#define PWR_CR6_STDBY_FS_W2 (0x01U << PWR_CR6_STDBY_FS_W_Pos) ///< 2 LSI cycle wake
#define PWR_CR6_STDBY_FS_W3 (0x02U << PWR_CR6_STDBY_FS_W_Pos) ///< 3 LSI cycle wake
#define PWR_CR6_STDBY_FS_W4 (0x03U << PWR_CR6_STDBY_FS_W_Pos) ///< 4 LSI cycle wake
#define PWR_CR6_STDBY_FS_W5 (0x04U << PWR_CR6_STDBY_FS_W_Pos) ///< 5 LSI cycle wake
#define PWR_CR6_STDBY_FS_W6 (0x05U << PWR_CR6_STDBY_FS_W_Pos) ///< 6 LSI cycle wake
#define PWR_CR6_STDBY_FS_W7 (0x06U << PWR_CR6_STDBY_FS_W_Pos) ///< 7 LSI cycle wake
#define PWR_CR6_STDBY_FS_W8 (0x07U << PWR_CR6_STDBY_FS_W_Pos) ///< 8 LSI cycle wake
////////////////////////////////////////////////////////////////////////////////
/// @brief PWR_SR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define PWR_SR_WUF1_Pos (0)
#define PWR_SR_WUF1 (0x01U << PWR_SR_WUF1_Pos) ///< wake-up flag 1
#define PWR_SR_WUF2_Pos (1)
#define PWR_SR_WUF2 (0x01U << PWR_SR_WUF2_Pos) ///< wake-up flag 2
#define PWR_SR_WUF3_Pos (2)
#define PWR_SR_WUF3 (0x01U << PWR_SR_WUF3_Pos) ///< wake-up flag 3
#define PWR_SR_WUF4_Pos (3)
#define PWR_SR_WUF4 (0x01U << PWR_SR_WUF4_Pos) ///< wake-up flag 4
#define PWR_SR_WUF5_Pos (4)
#define PWR_SR_WUF5 (0x01U << PWR_SR_WUF5_Pos) ///< wake-up flag 5
#define PWR_SR_WUF6_Pos (5)
#define PWR_SR_WUF6 (0x01U << PWR_SR_WUF6_Pos) ///< wake-up flag 6
////////////////////////////////////////////////////////////////////////////////
/// @brief PWR_SCR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define PWR_SCR_CWUF1_Pos (0)
#define PWR_SCR_CWUF1 (0x01U << PWR_SCR_CWUF1_Pos) ///< clear wake-up flag 1
#define PWR_SCR_CWUF2_Pos (1)
#define PWR_SCR_CWUF2 (0x01U << PWR_SCR_CWUF2_Pos) ///< clear wake-up flag 2
#define PWR_SCR_CWUF3_Pos (2)
#define PWR_SCR_CWUF3 (0x01U << PWR_SCR_CWUF3_Pos) ///< clear wake-up flag 3
#define PWR_SCR_CWUF4_Pos (3)
#define PWR_SCR_CWUF4 (0x01U << PWR_SCR_CWUF4_Pos) ///< clear wake-up flag 4
#define PWR_SCR_CWUF5_Pos (4)
#define PWR_SCR_CWUF5 (0x01U << PWR_SCR_CWUF5_Pos) ///< clear wake-up flag 5
#define PWR_SCR_CWUF6_Pos (5)
#define PWR_SCR_CWUF6 (0x01U << PWR_SCR_CWUF6_Pos) ///< clear wake-up flag 6
////////////////////////////////////////////////////////////////////////////////
/// @brief PWR_CFGR register Bit definition
////////////////////////////////////////////////////////////////////////////////
#define PWR_CFGR_LSICALSEL_Pos (0)
#define PWR_CFGR_LSICALSEL (0x1FU << PWR_CFGR_LSICALSEL_Pos) ///< Enable internal clock calibration
#define PWR_CFGR_LSICAL_Pos (5)
#define PWR_CFGR_LSICAL (0x1FU << PWR_CFGR_LSICAL_Pos) ///< Internal high-speed clock calibration
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_rcc.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_RCC_H
#define __REG_RCC_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_BASE (AHBPERIPH_BASE + 0x1000) ///< Base Address: 0x40021000
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 CR; ///< Control Register offset: 0x00
__IO u32 CFGR; ///< Configuration Register offset: 0x04
__IO u32 CIR; ///< Clock Interrupt Register offset: 0x08
__IO u32 AHB3RSTR; ///< Advanced High Performance Bus 3 Reset Register offset: 0x0C
__IO u32 AHB2RSTR; ///< Advanced High Performance Bus 2 Reset Register offset: 0x10
__IO u32 AHBRSTR; ///< Advanced High Performance Bus 1 Reset Register offset: 0x14
__IO u32 APB2RSTR; ///< Advanced Peripheral Bus 2 Reset Register offset: 0x18
__IO u32 APB1RSTR; ///< Advanced Peripheral Bus 1 Reset Register offset: 0x1C
__IO u32 AHB3ENR; ///< Advanced High Performance Bus 3 Enable Register offset: 0x20
__IO u32 AHB2ENR; ///< Advanced High Performance Bus 2 Enable Register offset: 0x24
union {
__IO u32 AHBENR; ///< Advanced High Performance Bus 1 Enable Register offset: 0x28
__IO u32 AHB1ENR;
};
__IO u32 APB2ENR; ///< Advanced Peripheral Bus 2 Enable Register offset: 0x2C
__IO u32 APB1ENR; ///< Advanced Peripheral Bus 1 Enable Register offset: 0x30
__IO u32 BDCR; ///< Backup Domain Control Register offset: 0x34
__IO u32 CSR; ///< Control Status Register offset: 0x38
__IO u32 SYSCFGR; ///< System Configuration Register offset: 0x3C
__IO u32 CFGR2; ///< System Configuration Register offset: 0x40
__IO u32 ICSCR; ///< Internal clock source calibration register offset: 0x44
__IO u32 PLLCFGR; ///< PLL configures registers offset: 0x48
u32 Reserved1[13]; ///< Reserved space
__IO u32 HSIDLY; ///< HSI delay register offset: 0x80
__IO u32 HSEDLY; ///< HSE delay register offset: 0x84
__IO u32 PLLDLY; ///< PLL delay register offset: 0x88
} RCC_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC ((RCC_TypeDef*) RCC_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_CR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_CR_HSION_Pos (0)
#define RCC_CR_HSION (0x01U << RCC_CR_HSION_Pos) ///< Internal High Speed clock enable
#define RCC_CR_HSIRDY_Pos (1)
#define RCC_CR_HSIRDY (0x01U << RCC_CR_HSIRDY_Pos) ///< Internal High Speed clock ready flag
#define RCC_CR_HSIDIV_Pos (11)
#define RCC_CR_HSIDIV_0 (0x00U << RCC_CR_HSIDIV_Pos) ///< HSI regardless of frequency
#define RCC_CR_HSIDIV_2 (0x01U << RCC_CR_HSIDIV_Pos) ///< HSI 2 frequency division
#define RCC_CR_HSIDIV_4 (0x02U << RCC_CR_HSIDIV_Pos) ///< HSI 4 frequency division
#define RCC_CR_HSIDIV_8 (0x03U << RCC_CR_HSIDIV_Pos) ///< HSI eight points and frequency
#define RCC_CR_HSIDIV_16 (0x04U << RCC_CR_HSIDIV_Pos) ///< HSI 16 points and frequency
#define RCC_CR_HSIDIV_32 (0x05U << RCC_CR_HSIDIV_Pos) ///< HSI 32 points and frequency
#define RCC_CR_HSIDIV_64 (0x06U << RCC_CR_HSIDIV_Pos) ///< HSI 64 frequency division
#define RCC_CR_HSIDIV_128 (0x07U << RCC_CR_HSIDIV_Pos) ///< HSI 128 frequency division
#define RCC_CR_HSEON_Pos (16)
#define RCC_CR_HSEON (0x01U << RCC_CR_HSEON_Pos) ///< External High Speed clock enable
#define RCC_CR_HSERDY_Pos (17)
#define RCC_CR_HSERDY (0x01U << RCC_CR_HSERDY_Pos) ///< External High Speed clock ready flag
#define RCC_CR_HSEBYP_Pos (18)
#define RCC_CR_HSEBYP (0x01U << RCC_CR_HSEBYP_Pos) ///< External High Speed clock Bypass
#define RCC_CR_CSSON_Pos (19)
#define RCC_CR_CSSON (0x01U << RCC_CR_CSSON_Pos) ///< Clock Security System enable
#define RCC_CR_PLLON_Pos (24)
#define RCC_CR_PLLON (0x01U << RCC_CR_PLLON_Pos) ///< PLL enable
#define RCC_CR_PLLRDY_Pos (25)
#define RCC_CR_PLLRDY (0x01U << RCC_CR_PLLRDY_Pos) ///< PLL clock ready flag
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_CFGR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_CFGR_SW_Pos (0)
#define RCC_CFGR_SW (0x03U << RCC_CFGR_SW_Pos) ///< SW[1:0] bits (System clock Switch)
#define RCC_CFGR_SW_HSI_DIV6 (0x00U << RCC_CFGR_SW_Pos) ///< HSI/6 selected as system clock
#define RCC_CFGR_SW_HSE (0x01U << RCC_CFGR_SW_Pos) ///< HSE selected as system clock
#define RCC_CFGR_SW_PLL (0x02U << RCC_CFGR_SW_Pos) ///< PLL selected as system clock
#define RCC_CFGR_SW_LSI (0x03U << RCC_CFGR_SW_Pos) ///< LSI selected as system clock
#define RCC_CFGR_SWS_Pos (2)
#define RCC_CFGR_SWS (0x03U << RCC_CFGR_SWS_Pos) ///< SWS[1:0] bits (System Clock Switch Status)
#define RCC_CFGR_SWS_HSI_DIV6 (0x00U << RCC_CFGR_SWS_Pos) ///< HSI/6 oscillator used as system clock
#define RCC_CFGR_SWS_HSE (0x01U << RCC_CFGR_SWS_Pos) ///< HSE oscillator used as system clock
#define RCC_CFGR_SWS_PLL (0x02U << RCC_CFGR_SWS_Pos) ///< PLL used as system clock
#define RCC_CFGR_SWS_LSI (0x03U << RCC_CFGR_SWS_Pos) ///< LSI used as system clock
#define RCC_CFGR_HPRE_Pos (4)
#define RCC_CFGR_HPRE (0x0FU << RCC_CFGR_HPRE_Pos) ///< HPRE[3:0] bits (AHB prescaler)
#define RCC_CFGR_PPRE_0 (0x01U << RCC_CFGR_HPRE_Pos) ///< Bit 0
#define RCC_CFGR_PPRE_1 (0x02U << RCC_CFGR_HPRE_Pos) ///< Bit 1
#define RCC_CFGR_PPRE_2 (0x04U << RCC_CFGR_HPRE_Pos) ///< Bit 2
#define RCC_CFGR_PPRE_3 (0x08U << RCC_CFGR_HPRE_Pos) ///< Bit 3
#define RCC_CFGR_HPRE_DIV1 (0x00U << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK not divided
#define RCC_CFGR_HPRE_DIV2 (0x08U << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 2
#define RCC_CFGR_HPRE_DIV4 (0x09U << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 4
#define RCC_CFGR_HPRE_DIV8 (0x0AU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 8
#define RCC_CFGR_HPRE_DIV16 (0x0BU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 16
#define RCC_CFGR_HPRE_DIV64 (0x0CU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 64
#define RCC_CFGR_HPRE_DIV128 (0x0DU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 128
#define RCC_CFGR_HPRE_DIV256 (0x0EU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 256
#define RCC_CFGR_HPRE_DIV512 (0x0FU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 512
#define RCC_CFGR_PPRE1_Pos (8)
#define RCC_CFGR_PPRE1 (0x07U << RCC_CFGR_PPRE1_Pos) ///< PRE1[2:0] bits (APB1 prescaler)
#define RCC_CFGR_PPRE1_0 (0x01U << RCC_CFGR_PPRE1_Pos) ///< Bit 0
#define RCC_CFGR_PPRE1_1 (0x02U << RCC_CFGR_PPRE1_Pos) ///< Bit 1
#define RCC_CFGR_PPRE1_2 (0x04U << RCC_CFGR_PPRE1_Pos) ///< Bit 2
#define RCC_CFGR_PPRE1_DIV1 (0x00U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK not divided
#define RCC_CFGR_PPRE1_DIV2 (0x04U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 2
#define RCC_CFGR_PPRE1_DIV4 (0x05U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 4
#define RCC_CFGR_PPRE1_DIV8 (0x06U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 8
#define RCC_CFGR_PPRE1_DIV16 (0x07U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 16
#define RCC_CFGR_PPRE2_Pos (11)
#define RCC_CFGR_PPRE2 (0x07U << RCC_CFGR_PPRE2_Pos) ///< PRE2[2:0] bits (APB2 prescaler)
#define RCC_CFGR_PPRE2_0 (0x01U << RCC_CFGR_PPRE2_Pos) ///< Bit 0
#define RCC_CFGR_PPRE2_1 (0x02U << RCC_CFGR_PPRE2_Pos) ///< Bit 1
#define RCC_CFGR_PPRE2_2 (0x04U << RCC_CFGR_PPRE2_Pos) ///< Bit 2
#define RCC_CFGR_PPRE2_DIV1 (0x00U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK not divided
#define RCC_CFGR_PPRE2_DIV2 (0x04U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 2
#define RCC_CFGR_PPRE2_DIV4 (0x05U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 4
#define RCC_CFGR_PPRE2_DIV8 (0x06U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 8
#define RCC_CFGR_PPRE2_DIV16 (0x07U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 16
#define RCC_CFGR_USBPRE_Pos (22)
#define RCC_CFGR_USBPRE (0x03U << RCC_CFGR_USBPRE_Pos) ///< USB prescaler BIT[1:0]
#define RCC_CFGR_MCO_Pos (24)
#define RCC_CFGR_MCO (0x07U << RCC_CFGR_MCO_Pos) ///< MCO[2:0] bits (Microcontroller Clock Output)
#define RCC_CFGR_MCO_NOCLOCK (0x00U << RCC_CFGR_MCO_Pos) ///< No clock
#define RCC_CFGR_MCO_LSI (0x02U << RCC_CFGR_MCO_Pos) ///< LSI clock
#define RCC_CFGR_MCO_LSE (0x03U << RCC_CFGR_MCO_Pos) ///< LSE clock
#define RCC_CFGR_MCO_SYSCLK (0x04U << RCC_CFGR_MCO_Pos) ///< System clock selected
#define RCC_CFGR_MCO_HSI (0x05U << RCC_CFGR_MCO_Pos) ///< Internal 48 MHz RC oscillator clock selected
#define RCC_CFGR_MCO_HSE (0x06U << RCC_CFGR_MCO_Pos) ///< External 1-25 MHz oscillator clock selected
#define RCC_CFGR_MCO_PLL (0x07U << RCC_CFGR_MCO_Pos) ///< PLL clock divided by 2 selected
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_CIR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_CIR_LSIRDYF_Pos (0)
#define RCC_CIR_LSIRDYF (0x01U << RCC_CIR_LSIRDYF_Pos) ///< LSI Ready Interrupt flag
#define RCC_CIR_LSERDYF_Pos (1)
#define RCC_CIR_LSERDYF (0x01U << RCC_CIR_LSERDYF_Pos) ///< LSE Ready Interrupt flag
#define RCC_CIR_HSIRDYF_Pos (2)
#define RCC_CIR_HSIRDYF (0x01U << RCC_CIR_HSIRDYF_Pos) ///< HSI Ready Interrupt flag
#define RCC_CIR_HSERDYF_Pos (3)
#define RCC_CIR_HSERDYF (0x01U << RCC_CIR_HSERDYF_Pos) ///< HSE Ready Interrupt flag
#define RCC_CIR_PLLRDYF_Pos (4)
#define RCC_CIR_PLLRDYF (0x01U << RCC_CIR_PLLRDYF_Pos) ///< PLL Ready Interrupt flag
#define RCC_CIR_CSSF_Pos (7)
#define RCC_CIR_CSSF (0x01U << RCC_CIR_CSSF_Pos) ///< Clock Security System Interrupt flag
#define RCC_CIR_LSIRDYIE_Pos (8)
#define RCC_CIR_LSIRDYIE (0x01U << RCC_CIR_LSIRDYIE_Pos) ///< LSI Ready Interrupt Enable
#define RCC_CIR_LSERDYIE_Pos (9)
#define RCC_CIR_LSERDYIE (0x01U << RCC_CIR_LSERDYIE_Pos) ///< LSE Ready Interrupt Enable
#define RCC_CIR_HSIRDYIE_Pos (10)
#define RCC_CIR_HSIRDYIE (0x01U << RCC_CIR_HSIRDYIE_Pos) ///< HSI Ready Interrupt Enable
#define RCC_CIR_HSERDYIE_Pos (11)
#define RCC_CIR_HSERDYIE (0x01U << RCC_CIR_HSIRDYIE_Pos) ///< HSE Ready Interrupt Enable
#define RCC_CIR_PLLRDYIE_Pos (12)
#define RCC_CIR_PLLRDYIE (0x01U << RCC_CIR_PLLRDYIE_Pos) ///< PLL Ready Interrupt Enable
#define RCC_CIR_LSIRDYC_Pos (16)
#define RCC_CIR_LSIRDYC (0x01U << RCC_CIR_LSIRDYC_Pos) ///< LSI Ready Interrupt Clear
#define RCC_CIR_LSERDYC_Pos (17)
#define RCC_CIR_LSERDYC (0x01U << RCC_CIR_LSERDYC_Pos) ///< LSE Ready Interrupt Clear
#define RCC_CIR_HSIRDYC_Pos (18)
#define RCC_CIR_HSIRDYC (0x01U << RCC_CIR_HSIRDYC_Pos) ///< HSI Ready Interrupt Clear
#define RCC_CIR_HSERDYC_Pos (19)
#define RCC_CIR_HSERDYC (0x01U << RCC_CIR_HSERDYC_Pos) ///< HSE Ready Interrupt Clear
#define RCC_CIR_PLLRDYC_Pos (20)
#define RCC_CIR_PLLRDYC (0x01U << RCC_CIR_PLLRDYC_Pos) ///< PLL Ready Interrupt Clear
#define RCC_CIR_CSSC_Pos (23)
#define RCC_CIR_CSSC (0x01U << RCC_CIR_CSSC_Pos) ///< Clock Security System Interrupt Clear
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_APB2RSTR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_APB2RSTR_TIM1_Pos (0)
#define RCC_APB2RSTR_TIM1 (0x01U << RCC_APB2RSTR_TIM1_Pos) ///< TIM1 reset
#define RCC_APB2RSTR_TIM8_Pos (1)
#define RCC_APB2RSTR_TIM8 (0x01U << RCC_APB2RSTR_TIM8_Pos) ///< TIM8 reset
#define RCC_APB2RSTR_UART1_Pos (4)
#define RCC_APB2RSTR_UART1 (0x01U << RCC_APB2RSTR_UART1_Pos) ///< UART1 reset
#define RCC_APB2RSTR_UART6_Pos (5)
#define RCC_APB2RSTR_UART6 (0x01U << RCC_APB2RSTR_UART6_Pos) ///< UART6 reset
#define RCC_APB2RSTR_ADC1_Pos (8)
#define RCC_APB2RSTR_ADC1 (0x01U << RCC_APB2RSTR_ADC1_Pos) ///< ADC1 reset
#define RCC_APB2RSTR_ADC2_Pos (9)
#define RCC_APB2RSTR_ADC2 (0x01U << RCC_APB2RSTR_ADC2_Pos) ///< ADC2 reset
#define RCC_APB2RSTR_ADC3_Pos (10)
#define RCC_APB2RSTR_ADC3 (0x01U << RCC_APB2RSTR_ADC3_Pos) ///< ADC3 reset
#define RCC_APB2RSTR_SPI1_Pos (12)
#define RCC_APB2RSTR_SPI1 (0x01U << RCC_APB2RSTR_SPI1_Pos) ///< SPI1 reset
#define RCC_APB2RSTR_SYSCFG_Pos (14)
#define RCC_APB2RSTR_SYSCFG (0x01U << RCC_APB2RSTR_SYSCFG_Pos) ///< SYSCFG reset
#define RCC_APB2RSTR_COMP_Pos (15)
#define RCC_APB2RSTR_COMP (0x01U << RCC_APB2RSTR_COMP_Pos) ///< COMP reset
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_AHB3RSTR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_AHB3RSTR_FSMC_Pos (0)
#define RCC_AHB3RSTR_FSMC (0x01U << RCC_AHB3RSTR_FSMC_Pos) ///< FSMC reset
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_APB1RSTR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_APB1RSTR_TIM2_Pos (0)
#define RCC_APB1RSTR_TIM2 (0x01U << RCC_APB1RSTR_TIM2_Pos) ///< Timer 2 reset
#define RCC_APB1RSTR_TIM3_Pos (1)
#define RCC_APB1RSTR_TIM3 (0x01U << RCC_APB1RSTR_TIM3_Pos) ///< Timer 3 reset
#define RCC_APB1RSTR_TIM4_Pos (2)
#define RCC_APB1RSTR_TIM4 (0x01U << RCC_APB1RSTR_TIM4_Pos) ///< Timer 4 reset
#define RCC_APB1RSTR_TIM5_Pos (3)
#define RCC_APB1RSTR_TIM5 (0x01U << RCC_APB1RSTR_TIM5_Pos) ///< Timer 5 reset
#define RCC_APB1RSTR_TIM6_Pos (4)
#define RCC_APB1RSTR_TIM6 (0x01U << RCC_APB1RSTR_TIM6_Pos) ///< Timer 6 reset
#define RCC_APB1RSTR_TIM7_Pos (5)
#define RCC_APB1RSTR_TIM7 (0x01U << RCC_APB1RSTR_TIM7_Pos) ///< Timer 7 reset
#define RCC_APB1RSTR_WWDG_Pos (11)
#define RCC_APB1RSTR_WWDG (0x01U << RCC_APB1RSTR_WWDG_Pos) ///< Window Watchdog reset
#define RCC_APB1RSTR_SPI2_Pos (14)
#define RCC_APB1RSTR_SPI2 (0x01U << RCC_APB1RSTR_SPI2_Pos) ///< SPI 2 reset
#define RCC_APB1RSTR_SPI3_Pos (15)
#define RCC_APB1RSTR_SPI3 (0x01U << RCC_APB1RSTR_SPI3_Pos) ///< SPI 3 reset
#define RCC_APB1RSTR_UART2_Pos (17)
#define RCC_APB1RSTR_UART2 (0x01U << RCC_APB1RSTR_UART2_Pos) ///< UART 2 reset
#define RCC_APB1RSTR_UART3_Pos (18)
#define RCC_APB1RSTR_UART3 (0x01U << RCC_APB1RSTR_UART3_Pos) ///< UART 3 reset
#define RCC_APB1RSTR_UART4_Pos (19)
#define RCC_APB1RSTR_UART4 (0x01U << RCC_APB1RSTR_UART4_Pos) ///< UART 4 reset
#define RCC_APB1RSTR_UART5_Pos (20)
#define RCC_APB1RSTR_UART5 (0x01U << RCC_APB1RSTR_UART5_Pos) ///< UART 5 reset
#define RCC_APB1RSTR_I2C1_Pos (21)
#define RCC_APB1RSTR_I2C1 (0x01U << RCC_APB1RSTR_I2C1_Pos) ///< I2C 1 reset
#define RCC_APB1RSTR_I2C2_Pos (22)
#define RCC_APB1RSTR_I2C2 (0x01U << RCC_APB1RSTR_I2C2_Pos) ///< I2C 2 reset
#define RCC_APB1RSTR_CRS_Pos (24)
#define RCC_APB1RSTR_CRS (0x01U << RCC_APB1RSTR_CRS_Pos) ///< CRS reset
#define RCC_APB1RSTR_CAN_Pos (25)
#define RCC_APB1RSTR_CAN (0x01U << RCC_APB1RSTR_CAN_Pos) ///< CAN reset
#define RCC_APB1RSTR_BKP_Pos (27)
#define RCC_APB1RSTR_BKP (0x01U << RCC_APB1RSTR_BKP_Pos) ///< Backup interface reset
#define RCC_APB1RSTR_PWR_Pos (28)
#define RCC_APB1RSTR_PWR (0x01U << RCC_APB1RSTR_PWR_Pos) ///< Power interface reset
#define RCC_APB1RSTR_DAC_Pos (29)
#define RCC_APB1RSTR_DAC (0x01U << RCC_APB1RSTR_DAC_Pos) ///< DAC interface reset
#define RCC_APB1RSTR_UART7_Pos (30)
#define RCC_APB1RSTR_UART7 (0x01U << RCC_APB1RSTR_UART7_Pos) ///< UART7 reset
#define RCC_APB1RSTR_UART8_Pos (31)
#define RCC_APB1RSTR_UART8 (0x01U << RCC_APB1RSTR_UART8_Pos) ///< UART8 reset
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_AHB2RSTR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_AHB2RSTR_USBFS_Pos (7)
#define RCC_AHB2RSTR_USBFS (0x01U << RCC_AHB2RSTR_USBFS_Pos) ///< USBFS reset
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_AHB3ENR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_AHB3ENR_FSMC_Pos (0)
#define RCC_AHB3ENR_FSMC (0x01U << RCC_AHB3ENR_FSMC_Pos) ///< FSMC reset
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_AHB2ENR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_AHB2ENR_USBFS_Pos (7)
#define RCC_AHB2ENR_USBFS (0x01U << RCC_AHB2ENR_USBFS_Pos) ///< USBFS reset
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_AHBENR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_AHBENR_GPIOA_Pos (0)
#define RCC_AHBENR_GPIOA (0x01U << RCC_AHBENR_GPIOA_Pos) ///< GPIOA clock enable
#define RCC_AHBENR_GPIOB_Pos (1)
#define RCC_AHBENR_GPIOB (0x01U << RCC_AHBENR_GPIOB_Pos) ///< GPIOB clock enable
#define RCC_AHBENR_GPIOC_Pos (2)
#define RCC_AHBENR_GPIOC (0x01U << RCC_AHBENR_GPIOC_Pos) ///< GPIOC clock enable
#define RCC_AHBENR_GPIOD_Pos (3)
#define RCC_AHBENR_GPIOD (0x01U << RCC_AHBENR_GPIOD_Pos) ///< GPIOD clock enable
#define RCC_AHBENR_GPIOE_Pos (4)
#define RCC_AHBENR_GPIOE (0x01U << RCC_AHBENR_GPIOE_Pos) ///< GPIOE clock enable
#define RCC_AHBENR_GPIOF_Pos (5)
#define RCC_AHBENR_GPIOF (0x01U << RCC_AHBENR_GPIOF_Pos) ///< GPIOF clock enable
#define RCC_AHBENR_GPIOG_Pos (6)
#define RCC_AHBENR_GPIOG (0x01U << RCC_AHBENR_GPIOG_Pos) ///< GPIOG clock enable
#define RCC_AHBENR_GPIOH_Pos (7)
#define RCC_AHBENR_GPIOH (0x01U << RCC_AHBENR_GPIOH_Pos) ///< GPIOH clock enable
#define RCC_AHBENR_SDIO_Pos (10)
#define RCC_AHBENR_SDIO (0x01U << RCC_AHBENR_SDIO_Pos) ///< SDIO clock enable
#define RCC_AHBENR_CRC_Pos (12)
#define RCC_AHBENR_CRC (0x01U << RCC_AHBENR_CRC_Pos) ///< CRC clock enable
#define RCC_AHBENR_FLASH_Pos (13)
#define RCC_AHBENR_FLASH (0x01U << RCC_AHBENR_FLASH_Pos) ///< FLASH clock enable
#define RCC_AHBENR_SRAM_Pos (14)
#define RCC_AHBENR_SRAM (0x01U << RCC_AHBENR_SRAM_Pos) ///< SRAM clock enable
#define RCC_AHBENR_DMA1_Pos (21)
#define RCC_AHBENR_DMA1 (0x01U << RCC_AHBENR_DMA1_Pos) ///< DMA1 clock enable
#define RCC_AHBENR_DMA2_Pos (22)
#define RCC_AHBENR_DMA2 (0x01U << RCC_AHBENR_DMA2_Pos) ///< DMA2 clock enable
#define RCC_AHBENR_ETHMAC_Pos (25)
#define RCC_AHBENR_ETHMAC (0x01U << RCC_AHBENR_ETHMAC_Pos) ///< ETHMAC clock enable
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_APB2ENR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_APB2ENR_TIM1_Pos (0)
#define RCC_APB2ENR_TIM1 (0x01U << RCC_APB2ENR_TIM1_Pos) ///< TIM1 enable
#define RCC_APB2ENR_TIM8_Pos (1)
#define RCC_APB2ENR_TIM8 (0x01U << RCC_APB2ENR_TIM8_Pos) ///< TIM8 enable
#define RCC_APB2ENR_UART1_Pos (4)
#define RCC_APB2ENR_UART1 (0x01U << RCC_APB2ENR_UART1_Pos) ///< UART1 enable
#define RCC_APB2ENR_UART6_Pos (5)
#define RCC_APB2ENR_UART6 (0x01U << RCC_APB2ENR_UART6_Pos) ///< UART6 enable
#define RCC_APB2ENR_ADC1_Pos (8)
#define RCC_APB2ENR_ADC1 (0x01U << RCC_APB2ENR_ADC1_Pos) ///< ADC1 enable
#define RCC_APB2ENR_ADC2_Pos (9)
#define RCC_APB2ENR_ADC2 (0x01U << RCC_APB2ENR_ADC2_Pos) ///< ADC2 enable
#define RCC_APB2ENR_ADC3_Pos (10)
#define RCC_APB2ENR_ADC3 (0x01U << RCC_APB2ENR_ADC3_Pos) ///< ADC3 enable
#define RCC_APB2ENR_SPI1_Pos (12)
#define RCC_APB2ENR_SPI1 (0x01U << RCC_APB2ENR_SPI1_Pos) ///< SPI1 enable
#define RCC_APB2ENR_EXTI_Pos (14)
#define RCC_APB2ENR_EXTI (0x01U << RCC_APB2ENR_EXTI_Pos) ///< EXTI Block enable
#define RCC_APB2ENR_SYSCFG_Pos (14)
#define RCC_APB2ENR_SYSCFG (0x01U << RCC_APB2ENR_SYSCFG_Pos) ///< SYSCFG enable
#define RCC_APB2ENR_COMP_Pos (15)
#define RCC_APB2ENR_COMP (0x01U << RCC_APB2ENR_COMP_Pos) ///< COMP enable
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_APB1ENR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_APB1ENR_TIM2_Pos (0)
#define RCC_APB1ENR_TIM2 (0x01U << RCC_APB1ENR_TIM2_Pos) ///< Timer 2 clock enable
#define RCC_APB1ENR_TIM3_Pos (1)
#define RCC_APB1ENR_TIM3 (0x01U << RCC_APB1ENR_TIM3_Pos) ///< Timer 3 clock enabled
#define RCC_APB1ENR_TIM4_Pos (2)
#define RCC_APB1ENR_TIM4 (0x01U << RCC_APB1ENR_TIM4_Pos) ///< Timer 4 clock enable
#define RCC_APB1ENR_TIM5_Pos (3)
#define RCC_APB1ENR_TIM5 (0x01U << RCC_APB1ENR_TIM5_Pos) ///< TIM5 Timer clock enable
#define RCC_APB1ENR_TIM6_Pos (4)
#define RCC_APB1ENR_TIM6 (0x01U << RCC_APB1ENR_TIM6_Pos) ///< TIM6 Timer clock enable
#define RCC_APB1ENR_TIM7_Pos (5)
#define RCC_APB1ENR_TIM7 (0x01U << RCC_APB1ENR_TIM7_Pos) ///< TIM7 Timer clock enable
#define RCC_APB1ENR_WWDG_Pos (11)
#define RCC_APB1ENR_WWDG (0x01U << RCC_APB1ENR_WWDG_Pos) ///< Window Watchdog clock enable
#define RCC_APB1ENR_SPI2_Pos (14)
#define RCC_APB1ENR_SPI2 (0x01U << RCC_APB1ENR_SPI2_Pos) ///< SPI 2 clock enable
#define RCC_APB1ENR_SPI3_Pos (15)
#define RCC_APB1ENR_SPI3 (0x01U << RCC_APB1ENR_SPI3_Pos) ///< SPI 3 clock enable
#define RCC_APB1ENR_UART2_Pos (17)
#define RCC_APB1ENR_UART2 (0x01U << RCC_APB1ENR_UART2_Pos) ///< UART 2 clock enable
#define RCC_APB1ENR_UART3_Pos (18)
#define RCC_APB1ENR_UART3 (0x01U << RCC_APB1ENR_UART3_Pos) ///< UART 3 clock enable
#define RCC_APB1ENR_UART4_Pos (19)
#define RCC_APB1ENR_UART4 (0x01U << RCC_APB1ENR_UART4_Pos) ///< UART 4 clock enable
#define RCC_APB1ENR_UART5_Pos (20)
#define RCC_APB1ENR_UART5 (0x01U << RCC_APB1ENR_UART5_Pos) ///< UART 5 clock enable
#define RCC_APB1ENR_I2C1_Pos (21)
#define RCC_APB1ENR_I2C1 (0x01U << RCC_APB1ENR_I2C1_Pos) ///< I2C 1 clock enable
#define RCC_APB1ENR_I2C2_Pos (22)
#define RCC_APB1ENR_I2C2 (0x01U << RCC_APB1ENR_I2C2_Pos) ///< I2C 2 clock enable
#define RCC_APB1ENR_CRS_Pos (24)
#define RCC_APB1ENR_CRS (0x01U << RCC_APB1ENR_CRS_Pos) ///< CRS 4 clock enable
#define RCC_APB1ENR_CAN_Pos (25)
#define RCC_APB1ENR_CAN (0x01U << RCC_APB1ENR_CAN_Pos) ///< CAN 5 clock enable
#define RCC_APB1ENR_BKP_Pos (27)
#define RCC_APB1ENR_BKP (0x01U << RCC_APB1ENR_BKP_Pos) ///< Backup interface clock enable
#define RCC_APB1ENR_PWR_Pos (28)
#define RCC_APB1ENR_PWR (0x01U << RCC_APB1ENR_PWR_Pos) ///< Power interface clock enable
#define RCC_APB1ENR_DBGMCU_Pos (28)
#define RCC_APB1ENR_DBGMCU (0x01U << RCC_APB1ENR_DBGMCU_Pos) ///< DBGMCU clock enable
#define RCC_APB1ENR_DAC_Pos (29)
#define RCC_APB1ENR_DAC (0x01U << RCC_APB1ENR_DAC_Pos) ///< DAC interface clock enable
#define RCC_APB1ENR_UART7_Pos (30)
#define RCC_APB1ENR_UART7 (0x01U << RCC_APB1ENR_UART7_Pos) ///< UART7 interface clock enable
#define RCC_APB1ENR_UART8_Pos (31)
#define RCC_APB1ENR_UART8 (0x01U << RCC_APB1ENR_UART8_Pos) ///< UART8 interface clock enable
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_BDCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_BDCR_LSEON_Pos (0)
#define RCC_BDCR_LSEON (0x01U << RCC_BDCR_LSEON_Pos) ///< External Low Speed oscillator enable
#define RCC_BDCR_LSERDY_Pos (1)
#define RCC_BDCR_LSERDY (0x01U << RCC_BDCR_LSERDY_Pos) ///< External Low Speed oscillator Ready
#define RCC_BDCR_LSEBYP_Pos (2)
#define RCC_BDCR_LSEBYP (0x01U << RCC_BDCR_LSEBYP_Pos) ///< External Low Speed oscillator Bypass
#define RCC_BDCR_RTCSEL_Pos (8)
#define RCC_BDCR_RTCSEL (0x03U << RCC_BDCR_RTCSEL_Pos) ///< RTCSEL[1:0] bits (RTC clock source selection)
#define RCC_BDCR_RTCSEL_LSE (0x01U << RCC_BDCR_RTCSEL_Pos) ///< LSE oscillator clock used as RTC clock
#define RCC_BDCR_RTCSEL_LSI (0x02U << RCC_BDCR_RTCSEL_Pos) ///< LSI oscillator clock used as RTC clock
#define RCC_BDCR_RTCSEL_HSE (0x03U << RCC_BDCR_RTCSEL_Pos) ///< HSE oscillator clock divided by 128 used as RTC clock
#define RCC_BDCR_RTCEN_Pos (15)
#define RCC_BDCR_RTCEN (0x01U << RCC_BDCR_RTCEN_Pos) ///< RTC clock enable
#define RCC_BDCR_BDRST_Pos (16)
#define RCC_BDCR_BDRST (0x01U << RCC_BDCR_BDRST_Pos) ///< Backup domain software reset
#define RCC_BDCR_DBP_Pos (24)
#define RCC_BDCR_DBP (0x01U << RCC_BDCR_DBP_Pos) ///< DBP clock enable
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_CSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_CSR_LSION_Pos (0)
#define RCC_CSR_LSION (0x01U << RCC_CSR_LSION_Pos) ///< Internal Low Speed oscillator enable
#define RCC_CSR_LSIRDY_Pos (1)
#define RCC_CSR_LSIRDY (0x01U << RCC_CSR_LSIRDY_Pos) ///< Internal Low Speed oscillator Ready
#define RCC_CSR_LSIOENLV_Pos (5)
#define RCC_CSR_LSIOENLV (0x01U << RCC_CSR_LSIOENLV_Pos) ///< LSI output enable lower voltage
#define RCC_CSR_PVDRSTEN_Pos (6)
#define RCC_CSR_PVDRSTEN (0x01U << RCC_CSR_PVDRSTEN_Pos) ///< PVD reset enable
#define RCC_CSR_LOCKUPEN_Pos (7)
#define RCC_CSR_LOCKUPEN (0x01U << RCC_CSR_LOCKUPEN_Pos) ///< CPU lockup reset enable
#define RCC_CSR_VDTRSTNEN_Pos (8)
#define RCC_CSR_VDTRSTNEN (0x01U << RCC_CSR_VDTRSTNEN_Pos) ///< Voltage detect reset enable
#define RCC_CSR_VDTRSTF_Pos (21)
#define RCC_CSR_VDTRSTF (0x01U << RCC_CSR_VDTRSTF_Pos) ///< Voltage detect reset flag
#define RCC_CSR_PVDRSTF_Pos (22)
#define RCC_CSR_PVDRSTF (0x01U << RCC_CSR_PVDRSTF_Pos) ///< PVD reset flag
#define RCC_CSR_LOCKUPF_Pos (23)
#define RCC_CSR_LOCKUPF (0x01U << RCC_CSR_LOCKUPF_Pos) ///< CPU lockup reset flag
#define RCC_CSR_RMVF_Pos (24)
#define RCC_CSR_RMVF (0x01U << RCC_CSR_RMVF_Pos) ///< Remove reset flag
#define RCC_CSR_PINRSTF_Pos (26)
#define RCC_CSR_PINRSTF (0x01U << RCC_CSR_PINRSTF_Pos) ///< PIN reset flag
#define RCC_CSR_PORRSTF_Pos (27)
#define RCC_CSR_PORRSTF (0x01U << RCC_CSR_PORRSTF_Pos) ///< POR/PDR reset flag
#define RCC_CSR_SFTRSTF_Pos (28)
#define RCC_CSR_SFTRSTF (0x01U << RCC_CSR_SFTRSTF_Pos) ///< Software Reset flag
#define RCC_CSR_IWDGRSTF_Pos (29)
#define RCC_CSR_IWDGRSTF (0x01U << RCC_CSR_IWDGRSTF_Pos) ///< Independent Watchdog reset flag
#define RCC_CSR_WWDGRSTF_Pos (30)
#define RCC_CSR_WWDGRSTF (0x01U << RCC_CSR_WWDGRSTF_Pos) ///< Window watchdog reset flag
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_AHBRSTR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_AHBRSTR_GPIOA_Pos (0)
#define RCC_AHBRSTR_GPIOA (0x01U << RCC_AHBRSTR_GPIOA_Pos) ///< GPIOA clock reset
#define RCC_AHBRSTR_GPIOB_Pos (1)
#define RCC_AHBRSTR_GPIOB (0x01U << RCC_AHBRSTR_GPIOB_Pos) ///< GPIOB clock reset
#define RCC_AHBRSTR_GPIOC_Pos (2)
#define RCC_AHBRSTR_GPIOC (0x01U << RCC_AHBRSTR_GPIOC_Pos) ///< GPIOC clock reset
#define RCC_AHBRSTR_GPIOD_Pos (3)
#define RCC_AHBRSTR_GPIOD (0x01U << RCC_AHBRSTR_GPIOD_Pos) ///< GPIOD clock reset
#define RCC_AHBRSTR_GPIOE_Pos (4)
#define RCC_AHBRSTR_GPIOE (0x01U << RCC_AHBRSTR_GPIOE_Pos) ///< GPIOE clock reset
#define RCC_AHBRSTR_GPIOF_Pos (5)
#define RCC_AHBRSTR_GPIOF (0x01U << RCC_AHBRSTR_GPIOF_Pos) ///< GPIOF clock reset
#define RCC_AHBRSTR_GPIOG_Pos (6)
#define RCC_AHBRSTR_GPIOG (0x01U << RCC_AHBRSTR_GPIOG_Pos) ///< GPIOG clock reset
#define RCC_AHBRSTR_GPIOH_Pos (7)
#define RCC_AHBRSTR_GPIOH (0x01U << RCC_AHBRSTR_GPIOH_Pos) ///< GPIOH clock reset
#define RCC_AHBRSTR_SDIO_Pos (10)
#define RCC_AHBRSTR_SDIO (0x01U << RCC_AHBRSTR_SDIO_Pos) ///< SDIO clock reset
#define RCC_AHBRSTR_CRC_Pos (12)
#define RCC_AHBRSTR_CRC (0x01U << RCC_AHBRSTR_CRC_Pos) ///< CRC clock reset
#define RCC_AHBRSTR_DMA1_Pos (21)
#define RCC_AHBRSTR_DMA1 (0x01U << RCC_AHBRSTR_DMA1_Pos) ///< DMA1 clock reset
#define RCC_AHBRSTR_DMA2_Pos (22)
#define RCC_AHBRSTR_DMA2 (0x01U << RCC_AHBRSTR_DMA2_Pos) ///< DMA2 clock reset
#define RCC_AHBRSTR_ETHMAC_Pos (25)
#define RCC_AHBRSTR_ETHMAC (0x01U << RCC_AHBRSTR_ETHMAC_Pos) ///< ETHMAC clock reset
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_SYSCFG Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_SYSCFG_PROGCHECKEN_Pos (0)
#define RCC_SYSCFG_PROGCHECKEN (0x01U << RCC_SYSCFG_PROGCHECKEN_Pos) ///< Whether to check the number in Flash when writing to Flash
#define RCC_SYSCFG_SECTOR1KCFG_Pos (1)
#define RCC_SYSCFG_SECTOR1KCFG (0x01U << RCC_SYSCFG_SECTOR1KCFG_Pos) ///< The size of the Flash page when erased.
#define RCC_SYSCFG_DATAPREFETCH_Pos (2)
#define RCC_SYSCFG_DATAPREFETCH (0x01U << RCC_SYSCFG_DATAPREFETCH_Pos) ///< DATA prefetch module enable bit
#define RCC_SYSCFG_PAD_OSC_TRIM_Pos (8)
#define RCC_SYSCFG_PAD_OSC_TRIM (0x1FU << RCC_SYSCFG_PAD_OSC_TRIM_Pos) ///< Calibration value of external crystal vibration
#define RCC_SYSCFG_OSC_LPFEN_Pos (14)
#define RCC_SYSCFG_OSC_LPFEN (0x01U << RCC_SYSCFG_OSC_LPFEN_Pos) ///< External crystal oscillator low pass filtering enables
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_CFGR2 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_CFGR2_TIMADVCKSEL_Pos (1)
#define RCC_CFGR2_TIMADVCKSEL (0x01U << RCC_CFGR2_TIMADVCKSEL_Pos) ///< TIMADV_CKSEL
#define RCC_CFGR2_TIMADV_PRE_Pos (1) ///<
#define RCC_CFGR2_TIMADV_PRE (0x07U << RCC_CFGR2_TIMADV_PRE_Pos) ///< SYSCLK's advance points are controlled by the software Frequency coefficient
#define RCC_CFGR2_FSMC_PRE_Pos (8)
#define RCC_CFGR2_FSMC_PRE (0x1FU << RCC_CFGR2_FSMC_PRE_Pos) ///< FSMC Output clock frequency division factor
#define RCC_CFGR2_APB1_CLK_HV_PRE_Pos (16)
#define RCC_CFGR2_APB1_CLK_HV_PRE (0x0FU << RCC_CFGR2_APB1_CLK_HV_PRE_Pos) ///< APB1 Output clock frequency division factor
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_ICSCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_ICSCR_TIME_CRS_SEL_Pos (0)
#define RCC_ICSCR_TIME_CRS_SEL (0x01U << RCC_ICSCR_TIME_CRS_SEL_Pos) ///< Whether to use the CRS module as source
#define RCC_ICSCR_HSI_CAL_SEL_Pos (11) ///<
#define RCC_ICSCR_HSI_CAL_SEL (0x1FU << RCC_ICSCR_HSI_CAL_SEL_Pos) ///< Select the internal high speed clock calibration value
#define RCC_ICSCR_HSI_CAL_SFT_Pos (16)
#define RCC_ICSCR_HSI_CAL_SFT (0x3FU << RCC_ICSCR_HSI_CAL_SFT_Pos) ///< Internal high-speed clock calibration
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_PLLCFGR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_PLLCFGR_PLLSRC_Pos (0)
#define RCC_PLLCFGR_PLLSRC (0x01U << RCC_PLLCFGR_PLLSRC_Pos) ///< PLL entry clock source
#define RCC_PLLCFGR_PLLXTPRE_Pos (1) ///<
#define RCC_PLLCFGR_PLLXTPRE (0x01U << RCC_PLLCFGR_PLLXTPRE_Pos) ///< HSE divider for PLL entry
#define RCC_PLLCFGR_PLL_ICTRL_Pos (2)
#define RCC_PLLCFGR_PLL_ICTRL (0x03U << RCC_PLLCFGR_PLL_ICTRL_Pos) ///< PLL CP current control signals
#define RCC_PLLCFGR_PLL_LDS_Pos (4)
#define RCC_PLLCFGR_PLL_LDS (0x03U << RCC_PLLCFGR_PLL_LDS_Pos) ///< PLL lock detector accuracy select
#define RCC_PLLCFGR_PLL_DP_Pos (8) ///<
#define RCC_PLLCFGR_PLL_DP (0x07U << RCC_PLLCFGR_PLL_DP_Pos) ///< PLL divider factor DP
#define RCC_PLLCFGR_PLL_DN_Pos (16)
#define RCC_PLLCFGR_PLL_DN (0x7FU << RCC_PLLCFGR_PLL_DN_Pos) ///< PLL divider factor DN
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_HSIDLY Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_HSIDLY_HSI_EQU_CNT (0xFFU) ///< HSI delay time
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_HSEDLY Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_HSEDLY_HSI_EQU_CNT (0xFFFFU) ///< HSE delay time
////////////////////////////////////////////////////////////////////////////////
/// @brief RCC_PLLDLY Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RCC_PLLDLY_HSI_EQU_CNT (0xFFU) ///< PLL delay time
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_rtc.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_RTC_H
#define __REG_RTC_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief RTC Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define RTC_BASE (APB1PERIPH_BASE + 0x2800) ///< Base Address: 0x40002800
////////////////////////////////////////////////////////////////////////////////
/// @brief RTC Registers Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
union {
__IO u32 CR; ///< Control Register, offset: 0x00
__IO u32 CRH;
};
union {
__IO u32 CSR; ///< Control & Status Register, offset: 0x04
__IO u32 CRL;
};
__IO u32 PRLH; ///< Prescaler Reload Value High, offset: 0x08
__IO u32 PRLL; ///< Prescaler Reload Value Low, offset: 0x0C
__IO u32 DIVH; ///< Clock Divider High, offset: 0x10
__IO u32 DIVL; ///< Clock Divider Low, offset: 0x14
__IO u32 CNTH; ///< Counter High, offset: 0x18
__IO u32 CNTL; ///< Counter Low, offset: 0x1C
__IO u32 ALRH; ///< Alarm High, offset: 0x20
__IO u32 ALRL; ///< Alarm Low, offset: 0x24
__IO u32 MSRH; ///< Millisecond alarm high register offset: 0x28
__IO u32 MSRL; ///< Millisecond alarm low register offset: 0x2C
__IO u32 RESERVED0; ///< Reserved offset: 0x30
__IO u32 RESERVED1; ///< Reserved offset: 0x34
__IO u32 RESERVED2; ///< Reserved offset: 0x38
__IO u32 LSE_CFG; ///< LSE configure register offset: 0x3C
} RTC_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief RTC type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define RTC ((RTC_TypeDef*)RTC_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief RTC_CR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RTC_CR_SECIE_Pos (0)
#define RTC_CR_SECIE (0x01U << RTC_CR_SECIE_Pos) ///< Second Interrupt Enable
#define RTC_CR_ALRIE_Pos (1)
#define RTC_CR_ALRIE (0x01U << RTC_CR_ALRIE_Pos) ///< Alarm Interrupt Enable
#define RTC_CR_OWIE_Pos (2)
#define RTC_CR_OWIE (0x01U << RTC_CR_OWIE_Pos) ///< OverfloW Interrupt Enable
////////////////////////////////////////////////////////////////////////////////
/// @brief RTC_CSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RTC_CSR_SECF_Pos (0)
#define RTC_CSR_SECF (0x01 << RTC_CSR_SECF_Pos) ///< Second Flag
#define RTC_CSR_ALRF_Pos (1)
#define RTC_CSR_ALRF (0x01 << RTC_CSR_ALRF_Pos) ///< Alarm Flag
#define RTC_CSR_OWF_Pos (2)
#define RTC_CSR_OWF (0x01 << RTC_CSR_OWF_Pos) ///< OverfloW Flag
#define RTC_CSR_RSF_Pos (3)
#define RTC_CSR_RSF (0x01 << RTC_CSR_RSF_Pos) ///< Registers Synchronized Flag
#define RTC_CSR_CNF_Pos (4)
#define RTC_CSR_CNF (0x01 << RTC_CSR_CNF_Pos) ///< Configuration Flag
#define RTC_CSR_RTOFF_Pos (5)
#define RTC_CSR_RTOFF (0x01 << RTC_CSR_RTOFF_Pos) ///< RTC operation OFF
#define RTC_CSR_ALPEN_Pos (6)
#define RTC_CSR_ALPEN (0x01 << RTC_CSR_ALPEN_Pos) ///< RTC Alarm Loop Enable
////////////////////////////////////////////////////////////////////////////////
/// @brief RTC_PRLH Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RTC_PRLH_PRL_Pos (0)
#define RTC_PRLH_PRL (0x0F << RTC_PRLH_PRL_Pos) ///< RTC Prescaler Reload Value High
////////////////////////////////////////////////////////////////////////////////
/// @brief RTC_PRLL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RTC_PRLL_PRL_Pos (0)
#define RTC_PRLL_PRL (0xFFFFU << RTC_PRLL_PRL_Pos) ///< RTC Prescaler Reload Value Low
////////////////////////////////////////////////////////////////////////////////
/// @brief RTC_DIVH Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RTC_DIVH_DIV_Pos (0)
#define RTC_DIVH_DIV (0x0F << RTC_DIVH_DIV_Pos) ///< RTC Clock Divider High
////////////////////////////////////////////////////////////////////////////////
/// @brief RTC_DIVL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RTC_DIVL_DIV_Pos (0)
#define RTC_DIVL_DIV (0xFFFFU << RTC_DIVL_DIV_Pos) ///< RTC Clock Divider Low
////////////////////////////////////////////////////////////////////////////////
/// @brief RTC_CNTH Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RTC_CNTH_CNT_Pos (0)
#define RTC_CNTH_CNT (0xFFFFU << RTC_CNTH_CNT_Pos) ///< RTC Counter High
////////////////////////////////////////////////////////////////////////////////
/// @brief RTC_CNTL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RTC_CNTL_CNT_Pos (0)
#define RTC_CNTL_CNT (0xFFFFU << RTC_CNTL_CNT_Pos) ///< RTC Counter Low
////////////////////////////////////////////////////////////////////////////////
/// @brief RTC_ALRH Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RTC_ALRH_ALR_Pos (0)
#define RTC_ALRH_ALR (0xFFFFU << RTC_ALRH_ALR_Pos) ///< RTC Alarm High
////////////////////////////////////////////////////////////////////////////////
/// @brief RTC_ALRL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RTC_ALRL_ALR_Pos (0)
#define RTC_ALRL_ALR (0xFFFFU << RTC_ALRL_ALR_Pos) ///< RTC Alarm Low
////////////////////////////////////////////////////////////////////////////////
/// @brief RTC_MSRH Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RTC_MSRH_MSR_Pos (0)
#define RTC_MSRH_MSR (0xFFFFU << RTC_MSRH_MSR_Pos) ///< RTC MS Alarm Register High
////////////////////////////////////////////////////////////////////////////////
/// @brief RTC_MSRL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RTC_MSRL_MSR_Pos (0)
#define RTC_MSRL_MSR (0xFFFFU << RTC_MSRL_MSR_Pos) ///< RTC MS Alarm Register Low
////////////////////////////////////////////////////////////////////////////////
/// @brief RTC_LSE_CFG Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define RTC_LSE_CFG_TEST_Pos (0)
#define RTC_LSE_CFG_TEST (0x0FU << RTC_LSE_CFG_TEST_Pos) ///< Test control signal
#define RTC_LSE_CFG_DR_Pos (4)
#define RTC_LSE_CFG_DR (0x03U << RTC_LSE_CFG_DR_Pos) ///< Drive capability selection
#define RTC_LSE_CFG_RFB_SEL_Pos (6)
#define RTC_LSE_CFG_RFB_SEL_3 (0x03U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 3M
#define RTC_LSE_CFG_RFB_SEL_6 (0x02U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 6M
#define RTC_LSE_CFG_RFB_SEL_10 (0x01U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 10M
#define RTC_LSE_CFG_RFB_SEL_12 (0x00U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 12M
#define RTC_LSE_CFG_IB_Pos (8)
#define RTC_LSE_CFG_IB (0x01U << RTC_MSRL_MSR_Pos) ///< Bias current regulation
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_sdio.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_SDIO_H
#define __REG_SDIO_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
//#include "types.h"
#include "mm32_reg.h"
//#if defined ( __CC_ARM )
//#pragma anon_unions
//#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_BASE (0x40018000U) ///< Base Address: 0x40018000
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 MMC_CTRL; ///< SDIO transmit data register, offset: 0x00
__IO u32 MMC_IO; ///< SDIO receive data register, offset: 0x04
__IO u32 MMC_BYTECNTL; ///< SDIO current state register, offset: 0x08
__IO u32 MMC_TR_BLOCKCNT; ///< SDIO interruput state register, offset: 0x0C
__IO u32 MMC_CRCCTL; ///< SDIO interruput enable register, offset: 0x10
__IO u32 CMD_CRC; ///< SDIO interruput control register, offset: 0x14
__IO u32 DAT_CRCL; ///< SDIO global control register, offset: 0x18
__IO u32 DAT_CRCH; ///< SDIO common control register, offset: 0x1C
__IO u32 MMC_PORT; ///< SDIO baud rate control register, offset: 0x20
__IO u32 MMC_INT_MASK; ///< SDIO receive data number register, offset: 0x24
__IO u32 CLR_MMC_INT; ///< SDIO chip select register, offset: 0x28
__IO u32 MMC_CARDSEL; ///< SDIO extand control register, offset: 0x2C
__IO u32 MMC_SIG; ///< 0ffset: 0x30
__IO u32 MMC_IO_MBCTL; ///< 0ffset: 0x34
__IO u32 MMC_BLOCKCNT; ///< 0ffset: 0x38
__IO u32 MMC_TIMEOUTCNT; ///< 0ffset: 0x3C
__IO u32 CMD_BUF0; ///< 0ffset: 0x40
__IO u32 CMD_BUF1; ///< 0ffset: 0x44
__IO u32 CMD_BUF2; ///< 0ffset: 0x48
__IO u32 CMD_BUF3; ///< 0ffset: 0x4C
__IO u32 CMD_BUF4; ///< 0ffset: 0x50
__IO u32 CMD_BUF5; ///< 0ffset: 0x54
__IO u32 CMD_BUF6; ///< 0ffset: 0x58
__IO u32 CMD_BUF7; ///< 0ffset: 0x5C
__IO u32 CMD_BUF8; ///< 0ffset: 0x60
__IO u32 CMD_BUF9; ///< 0ffset: 0x64
__IO u32 CMD_BUF10; ///< 0ffset: 0x68
__IO u32 CMD_BUF11; ///< 0ffset: 0x6C
__IO u32 CMD_BUF12; ///< 0ffset: 0x70
__IO u32 CMD_BUF13; ///< 0ffset: 0x74
__IO u32 CMD_BUF14; ///< 0ffset: 0x78
__IO u32 CMD_BUF15; ///< 0ffset: 0x7C
__IO u32 BUF_CTL; ///< 0ffset: 0x80
__IO u32 RESERVED[31]; ///< 0ffset: 0x84
union {
__IO u32 DATA_BUF0; ///< 0ffset: 0x100
__IO u32 FIFO;
};
__IO u32 DATA_BUF1; ///< 0ffset: 0x104
__IO u32 DATA_BUF2; ///< 0ffset: 0x108
__IO u32 DATA_BUF3; ///< 0ffset: 0x10C
__IO u32 DATA_BUF4; ///< 0ffset: 0x110
} SDIO_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO ((SDIO_TypeDef*) SDIO_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_MMC_CTRL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_MMC_CTRL_OPMSel_Pos (0)
#define SDIO_MMC_CTRL_OPMSel (0x01U << SDIO_MMC_CTRL_OPMSel_Pos) ///< SD/MMC/SDIO port operation mode select
#define SDIO_MMC_CTRL_SelSM_Pos (1)
#define SDIO_MMC_CTRL_SelSM (0x01U << SDIO_MMC_CTRL_SelSM_Pos) ///< Select automatic mode
#define SDIO_MMC_CTRL_OUTM_Pos (2)
#define SDIO_MMC_CTRL_OUTM (0x01U << SDIO_MMC_CTRL_OUTM_Pos) ///< SD/MMC/SDIO port CMD line output driver mode selection Open drain
#define SDIO_MMC_CTRL_CLKSP_Pos (3)
#define SDIO_MMC_CTRL_CLKSP2 (0x00U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/2 baseclock
#define SDIO_MMC_CTRL_CLKSP4 (0x01U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/4 baseclock
#define SDIO_MMC_CTRL_CLKSP6 (0x02U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/6 baseclock
#define SDIO_MMC_CTRL_CLKSP8 (0x03U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/8 baseclock
#define SDIO_MMC_CTRL_CLKSP10 (0x04U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/10 baseclock
#define SDIO_MMC_CTRL_CLKSP12 (0x05U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/12 baseclock
#define SDIO_MMC_CTRL_CLKSP14 (0x06U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/14 baseclock
#define SDIO_MMC_CTRL_CLKSP16 (0x07U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/16 baseclock
#define SDIO_MMC_CTRL_SelPTSM_Pos (6)
#define SDIO_MMC_CTRL_SelPTSM (0x01U << SDIO_MMC_CTRL_SelPTSM_Pos) ///< SelectSD/MMC/SDIO port transfer high speed mode
#define SDIO_MMC_CTRL_DATWT_Pos (7)
#define SDIO_MMC_CTRL_DATWT (0x01U << SDIO_MMC_CTRL_DATWT_Pos) ///< Definethe bus width of SD/MMC/SDIO port DAT line
#define SDIO_MMC_CTRL_MDEN_Pos (8)
#define SDIO_MMC_CTRL_MDEN (0x01U << SDIO_MMC_CTRL_MDEN_Pos) ///< SDIO mode enable
#define SDIO_MMC_CTRL_INTEN_Pos (9)
#define SDIO_MMC_CTRL_INTEN (0x01U << SDIO_MMC_CTRL_INTEN_Pos) ///< SDIO interrupt enale signal
#define SDIO_MMC_CTRL_RDWTEN_Pos (10)
#define SDIO_MMC_CTRL_RDWTEN (0x01U << SDIO_MMC_CTRL_RDWTEN_Pos) ///< SDIO read wait enable signal
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_MMC_IO Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_MMC_IO_AUTODATTR_Pos (0)
#define SDIO_MMC_IO_AUTODATTR (0x01U << SDIO_MMC_IO_AUTODATTR_Pos) ///< Set up automatic data transfer
#define SDIO_MMC_IO_TRANSFDIR_Pos (1)
#define SDIO_MMC_IO_TRANSFDIR (0x01U << SDIO_MMC_IO_TRANSFDIR_Pos) ///< Set the direction of data transfer
#define SDIO_MMC_IO_AUTOTR_Pos (2)
#define SDIO_MMC_IO_AUTOTR (0x01U << SDIO_MMC_IO_AUTOTR_Pos) ///< Set up automatic 8-bit/command/response transmission.
#define SDIO_MMC_IO_RESPCMDSEL_Pos (3)
#define SDIO_MMC_IO_RESPCMDSEL (0x01U << SDIO_MMC_IO_RESPCMDSEL_Pos) ///< Receive response
#define SDIO_MMC_IO_CID_CSDRD_Pos (4)
#define SDIO_MMC_IO_CID_CSDRD (0x01U << SDIO_MMC_IO_CID_CSDRD_Pos) ///< CID and CSD reads
#define SDIO_MMC_IO_PCLKG_Pos (5)
#define SDIO_MMC_IO_PCLKG (0x01U << SDIO_MMC_IO_PCLKG_Pos) ///< SD/MMC/SDIO port CLK line 8 empty clock generated
#define SDIO_MMC_IO_ENRRESP_Pos (6)
#define SDIO_MMC_IO_ENRRESP (0x01U << SDIO_MMC_IO_ENRRESP_Pos) ///< Enable automatic receiving of responses after a command
#define SDIO_MMC_IO_AUTOCLKG_Pos (7)
#define SDIO_MMC_IO_AUTOCLKG (0x01U << SDIO_MMC_IO_AUTOCLKG_Pos) ///< Enable automatic conversion of the 8 empty clock after a response/command or a single block of data
#define SDIO_MMC_IO_CMDCH_Pos (8)
#define SDIO_MMC_IO_CMDCH (0x01U << SDIO_MMC_IO_CMDCH_Pos) ///< SDIO mode enable
#define SDIO_MMC_IO_CMDAF_Pos (9)
#define SDIO_MMC_IO_CMDAF (0x01U << SDIO_MMC_IO_CMDAF_Pos) ///< SDIO CMD12 / IO abort flag
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_MMC_BYTECNTL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_MMC_BYTECNTL_CNT (0xFFFFU) ///< Data transfer byte count register
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_MMC_TR_BLOCKCNT Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_MMC_TR_BLOCKCNT_CNT (0xFFFFU) ///< The value of the counter that completes the transfer when multiple blocks are transferred.
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_MMC_CRCCTL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_MMC_CRCCTL_DAT_CRCE_Pos (0)
#define SDIO_MMC_CRCCTL_DAT_CRCE (0x01U << SDIO_MMC_CRCCTL_DAT_CRCE_Pos) ///< DAT CRC error
#define SDIO_MMC_CRCCTL_CMD_CRCE_Pos (1)
#define SDIO_MMC_CRCCTL_CMD_CRCE (0x01U << SDIO_MMC_CRCCTL_CMD_CRCE_Pos) ///< CMD CRC error
#define SDIO_MMC_CRCCTL_DAT_CRCS_Pos (2)
#define SDIO_MMC_CRCCTL_DAT_CRCS (0x03U << SDIO_MMC_CRCCTL_DAT_CRCS_Pos) ///< DAT CRC selection
#define SDIO_MMC_CRCCTL_ENRDMB_Pos (4)
#define SDIO_MMC_CRCCTL_ENRDMB (0x01U << SDIO_MMC_CRCCTL_ENRDMB_Pos) ///< Enable reading multiple blocks of data before responding
#define SDIO_MMC_CRCCTL_ENCHK_Pos (5)
#define SDIO_MMC_CRCCTL_ENCHK (0x01U << SDIO_MMC_CRCCTL_ENCHK_Pos) ///< Enable automatic checking
#define SDIO_MMC_CRCCTL_DAT_CRCEN_Pos (6)
#define SDIO_MMC_CRCCTL_DAT_CRCEN (0x01U << SDIO_MMC_CRCCTL_DAT_CRCEN_Pos) ///< SD/MMC/SDIO PORT DAT line CRC circuit enablement
#define SDIO_MMC_CRCCTL_CMD_CRCEN_Pos (7)
#define SDIO_MMC_CRCCTL_CMD_CRCEN (0x01U << SDIO_MMC_CRCCTL_CMD_CRCEN_Pos) ///< SD/MMC/SDIO port CMD line CRC circuit enablement
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CMD_CRC Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CMD_CRC_CMD_CRCV (0x7FU) ///< CMD_CRCV register value
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_DAT_CRCL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_DAT_CRCL_DAT_CRCLV (0xFFU) ///< CMD_CRCV low register value
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_DAT_CRCH Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_DAT_CRCL_DAT_CRCHV (0xFFU) ///< CMD_CRCV high register value
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_MMC_PORT Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_MMC_PORT_NTCR_Pos (0)
#define SDIO_MMC_PORT_NTCR (0x0FU << SDIO_MMC_PORT_NTCR_Pos) ///< Ncr timeout count register
#define SDIO_MMC_PORT_AUTONTEN_Pos (4)
#define SDIO_MMC_PORT_AUTONTEN (0x01U << SDIO_MMC_PORT_AUTONTEN_Pos) ///< Automatic Ncr timer output enablement
#define SDIO_MMC_PORT_PDATS_Pos (5)
#define SDIO_MMC_PORT_PDATS (0x01U << SDIO_MMC_PORT_PDATS_Pos) ///< SD/MMC/SDIO port DAT line signal
#define SDIO_MMC_PORT_PCMDS_Pos (6)
#define SDIO_MMC_PORT_PCMDS (0x01U << SDIO_MMC_PORT_PCMDS_Pos) ///< SD/MMC/SDIO port CMD line signal
#define SDIO_MMC_PORT_PCLKS_Pos (7)
#define SDIO_MMC_PORT_PCLKS (0x01U << SDIO_MMC_PORT_PCLKS_Pos) ///< SD/MMC/SDIO port CLK line signal
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_MMC_INT_MASK Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_MMC_INT_MASK_CMDDINT_Pos (0)
#define SDIO_MMC_INT_MASK_CMDDINT (0x01U << SDIO_MMC_INT_MASK_CMDDINT_Pos) ///<CMD completes interrupt shielding
#define SDIO_MMC_INT_MASK_DATDINT_Pos (1)
#define SDIO_MMC_INT_MASK_DATDINT (0x01U << SDIO_MMC_INT_MASK_DATDINT_Pos) ///< DAT completes interrupt shielding
#define SDIO_MMC_INT_MASK_DATEINT_Pos (2)
#define SDIO_MMC_INT_MASK_DATEINT (0x01U << SDIO_MMC_INT_MASK_DATEINT_Pos) ///< DAT CRC error interrupt masking
#define SDIO_MMC_INT_MASK_CMDEINT_Pos (3)
#define SDIO_MMC_INT_MASK_CMDEINT (0x01U << SDIO_MMC_INT_MASK_CMDEINT_Pos) ///< CMD CRC error interrupt masking
#define SDIO_MMC_INT_MASK_MBDINTM_Pos (4)
#define SDIO_MMC_INT_MASK_MBDINTM (0x01U << SDIO_MMC_INT_MASK_MBDINTM_Pos) ///< Multiple blocks complete interrupt shielding
#define SDIO_MMC_INT_MASK_MBTINTM_Pos (5)
#define SDIO_MMC_INT_MASK_MBTINTM (0x01U << SDIO_MMC_INT_MASK_MBTINTM_Pos) ///< Multiblock timeout interrupt shielding
#define SDIO_MMC_INT_MASK_CRTINTM_Pos (6)
#define SDIO_MMC_INT_MASK_CRTINTM (0x01U << SDIO_MMC_INT_MASK_CRTINTM_Pos) ///< Cmd and Resp Ncr timeout interrupt shielding
#define SDIO_MMC_INT_MASK_CRCINTM_Pos (7)
#define SDIO_MMC_INT_MASK_CRCINTM (0x01U << SDIO_MMC_INT_MASK_CRCINTM_Pos) ///< CRC status token error interrupt masking
#define SDIO_MMC_INT_MASK_D1INTM_Pos (8)
#define SDIO_MMC_INT_MASK_D1INTM (0x01U << SDIO_MMC_INT_MASK_D1INTM_Pos) ///< SDIO Data 1 Line Interrupt Mask
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CLR_MMC_INT Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CLR_MMC_INT_CMDDMC_Pos (0)
#define SDIO_CLR_MMC_INT_CMDDMC (0x01U << SDIO_CLR_MMC_INT_CMDDMC_Pos) ///< CMD completes interrupt mask bit
#define SDIO_CLR_MMC_INT_DATDMC_Pos (1)
#define SDIO_CLR_MMC_INT_DATDMC (0x01U << SDIO_CLR_MMC_INT_DATDMC_Pos) ///< DAT completes interrupt mask bit
#define SDIO_CLR_MMC_INT_DATEMC_Pos (2)
#define SDIO_CLR_MMC_INT_DATEMC (0x01U << SDIO_CLR_MMC_INT_DATEMC_Pos) ///< DAT CRC error interrupt mask bit
#define SDIO_CLR_MMC_INT_CMDEMC_Pos (3)
#define SDIO_CLR_MMC_INT_CMDEMC (0x01U << SDIO_CLR_MMC_INT_CMDEMC_Pos) ///< CMD CRC error interrupt mask bit
#define SDIO_CLR_MMC_INT_MBDMC_Pos (4)
#define SDIO_CLR_MMC_INT_MBDMC (0x01U << SDIO_CLR_MMC_INT_MBDMC_Pos) ///< Multi - block transmission completion interrupt mask bit
#define SDIO_CLR_MMC_INT_MBTMC_Pos (5)
#define SDIO_CLR_MMC_INT_MBTMC (0x01U << SDIO_CLR_MMC_INT_MBTMC_Pos) ///< Multiblock transmission timeout interrupt mask bit
#define SDIO_CLR_MMC_INT_CRNTMC_Pos (6)
#define SDIO_CLR_MMC_INT_CRNTMC (0x01U << SDIO_CLR_MMC_INT_CRNTMC_Pos) ///< Command and response Ncr timeout interrupt mask bit
#define SDIO_CLR_MMC_INT_CRCEMC_Pos (7)
#define SDIO_CLR_MMC_INT_CRCEMC (0x01U << SDIO_CLR_MMC_INT_CRCEMC_Pos) ///< CRC status error marks the interrupt mask bit
#define SDIO_CLR_MMC_INT_D1MC_Pos (8)
#define SDIO_CLR_MMC_INT_D1MC (0x01U << SDIO_CLR_MMC_INT_D1MC_Pos) ///< SDIO DatA1 line interrupt flag/clear bit
#define SDIO_CLR_MMC_INT_MASK (0XFFU)
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_MMC_CARDSEL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_MMC_CARDSEL_TSCALE_Pos (0)
#define SDIO_MMC_CARDSEL_TSCALE (0x01U << SDIO_MMC_CARDSEL_TSCALE_Pos) ///< SD/MMC/SDIO clock frequency division factor (based on 1MHz
#define SDIO_MMC_CARDSEL_ENPCLK_Pos (6)
#define SDIO_MMC_CARDSEL_ENPCLK (0x01U << SDIO_MMC_CARDSEL_ENPCLK_Pos) ///< Enabling card's SD/MMC/SDIO port CLK clock
#define SDIO_MMC_CARDSEL_CTREN_Pos (7)
#define SDIO_MMC_CARDSEL_CTREN (0x01U << SDIO_MMC_CARDSEL_CTREN_Pos) ///< SD/MMC/SDIO controller enablement bit
#define SDIO_MMC_CARDSEL_MASK (0XFFU)
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_MMC_SIQ Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_MMC_SIQ_PDAT0S_Pos (0)
#define SDIO_MMC_SIQ_PDAT0S (0x01U << SDIO_MMC_SIQ_PDAT0S_Pos) ///< SD/MMC/SDIO port DAT0 line signal
#define SDIO_MMC_SIQ_PDAT1S_Pos (1)
#define SDIO_MMC_SIQ_PDAT1S (0x01U << SDIO_MMC_SIQ_PDAT1S_Pos) ///< SD/MMC/SDIO port DAT1 line signal
#define SDIO_MMC_SIQ_PDAT2S_Pos (2)
#define SDIO_MMC_SIQ_PDAT2S (0x01U << SDIO_MMC_SIQ_PDAT2S_Pos) ///< SD/MMC/SDIO port DAT2 line signal
#define SDIO_MMC_SIQ_PDAT3S_Pos (3)
#define SDIO_MMC_SIQ_PDAT3S (0x01U << SDIO_MMC_SIQ_PDAT3S_Pos) ///< SD/MMC/SDIO port DAT3 line signal
#define SDIO_MMC_SIQ_CRC_status_Pos (4)
#define SDIO_MMC_SIQ_CRC_status (0x07U << SDIO_MMC_SIQ_CRC_status_Pos) ///< CRC state
#define SDIO_MMC_SIQ_PCMDS_Pos (7)
#define SDIO_MMC_SIQ_PCMDS (0x01U << SDIO_MMC_SIQ_PCMDS_Pos) ///< SD/MMC/SDIO port CMD line signal
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_MMC_IO_MBCTL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_MMC_IO_MBCTL_SPMBDTR_Pos (0)
#define SDIO_MMC_IO_MBCTL_SPMBDTR (0x01U << SDIO_MMC_IO_MBCTL_SPMBDTR_Pos) ///< Set the SD/MMC/SDIO port to automatically multiblock data transfer bit
#define SDIO_MMC_IO_MBCTL_SMBDTD_Pos (1)
#define SDIO_MMC_IO_MBCTL_SMBDTD (0x01U << SDIO_MMC_IO_MBCTL_SMBDTD_Pos) //< Multi - block data transfer direction selection bit
#define SDIO_MMC_IO_MBCTL_PAUTOTR_Pos (2)
#define SDIO_MMC_IO_MBCTL_PAUTOTR (0x01U << SDIO_MMC_IO_MBCTL_PAUTOTR_Pos) ///< Set up SD/MMC/SDIO port automatic command and multi - block data transfer
#define SDIO_MMC_IO_MBCTL_PCLKP_Pos (3)
#define SDIO_MMC_IO_MBCTL_PCLKP (0x01U << SDIO_MMC_IO_MBCTL_PCLKP_Pos) ///< SD/MMC/SDIO port CLK line polarity selection bit
#define SDIO_MMC_IO_MBCTL_BTSSel_Pos (4)
#define SDIO_MMC_IO_MBCTL_BTSSel (0x03U << SDIO_MMC_SIQ_CRC_status_Pos) ///< SD/MMC/SDIO BUSY Timeout level selects bits
#define SDIO_MMC_IO_MBCTL_BTSSel_2 (0x02U << SDIO_MMC_SIQ_CRC_status_Pos) ///< SD/MMC/SDIO BUSY Timeout level selects bits
#define SDIO_MMC_IO_MBCTL_NTSSel_Pos (6)
#define SDIO_MMC_IO_MBCTL_NTSSel (0x03U << SDIO_MMC_IO_MBCTL_NTSSel_Pos) ///< SD/MMC/SDIO NAC timeout level selection bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_MMC_BLOCKCNT Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_MMC_BLOCKCNT_EN (0xFFFFU) ///< Block count register
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_MMC_TIMEOUTCNT Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_MMC_TIMEOUTCNT_DTCNT (0xFFU) ///< Data transfer timeout count register
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CMD_BUF0 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CMD_BUF0_DAT (0xFFU) ///< Cmd_buf0 byte mapping bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CMD_BUF1 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CMD_BUF1_DAT (0xFFU) ///< Cmd_buf1 byte mapping bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CMD_BUF2 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CMD_BUF2_DAT (0xFFU) ///< Cmd_buf2 byte mapping bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CMD_BUF3 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CMD_BUF3_DAT (0xFFU) ///< Cmd_buf3 byte mapping bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CMD_BUF4 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CMD_BUF4_DAT (0xFFU) ///< Cmd_buf4 byte mapping bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CMD_BUF5 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CMD_BUF5_DAT (0xFFU) ///< Cmd_buf5 byte mapping bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CMD_BUF6 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CMD_BUF6_DAT (0xFFU) ///< Cmd_buf6 byte mapping bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CMD_BUF7 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CMD_BUF7_DAT (0xFFU) ///< Cmd_buf7 byte mapping bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CMD_BUF8 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CMD_BUF8_DAT (0xFFU) ///< Cmd_buf8 byte mapping bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CMD_BUF9 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CMD_BUF9_DAT (0xFFU) ///< Cmd_buf9 byte mapping bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CMD_BUF10 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CMD_BUF10_DAT (0xFFU) ///< Cmd_buf10 byte mapping bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CMD_BUF11 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CMD_BUF11_DAT (0xFFU) ///< Cmd_buf11 byte mapping bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CMD_BUF12 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CMD_BUF12_DAT (0xFFU) ///< Cmd_buf12 byte mapping bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CMD_BUF13 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CMD_BUF13_DAT (0xFFU) ///< Cmd_buf13 byte mapping bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CMD_BUF14 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CMD_BUF14_DAT (0xFFU) ///< Cmd_buf14 byte mapping bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_CMD_BUF15 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_CMD_BUF15_DAT (0xFFU) ///< Cmd_buf15 byte mapping bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_BUF_CTLL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_BUF_CTLL_DBF_Pos (0)
#define SDIO_BUF_CTLL_DBF (0x01U << SDIO_BUF_CTLL_DBF_Pos) ///< The data cache is full
#define SDIO_BUF_CTLL_DBE_Pos (1)
#define SDIO_BUF_CTLL_DBE (0x01U << SDIO_BUF_CTLL_DBE_Pos) ///< Data buff is null
#define SDIO_BUF_CTLL_DBML_Pos (2)
#define SDIO_BUF_CTLL_DBML (0xFFU << SDIO_BUF_CTLL_DBML_Pos) ////< Data buff tags
#define SDIO_BUF_CTLL_DMAHEN_Pos (10)
#define SDIO_BUF_CTLL_DMAHEN (0x01U << SDIO_BUF_CTLL_DMAHEN_Pos) ///< DMA hardware interface enablement
#define SDIO_BUF_CTLL_SBAD_Pos (11)
#define SDIO_BUF_CTLL_SBAD (0x01U << SDIO_BUF_CTLL_SBAD_Pos) ///< Sets the access direction of the buff
#define SDIO_BUF_CTLL_DFIFOSM_Pos (12)
#define SDIO_BUF_CTLL_DFIFOSM (0x01U << SDIO_BUF_CTLL_DFIFOSM_Pos) ///< Data FIFO status signal shielding bit
#define SDIO_BUF_CTLL_DRM_Pos (14)
#define SDIO_BUF_CTLL_DRM (0x01U << SDIO_BUF_CTLL_DRM_Pos) ///< DMA request masking
#define SDIO_BUF_CTLL_DBFEN_Pos (15)
#define SDIO_BUF_CTLL_DBFEN (0x01U << SDIO_BUF_CTLL_DBFEN_Pos) ///< Data Buf empty enable bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SDIO_DATA_BUF Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SDIO_DATA_BUF_DB (0xFFFFFFFFU) ///< Data buffer
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_spi.h
+359
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@@ -0,0 +1,359 @@
////////////////////////////////////////////////////////////////////////////////
/// @file reg_spi.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_SPI_H
#define __REG_SPI_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief SPI Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) ///< Base Address: 0x40003800
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) ///< Base Address: 0x400013000
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) ///< Base Address: 0x40003C000
////////////////////////////////////////////////////////////////////////////////
/// @brief SPI Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
#undef USENCOMBINEREGISTER
#undef USENNEWREGISTER
#undef USENOLDREGISTER
#define USENCOMBINEREGISTER
#ifdef USENCOMBINEREGISTER
typedef struct {
union {
__IO u32 TDR; ///< SPI transmit data register, offset: 0x00
__IO u32 TXREG;
};
union {
__IO u32 RDR; ///< SPI receive data register, offset: 0x04
__IO u32 RXREG;
};
union {
__IO u32 SR; ///< SPI current state register, offset: 0x08
__IO u32 CSTAT;
};
union {
__IO u32 ISR; ///< SPI interruput state register, offset: 0x0C
__IO u32 INTSTAT;
};
union {
__IO u32 IER; ///< SPI interruput enable register, offset: 0x10
__IO u32 INTEN;
};
union {
__IO u32 ICR; ///< SPI interruput control register, offset: 0x14
__IO u32 INTCLR;
};
union {
__IO u32 GCR; ///< SPI global control register, offset: 0x18
__IO u32 GCTL;
};
union {
__IO u32 CCR; ///< SPI common control register, offset: 0x1C
__IO u32 CCTL;
};
union {
__IO u32 BRR; ///< SPI baud rate control register, offset: 0x20
__IO u32 SPBRG;
};
union {
__IO u32 RDNR; ///< SPI receive data number register, offset: 0x24
__IO u32 RXDNR;
};
union {
__IO u32 NSSR; ///< SPI chip select register, offset: 0x28
__IO u32 SCSR;
};
union {
__IO u32 ECR; ///< SPI extand control register, offset: 0x2C
__IO u32 EXTCTL;
};
__IO u32 CFGR; ///< I2S configuration register, offset: 0x30
} SPI_TypeDef;
#endif
#ifdef USENNEWREGISTER
typedef struct {
__IO u32 TDR; ///< SPI transmit data register, offset: 0x00
__IO u32 RDR; ///< SPI receive data register, offset: 0x04
__IO u32 SR; ///< SPI current state register, offset: 0x08
__IO u32 ISR; ///< SPI interruput state register, offset: 0x0C
__IO u32 IER; ///< SPI interruput enable register, offset: 0x10
__IO u32 ICR; ///< SPI interruput control register, offset: 0x14
__IO u32 GCR; ///< SPI global control register, offset: 0x18
__IO u32 CCR; ///< SPI common control register, offset: 0x1C
__IO u32 BRR; ///< SPI baud rate control register, offset: 0x20
__IO u32 RDNR; ///< SPI receive data number register, offset: 0x24
__IO u32 NSSR; ///< SPI chip select register, offset: 0x28
__IO u32 ECR; ///< SPI extand control register, offset: 0x2C
} SPI_TypeDef;
#endif
#ifdef USENOLDREGISTER
typedef struct {
__IO u32 TXREG; ///< SPI transmit data register, offset: 0x00
__IO u32 RXREG; ///< SPI receive data register, offset: 0x04
__IO u32 CSTAT; ///< SPI current state register, offset: 0x08
__IO u32 INTSTAT; ///< SPI interruput state register, offset: 0x0C
__IO u32 INTEN; ///< SPI interruput enable register, offset: 0x10
__IO u32 INTCLR; ///< SPI interruput control register, offset: 0x14
__IO u32 GCTL; ///< SPI global control register, offset: 0x18
__IO u32 CCTL; ///< SPI common control register, offset: 0x1C
__IO u32 SPBRG; ///< SPI baud rate control register, offset: 0x20
__IO u32 RXDNR; ///< SPI receive data number register, offset: 0x24
__IO u32 NSSR; ///< SPI chip select register, offset: 0x28
__IO u32 EXTCTL; ///< SPI extand control register, offset: 0x2C
} SPI_TypeDef;
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief SPI type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define SPI2 ((SPI_TypeDef*) SPI2_BASE)
#define SPI1 ((SPI_TypeDef*) SPI1_BASE)
#define SPI3 ((SPI_TypeDef*) SPI3_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief SPI_TDR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SPI_TDR_TXREG_Pos (0)
#define SPI_TDR_TXREG (0xFFFFFFFFU << SPI_TDR_TXREG_Pos) ///< Transmit data register
////////////////////////////////////////////////////////////////////////////////
/// @brief SPI_RDR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SPI_RDR_RXREG_Pos (0)
#define SPI_RDR_RXREG (0xFFFFFFFFU << SPI_RDR_RXREG_Pos) ///< Receive data register
////////////////////////////////////////////////////////////////////////////////
/// @brief SPI_SR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SPI_SR_TXEPT_Pos (0)
#define SPI_SR_TXEPT (0x01U << SPI_SR_TXEPT_Pos) ///< Transmitter empty bit
#define SPI_SR_RXAVL_Pos (1)
#define SPI_SR_RXAVL (0x01U << SPI_SR_RXAVL_Pos) ///< Receive available byte data message
#define SPI_SR_TXFULL_Pos (2)
#define SPI_SR_TXFULL (0x01U << SPI_SR_TXFULL_Pos) ///< Transmitter FIFO full status bit
#define SPI_SR_RXAVL_4BYTE_Pos (3)
#define SPI_SR_RXAVL_4BYTE (0x01U << SPI_SR_RXAVL_4BYTE_Pos) ///< Receive available 4 byte data message
#define SPI_SR_TXFADDR_Pos (4)
#define SPI_SR_TXFADDR (0x0FU << SPI_SR_TXFADDR_Pos) ///< Transmit FIFO address
#define SPI_SR_RXFADDR_Pos (8)
#define SPI_SR_RXFADDR (0x0FU << SPI_SR_RXFADDR_Pos) ///< Receive FIFO address
#define SPI_SR_BUSY_Pos (12)
#define SPI_SR_BUSY (0x01U << SPI_SR_BUSY_Pos) ///< Data transfer flag
#define SPI_SR_CHSIDE_Pos (13)
#define SPI_SR_CHSIDE (0x01U << SPI_SR_CHSIDE_Pos) ///< transmission channel
////////////////////////////////////////////////////////////////////////////////
/// @brief SPI_ISR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SPI_ISR_TX_INTF_Pos (0)
#define SPI_ISR_TX_INTF (0x01U << SPI_ISR_TX_INTF_Pos) ///< Transmit FIFO available interrupt flag bit
#define SPI_ISR_RX_INTF_Pos (1)
#define SPI_ISR_RX_INTF (0x01U << SPI_ISR_RX_INTF_Pos) ///< Receive data available interrupt flag bit
#define SPI_ISR_UNDERRUN_INTF_Pos (2)
#define SPI_ISR_UNDERRUN_INTF (0x01U << SPI_ISR_UNDERRUN_INTF_Pos) ///< SPI underrun interrupt flag bit
#define SPI_ISR_RXOERR_INTF_Pos (3)
#define SPI_ISR_RXOERR_INTF (0x01U << SPI_ISR_RXOERR_INTF_Pos) ///< Receive overrun error interrupt flag bit
#define SPI_ISR_RXMATCH_INTF_Pos (4)
#define SPI_ISR_RXMATCH_INTF (0x01U << SPI_ISR_RXMATCH_INTF_Pos) ///< Receive data match the RXDNR number, the receive process will be completed and generate the interrupt
#define SPI_ISR_RXFULL_INTF_Pos (5)
#define SPI_ISR_RXFULL_INTF (0x01U << SPI_ISR_RXFULL_INTF_Pos) ///< RX FIFO full interrupt flag bit
#define SPI_ISR_TXEPT_INTF_Pos (6)
#define SPI_ISR_TXEPT_INTF (0x01U << SPI_ISR_TXEPT_INTF_Pos) ///< Transmitter empty interrupt flag bit
#define SPI_ISR_FRE_INTF_Pos (7)
#define SPI_ISR_FRE_INTF (0x01U << SPI_ISR_FRE_INTF_Pos) ///< I2S frame transmission error flag bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SPI_IER Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SPI_IER_TX_IEN_Pos (0)
#define SPI_IER_TX_IEN (0x01U << SPI_IER_TX_IEN_Pos) ///< Transmit FIFO empty interrupt enable bit
#define SPI_IER_RX_IEN_Pos (1)
#define SPI_IER_RX_IEN (0x01U << SPI_IER_RX_IEN_Pos) ///< Receive FIFO interrupt enable bit
#define SPI_IER_UNDERRUN_IEN_Pos (2)
#define SPI_IER_UNDERRUN_IEN (0x01U << SPI_IER_UNDERRUN_IEN_Pos) ///< Transmitter underrun interrupt enable bit
#define SPI_IER_RXOERR_IEN_Pos (3)
#define SPI_IER_RXOERR_IEN (0x01U << SPI_IER_RXOERR_IEN_Pos) ///< Overrun error interrupt enable bit
#define SPI_IER_RXMATCH_IEN_Pos (4)
#define SPI_IER_RXMATCH_IEN (0x01U << SPI_IER_RXMATCH_IEN_Pos) ///< Receive data complete interrupt enable bit
#define SPI_IER_RXFULL_IEN_Pos (5)
#define SPI_IER_RXFULL_IEN (0x01U << SPI_IER_RXFULL_IEN_Pos) ///< Receive FIFO full interrupt enable bit
#define SPI_IER_TXEPT_IEN_Pos (6)
#define SPI_IER_TXEPT_IEN (0x01U << SPI_IER_TXEPT_IEN_Pos) ///< Transmit empty interrupt enable bit
#define SPI_IER_FRE_IEN_Pos (7)
#define SPI_IER_FRE_IEN (0x01U << SPI_IER_FRE_IEN_Pos) ///< I2S frame transmission interrupt enable bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SPI_ICR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SPI_ICR_TX_ICLR_Pos (0)
#define SPI_ICR_TX_ICLR (0x01U << SPI_ICR_TX_ICLR_Pos) ///< Transmitter FIFO empty interrupt clear bit
#define SPI_ICR_RX_ICLR_Pos (1)
#define SPI_ICR_RX_ICLR (0x01U << SPI_ICR_RX_ICLR_Pos) ///< Receive interrupt clear bit
#define SPI_ICR_UNDERRUN_ICLR_Pos (2)
#define SPI_ICR_UNDERRUN_ICLR (0x01U << SPI_ICR_UNDERRUN_ICLR_Pos) ///< Transmitter underrun interrupt clear bit
#define SPI_ICR_RXOERR_ICLR_Pos (3)
#define SPI_ICR_RXOERR_ICLR (0x01U << SPI_ICR_RXOERR_ICLR_Pos) ///< Overrun error interrupt clear bit
#define SPI_ICR_RXMATCH_ICLR_Pos (4)
#define SPI_ICR_RXMATCH_ICLR (0x01U << SPI_ICR_RXMATCH_ICLR_Pos) ///< Receive completed interrupt clear bit
#define SPI_ICR_RXFULL_ICLR_Pos (5)
#define SPI_ICR_RXFULL_ICLR (0x01U << SPI_ICR_RXFULL_ICLR_Pos) ///< Receiver buffer full interrupt clear bit
#define SPI_ICR_TXEPT_ICLR_Pos (6)
#define SPI_ICR_TXEPT_ICLR (0x01U << SPI_ICR_TXEPT_ICLR_Pos) ///< Transmitter empty interrupt clear bit
#define SPI_ICR_FRE_ICLR_Pos (7)
#define SPI_ICR_FRE_ICLR (0x01U << SPI_ICR_FRE_ICLR_Pos) ///< I2S frame transmission interrupt clear bit
////////////////////////////////////////////////////////////////////////////////
/// @brief SPI_GCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SPI_GCR_SPIEN_Pos (0)
#define SPI_GCR_SPIEN (0x01U << SPI_GCR_SPIEN_Pos) ///< SPI select bit
#define SPI_GCR_IEN_Pos (1)
#define SPI_GCR_IEN (0x01U << SPI_GCR_IEN_Pos) ///< SPI interrupt enable bit
#define SPI_GCR_MODE_Pos (2)
#define SPI_GCR_MODE (0x01U << SPI_GCR_MODE_Pos) ///< Master mode bit
#define SPI_GCR_TXEN_Pos (3)
#define SPI_GCR_TXEN (0x01U << SPI_GCR_TXEN_Pos) ///< Transmit enable bit
#define SPI_GCR_RXEN_Pos (4)
#define SPI_GCR_RXEN (0x01U << SPI_GCR_RXEN_Pos) ///< Receive enable bit
#define SPI_GCR_RXTLF_Pos (5)
#define SPI_GCR_RXTLF (0x03U << SPI_GCR_RXTLF_Pos) ///< RX FIFO trigger level bit
#define SPI_GCR_RXTLF_One (0x00U << SPI_GCR_RXTLF_Pos) ///<
#define SPI_GCR_RXTLF_Half (0x01U << SPI_GCR_RXTLF_Pos) ///<
#define SPI_GCR_TXTLF_Pos (7)
#define SPI_GCR_TXTLF (0x03U << SPI_GCR_TXTLF_Pos) ///< TX FIFO trigger level bit
#define SPI_GCR_TXTLF_One (0x00U << SPI_GCR_TXTLF_Pos) ///<
#define SPI_GCR_TXTLF_Half (0x01U << SPI_GCR_TXTLF_Pos) ///<
#define SPI_GCR_DMAEN_Pos (9)
#define SPI_GCR_DMAEN (0x01U << SPI_GCR_DMAEN_Pos) ///< DMA access mode enable
#define SPI_GCR_NSS_Pos (10)
#define SPI_GCR_NSS (0x01U << SPI_GCR_NSS_Pos) ///< NSS select signal that from software or hardware
#define SPI_GCR_DWSEL_Pos (11)
#define SPI_GCR_DWSEL (0x01U << SPI_GCR_DWSEL_Pos) ///< Valid byte or double-word data select signal
#define SPI_GCR_NSSTOG_Pos (12)
#define SPI_GCR_NSSTOG (0x01U << SPI_GCR_NSSTOG_Pos) ///< Slave select toggle
#define SPI_GCR_PAD_SEL_Pos (13)
#define SPI_GCR_PAD_SEL (0x1FU << SPI_GCR_PAD_SEL_Pos) ///< Bus mapping transformation
////////////////////////////////////////////////////////////////////////////////
/// @brief SPI_CCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SPI_CCR_CPHA_Pos (0)
#define SPI_CCR_CPHA (0x01U << SPI_CCR_CPHA_Pos) ///< Clock phase select bit
#define SPI_CCR_CPOL_Pos (1)
#define SPI_CCR_CPOL (0x01U << SPI_CCR_CPOL_Pos) ///< Clock polarity select bit
#define SPI_CCR_LSBFE_Pos (2)
#define SPI_CCR_LSBFE (0x01U << SPI_CCR_LSBFE_Pos) ///< LSI first enable bit
#define SPI_CCR_SPILEN_Pos (3)
#define SPI_CCR_SPILEN (0x01U << SPI_CCR_SPILEN_Pos) ///< SPI character length bit
#define SPI_CCR_RXEDGE_Pos (4)
#define SPI_CCR_RXEDGE (0x01U << SPI_CCR_RXEDGE_Pos) ///< Receive data edge select
#define SPI_CCR_TXEDGE_Pos (5)
#define SPI_CCR_TXEDGE (0x01U << SPI_CCR_TXEDGE_Pos) ///< Transmit data edge select
#define SPI_CCR_CPHASEL_Pos (6)
#define SPI_CCR_CPHASEL (0x01U << SPI_CCR_CPHASEL) ///< CPHA polarity select
#define SPI_CCR_HISPD_Pos (7)
#define SPI_CCR_HISPD (0x01U << SPI_CCR_HISPD) ///< High speed slave mode
////////////////////////////////////////////////////////////////////////////////
/// @brief SPI_BRR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SPI_BRR_DIVF_Pos (0)
#define SPI_BRR_DIVF (0xFFFFU << SPI_BRR_DIVF_Pos) ///< SPI baud rate control register for baud rate
////////////////////////////////////////////////////////////////////////////////
/// @brief SPI_RDNR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SPI_RDNR_RDN_Pos (0)
#define SPI_RDNR_RDN (0xFFFFU << SPI_RDNR_RDN_Pos) ///< The register is used to hold a count of to be received bytes in next receive process
////////////////////////////////////////////////////////////////////////////////
/// @brief SPI_NSSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SPI_NSSR_NSS_Pos (0)
#define SPI_NSSR_NSS (0xFFU << SPI_NSSR_NSS_Pos) ///< Chip select output signal in Master mode
////////////////////////////////////////////////////////////////////////////////
/// @brief SPI_ECR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define SPI_ECR_EXTLEN_Pos (0)
#define SPI_ECR_EXTLEN (0x1FU << SPI_ECR_EXTLEN_Pos) ///< control SPI data length
////////////////////////////////////////////////////////////////////////////////
/// @brief I2S_CFGR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define I2SCFGR_CLEAR_Mask ((u32)0xFE00F388)
#define I2S_CFGR_CHLEN_Pos (0)
#define I2S_CFGR_CHLEN (0x01U << I2S_CFGR_CHLEN_Pos) ///< Vocal tract length
#define I2S_CFGR_DATLEN_Pos (1)
#define I2S_CFGR_DATLEN_16 (0x00U << I2S_CFGR_DATLEN_Pos) ///< Audio data width 16
#define I2S_CFGR_DATLEN_24 (0x01U << I2S_CFGR_DATLEN_Pos) ///< Audio data width 24
#define I2S_CFGR_DATLEN_32 (0x02U << I2S_CFGR_DATLEN_Pos) ///< Audio data width 32
#define I2S_CFGR_I2SSTD_Pos (4)
#define I2S_CFGR_I2SSTD_PCM (0x00U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection PCM standard
#define I2S_CFGR_I2SSTD_MSB_R (0x01U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection Right alignment (MSB) standard
#define I2S_CFGR_I2SSTD_MSB_L (0x02U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection Left aligned (MSB) standard
#define I2S_CFGR_I2SSTD_Philips (0x03U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection Philips standard
#define I2S_CFGR_PCMSYNC_Pos (6)
#define I2S_CFGR_PCMSYNC (0x01U << I2S_CFGR_PCMSYNC_Pos) ///< PCM frame synchronization mode
#define I2S_CFGR_SPI_I2S_Pos (10)
#define I2S_CFGR_SPI_I2S (0x01U << I2S_CFGR_SPI_I2S_Pos) ///< SPI/I2S module function selection
#define I2S_CFGR_MCKOE_Pos (11)
#define I2S_CFGR_MCKOE (0x01U << I2S_CFGR_MCKOE_Pos) ///< I2S master clock output enable
#define I2S_CFGR_I2SDIV_Pos (16)
#define I2S_CFGR_I2SDIV (0x1FFU << I2S_CFGR_I2SDIV_Pos) ///< The frequency division
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_syscfg.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_SYSCFG_H
#define __REG_SYSCFG_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) ///< Base Address: 0x40010000
////////////////////////////////////////////////////////////////////////////////
/// @brief SysTem Configuration Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
union {
__IO u32 CFGR; ///< SYSCFG configuration register offset: 0x00
__IO u32 CFGR1;
};
__IO u32 RESERVED0x04; ///< RESERVED register offset: 0x04
__IO u32 EXTICR[4]; ///< SYSCFG configuration register offset: 0x08-0x14
__IO u32 CFGR2; ///< SYSCFG configuration2 register offset: 0x18
__IO u32 PDETCSR; ///< SYSCFG Power Detect configuration stautus reg offset: 0x1C
__IO u32 VOSDLY; ///< SYSCFG VOSDLY Counter register offset: 0x20
} SYSCFG_TypeDef;
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
////////////////////////////////////////////////////////////////////////////////
///@brief System Configuration (SYSCFG)
////////////////////////////////////////////////////////////////////////////////
/// @brief SYSCFG_CFGR Register Bit definition
#define SYSCFG_CFGR_MEM_MODE_Pos (0)
#define SYSCFG_CFGR_MEM_MODE ((u32)0x00000003) ///< SYSCFG_Memory Remap Config
#define SYSCFG_CFGR_MEM_MODE_0 ((u32)0x00000001) ///< SYSCFG_Memory Remap Config Bit 0
#define SYSCFG_CFGR_MEM_MODE_1 ((u32)0x00000002) ///< SYSCFG_Memory Remap Config Bit 1
///
#define SYSCFG_CFGR_FSMC_SYNC_EN_Pos (27)
#define SYSCFG_CFGR_FSMC_SYNC_EN (0x01U << SYSCFG_CFGR_FSMC_SYNC_EN_Pos)///< FSMC SYNC Enable
#define SYSCFG_CFGR_FSMC_AF_ADDR_Pos (28)
#define SYSCFG_CFGR_FSMC_AF_ADDR (0x01U << SYSCFG_CFGR_FSMC_AF_ADDR_Pos)///< FSMC Databus AF Address
#define SYSCFG_CFGR_FSMC_MODE_Pos (29)
#define SYSCFG_CFGR_FSMC_MODE ((u32)0x03<<SYSCFG_CFGR_FSMC_MODE_Pos) ///< FSMC Interface Mode Config
#define SYSCFG_CFGR_FSMC_MODE0 ((u32)0x00<<SYSCFG_CFGR_FSMC_MODE_Pos) ///< FSMC Mode Config Mode 0
#define SYSCFG_CFGR_FSMC_MODE1 ((u32)0x01<<SYSCFG_CFGR_FSMC_MODE_Pos) ///< FSMC Mode Config Mode 1
/// @brief SYSCFG_EXTICR1 Register Bit definition
#define SYSCFG_EXTICR1_EXTI0 ((u16)0x000F) ///< EXTI 0 configuration
#define SYSCFG_EXTICR1_EXTI1 ((u16)0x00F0) ///< EXTI 1 configuration
#define SYSCFG_EXTICR1_EXTI2 ((u16)0x0F00) ///< EXTI 2 configuration
#define SYSCFG_EXTICR1_EXTI3 ((u16)0xF000) ///< EXTI 3 configuration
/// @brief EXTI0 configuration
#define SYSCFG_EXTICR1_EXTI0_PA ((u16)0x0000) ///< PA[0] pin
#define SYSCFG_EXTICR1_EXTI0_PB ((u16)0x0001) ///< PB[0] pin
#define SYSCFG_EXTICR1_EXTI0_PC ((u16)0x0002) ///< PC[0] pin
#define SYSCFG_EXTICR1_EXTI0_PD ((u16)0x0003) ///< PD[0] pin
/// @brief EXTI1 configuration
#define SYSCFG_EXTICR1_EXTI1_PA ((u16)0x0000) ///< PA[1] pin
#define SYSCFG_EXTICR1_EXTI1_PB ((u16)0x0010) ///< PB[1] pin
#define SYSCFG_EXTICR1_EXTI1_PC ((u16)0x0020) ///< PC[1] pin
#define SYSCFG_EXTICR1_EXTI1_PD ((u16)0x0030) ///< PD[1] pin
/// @brief EXTI2 configuration
#define SYSCFG_EXTICR1_EXTI2_PA ((u16)0x0000) ///< PA[2] pin
#define SYSCFG_EXTICR1_EXTI2_PB ((u16)0x0100) ///< PB[2] pin
#define SYSCFG_EXTICR1_EXTI2_PC ((u16)0x0200) ///< PC[2] pin
#define SYSCFG_EXTICR1_EXTI2_PD ((u16)0x0300) ///< PD[2] pin
/// @brief EXTI3 configuration
#define SYSCFG_EXTICR1_EXTI3_PA ((u16)0x0000) ///< PA[3] pin
#define SYSCFG_EXTICR1_EXTI3_PB ((u16)0x1000) ///< PB[3] pin
#define SYSCFG_EXTICR1_EXTI3_PC ((u16)0x2000) ///< PC[3] pin
#define SYSCFG_EXTICR1_EXTI3_PD ((u16)0x3000) ///< PD[3] pin
/// @brief SYSCFG_EXTICR2 Register Bit definition
#define SYSCFG_EXTICR2_EXTI4 ((u16)0x000F) ///< EXTI 4 configuration
#define SYSCFG_EXTICR2_EXTI5 ((u16)0x00F0) ///< EXTI 5 configuration
#define SYSCFG_EXTICR2_EXTI6 ((u16)0x0F00) ///< EXTI 6 configuration
#define SYSCFG_EXTICR2_EXTI7 ((u16)0xF000) ///< EXTI 7 configuration
/// @brief EXTI4 configuration
#define SYSCFG_EXTICR2_EXTI4_PA ((u16)0x0000) ///< PA[4] pin
#define SYSCFG_EXTICR2_EXTI4_PB ((u16)0x0001) ///< PB[4] pin
#define SYSCFG_EXTICR2_EXTI4_PC ((u16)0x0002) ///< PC[4] pin
#define SYSCFG_EXTICR2_EXTI4_PD ((u16)0x0003) ///< PD[4] pin
/// @brief EXTI5 configuration
#define SYSCFG_EXTICR2_EXTI5_PA ((u16)0x0000) ///< PA[5] pin
#define SYSCFG_EXTICR2_EXTI5_PB ((u16)0x0010) ///< PB[5] pin
#define SYSCFG_EXTICR2_EXTI5_PC ((u16)0x0020) ///< PC[5] pin
#define SYSCFG_EXTICR2_EXTI5_PD ((u16)0x0030) ///< PD[5] pin
/// @brief EXTI6 configuration
#define SYSCFG_EXTICR2_EXTI6_PA ((u16)0x0000) ///< PA[6] pin
#define SYSCFG_EXTICR2_EXTI6_PB ((u16)0x0100) ///< PB[6] pin
#define SYSCFG_EXTICR2_EXTI6_PC ((u16)0x0200) ///< PC[6] pin
#define SYSCFG_EXTICR2_EXTI6_PD ((u16)0x0300) ///< PD[6] pin
/// @brief EXTI7 configuration
#define SYSCFG_EXTICR2_EXTI7_PA ((u16)0x0000) ///< PA[7] pin
#define SYSCFG_EXTICR2_EXTI7_PB ((u16)0x1000) ///< PB[7] pin
#define SYSCFG_EXTICR2_EXTI7_PC ((u16)0x2000) ///< PC[7] pin
#define SYSCFG_EXTICR2_EXTI7_PD ((u16)0x3000) ///< PD[7] pin
/// @brief SYSCFG_EXTICR3 Register Bit definition
#define SYSCFG_EXTICR3_EXTI8 ((u16)0x000F) ///< EXTI 8 configuration
#define SYSCFG_EXTICR3_EXTI9 ((u16)0x00F0) ///< EXTI 9 configuration
#define SYSCFG_EXTICR3_EXTI10 ((u16)0x0F00) ///< EXTI 10 configuration
#define SYSCFG_EXTICR3_EXTI11 ((u16)0xF000) ///< EXTI 11 configuration
/// @brief EXTI8 configuration
#define SYSCFG_EXTICR3_EXTI8_PA ((u16)0x0000) ///< PA[8] pin
#define SYSCFG_EXTICR3_EXTI8_PB ((u16)0x0001) ///< PB[8] pin
#define SYSCFG_EXTICR3_EXTI8_PC ((u16)0x0002) ///< PC[8] pin
#define SYSCFG_EXTICR3_EXTI8_PD ((u16)0x0003) ///< PD[8] pin
/// @brief EXTI9 configuration
#define SYSCFG_EXTICR3_EXTI9_PA ((u16)0x0000) ///< PA[9] pin
#define SYSCFG_EXTICR3_EXTI9_PB ((u16)0x0010) ///< PB[9] pin
#define SYSCFG_EXTICR3_EXTI9_PC ((u16)0x0020) ///< PC[9] pin
#define SYSCFG_EXTICR3_EXTI9_PD ((u16)0x0030) ///< PD[9] pin
/// @brief EXTI10 configuration
#define SYSCFG_EXTICR3_EXTI10_PA ((u16)0x0000) ///< PA[10] pin
#define SYSCFG_EXTICR3_EXTI10_PB ((u16)0x0100) ///< PB[10] pin
#define SYSCFG_EXTICR3_EXTI10_PC ((u16)0x0200) ///< PC[10] pin
#define SYSCFG_EXTICR3_EXTI10_PD ((u16)0x0300) ///< PE[10] pin
/// @brief EXTI11 configuration
#define SYSCFG_EXTICR3_EXTI11_PA ((u16)0x0000) ///< PA[11] pin
#define SYSCFG_EXTICR3_EXTI11_PB ((u16)0x1000) ///< PB[11] pin
#define SYSCFG_EXTICR3_EXTI11_PC ((u16)0x2000) ///< PC[11] pin
#define SYSCFG_EXTICR3_EXTI11_PD ((u16)0x3000) ///< PD[11] pin
/// @brief SYSCFG_EXTICR4 Register Bit definition
#define SYSCFG_EXTICR4_EXTI12 ((u16)0x000F) ///< EXTI 12 configuration
#define SYSCFG_EXTICR4_EXTI13 ((u16)0x00F0) ///< EXTI 13 configuration
#define SYSCFG_EXTICR4_EXTI14 ((u16)0x0F00) ///< EXTI 14 configuration
#define SYSCFG_EXTICR4_EXTI15 ((u16)0xF000) ///< EXTI 15 configuration
#define SYSCFG_EXTICR4_EXTI12_PA ((u16)0x0000) ///< PA[12] pin for EXTI12
#define SYSCFG_EXTICR4_EXTI12_PB ((u16)0x0001) ///< PB[12] pin for EXTI12
#define SYSCFG_EXTICR4_EXTI12_PC ((u16)0x0002) ///< PC[12] pin for EXTI12
#define SYSCFG_EXTICR4_EXTI12_PD ((u16)0x0003) ///< PD[12] pin for EXTI12
#define SYSCFG_EXTICR4_EXTI13_PA ((u16)0x0000) ///< PA[13] pin for EXTI13
#define SYSCFG_EXTICR4_EXTI13_PB ((u16)0x0010) ///< PB[13] pin for EXTI13
#define SYSCFG_EXTICR4_EXTI13_PC ((u16)0x0020) ///< PC[13] pin for EXTI13
#define SYSCFG_EXTICR4_EXTI13_PD ((u16)0x0030) ///< PD[13] pin for EXTI13
#define SYSCFG_EXTICR4_EXTI14_PA ((u16)0x0000) ///< PA[14] pin for EXTI14
#define SYSCFG_EXTICR4_EXTI14_PB ((u16)0x0100) ///< PB[14] pin for EXTI14
#define SYSCFG_EXTICR4_EXTI14_PC ((u16)0x0200) ///< PC[14] pin for EXTI14
#define SYSCFG_EXTICR4_EXTI14_PD ((u16)0x0300) ///< PD[14] pin for EXTI14
#define SYSCFG_EXTICR4_EXTI15_PA ((u16)0x0000) ///< PA[15] pin for EXTI15
#define SYSCFG_EXTICR4_EXTI15_PB ((u16)0x1000) ///< PB[15] pin for EXTI15
#define SYSCFG_EXTICR4_EXTI15_PC ((u16)0x2000) ///< PC[15] pin for EXTI15
#define SYSCFG_EXTICR4_EXTI15_PD ((u16)0x3000) ///< PD[15] pin for EXTI15
#define SYSCFG_CFGR2_I2C1_MODE_SEL_Pos (16)
#define SYSCFG_CFGR2_I2C1_MODE_SEL (0x01U << SYSCFG_CFGR2_I2C1_MODE_SEL_Pos) ///< I2C1 Enable PushPull mode
#define SYSCFG_CFGR2_I2C2_MODE_SEL_Pos (17)
#define SYSCFG_CFGR2_I2C2_MODE_SEL (0x01U << SYSCFG_CFGR2_I2C2_MODE_SEL_Pos) ///< I2C2 Enable PushPull mode
#define SYSCFG_CFGR2_MII_RMII_MODE_SEL_Pos (20)
#define SYSCFG_CFGR2_MII_RMII_MODE_SEL (0x01U << SYSCFG_CFGR2_MII_RMII_MODE_SEL_Pos) ///< MII_RMII mode
#define SYSCFG_CFGR2_MAC_SPEED_SEL_Pos (21)
#define SYSCFG_CFGR2_MAC_SPEED_SEL (0x01U << SYSCFG_CFGR2_MAC_SPEED_SEL_Pos) ///< MAC_SPEED mode
#define SYSCFG_PDETCSR_PVDE_Pos (0)
#define SYSCFG_PDETCSR_PVDE (0x01U << SYSCFG_PDETCSR_PVDE_Pos) ///< Power Voltage Detector Enable
#define SYSCFG_PDETCSR_PLS_Pos (1)
#define SYSCFG_PDETCSR_PLS (0x0FU << SYSCFG_PDETCSR_PLS_Pos)
#define SYSCFG_PDETCSR_PLS_1V7 (0x00U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 1.7V
#define SYSCFG_PDETCSR_PLS_2V0 (0x01U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 2.0V
#define SYSCFG_PDETCSR_PLS_2V3 (0x02U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 2.3V
#define SYSCFG_PDETCSR_PLS_2V6 (0x03U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 2.6V
#define SYSCFG_PDETCSR_PLS_2V9 (0x04U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 2.9V
#define SYSCFG_PDETCSR_PLS_3V2 (0x05U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 3.2V
#define SYSCFG_PDETCSR_PLS_3V5 (0x06U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 3.5V
#define SYSCFG_PDETCSR_PLS_3V8 (0x07U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 3.8V
#define SYSCFG_PDETCSR_PLS_4V1 (0x08U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 4.1V
#define SYSCFG_PDETCSR_PLS_4V4 (0x09U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 4.4V
#define SYSCFG_PDETCSR_PLS_4V7 (0x0AU << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 4.7V
// #define PWR_CR_PLS_Pos SYSCFG_PDETCSR_PLS_Pos
// #define PWR_CR_PLS SYSCFG_PDETCSR_PLS
// #define PWR_CR_PLS_1V8 SYSCFG_PDETCSR_PLS_1V7 ///< PVD level 1.8V
// #define PWR_CR_PLS_2V1 SYSCFG_PDETCSR_PLS_2V0 ///< PVD level 2.1V
// #define PWR_CR_PLS_2V4 SYSCFG_PDETCSR_PLS_2V3 ///< PVD level 2.4V
// #define PWR_CR_PLS_2V7 SYSCFG_PDETCSR_PLS_2V6 ///< PVD level 2.7V
// #define PWR_CR_PLS_3V0 SYSCFG_PDETCSR_PLS_2V9 ///< PVD level 3.0V
// #define PWR_CR_PLS_3V3 SYSCFG_PDETCSR_PLS_3V2 ///< PVD level 3.3V
// #define PWR_CR_PLS_3V6 SYSCFG_PDETCSR_PLS_3V5 ///< PVD level 3.6V
// #define PWR_CR_PLS_3V9 SYSCFG_PDETCSR_PLS_3V8 ///< PVD level 3.9V
// #define PWR_CR_PLS_4V2 SYSCFG_PDETCSR_PLS_4V1 ///< PVD level 4.2V
// #define PWR_CR_PLS_4V5 SYSCFG_PDETCSR_PLS_4V4 ///< PVD level 4.5V
// #define PWR_CR_PLS_4V8 SYSCFG_PDETCSR_PLS_4V7 ///< PVD level 4.8V
#define SYSCFG_PDETCSR_PVDO_Pos (5)
#define SYSCFG_PDETCSR_PVDO (0x01U << SYSCFG_PDETCSR_PVDO_Pos) ///< PVD Output
// #define PWR_CSR_PVDO_Pos SYSCFG_PDETCSR_PVDO_Pos
// #define PWR_CSR_PVDO SYSCFG_PDETCSR_PVDO ///< PVD Output
#define SYSCFG_PDETCSR_VDTO_Pos (6)
#define SYSCFG_PDETCSR_VDTO (0x01U << SYSCFG_PDETCSR_VDTO_Pos) ///< VDT Output Enable
#define SYSCFG_PDETCSR_VDTE_Pos (8)
#define SYSCFG_PDETCSR_VDTE (0x01U << SYSCFG_PDETCSR_VDTE_Pos) ///< VDT Output
#define SYSCFG_PDETCSR_VDTLS_Pos (9)
#define SYSCFG_PDETCSR_VDTLS (0x0FU << SYSCFG_PDETCSR_VDTLS_Pos)
#define SYSCFG_PDETCSR_VDTLS_0V9 (0x00U << SYSCFG_PDETCSR_VDTLS_Pos) ///< VDT level 0.9V
#define SYSCFG_PDETCSR_VDTLS_1V0 (0x01U << SYSCFG_PDETCSR_VDTLS_Pos) ///< VDT level 1.0V
#define SYSCFG_PDETCSR_VDTLS_1V1 (0x02U << SYSCFG_PDETCSR_VDTLS_Pos) ///< VDT level 1.1V
#define SYSCFG_PDETCSR_VDTLS_1V2 (0x03U << SYSCFG_PDETCSR_VDTLS_Pos) ///< VDT level 1.2V
#define SYSCFG_PDETCSR_VBATDIV3EN_Pos (11)
#define SYSCFG_PDETCSR_VBATDIV3EN (0x01U << SYSCFG_PDETCSR_VBATDIV3EN_Pos) ///< VBATDIV3 Enable
#define SYSCFG_VOSDLY_CNT_Pos (0)
#define SYSCFG_VOSDLY_CNT (0x03FFU << SYSCFG_VOSDLY_CNT_Pos) ///< SYSCFG VOSDLY CNT
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_tim.h
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_tim.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_TIM_H
#define __REG_TIM_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) ///< Base Address: 0x40012C00
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) ///< Base Address: 0x40000000
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) ///< Base Address: 0x40000400
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) ///< Base Address: 0x40000800
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) ///< Base Address: 0x40000C00
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) ///< Base Address: 0x40001000
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) ///< Base Address: 0x40001400
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) ///< Base Address: 0x40013400
////////////////////////////////////////////////////////////////////////////////
/// @brief Timer Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 CR1; ///< TIM control register 1, offset: 0x00
__IO u32 CR2; ///< TIM control register 2, offset: 0x04
__IO u32 SMCR; ///< TIM slave Mode Control register, offset: 0x08
__IO u32 DIER; ///< TIM DMA/interrupt enable register, offset: 0x0C
__IO u32 SR; ///< TIM status register, offset: 0x10
__IO u32 EGR; ///< TIM event generation register, offset: 0x14
__IO u32 CCMR1; ///< TIM capture/compare mode register 1, offset: 0x18
__IO u32 CCMR2; ///< TIM capture/compare mode register 2, offset: 0x1C
__IO u32 CCER; ///< TIM capture/compare enable register, offset: 0x20
__IO u32 CNT; ///< TIM counter register, offset: 0x24
__IO u32 PSC; ///< TIM prescaler register, offset: 0x28
__IO u32 ARR; ///< TIM auto-reload register, offset: 0x2C
__IO u32 RCR; ///< TIM repetition counter register, offset: 0x30
__IO u32 CCR1; ///< TIM capture/compare register 1, offset: 0x34
__IO u32 CCR2; ///< TIM capture/compare register 2, offset: 0x38
__IO u32 CCR3; ///< TIM capture/compare register 3, offset: 0x3C
__IO u32 CCR4; ///< TIM capture/compare register 4, offset: 0x40
__IO u32 BDTR; ///< TIM break and dead-time register, offset: 0x44
__IO u32 DCR; ///< TIM DMA control register, offset: 0x48
__IO u32 DMAR; ///< TIM DMA address for full transfer register, offset: 0x4C
__IO u32 OR; ///< Option register, offset: 0x50
__IO u32 CCMR3; ///< TIM capture/compare mode register 3, offset: 0x54
__IO u32 CCR5; ///< TIM capture/compare register 5, offset: 0x58
__IO u32 PDER; ///< PWM Shift repeat enable register, offset: 0x5C
__IO u32 CCR1FALL; ///< PWM shift count CCR1 register, offset: 0x60
__IO u32 CCR2FALL; ///< PWM shift count CCR2 register, offset: 0x64
__IO u32 CCR3FALL; ///< PWM shift count CCR3 register, offset: 0x68
__IO u32 CCR4FALL; ///< PWM shift count CCR4 register, offset: 0x6c
__IO u32 CCR5FALL; ///< PWM shift count CCR5 register, offset: 0x70
} TIM_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM1 ((TIM_TypeDef*) TIM1_BASE)
#define TIM2 ((TIM_TypeDef*) TIM2_BASE)
#define TIM3 ((TIM_TypeDef*) TIM3_BASE)
#define TIM4 ((TIM_TypeDef*) TIM4_BASE)
#define TIM5 ((TIM_TypeDef*) TIM5_BASE)
#define TIM6 ((TIM_TypeDef*) TIM6_BASE)
#define TIM7 ((TIM_TypeDef*) TIM7_BASE)
#define TIM8 ((TIM_TypeDef*) TIM8_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_CR1 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_CR1_CEN_Pos (0)
#define TIM_CR1_CEN (0x01U << TIM_CR1_CEN_Pos) ///< Counter enable
#define TIM_CR1_UDIS_Pos (1)
#define TIM_CR1_UDIS (0x01U << TIM_CR1_UDIS_Pos) ///< Update disable
#define TIM_CR1_URS_Pos (2)
#define TIM_CR1_URS (0x01U << TIM_CR1_URS_Pos) ///< Update request source
#define TIM_CR1_OPM_Pos (3)
#define TIM_CR1_OPM (0x01U << TIM_CR1_OPM_Pos) ///< One pulse mode
#define TIM_CR1_DIR_Pos (4)
#define TIM_CR1_DIR (0x01U << TIM_CR1_DIR_Pos) ///< Direction
#define TIM_CR1_CMS_Pos (5)
#define TIM_CR1_CMS (0x03U << TIM_CR1_CMS_Pos) ///< CMS[1:0] bits (Center-aligned mode selection)
#define TIM_CR1_CMS_EDGEALIGNED (0x00U << TIM_CR1_CMS_Pos) ///< Edge-aligned mode
#define TIM_CR1_CMS_CENTERALIGNED1 (0x01U << TIM_CR1_CMS_Pos) ///< Center-aligned mode 1
#define TIM_CR1_CMS_CENTERALIGNED2 (0x02U << TIM_CR1_CMS_Pos) ///< Center-aligned mode 2
#define TIM_CR1_CMS_CENTERALIGNED3 (0x03U << TIM_CR1_CMS_Pos) ///< Center-aligned mode 3
#define TIM_CR1_ARPEN_Pos (7)
#define TIM_CR1_ARPEN (0x01U << TIM_CR1_ARPEN_Pos) ///< Auto-reload preload enable
#define TIM_CR1_CKD_Pos (8)
#define TIM_CR1_CKD (0x03U << TIM_CR1_CKD_Pos) ///< CKD[1:0] bits (clock division)
#define TIM_CR1_CKD_DIV1 (0x00U << TIM_CR1_CKD_Pos) ///< Divided by 1
#define TIM_CR1_CKD_DIV2 (0x01U << TIM_CR1_CKD_Pos) ///< Divided by 2
#define TIM_CR1_CKD_DIV4 (0x02U << TIM_CR1_CKD_Pos) ///< Divided by 4
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_CR2 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_CR2_CCPC_Pos (0)
#define TIM_CR2_CCPC (0x01U << TIM_CR2_CCPC_Pos) ///< Capture/Compare Preloaded Control
#define TIM_CR2_CCUS_Pos (2)
#define TIM_CR2_CCUS (0x01U << TIM_CR2_CCUS_Pos) ///< Capture/Compare Control Update Selection
#define TIM_CR2_CCDS_Pos (3)
#define TIM_CR2_CCDS (0x01U << TIM_CR2_CCDS_Pos) ///< Capture/Compare DMA Selection
#define TIM_CR2_MMS_Pos (4)
#define TIM_CR2_MMS (0x07U << TIM_CR2_MMS_Pos) ///< MMS[2:0] bits (Master Mode Selection)
#define TIM_CR2_MMS_RESET (0x00U << TIM_CR2_MMS_Pos) ///< Master Mode Select: Reset
#define TIM_CR2_MMS_ENABLE (0x01U << TIM_CR2_MMS_Pos) ///< Master Mode Select: Enable
#define TIM_CR2_MMS_UPDATE (0x02U << TIM_CR2_MMS_Pos) ///< Master Mode Select: Update
#define TIM_CR2_MMS_OC1 (0x03U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC1
#define TIM_CR2_MMS_OC1REF (0x04U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC1Ref
#define TIM_CR2_MMS_OC2REF (0x05U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC2Ref
#define TIM_CR2_MMS_OC3REF (0x06U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC3Ref
#define TIM_CR2_MMS_OC4REF (0x07U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC4Ref
#define TIM_CR2_TI1S_Pos (7)
#define TIM_CR2_TI1S (0x01U << TIM_CR2_TI1S_Pos) ///< TI1 Selection
#define TIM_CR2_OIS1_Pos (8)
#define TIM_CR2_OIS1 (0x01U << TIM_CR2_OIS1_Pos) ///< Output Idle state 1 (OC1 output)
#define TIM_CR2_OIS1N_Pos (9)
#define TIM_CR2_OIS1N (0x01U << TIM_CR2_OIS1N_Pos) ///< Output Idle state 1 (OC1N output)
#define TIM_CR2_OIS2_Pos (10)
#define TIM_CR2_OIS2 (0x01U << TIM_CR2_OIS2_Pos) ///< Output Idle state 2 (OC2 output)
#define TIM_CR2_OIS2N_Pos (11)
#define TIM_CR2_OIS2N (0x01U << TIM_CR2_OIS2N_Pos) ///< Output Idle state 2 (OC2N output)
#define TIM_CR2_OIS3_Pos (12)
#define TIM_CR2_OIS3 (0x01U << TIM_CR2_OIS3_Pos) ///< Output Idle state 3 (OC3 output)
#define TIM_CR2_OIS3N_Pos (13)
#define TIM_CR2_OIS3N (0x01U << TIM_CR2_OIS3N_Pos) ///< Output Idle state 3 (OC3N output)
#define TIM_CR2_OIS4_Pos (14)
#define TIM_CR2_OIS4 (0x01U << TIM_CR2_OIS4_Pos) ///< Output Idle state 4 (OC4 output)
#define TIM_CR2_OIS5_Pos (16)
#define TIM_CR2_OIS5 (0x01U << TIM_CR2_OIS5_Pos) ///< Output Idle state 5 (OC5 output)
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_SMCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_SMCR_SMS_Pos (0)
#define TIM_SMCR_SMS (0x07U << TIM_SMCR_SMS_Pos) ///< SMS[2:0] bits (Slave mode selection)
#define TIM_SMCR_SMS_OFF (0x00U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: OFF
#define TIM_SMCR_SMS_ENCODER1 (0x01U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Encoder1
#define TIM_SMCR_SMS_ENCODER2 (0x02U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Encoder2
#define TIM_SMCR_SMS_ENCODER3 (0x03U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Encoder3
#define TIM_SMCR_SMS_RESET (0x04U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Reset
#define TIM_SMCR_SMS_GATED (0x05U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Gated
#define TIM_SMCR_SMS_TRIGGER (0x06U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Trigger
#define TIM_SMCR_SMS_EXTERNAL1 (0x07U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: External1
#define TIM_SMCR_OCCS_Pos (3)
#define TIM_SMCR_OCCS (0x01U << TIM_SMCR_OCCS_Pos) ///< Output compare clear selection
#define TIM_SMCR_TS_Pos (4)
#define TIM_SMCR_TS (0x07U << TIM_SMCR_TS_Pos) ///< TS[2:0] bits (Trigger selection)
#define TIM_SMCR_TS_ITR0 (0x00U << TIM_SMCR_TS_Pos) ///< Internal Trigger 0 (ITR0)
#define TIM_SMCR_TS_ITR1 (0x01U << TIM_SMCR_TS_Pos) ///< Internal Trigger 1 (ITR1)
#define TIM_SMCR_TS_ITR2 (0x02U << TIM_SMCR_TS_Pos) ///< Internal Trigger 2 (ITR2)
#define TIM_SMCR_TS_ITR3 (0x03U << TIM_SMCR_TS_Pos) ///< Internal Trigger 3 (ITR3)
#define TIM_SMCR_TS_TI1F_ED (0x04U << TIM_SMCR_TS_Pos) ///< TI1 Edge Detector (TI1F_ED)
#define TIM_SMCR_TS_TI1FP1 (0x05U << TIM_SMCR_TS_Pos) ///< Filtered Timer Input 1 (TI1FP1)
#define TIM_SMCR_TS_TI2FP2 (0x06U << TIM_SMCR_TS_Pos) ///< Filtered Timer Input 2 (TI2FP2)
#define TIM_SMCR_TS_ETRF (0x07U << TIM_SMCR_TS_Pos) ///< External Trigger input (ETRF)
#define TIM_SMCR_MSM_Pos (7)
#define TIM_SMCR_MSM (0x01U << TIM_SMCR_MSM_Pos) ///< Master/slave mode
#define TIM_SMCR_ETF_Pos (8)
#define TIM_SMCR_ETF (0x0FU << TIM_SMCR_ETF_Pos) ///< ETF[3:0] bits (External trigger filter)
#define TIM_SMCR_ETF_0 (0x01U << TIM_SMCR_ETF_Pos) ///< Bit 0
#define TIM_SMCR_ETF_1 (0x02U << TIM_SMCR_ETF_Pos) ///< Bit 1
#define TIM_SMCR_ETF_2 (0x04U << TIM_SMCR_ETF_Pos) ///< Bit 2
#define TIM_SMCR_ETF_3 (0x08U << TIM_SMCR_ETF_Pos) ///< Bit 3
#define TIM_SMCR_ETPS_Pos (12)
#define TIM_SMCR_ETPS (0x03U << TIM_SMCR_ETPS_Pos) ///< ETPS[1:0] bits (External trigger prescaler)
#define TIM_SMCR_ETPS_OFF (0x00U << TIM_SMCR_ETPS_Pos) ///< Prescaler OFF
#define TIM_SMCR_ETPS_DIV2 (0x01U << TIM_SMCR_ETPS_Pos) ///< ETRP frequency divided by 2
#define TIM_SMCR_ETPS_DIV4 (0x02U << TIM_SMCR_ETPS_Pos) ///< ETRP frequency divided by 4
#define TIM_SMCR_ETPS_DIV8 (0x03U << TIM_SMCR_ETPS_Pos) ///< ETRP frequency divided by 8
#define TIM_SMCR_ECEN_Pos (14)
#define TIM_SMCR_ECEN (0x01U << TIM_SMCR_ECEN_Pos) ///< External clock enable
#define TIM_SMCR_ETP_Pos (15)
#define TIM_SMCR_ETP (0x01U << TIM_SMCR_ETP_Pos) ///< External trigger polarity
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_DIER Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_DIER_UI_Pos (0)
#define TIM_DIER_UI (0x01U << TIM_DIER_UI_Pos) ///< Update interrupt enable
#define TIM_DIER_CC1I_Pos (1)
#define TIM_DIER_CC1I (0x01U << TIM_DIER_CC1I_Pos) ///< Capture/Compare 1 interrupt enable
#define TIM_DIER_CC2I_Pos (2)
#define TIM_DIER_CC2I (0x01U << TIM_DIER_CC2I_Pos) ///< Capture/Compare 2 interrupt enable
#define TIM_DIER_CC3I_Pos (3)
#define TIM_DIER_CC3I (0x01U << TIM_DIER_CC3I_Pos) ///< Capture/Compare 3 interrupt enable
#define TIM_DIER_CC4I_Pos (4)
#define TIM_DIER_CC4I (0x01U << TIM_DIER_CC4I_Pos) ///< Capture/Compare 4 interrupt enable
#define TIM_DIER_COMI_Pos (5)
#define TIM_DIER_COMI (0x01U << TIM_DIER_COMI_Pos) ///< COM interrupt enable
#define TIM_DIER_TI_Pos (6)
#define TIM_DIER_TI (0x01U << TIM_DIER_TI_Pos) ///< Trigger interrupt enable
#define TIM_DIER_BI_Pos (7)
#define TIM_DIER_BI (0x01U << TIM_DIER_BI_Pos) ///< Break interrupt enable
#define TIM_DIER_UD_Pos (8)
#define TIM_DIER_UD (0x01U << TIM_DIER_UD_Pos) ///< Update DMA request enable
#define TIM_DIER_CC1D_Pos (9)
#define TIM_DIER_CC1D (0x01U << TIM_DIER_CC1D_Pos) ///< Capture/Compare 1 DMA request enable
#define TIM_DIER_CC2D_Pos (10)
#define TIM_DIER_CC2D (0x01U << TIM_DIER_CC2D_Pos) ///< Capture/Compare 2 DMA request enable
#define TIM_DIER_CC3D_Pos (11)
#define TIM_DIER_CC3D (0x01U << TIM_DIER_CC3D_Pos) ///< Capture/Compare 3 DMA request enable
#define TIM_DIER_CC4D_Pos (12)
#define TIM_DIER_CC4D (0x01U << TIM_DIER_CC4D_Pos) ///< Capture/Compare 4 DMA request enable
#define TIM_DIER_COMD_Pos (13)
#define TIM_DIER_COMD (0x01U << TIM_DIER_COMD_Pos) ///< COM DMA request enable
#define TIM_DIER_TD_Pos (14)
#define TIM_DIER_TD (0x01U << TIM_DIER_TD_Pos) ///< Trigger DMA request enable
#define TIM_DIER_CC5I_Pos (16)
#define TIM_DIER_CC5I (0x01U << TIM_DIER_CC5I_Pos) ///< Capture/Compare 5 interrupt enable
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_SR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_SR_UI_Pos (0)
#define TIM_SR_UI (0x01U << TIM_SR_UI_Pos) ///< Update interrupt Flag
#define TIM_SR_CC1I_Pos (1)
#define TIM_SR_CC1I (0x01U << TIM_SR_CC1I_Pos) ///< Capture/Compare 1 interrupt Flag
#define TIM_SR_CC2I_Pos (2)
#define TIM_SR_CC2I (0x01U << TIM_SR_CC2I_Pos) ///< Capture/Compare 2 interrupt Flag
#define TIM_SR_CC3I_Pos (3)
#define TIM_SR_CC3I (0x01U << TIM_SR_CC3I_Pos) ///< Capture/Compare 3 interrupt Flag
#define TIM_SR_CC4I_Pos (4)
#define TIM_SR_CC4I (0x01U << TIM_SR_CC4I_Pos) ///< Capture/Compare 4 interrupt Flag
#define TIM_SR_COMI_Pos (5)
#define TIM_SR_COMI (0x01U << TIM_SR_COMI_Pos) ///< COM interrupt Flag
#define TIM_SR_TI_Pos (6)
#define TIM_SR_TI (0x01U << TIM_SR_TI_Pos) ///< Trigger interrupt Flag
#define TIM_SR_BI_Pos (7)
#define TIM_SR_BI (0x01U << TIM_SR_BI_Pos) ///< Break interrupt Flag
#define TIM_SR_CC1O_Pos (9)
#define TIM_SR_CC1O (0x01U << TIM_SR_CC1O_Pos) ///< Capture/Compare 1 Overcapture Flag
#define TIM_SR_CC2O_Pos (10)
#define TIM_SR_CC2O (0x01U << TIM_SR_CC2O_Pos) ///< Capture/Compare 2 Overcapture Flag
#define TIM_SR_CC3O_Pos (11)
#define TIM_SR_CC3O (0x01U << TIM_SR_CC3O_Pos) ///< Capture/Compare 3 Overcapture Flag
#define TIM_SR_CC4O_Pos (12)
#define TIM_SR_CC4O (0x01U << TIM_SR_CC4O_Pos) ///< Capture/Compare 4 Overcapture Flag
#define TIM_SR_CC5I_Pos (16)
#define TIM_SR_CC5I (0x01U << TIM_SR_CC5I_Pos) ///< Capture/Compare 5 interrupt Flag
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_EGR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_EGR_UG_Pos (0)
#define TIM_EGR_UG (0x01U << TIM_EGR_UG_Pos) ///< Update Generation
#define TIM_EGR_CC1G_Pos (1)
#define TIM_EGR_CC1G (0x01U << TIM_EGR_CC1G_Pos) ///< Capture/Compare 1 Generation
#define TIM_EGR_CC2G_Pos (2)
#define TIM_EGR_CC2G (0x01U << TIM_EGR_CC2G_Pos) ///< Capture/Compare 2 Generation
#define TIM_EGR_CC3G_Pos (3)
#define TIM_EGR_CC3G (0x01U << TIM_EGR_CC3G_Pos) ///< Capture/Compare 3 Generation
#define TIM_EGR_CC4G_Pos (4)
#define TIM_EGR_CC4G (0x01U << TIM_EGR_CC4G_Pos) ///< Capture/Compare 4 Generation
#define TIM_EGR_COMG_Pos (5)
#define TIM_EGR_COMG (0x01U << TIM_EGR_COMG_Pos) ///< Capture/Compare Control Update Generation
#define TIM_EGR_TG_Pos (6)
#define TIM_EGR_TG (0x01U << TIM_EGR_TG_Pos) ///< Trigger Generation
#define TIM_EGR_BG_Pos (7)
#define TIM_EGR_BG (0x01U << TIM_EGR_BG_Pos) ///< Break Generation
#define TIM_EGR_CC5G_Pos (16)
#define TIM_EGR_CC5G (0x01U << TIM_EGR_CC5G_Pos) ///< Capture/Compare 5 Generation
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_CCMR1 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_CCMR1_CC1S_Pos (0)
#define TIM_CCMR1_CC1S (0x03U << TIM_CCMR1_CC1S_Pos) ///< CC1S[1:0] bits (Capture/Compare 1 Selection)
#define TIM_CCMR1_CC1S_OC (0x00U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as output
#define TIM_CCMR1_CC1S_DIRECTTI (0x01U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as input, IC1 is mapped on TI1
#define TIM_CCMR1_CC1S_INDIRECTTI (0x02U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as input, IC1 is mapped on TI2
#define TIM_CCMR1_CC1S_TRC (0x03U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as input, IC1 is mapped on TRC
#define TIM_CCMR1_OC1FEN_Pos (2)
#define TIM_CCMR1_OC1FEN (0x01U << TIM_CCMR1_OC1FEN_Pos) ///< Output Compare 1 Fast enable
#define TIM_CCMR1_OC1PEN_Pos (3)
#define TIM_CCMR1_OC1PEN (0x01U << TIM_CCMR1_OC1PEN_Pos) ///< Output Compare 1 Preload enable
#define TIM_CCMR1_OC1M_Pos (4)
#define TIM_CCMR1_OC1M (0x07U << TIM_CCMR1_OC1M_Pos) ///< OC1M[2:0] bits (Output Compare 1 Mode)
#define TIM_CCMR1_OC1M_TIMING (0x00U << TIM_CCMR1_OC1M_Pos) ///< Timing
#define TIM_CCMR1_OC1M_ACTIVE (0x01U << TIM_CCMR1_OC1M_Pos) ///< Active
#define TIM_CCMR1_OC1M_INACTIVE (0x02U << TIM_CCMR1_OC1M_Pos) ///< Inactive
#define TIM_CCMR1_OC1M_TOGGLE (0x03U << TIM_CCMR1_OC1M_Pos) ///< Toggle
#define TIM_CCMR1_OC1M_FORCEINACTIVE (0x04U << TIM_CCMR1_OC1M_Pos) ///< Forceinactive
#define TIM_CCMR1_OC1M_FORCEACTIVE (0x05U << TIM_CCMR1_OC1M_Pos) ///< Forceactive
#define TIM_CCMR1_OC1M_PWM1 (0x06U << TIM_CCMR1_OC1M_Pos) ///< PWM1
#define TIM_CCMR1_OC1M_PWM2 (0x07U << TIM_CCMR1_OC1M_Pos) ///< PWM2
#define TIM_CCMR1_OC1CEN_Pos (7)
#define TIM_CCMR1_OC1CEN (0x01U << TIM_CCMR1_OC1CEN_Pos) ///< Output Compare 1Clear Enable
#define TIM_CCMR1_CC2S_Pos (8)
#define TIM_CCMR1_CC2S (0x03U << TIM_CCMR1_CC2S_Pos) ///< CC2S[1:0] bits (Capture/Compare 2 Selection)
#define TIM_CCMR1_CC2S_OC (0x00U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as output
#define TIM_CCMR1_CC2S_DIRECTTI (0x01U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as input, IC2 is mapped on TI2
#define TIM_CCMR1_CC2S_INDIRECTTI (0x02U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as input, IC2 is mapped on TI1
#define TIM_CCMR1_CC2S_TRC (0x03U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as input, IC2 is mapped on TRC
#define TIM_CCMR1_OC2FEN_Pos (10)
#define TIM_CCMR1_OC2FEN (0x01U << TIM_CCMR1_OC2FEN_Pos) ///< Output Compare 2 Fast enable
#define TIM_CCMR1_OC2PEN_Pos (11)
#define TIM_CCMR1_OC2PEN (0x01U << TIM_CCMR1_OC2PEN_Pos) ///< Output Compare 2 Preload enable
#define TIM_CCMR1_OC2M_Pos (12)
#define TIM_CCMR1_OC2M (0x07U << TIM_CCMR1_OC2M_Pos) ///< OC2M[2:0] bits (Output Compare 2 Mode)
#define TIM_CCMR1_OC2M_TIMING (0x00U << TIM_CCMR1_OC2M_Pos) ///< Timing
#define TIM_CCMR1_OC2M_ACTIVE (0x01U << TIM_CCMR1_OC2M_Pos) ///< Active
#define TIM_CCMR1_OC2M_INACTIVE (0x02U << TIM_CCMR1_OC2M_Pos) ///< Inactive
#define TIM_CCMR1_OC2M_TOGGLE (0x03U << TIM_CCMR1_OC2M_Pos) ///< Toggle
#define TIM_CCMR1_OC2M_FORCEINACTIVE (0x04U << TIM_CCMR1_OC2M_Pos) ///< Forceinactive
#define TIM_CCMR1_OC2M_FORCEACTIVE (0x05U << TIM_CCMR1_OC2M_Pos) ///< Forceactive
#define TIM_CCMR1_OC2M_PWM1 (0x06U << TIM_CCMR1_OC2M_Pos) ///< PWM1
#define TIM_CCMR1_OC2M_PWM2 (0x07U << TIM_CCMR1_OC2M_Pos) ///< PWM2
#define TIM_CCMR1_OC2CEN_Pos (15)
#define TIM_CCMR1_OC2CEN (0x01U << TIM_CCMR1_OC2CEN_Pos) ///< Output Compare 2 Clear Enable
#define TIM_CCMR1_IC1PSC_Pos (2)
#define TIM_CCMR1_IC1PSC (0x03U << TIM_CCMR1_IC1PSC_Pos) ///< IC1PSC[1:0] bits (Input Capture 1 Prescaler)
#define TIM_CCMR1_IC1PSC_DIV1 (0x00U << TIM_CCMR1_IC1PSC_Pos) ///< No Prescaler
#define TIM_CCMR1_IC1PSC_DIV2 (0x01U << TIM_CCMR1_IC1PSC_Pos) ///< Capture is done once every 2 events
#define TIM_CCMR1_IC1PSC_DIV4 (0x02U << TIM_CCMR1_IC1PSC_Pos) ///< Capture is done once every 4 events
#define TIM_CCMR1_IC1PSC_DIV8 (0x03U << TIM_CCMR1_IC1PSC_Pos) ///< Capture is done once every 8 events
#define TIM_CCMR1_IC1F_Pos (4)
#define TIM_CCMR1_IC1F (0x0FU << TIM_CCMR1_IC1F_Pos) ///< IC1F[3:0] bits (Input Capture 1 Filter)
#define TIM_CCMR1_IC1F_0 (0x01U << TIM_CCMR1_IC1F_Pos) ///< Bit 0
#define TIM_CCMR1_IC1F_1 (0x02U << TIM_CCMR1_IC1F_Pos) ///< Bit 1
#define TIM_CCMR1_IC1F_2 (0x04U << TIM_CCMR1_IC1F_Pos) ///< Bit 2
#define TIM_CCMR1_IC1F_3 (0x08U << TIM_CCMR1_IC1F_Pos) ///< Bit 3
#define TIM_CCMR1_IC2PSC_Pos (10)
#define TIM_CCMR1_IC2PSC (0x03U << TIM_CCMR1_IC2PSC_Pos) ///< IC2PSC[1:0] bits (Input Capture 2 Prescaler)
#define TIM_CCMR1_IC2PSC_DIV1 (0x00U << TIM_CCMR1_IC2PSC_Pos) ///< No Prescaler
#define TIM_CCMR1_IC2PSC_DIV2 (0x01U << TIM_CCMR1_IC2PSC_Pos) ///< Capture is done once every 2 events
#define TIM_CCMR1_IC2PSC_DIV4 (0x02U << TIM_CCMR1_IC2PSC_Pos) ///< Capture is done once every 4 events
#define TIM_CCMR1_IC2PSC_DIV8 (0x03U << TIM_CCMR1_IC2PSC_Pos) ///< Capture is done once every 8 events
#define TIM_CCMR1_IC2F_Pos (12)
#define TIM_CCMR1_IC2F (0x0FU << TIM_CCMR1_IC2F_Pos) ///< IC2F[3:0] bits (Input Capture 2 Filter)
#define TIM_CCMR1_IC2F_0 (0x01U << TIM_CCMR1_IC2F_Pos) ///< Bit 0
#define TIM_CCMR1_IC2F_1 (0x02U << TIM_CCMR1_IC2F_Pos) ///< Bit 1
#define TIM_CCMR1_IC2F_2 (0x04U << TIM_CCMR1_IC2F_Pos) ///< Bit 2
#define TIM_CCMR1_IC2F_3 (0x08U << TIM_CCMR1_IC2F_Pos) ///< Bit 3
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_CCMR2 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_CCMR2_CC3S_Pos (0)
#define TIM_CCMR2_CC3S (0x03U << TIM_CCMR2_CC3S_Pos) ///< CC3S[1:0] bits (Capture/Compare 3 Selection)
#define TIM_CCMR2_CC3S_OC (0x00U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as output
#define TIM_CCMR2_CC3S_DIRECTTI (0x01U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as input, IC3 is mapped on TI3
#define TIM_CCMR2_CC3S_INDIRECTTI (0x02U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as input, IC3 is mapped on TI4
#define TIM_CCMR2_CC3S_TRC (0x03U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as input, IC3 is mapped on TRC
#define TIM_CCMR2_OC3FEN_Pos (2)
#define TIM_CCMR2_OC3FEN (0x01U << TIM_CCMR2_OC3FEN_Pos) ///< Output Compare 3 Fast enable
#define TIM_CCMR2_IC3PSC_Pos (2)
#define TIM_CCMR2_IC3PSC (0x03U << TIM_CCMR2_IC3PSC_Pos) ///< IC3PSC[1:0] bits (Input Capture 3 Prescaler)
#define TIM_CCMR2_IC3PSC_DIV1 (0x00U << TIM_CCMR2_IC3PSC_Pos) ///< No Prescaler
#define TIM_CCMR2_IC3PSC_DIV2 (0x01U << TIM_CCMR2_IC3PSC_Pos) ///< Capture is done once every 2 events
#define TIM_CCMR2_IC3PSC_DIV4 (0x02U << TIM_CCMR2_IC3PSC_Pos) ///< Capture is done once every 4 events
#define TIM_CCMR2_IC3PSC_DIV8 (0x03U << TIM_CCMR2_IC3PSC_Pos) ///< Capture is done once every 8 events
#define TIM_CCMR2_OC3PEN_Pos (3)
#define TIM_CCMR2_OC3PEN (0x01U << TIM_CCMR2_OC3PEN_Pos) ///< Output Compare 3 Preload enable
#define TIM_CCMR2_OC3M_Pos (4)
#define TIM_CCMR2_OC3M (0x07U << TIM_CCMR2_OC3M_Pos) ///< OC3M[2:0] bits (Output Compare 3 Mode)
#define TIM_CCMR2_OC3M_TIMING (0x00U << TIM_CCMR2_OC3M_Pos) ///< Timing
#define TIM_CCMR2_OC3M_ACTIVE (0x01U << TIM_CCMR2_OC3M_Pos) ///< Active
#define TIM_CCMR2_OC3M_INACTIVE (0x02U << TIM_CCMR2_OC3M_Pos) ///< Inactive
#define TIM_CCMR2_OC3M_TOGGLE (0x03U << TIM_CCMR2_OC3M_Pos) ///< Toggle
#define TIM_CCMR2_OC3M_FORCEINACTIVE (0x04U << TIM_CCMR2_OC3M_Pos) ///< Forceinactive
#define TIM_CCMR2_OC3M_FORCEACTIVE (0x05U << TIM_CCMR2_OC3M_Pos) ///< Forceactive
#define TIM_CCMR2_OC3M_PWM1 (0x06U << TIM_CCMR2_OC3M_Pos) ///< PWM1
#define TIM_CCMR2_OC3M_PWM2 (0x07U << TIM_CCMR2_OC3M_Pos) ///< PWM2
#define TIM_CCMR2_IC3F_Pos (4)
#define TIM_CCMR2_IC3F (0x0FU << TIM_CCMR2_IC3F_Pos) ///< IC3F[3:0] bits (Input Capture 3 Filter)
#define TIM_CCMR2_IC3F_0 (0x01U << TIM_CCMR2_IC3F_Pos) ///< Bit 0
#define TIM_CCMR2_IC3F_1 (0x02U << TIM_CCMR2_IC3F_Pos) ///< Bit 1
#define TIM_CCMR2_IC3F_2 (0x04U << TIM_CCMR2_IC3F_Pos) ///< Bit 2
#define TIM_CCMR2_IC3F_3 (0x08U << TIM_CCMR2_IC3F_Pos) ///< Bit 3
#define TIM_CCMR2_OC3CEN_Pos (7)
#define TIM_CCMR2_OC3CEN (0x01U << TIM_CCMR2_OC3CEN_Pos) ///< Output Compare 3 Clear Enable
#define TIM_CCMR2_CC4S_Pos (8)
#define TIM_CCMR2_CC4S (0x03U << TIM_CCMR2_CC4S_Pos) ///< CC4S[1:0] bits (Capture/Compare 4 Selection)
#define TIM_CCMR2_CC4S_OC (0x00U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as output
#define TIM_CCMR2_CC4S_DIRECTTI (0x01U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as input, IC4 is mapped on TI4
#define TIM_CCMR2_CC4S_INDIRECTTI (0x02U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as input, IC4 is mapped on TI3
#define TIM_CCMR2_CC4S_TRC (0x03U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as input, IC4 is mapped on TRC
#define TIM_CCMR2_OC4FEN_Pos (10)
#define TIM_CCMR2_OC4FEN (0x01U << TIM_CCMR2_OC4FEN_Pos) ///< Output Compare 4 Fast enable
#define TIM_CCMR2_OC4PEN_Pos (11)
#define TIM_CCMR2_OC4PEN (0x01U << TIM_CCMR2_OC4PEN_Pos) ///< Output Compare 4 Preload enable
#define TIM_CCMR2_OC4M_Pos (12)
#define TIM_CCMR2_OC4M (0x07U << TIM_CCMR2_OC4M_Pos) ///< OC4M[2:0] bits (Output Compare 4 Mode)
#define TIM_CCMR2_OC4M_TIMING (0x00U << TIM_CCMR2_OC4M_Pos) ///< Timing
#define TIM_CCMR2_OC4M_ACTIVE (0x01U << TIM_CCMR2_OC4M_Pos) ///< Active
#define TIM_CCMR2_OC4M_INACTIVE (0x02U << TIM_CCMR2_OC4M_Pos) ///< Inactive
#define TIM_CCMR2_OC4M_TOGGLE (0x03U << TIM_CCMR2_OC4M_Pos) ///< Toggle
#define TIM_CCMR2_OC4M_FORCEINACTIVE (0x04U << TIM_CCMR2_OC4M_Pos) ///< Forceinactive
#define TIM_CCMR2_OC4M_FORCEACTIVE (0x05U << TIM_CCMR2_OC4M_Pos) ///< Forceactive
#define TIM_CCMR2_OC4M_PWM1 (0x06U << TIM_CCMR2_OC4M_Pos) ///< PWM1
#define TIM_CCMR2_OC4M_PWM2 (0x07U << TIM_CCMR2_OC4M_Pos) ///< PWM2
#define TIM_CCMR2_OC4CEN_Pos (15)
#define TIM_CCMR2_OC4CEN (0x01U << TIM_CCMR2_OC4CEN_Pos) ///< Output Compare 4 Clear Enable
#define TIM_CCMR2_IC4PSC_Pos (10)
#define TIM_CCMR2_IC4PSC (0x03U << TIM_CCMR2_IC4PSC_Pos) ///< IC4PSC[1:0] bits (Input Capture 4 Prescaler)
#define TIM_CCMR2_IC4PSC_DIV1 (0x00U << TIM_CCMR2_IC4PSC_Pos) ///< No Prescaler
#define TIM_CCMR2_IC4PSC_DIV2 (0x01U << TIM_CCMR2_IC4PSC_Pos) ///< Capture is done once every 2 events
#define TIM_CCMR2_IC4PSC_DIV4 (0x02U << TIM_CCMR2_IC4PSC_Pos) ///< Capture is done once every 4 events
#define TIM_CCMR2_IC4PSC_DIV8 (0x03U << TIM_CCMR2_IC4PSC_Pos) ///< Capture is done once every 8 events
#define TIM_CCMR2_IC4F_Pos (12)
#define TIM_CCMR2_IC4F (0x0FU << TIM_CCMR2_IC4F_Pos) ///< IC4F[3:0] bits (Input Capture 4 Filter)
#define TIM_CCMR2_IC4F_0 (0x01U << TIM_CCMR2_IC4F_Pos) ///< Bit 0
#define TIM_CCMR2_IC4F_1 (0x02U << TIM_CCMR2_IC4F_Pos) ///< Bit 1
#define TIM_CCMR2_IC4F_2 (0x04U << TIM_CCMR2_IC4F_Pos) ///< Bit 2
#define TIM_CCMR2_IC4F_3 (0x08U << TIM_CCMR2_IC4F_Pos) ///< Bit 3
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_CCER Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_CCER_CC1EN_Pos (0)
#define TIM_CCER_CC1EN (0x01U << TIM_CCER_CC1EN_Pos) ///< Capture/Compare 1 output enable
#define TIM_CCER_CC1P_Pos (1)
#define TIM_CCER_CC1P (0x01U << TIM_CCER_CC1P_Pos) ///< Capture/Compare 1 output Polarity
#define TIM_CCER_CC1NEN_Pos (2)
#define TIM_CCER_CC1NEN (0x01U << TIM_CCER_CC1NEN_Pos) ///< Capture/Compare 1 Complementary output enable
#define TIM_CCER_CC1NP_Pos (3)
#define TIM_CCER_CC1NP (0x01U << TIM_CCER_CC1NP_Pos) ///< Capture/Compare 1 Complementary output Polarity
#define TIM_CCER_CC2EN_Pos (4)
#define TIM_CCER_CC2EN (0x01U << TIM_CCER_CC2EN_Pos) ///< Capture/Compare 2 output enable
#define TIM_CCER_CC2P_Pos (5)
#define TIM_CCER_CC2P (0x01U << TIM_CCER_CC2P_Pos) ///< Capture/Compare 2 output Polarity
#define TIM_CCER_CC2NEN_Pos (6)
#define TIM_CCER_CC2NEN (0x01U << TIM_CCER_CC2NEN_Pos) ///< Capture/Compare 2 Complementary output enable
#define TIM_CCER_CC2NP_Pos (7)
#define TIM_CCER_CC2NP (0x01U << TIM_CCER_CC2NP_Pos) ///< Capture/Compare 2 Complementary output Polarity
#define TIM_CCER_CC3EN_Pos (8)
#define TIM_CCER_CC3EN (0x01U << TIM_CCER_CC3EN_Pos) ///< Capture/Compare 3 output enable
#define TIM_CCER_CC3P_Pos (9)
#define TIM_CCER_CC3P (0x01U << TIM_CCER_CC3P_Pos) ///< Capture/Compare 3 output Polarity
#define TIM_CCER_CC3NEN_Pos (10)
#define TIM_CCER_CC3NEN (0x01U << TIM_CCER_CC3NEN_Pos) ///< Capture/Compare 3 Complementary output enable
#define TIM_CCER_CC3NP_Pos (11)
#define TIM_CCER_CC3NP (0x01U << TIM_CCER_CC3NP_Pos) ///< Capture/Compare 3 Complementary output Polarity
#define TIM_CCER_CC4EN_Pos (12)
#define TIM_CCER_CC4EN (0x01U << TIM_CCER_CC4EN_Pos) ///< Capture/Compare 4 output enable
#define TIM_CCER_CC4P_Pos (13)
#define TIM_CCER_CC4P (0x01U << TIM_CCER_CC4P_Pos) ///< Capture/Compare 4 output Polarity
#define TIM_CCER_CC4NP_Pos (15)
#define TIM_CCER_CC4NP (0x01U << TIM_CCER_CC4NP_Pos) ///< Capture/Compare 4 complementary output polarity
#define TIM_CCER_CC5EN_Pos (16)
#define TIM_CCER_CC5EN (0x01U << TIM_CCER_CC5EN_Pos) ///< Capture/Compare 5 output enable
#define TIM_CCER_CC5P_Pos (17)
#define TIM_CCER_CC5P (0x01U << TIM_CCER_CC5P_Pos) ///< Capture/Compare 5 output Polarity
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_CNT Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_CNT_CNT (0xFFFFU) ///< Counter Value
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_PSC Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_PSC_PSC (0xFFFFU) ///< Prescaler Value
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_ARR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_ARR_ARR (0xFFFFU) ///< actual auto-reload Value
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_RCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_RCR_REP (0xFFU) ///< Repetition Counter Value
#define TIM_RCR_REP_CNT_Pos (8)
#define TIM_RCR_REP_CNT (0xFFU << TIM_RCR_REP_CNT_Pos) ///< Repetition counter value of real-time writing
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_CCR1 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_CCR1_CCR1 (0xFFFFU) ///< Capture/Compare 1 Value
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_CCR2 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_CCR2_CCR2 (0xFFFFU) ///< Capture/Compare 2 Value
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_CCR3 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_CCR3_CCR3 (0xFFFFU) ///< Capture/Compare 3 Value
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_CCR4 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_CCR4_CCR4 (0xFFFFU) ///< Capture/Compare 4 Value
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_BDTR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_BDTR_DTG_Pos (0)
#define TIM_BDTR_DTG (0xFFU << TIM_BDTR_DTG_Pos) ///< DTG[0:7] bits (Dead-Time Generator set-up)
#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) ///< Bit 0
#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) ///< Bit 1
#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) ///< Bit 2
#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) ///< Bit 3
#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) ///< Bit 4
#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) ///< Bit 5
#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) ///< Bit 6
#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) ///< Bit 7
#define TIM_BDTR_LOCK_Pos (8)
#define TIM_BDTR_LOCK (0x03U << TIM_BDTR_LOCK_Pos) ///< LOCK[1:0] bits (Lock Configuration)
#define TIM_BDTR_LOCK_OFF (0x00U << TIM_BDTR_LOCK_Pos) ///< Lock Off
#define TIM_BDTR_LOCK_1 (0x01U << TIM_BDTR_LOCK_Pos) ///< Lock Level 1
#define TIM_BDTR_LOCK_2 (0x02U << TIM_BDTR_LOCK_Pos) ///< Lock Level 2
#define TIM_BDTR_LOCK_3 (0x03U << TIM_BDTR_LOCK_Pos) ///< Lock Level 3
#define TIM_BDTR_OSSI_Pos (10)
#define TIM_BDTR_OSSI (0x01U << TIM_BDTR_OSSI_Pos) ///< Off-State Selection for Idle mode
#define TIM_BDTR_OSSR_Pos (11)
#define TIM_BDTR_OSSR (0x01U << TIM_BDTR_OSSR_Pos) ///< Off-State Selection for Run mode
#define TIM_BDTR_BKEN_Pos (12)
#define TIM_BDTR_BKEN (0x01U << TIM_BDTR_BKEN_Pos) ///< Break enable
#define TIM_BDTR_BKP_Pos (13)
#define TIM_BDTR_BKP (0x01U << TIM_BDTR_BKP_Pos) ///< Break Polarity
#define TIM_BDTR_AOEN_Pos (14)
#define TIM_BDTR_AOEN (0x01U << TIM_BDTR_AOEN_Pos) ///< Automatic Output enable
#define TIM_BDTR_MOEN_Pos (15)
#define TIM_BDTR_MOEN (0x01U << TIM_BDTR_MOEN_Pos) ///< Main Output enable
#define TIM_BDTR_DOEN_Pos (16)
#define TIM_BDTR_DOEN (0x01U << TIM_BDTR_DOEN_Pos) ///< Direct Output enable
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_DCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_DCR_DBA_Pos (0)
#define TIM_DCR_DBA (0x1FU << TIM_DCR_DBA_Pos) ///< DBA[4:0] bits (DMA Base Address)
#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) ///< Bit 0
#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) ///< Bit 1
#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) ///< Bit 2
#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) ///< Bit 3
#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) ///< Bit 4
#define TIM_DCR_DBL_Pos (8)
#define TIM_DCR_DBL (0x1FU << TIM_DCR_DBL_Pos) ///< DBL[4:0] bits (DMA Burst Length)
#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) ///< Bit 0
#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) ///< Bit 1
#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) ///< Bit 2
#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) ///< Bit 3
#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) ///< Bit 4
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_DMAR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_DMAR_DMAB (0xFFFFU) ///< DMA register for burst accesses
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_CCMR3 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_CCMR3_OC5FEN_Pos (2)
#define TIM_CCMR3_OC5FEN (0x01U << TIM_CCMR3_OC5FEN_Pos) ///< Output Compare 5 Fast enable
#define TIM_CCMR3_OC5PEN_Pos (3)
#define TIM_CCMR3_OC5PEN (0x01U << TIM_CCMR3_OC5PEN_Pos) ///< Output Compare 5 Preload enable
#define TIM_CCMR3_OC5M_Pos (4)
#define TIM_CCMR3_OC5M (0x07U << TIM_CCMR3_OC5M_Pos) ///< OC5M[2:0] bits (Output Compare 5 Mode)
#define TIM_CCMR3_OC5CEN_Pos (7)
#define TIM_CCMR3_OC5CEN (0x01U << TIM_CCMR3_OC5CEN_Pos) ///< Output Compare 5 Clear Enable
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_CCR5 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_CCR5_CCR5 (0xFFFF) ///< Capture/Compare 5 Value
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_PDER Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_PDER_CCDREPE_Pos (0)
#define TIM_PDER_CCDREPE (0x01U << TIM_PDER_CCDREPE_Pos) ///< DMA request flow enable
#define TIM_PDER_CCR1SHIFTEN_Pos (1)
#define TIM_PDER_CCR1SHIFTEN (0x01U << TIM_PDER_CCR1SHIFTEN_Pos) ///< CCR1 pwm shift enable
#define TIM_PDER_CCR2SHIFTEN_Pos (2)
#define TIM_PDER_CCR2SHIFTEN (0x01U << TIM_PDER_CCR2SHIFTEN_Pos) ///< CCR2 pwm shift enable
#define TIM_PDER_CCR3SHIFTEN_Pos (3)
#define TIM_PDER_CCR3SHIFTEN (0x01U << TIM_PDER_CCR3SHIFTEN_Pos) ///< CCR3 pwm shift enable
#define TIM_PDER_CCR4SHIFTEN_Pos (4)
#define TIM_PDER_CCR4SHIFTEN (0x01U << TIM_PDER_CCR4SHIFTEN_Pos) ///< CCR4 pwm shift enable
#define TIM_PDER_CCR5SHIFTEN_Pos (5)
#define TIM_PDER_CCR5SHIFTEN (0x01U << TIM_PDER_CCR5SHIFTEN_Pos) ///< CCR5 pwm shift enable
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_CCR1FALL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_CCR1FALL_CCR1FALL (0xFFFFU) ///< Capture/compare value for ch1 when counting down in PWM center-aligned mode
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_CCR2FALL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_CCR2FALL_CCR2FALL (0xFFFFU) ///< Capture/compare value for ch2 when counting down in PWM center-aligned mode
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_CCR3FALL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_CCR3FALL_CCR3FALL (0xFFFFU) ///< Capture/compare value for ch3 when counting down in PWM center-aligned mode
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_CCR4FALL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_CCR4FALL_CCR4FALL (0xFFFFU) ///< Capture/compare value for ch4 when counting down in PWM center-aligned mode
////////////////////////////////////////////////////////////////////////////////
/// @brief TIM_CCR5FALL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define TIM_CCR5FALL_CCR5FALL (0xFFFFU) ///< Capture/compare value for ch5 when counting down in PWM center-aligned mode
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h
+362
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@@ -0,0 +1,362 @@
////////////////////////////////////////////////////////////////////////////////
/// @file reg_uart.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_UART_H
#define __REG_UART_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief UART Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define UART1_BASE (APB2PERIPH_BASE + 0x3800) ///< Base Address: 0x40013800
#define UART2_BASE (APB1PERIPH_BASE + 0x4400) ///< Base Address: 0x40004400
#define UART3_BASE (APB1PERIPH_BASE + 0x4800) ///< Base Address: 0x40004800
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) ///< Base Address: 0x40004C00
#define UART5_BASE (APB1PERIPH_BASE + 0x5000) ///< Base Address: 0x40005000
#define UART6_BASE (APB2PERIPH_BASE + 0x3C00) ///< Base Address: 0x40013C00
#define UART7_BASE (APB1PERIPH_BASE + 0x7800) ///< Base Address: 0x40007800
#define UART8_BASE (APB1PERIPH_BASE + 0x7C00) ///< Base Address: 0x40007C00
////////////////////////////////////////////////////////////////////////////////
/// @brief UART Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 TDR; ///< Transmit Data Register, offset: 0x00
__IO u32 RDR; ///< Receive Data Register, offset: 0x04
__IO u32 CSR; ///< Current Status Register, offset: 0x08
__IO u32 ISR; ///< Interrupt Status Register, offset: 0x0C
__IO u32 IER; ///< Interrupt Enable Register, offset: 0x10
__IO u32 ICR; ///< Interrupt Clear Register, offset: 0x14
__IO u32 GCR; ///< Global Control Register, offset: 0x18
__IO u32 CCR; ///< Config Control Register, offset: 0x1C
__IO u32 BRR; ///< Baud Rate Register, offset: 0x20
__IO u32 FRA; ///< Fraction Register, offset: 0x24
__IO u32 RXAR; ///< Receive Address Register, offset: 0x28
__IO u32 RXMR; ///< Receive Address Mask Register, offset: 0x2C
__IO u32 SCR; ///< Smart Card Register, offset: 0x30
__IO u32 IDLR; ///< Data length register offset: 0x34
__IO u32 ABRCR; ///< automatic Baud rate control delivery offset: 0x38
__IO u32 IRDA; ///< Infrared function control register, offset: 0x3C
} UART_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief UART type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define UART1 ((UART_TypeDef*) UART1_BASE)
#define UART2 ((UART_TypeDef*) UART2_BASE)
#define UART3 ((UART_TypeDef*) UART3_BASE)
#define UART4 ((UART_TypeDef*) UART4_BASE)
#define UART5 ((UART_TypeDef*) UART5_BASE)
#define UART6 ((UART_TypeDef*) UART6_BASE)
#define UART7 ((UART_TypeDef*) UART7_BASE)
#define UART8 ((UART_TypeDef*) UART8_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief UART_TDR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define UART_TDR_DATA_Pos (0)
#define UART_TDR_DATA (0xFFU << UART_TDR_DATA_Pos) ///< Transmit data register
////////////////////////////////////////////////////////////////////////////////
/// @brief UART_RDR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define UART_RDR_DATA_Pos (0)
#define UART_RDR_DATA (0xFFU << UART_RDR_DATA_Pos) ///< Receive data register
////////////////////////////////////////////////////////////////////////////////
/// @brief UART_CSR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define UART_CSR_TXC_Pos (0)
#define UART_CSR_TXC (0x01U << UART_CSR_TXC_Pos) ///< Transmit complete flag bit
#define UART_CSR_RXAVL_Pos (1)
#define UART_CSR_RXAVL (0x01U << UART_CSR_RXAVL_Pos) ///< Receive valid data flag bit
#define UART_CSR_TXFULL_Pos (2)
#define UART_CSR_TXFULL (0x01U << UART_CSR_TXFULL_Pos) ///< Transmit buffer full flag bit
#define UART_CSR_TXEPT_Pos (3)
#define UART_CSR_TXEPT (0x01U << UART_CSR_TXEPT_Pos) ///< Transmit buffer empty flag bit
////////////////////////////////////////////////////////////////////////////////
/// @brief UART_ISR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define UART_ISR_TX_Pos (0)
#define UART_ISR_TX (0x01U << UART_ISR_TX_Pos) ///< Transmit buffer empty interrupt flag bit
#define UART_ISR_RX_Pos (1)
#define UART_ISR_RX (0x01U << UART_ISR_RX_Pos) ///< Receive valid data interrupt flag bit
#define UART_ISR_TXC_Pos (2)
#define UART_ISR_TXC (0x01U << UART_ISR_TXC_Pos) ///< Transmit complete interrupt flag bit
#define UART_ISR_RXOERR_Pos (3)
#define UART_ISR_RXOERR (0x01U << UART_ISR_RXOERR_Pos) ///< Receive overflow error interrupt flag bit
#define UART_ISR_RXPERR_Pos (4)
#define UART_ISR_RXPERR (0x01U << UART_ISR_RXPERR_Pos) ///< Parity error interrupt flag bit
#define UART_ISR_RXFERR_Pos (5)
#define UART_ISR_RXFERR (0x01U << UART_ISR_RXFERR_Pos) ///< Frame error interrupt flag bit
#define UART_ISR_RXBRK_Pos (6)
#define UART_ISR_RXBRK (0x01U << UART_ISR_RXBRK_Pos) ///< Receive frame break interrupt flag bit
#define UART_ISR_TXBRK_Pos (7)
#define UART_ISR_TXBRK (0x01U << UART_ISR_TXBRK_Pos) ///< Transmit Break Frame Interrupt Flag Bit
#define UART_ISR_RXB8_Pos (8)
#define UART_ISR_RXB8 (0x01U << UART_ISR_RXB8_Pos) ///< Receive Bit 8 Interrupt Flag Bit
#define UART_ISR_RXIDLE_Pos (9)
#define UART_ISR_RXIDLE (0x01U << UART_ISR_RXIDLE_Pos) ///< Receive Bit 8 Interrupt clear Bit
#define UART_ISR_ABREND_INTF_Pos (10)
#define UART_ISR_ABREND_INTF (0x01U << UART_ISR_ABREND_INTF_Pos) ///< Auto baud rate end interrupt flag bit
#define UART_ISR_ABRERR_INTF_Pos (11)
#define UART_ISR_ABRERR_INTF (0x01U << UART_ISR_ABRERR_INTF_Pos) ///< Auto baud rate error interrupt flag bit
////////////////////////////////////////////////////////////////////////////////
/// @brief UART_IER Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define UART_IER_TX_Pos (0)
#define UART_IER_TX (0x01U << UART_IER_TX_Pos) ///< Transmit buffer empty interrupt enable bit
#define UART_IER_RX_Pos (1)
#define UART_IER_RX (0x01U << UART_IER_RX_Pos) ///< Receive buffer interrupt enable bit
#define UART_IER_TXC_Pos (2)
#define UART_IER_TXC (0x01U << UART_IER_TXC_Pos) ///< Transmit complete interrupt enable bit
#define UART_IER_RXOERR_Pos (3)
#define UART_IER_RXOERR (0x01U << UART_IER_RXOERR_Pos) ///< Receive overflow error interrupt enable bit
#define UART_IER_RXPERR_Pos (4)
#define UART_IER_RXPERR (0x01U << UART_IER_RXPERR_Pos) ///< Parity error interrupt enable bit
#define UART_IER_RXFERR_Pos (5)
#define UART_IER_RXFERR (0x01U << UART_IER_RXFERR_Pos) ///< Frame error interrupt enable bit
#define UART_IER_RXBRK_Pos (6)
#define UART_IER_RXBRK (0x01U << UART_IER_RXBRK_Pos) ///< Receive frame break interrupt enable bit
#define UART_IER_TXBRK_Pos (7)
#define UART_IER_TXBRK (0x01U << UART_IER_TXBRK_Pos) ///< Transmit Break Frame Interrupt Enable Bit
#define UART_IER_RXB8_Pos (8)
#define UART_IER_RXB8 (0x01U << UART_IER_RXB8_Pos) ///< Receive Bit 8 Interrupt Enable Bit
#define UART_IER_RXIDLE_Pos (9)
#define UART_IER_RXIDLE (0x01U << UART_IER_RXIDLE_Pos) ///< Receive Bit 8 Interrupt clear Bit
#define UART_IER_ABREND_IEN_Pos (10)
#define UART_IER_ABREND_IEN (0x01U << UART_IER_ABREND_IEN_Pos) ///< Auto baud rate end enable bit
#define UART_IER_ABRERR_IEN_Pos (11)
#define UART_IER_ABRERR_IEN (0x01U << UART_IER_ABRERR_IEN_Pos) ///< Auto baud rate error enable bit
////////////////////////////////////////////////////////////////////////////////
/// @brief UART_ICR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define UART_ICR_TX_Pos (0)
#define UART_ICR_TX (0x01U << UART_ICR_TX_Pos) ///< Transmit buffer empty interrupt clear bit
#define UART_ICR_RX_Pos (1)
#define UART_ICR_RX (0x01U << UART_ICR_RX_Pos) ///< Receive interrupt clear bit
#define UART_ICR_TXC_Pos (2)
#define UART_ICR_TXC (0x01U << UART_ICR_TXC_Pos) ///< Transmit complete interrupt clear bit
#define UART_ICR_RXOERR_Pos (3)
#define UART_ICR_RXOERR (0x01U << UART_ICR_RXOERR_Pos) ///< Receive overflow error interrupt clear bit
#define UART_ICR_RXPERR_Pos (4)
#define UART_ICR_RXPERR (0x01U << UART_ICR_RXPERR_Pos) ///< Parity error interrupt clear bit
#define UART_ICR_RXFERR_Pos (5)
#define UART_ICR_RXFERR (0x01U << UART_ICR_RXFERR_Pos) ///< Frame error interrupt clear bit
#define UART_ICR_RXBRK_Pos (6)
#define UART_ICR_RXBRK (0x01U << UART_ICR_RXBRK_Pos) ///< Receive frame break interrupt clear bit
#define UART_ICR_TXBRK_Pos (7)
#define UART_ICR_TXBRK (0x01U << UART_ICR_TXBRK_Pos) ///< Transmit Break Frame Interrupt clear Bit
#define UART_ICR_RXB8_Pos (8)
#define UART_ICR_RXB8 (0x01U << UART_ICR_RXB8_Pos) ///< Receive Bit 8 Interrupt clear Bit
#define UART_ICR_RXIDLE_Pos (9)
#define UART_ICR_RXIDLE (0x01U << UART_ICR_RXIDLE_Pos) ///< Receive Bit 8 Interrupt clear Bit
#define UART_ICR_ABRENDCLR_Pos (10)
#define UART_ICR_ABRENDCLR (0x01U << UART_ICR_ABRENDCLR_Pos) ///< Auto baud rate end clear bit
#define UART_ICR_ABRERRCLR_Pos (11)
#define UART_ICR_ABRERRCLR (0x01U << UART_ICR_ABRERRCLR_Pos) ///< Auto baud rate error clear bit
////////////////////////////////////////////////////////////////////////////////
/// @brief UART_GCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define UART_GCR_UART_Pos (0)
#define UART_GCR_UART (0x01U << UART_GCR_UART_Pos) ///< UART mode selection bit
#define UART_GCR_DMA_Pos (1)
#define UART_GCR_DMA (0x01U << UART_GCR_DMA_Pos) ///< DMA mode selection bit
#define UART_GCR_AUTOFLOW_Pos (2)
#define UART_GCR_AUTOFLOW (0x01U << UART_GCR_AUTOFLOW_Pos) ///< Automatic flow control enable bit
#define UART_GCR_RX_Pos (3)
#define UART_GCR_RX (0x01U << UART_GCR_RX_Pos) ///< Enable receive
#define UART_GCR_TX_Pos (4)
#define UART_GCR_TX (0x01U << UART_GCR_TX_Pos) ///< Enable transmit
#define UART_GCR_SELB8_Pos (7)
#define UART_GCR_SELB8 (0x01U << UART_GCR_SELB8_Pos) ///< UART mode selection bit
#define UART_GCR_SWAP_Pos (8)
#define UART_GCR_SWAP (0x01U << UART_GCR_SWAP_Pos) ///< DMA mode selection bit
#define UART_GCR_RXTOG_Pos (9)
#define UART_GCR_RXTOG (0x01U << UART_GCR_RXTOG_Pos) ///< Automatic flow control enable bit
#define UART_GCR_TXTOG_Pos (10)
#define UART_GCR_TXTOG (0x01U << UART_GCR_TXTOG_Pos) ///< Enable receive
////////////////////////////////////////////////////////////////////////////////
/// @brief UART_CCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define UART_CCR_PEN_Pos (0)
#define UART_CCR_PEN (0x01U << UART_CCR_PEN_Pos) ///< Parity enable bit
#define UART_CCR_PSEL_Pos (1)
#define UART_CCR_PSEL (0x01U << UART_CCR_PSEL_Pos) ///< Parity selection bit
#define UART_CCR_SPB_Pos (2)
#define UART_CCR_SPB (0x01U << UART_CCR_SPB_Pos) ///< Stop bit selection
#define UART_CCR_SPB0_Pos UART_CCR_SPB_Pos
#define UART_CCR_SPB0 UART_CCR_SPB ///< Stop bit 0 selection
#define UART_CCR_BRK_Pos (3)
#define UART_CCR_BRK (0x01U << UART_CCR_BRK_Pos) ///< UART transmit frame break
#define UART_CCR_CHAR_Pos (4)
#define UART_CCR_CHAR (0x03U << UART_CCR_CHAR_Pos) ///< UART width bit
#define UART_CCR_CHAR_5b (0x00U << UART_CCR_CHAR_Pos) ///< UART Word Length 5b
#define UART_CCR_CHAR_6b (0x01U << UART_CCR_CHAR_Pos) ///< UART Word Length 6b
#define UART_CCR_CHAR_7b (0x02U << UART_CCR_CHAR_Pos) ///< UART Word Length 7b
#define UART_CCR_CHAR_8b (0x03U << UART_CCR_CHAR_Pos) ///< UART Word Length 8b
#define UART_CCR_SPB1_Pos (6)
#define UART_CCR_SPB1 (0x01U << UART_CCR_SPB1_Pos) ///< Stop bit 1 selection
#define UART_CCR_B8RXD_Pos (7)
#define UART_CCR_B8RXD (0x01U << UART_CCR_B8RXD_Pos) ///< Synchronous frame receive
#define UART_CCR_B8TXD_Pos (8)
#define UART_CCR_B8TXD (0x01U << UART_CCR_B8TXD_Pos) ///< Synchronous frame transmit
#define UART_CCR_B8POL_Pos (9)
#define UART_CCR_B8POL (0x01U << UART_CCR_B8POL_Pos) ///< Synchronous frame polarity control bit
#define UART_CCR_B8TOG_Pos (10)
#define UART_CCR_B8TOG (0x01U << UART_CCR_B8TOG_Pos) ///< Synchronous frame auto toggle bit
#define UART_CCR_B8EN_Pos (11)
#define UART_CCR_B8EN (0x01U << UART_CCR_B8EN_Pos) ///< Synchronous frame enable bit
#define UART_CCR_RWU_Pos (12)
#define UART_CCR_RWU (0x01U << UART_CCR_RWU_Pos) ///< Receive wake up method
#define UART_CCR_WAKE_Pos (13)
#define UART_CCR_WAKE (0x01U << UART_CCR_WAKE_Pos) ///< Wake up method
#define UART_CCR_LIN_Pos (14)
#define UART_CCR_LIN (0x01U << UART_CCR_LIN_Pos) ///< Wake up method
////////////////////////////////////////////////////////////////////////////////
/// @brief UART_BRR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define UART_BRR_MANTISSA_Pos (0)
#define UART_BRR_MANTISSA (0xFFFFU << UART_BRR_MANTISSA_Pos) ///< UART DIV MANTISSA
////////////////////////////////////////////////////////////////////////////////
/// @brief UART_FRA Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define UART_BRR_FRACTION_Pos (0)
#define UART_BRR_FRACTION (0x0FU << UART_BRR_FRACTION_Pos) ///< UART DIV FRACTION
////////////////////////////////////////////////////////////////////////////////
/// @brief UART_RXAR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define UART_RXAR_ADDR_Pos (0)
#define UART_RXAR_ADDR (0xFFU << UART_RXAR_ADDR_Pos) ///< Synchronous frame match address
////////////////////////////////////////////////////////////////////////////////
/// @brief UART_RXMR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define UART_RXMR_MASK_Pos (0)
#define UART_RXMR_MASK (0xFFU << UART_RXMR_MASK_Pos) ///< Synchronous frame match address mask
////////////////////////////////////////////////////////////////////////////////
/// @brief UART_SCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define UART_SCR_SCEN_Pos (0)
#define UART_SCR_SCEN (0x01U << UART_SCR_SCEN_Pos) ///< ISO7816 enable bit
#define UART_SCR_SCARB_Pos (1)
#define UART_SCR_SCARB (0x01U << UART_SCR_SCARB_Pos) ///< ISO7816 check auto answer bit
#define UART_SCR_NACK_Pos (2)
#define UART_SCR_NACK (0x01U << UART_SCR_NACK_Pos) ///< Master receive frame answer bit
#define UART_SCR_SCFCNT_Pos (4)
#define UART_SCR_SCFCNT (0xFFU << UART_SCR_SCFCNT_Pos) ///< ISO7816 protection counter bit
#define UART_SCR_HDSEL_Pos (12)
#define UART_SCR_HDSEL (0x01U << UART_SCR_HDSEL_Pos) ///< Single-line half-duplex mode selection bit
////////////////////////////////////////////////////////////////////////////////
/// @brief UART_ABRCR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define UART_ABRCR_ABREN_Pos (0)
#define UART_ABRCR_ABREN (0x01U<<UART_ABRCR_ABREN_Pos)
#define UART_ABRCR_BITCNT_Pos (1)
#define UART_ABRCR_BITCNT (0x03U<<UART_ABRCR_BITCNT_Pos)
#define UART_ABRCR_BITCNT_MODE0 (0x00U<<UART_ABRCR_BITCNT_Pos)
#define UART_ABRCR_BITCNT_MODE1 (0x01U<<UART_ABRCR_BITCNT_Pos)
#define UART_ABRCR_BITCNT_MODE2 (0x02U<<UART_ABRCR_BITCNT_Pos)
#define UART_ABRCR_BITCNT_MODE3 (0x03U<<UART_ABRCR_BITCNT_Pos)
#define UART_ABRCR_FORMER_Pos (3)
#define UART_ABRCR_FORMER (0x01U<<UART_ABRCR_FORMER_Pos)
#define UART_ABRCR_LATTER_Pos (4)
#define UART_ABRCR_LATTER (0x01U<<UART_ABRCR_LATTER_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief UART_IDLR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define UART_IDLR_IDLR_Pos (0)
#define UART_IDLR_IDLR (0xFFFFU << UART_IDLR_IDLR_Pos) ///< ISO7816 enable bit
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_usb_otg_fs.h
+923
View File
@@ -0,0 +1,923 @@
////////////////////////////////////////////////////////////////////////////////
/// @file reg_usb_otg_fs.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_USB_OTG_FS_H
#define __REG_USB_OTG_FS_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief USB Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define USB_OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000) ///< Base Address: 0x50000000
////////////////////////////////////////////////////////////////////////////////
/// @brief USB Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
__IO u32 PER_ID; ///< Peripheral ID register offset: 0x00
__IO u32 ID_COMP; ///< Peripheral ID complement register offset: 0x04
__IO u32 REV; ///< Peripheral revision register offset: 0x08
__IO u32 ADD_INFO; ///< Peripheral additional info register offset: 0x0C
__IO u32 OTG_ISTAT; ///< OTG Interrupt Status Register offset: 0x10
__IO u32 OTG_ICTRL; ///< OTG Interrupt Control Register offset: 0x14
__IO u32 OTG_STAT; ///< OTG Status Register offset: 0x18
__IO u32 OTG_CTRL; ///< OTG Control register offset: 0x1C
__IO u32 RESERVED0[24]; ///< Reserved offset: 0x20
__IO u32 INT_STAT; ///< Interrupt status register offset: 0x80
__IO u32 INT_ENB; ///< Interrupt enable register offset: 0x84
__IO u32 ERR_STAT; ///< Error interrupt status register offset: 0x88
__IO u32 ERR_ENB; ///< Error interrupt enable register offset: 0x8C
__IO u32 STAT; ///< Status register offset: 0x90
__IO u32 CTL; ///< Control register offset: 0x94
__IO u32 ADDR; ///< Address register offset: 0x98
__IO u32 BDT_PAGE_01; ///< BDT page register 1 offset: 0x9C
__IO u32 FRM_NUML; ///< Frame number register offset: 0xA0
__IO u32 FRM_NUMH; ///< Frame number register offset: 0xA4
__IO u32 TOKEN; ///< Token register offset: 0xA8
__IO u32 SOF_THLD; ///< SOF threshold register offset: 0xAC
__IO u32 BDT_PAGE_02; ///< BDT page register 2 offset: 0xB0
__IO u32 BDT_PAGE_03; ///< BDT page register 3 offset: 0xB4
__IO u32 RESERVED1; ///< Reserved offset: 0xB8
__IO u32 RESERVED2; ///< Reserved offset: 0xBC
__IO u32 EP_CTL[16]; ///< Endpoint control register offset: 0xC0
} USB_OTG_FS_TypeDef;
////////////////////////////////////////////////////////////////////////////////
/// @brief USBD type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define USB_OTG_FS ((USB_OTG_FS_TypeDef*) USB_OTG_FS_BASE )
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_PER_ID Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_PER_ID_ID_Pos (0)
#define OTG_FS_PER_ID_ID (0x3FU << OTG_FS_PER_ID_ID_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_ID_COMP Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_ID_COMP_NID_Pos (0)
#define OTG_FS_ID_COMP_NID (0x3FU << OTG_FS_ID_COMP_NID_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_REV Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_REV_REV_Pos (0)
#define OTG_FS_REV_REV (0xFFU << OTG_FS_REV_REV_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_ADD_INFO Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_ADD_INFO_HOST_Pos (0)
#define OTG_FS_ADD_INFO_HOST (0x01U << OTG_FS_ADD_INFO_HOST_Pos)
#define OTG_FS_ADD_INFO_IRQ_NUM_Pos (3)
#define OTG_FS_ADD_INFO_IRQ_NUM (0x1FU << OTG_FS_ADD_INFO_IRQ_NUM_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_OTG_ISTAT Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG_Pos (0)
#define OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG (0x01U << OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG_Pos)
#define OTG_FS_OTG_ISTAT_B_SESS_END_CHG_Pos (2)
#define OTG_FS_OTG_ISTAT_B_SESS_END_CHG (0x01U << OTG_FS_OTG_ISTAT_B_SESS_END_CHG_Pos)
#define OTG_FS_OTG_ISTAT_SESS_VLD_CHG_Pos (3)
#define OTG_FS_OTG_ISTAT_SESS_VLD_CHG (0x01U << OTG_FS_OTG_ISTAT_SESS_VLD_CHG_Pos)
#define OTG_FS_OTG_ISTAT_LINE_STATE_CHG_Pos (5)
#define OTG_FS_OTG_ISTAT_LINE_STATE_CHG (0x01U << OTG_FS_OTG_ISTAT_LINE_STATE_CHG_Pos)
#define OTG_FS_OTG_ISTAT_1_MSEC_Pos (6)
#define OTG_FS_OTG_ISTAT_1_MSEC (0x01U << OTG_FS_OTG_ISTAT_1_MSEC_Pos)
#define OTG_FS_OTG_ISTAT_ID_CHG_Pos (7)
#define OTG_FS_OTG_ISTAT_ID_CHG (0x01U << OTG_FS_OTG_ISTAT_ID_CHG_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_OTG_ICTRL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN_Pos (0)
#define OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN (0x01U << OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN_Pos)
#define OTG_FS_OTG_ICTRL_B_SESS_END_EN_Pos (2)
#define OTG_FS_OTG_ICTRL_B_SESS_END_EN (0x01U << OTG_FS_OTG_ICTRL_B_SESS_END_EN_Pos)
#define OTG_FS_OTG_ICTRL_SESS_VLD_EN_Pos (3)
#define OTG_FS_OTG_ICTRL_SESS_VLD_EN (0x01U << OTG_FS_OTG_ICTRL_SESS_VLD_EN_Pos)
#define OTG_FS_OTG_ICTRL_LINE_STATE_EN_Pos (5)
#define OTG_FS_OTG_ICTRL_LINE_STATE_EN (0x01U << OTG_FS_OTG_ICTRL_LINE_STATE_EN_Pos)
#define OTG_FS_OTG_ICTRL_1_MSEC_EN_Pos (6)
#define OTG_FS_OTG_ICTRL_1_MSEC_EN (0x01U << OTG_FS_OTG_ICTRL_1_MSEC_EN_Pos)
#define OTG_FS_OTG_ICTRL_ID_EN_Pos (7)
#define OTG_FS_OTG_ICTRL_ID_EN (0x01U << OTG_FS_OTG_ICTRL_ID_EN_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_OTG_STAT Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_OTG_STAT_A_VBUS_VLD_Pos (0)
#define OTG_FS_OTG_STAT_A_VBUS_VLD (0x01U << OTG_FS_OTG_STAT_A_VBUS_VLD_Pos)
#define OTG_FS_OTG_STAT_B_SESS_END_Pos (2)
#define OTG_FS_OTG_STAT_B_SESS_END (0x01U << OTG_FS_OTG_STAT_B_SESS_END_Pos)
#define OTG_FS_OTG_STAT_SESS_VLD_Pos (3)
#define OTG_FS_OTG_STAT_SESS_VLD (0x01U << OTG_FS_OTG_STAT_SESS_VLD_Pos)
#define OTG_FS_OTG_STAT_LINE_STATE_STABLE_Pos (5)
#define OTG_FS_OTG_STAT_LINE_STATE_STABLE (0x01U << OTG_FS_OTG_STAT_LINE_STATE_STABLE_Pos)
#define OTG_FS_OTG_STAT_1_MSEC_Pos (6)
#define OTG_FS_OTG_STAT_1_MSEC (0x01U << OTG_FS_OTG_STAT_1_MSEC_Pos)
#define OTG_FS_OTG_STAT_ID_Pos (7)
#define OTG_FS_OTG_STAT_ID (0x01U << OTG_FS_OTG_STAT_ID_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_OTG_CTRL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_OTG_CTRL_VBUS_DSCHG_Pos (0)
#define OTG_FS_OTG_CTRL_VBUS_DSCHG (0x01U << OTG_FS_OTG_CTRL_VBUS_DSCHG_Pos)
#define OTG_FS_OTG_CTRL_VBUS_CHG_Pos (1)
#define OTG_FS_OTG_CTRL_VBUS_CHG (0x01U << OTG_FS_OTG_CTRL_VBUS_CHG_Pos)
#define OTG_FS_OTG_CTRL_OTG_EN_Pos (2)
#define OTG_FS_OTG_CTRL_OTG_EN (0x01U << OTG_FS_OTG_CTRL_OTG_EN_Pos)
#define OTG_FS_OTG_CTRL_VBUS_ON_Pos (3)
#define OTG_FS_OTG_CTRL_VBUS_ON (0x01U << OTG_FS_OTG_CTRL_VBUS_ON_Pos)
#define OTG_FS_OTG_CTRL_DM_LOW_Pos (4)
#define OTG_FS_OTG_CTRL_DM_LOW (0x01U << OTG_FS_OTG_CTRL_DM_LOW_Pos)
#define OTG_FS_OTG_CTRL_DP_LOW_Pos (5)
#define OTG_FS_OTG_CTRL_DP_LOW (0x01U << OTG_FS_OTG_CTRL_DP_LOW_Pos)
#define OTG_FS_OTG_CTRL_DM_HIGH_Pos (6)
#define OTG_FS_OTG_CTRL_DM_HIGH (0x01U << OTG_FS_OTG_CTRL_DM_HIGH_Pos)
#define OTG_FS_OTG_CTRL_DP_HIGH_Pos (7)
#define OTG_FS_OTG_CTRL_DP_HIGH (0x01U << OTG_FS_OTG_CTRL_DP_HIGH_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_INT_STAT Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_INT_STAT_USB_RST_Pos (0)
#define OTG_FS_INT_STAT_USB_RST (0x01U << OTG_FS_INT_STAT_USB_RST_Pos)
#define OTG_FS_INT_STAT_ERROR_Pos (1)
#define OTG_FS_INT_STAT_ERROR (0x01U << OTG_FS_INT_STAT_ERROR_Pos)
#define OTG_FS_INT_STAT_SOF_TOK_Pos (2)
#define OTG_FS_INT_STAT_SOF_TOK (0x01U << OTG_FS_INT_STAT_SOF_TOK_Pos)
#define OTG_FS_INT_STAT_TOK_DNE_Pos (3)
#define OTG_FS_INT_STAT_TOK_DNE (0x01U << OTG_FS_INT_STAT_TOK_DNE_Pos)
#define OTG_FS_INT_STAT_SLEEP_Pos (4)
#define OTG_FS_INT_STAT_SLEEP (0x01U << OTG_FS_INT_STAT_SLEEP_Pos)
#define OTG_FS_INT_STAT_RESUME_Pos (5)
#define OTG_FS_INT_STAT_RESUME (0x01U << OTG_FS_INT_STAT_RESUME_Pos)
#define OTG_FS_INT_STAT_ATTACH_Pos (6)
#define OTG_FS_INT_STAT_ATTACH (0x01U << OTG_FS_INT_STAT_ATTACH_Pos)
#define OTG_FS_INT_STAT_STALL_Pos (7)
#define OTG_FS_INT_STAT_STALL (0x01U << OTG_FS_INT_STAT_STALL_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_INT_ENB Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_INT_ENB_USB_RST_EN_Pos (0)
#define OTG_FS_INT_ENB_USB_RST_EN (0x01U << OTG_FS_INT_ENB_USB_RST_EN_Pos)
#define OTG_FS_INT_ENB_ERROR_EN_Pos (1)
#define OTG_FS_INT_ENB_ERROR_EN (0x01U << OTG_FS_INT_ENB_ERROR_EN_Pos)
#define OTG_FS_INT_ENB_SOF_TOK_EN_Pos (2)
#define OTG_FS_INT_ENB_SOF_TOK_EN (0x01U << OTG_FS_INT_ENB_SOF_TOK_EN_Pos)
#define OTG_FS_INT_ENB_TOK_DNE_EN_Pos (3)
#define OTG_FS_INT_ENB_TOK_DNE_EN (0x01U << OTG_FS_INT_ENB_TOK_DNE_EN_Pos)
#define OTG_FS_INT_ENB_SLEEP_EN_Pos (4)
#define OTG_FS_INT_ENB_SLEEP_EN (0x01U << OTG_FS_INT_ENB_SLEEP_EN_Pos)
#define OTG_FS_INT_ENB_RESUME_EN_Pos (5)
#define OTG_FS_INT_ENB_RESUME_EN (0x01U << OTG_FS_INT_ENB_RESUME_EN_Pos)
#define OTG_FS_INT_ENB_ATTACH_EN_Pos (6)
#define OTG_FS_INT_ENB_ATTACH_EN (0x01U << OTG_FS_INT_ENB_ATTACH_EN_Pos)
#define OTG_FS_INT_ENB_STALL_EN_Pos (7)
#define OTG_FS_INT_ENB_STALL_EN (0x01U << OTG_FS_INT_ENB_STALL_EN_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_ERR_STAT Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_ERR_STAT_PID_ERR_Pos (0)
#define OTG_FS_ERR_STAT_PID_ERR (0x01U << OTG_FS_ERR_STAT_PID_ERR_Pos)
#define OTG_FS_ERR_STAT_CRC5_EOF_Pos (1)
#define OTG_FS_ERR_STAT_CRC5_EOF (0x01U << OTG_FS_ERR_STAT_CRC5_EOF_Pos)
#define OTG_FS_ERR_STAT_CRC16_Pos (2)
#define OTG_FS_ERR_STAT_CRC16 (0x01U << OTG_FS_ERR_STAT_CRC16_Pos)
#define OTG_FS_ERR_STAT_DFN8_Pos (3)
#define OTG_FS_ERR_STAT_DFN8 (0x01U << OTG_FS_ERR_STAT_DFN8_Pos)
#define OTG_FS_ERR_STAT_BTO_ERR_Pos (4)
#define OTG_FS_ERR_STAT_BTO_ERR (0x01U << OTG_FS_ERR_STAT_BTO_ERR_Pos)
#define OTG_FS_ERR_STAT_DMA_ERR_Pos (5)
#define OTG_FS_ERR_STAT_DMA_ERR (0x01U << OTG_FS_ERR_STAT_DMA_ERR_Pos)
#define OTG_FS_ERR_STAT_BTS_ERR_Pos (7)
#define OTG_FS_ERR_STAT_BTS_ERR (0x01U << OTG_FS_ERR_STAT_BTS_ERR_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_ERR_ENB Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_ERR_ENB_PID_ERR_EN_Pos (0)
#define OTG_FS_ERR_ENB_PID_ERR_EN (0x01U << OTG_FS_ERR_ENB_PID_ERR_EN_Pos)
#define OTG_FS_ERR_ENB_CRC5_EOF_EN_Pos (1)
#define OTG_FS_ERR_ENB_CRC5_EOF_EN (0x01U << OTG_FS_ERR_ENB_CRC5_EOF_EN_Pos)
#define OTG_FS_ERR_ENB_CRC16_EN_Pos (2)
#define OTG_FS_ERR_ENB_CRC16_EN (0x01U << OTG_FS_ERR_ENB_CRC16_EN_Pos)
#define OTG_FS_ERR_ENB_DFN8_EN_Pos (3)
#define OTG_FS_ERR_ENB_DFN8_EN (0x01U << OTG_FS_ERR_ENB_DFN8_EN_Pos)
#define OTG_FS_ERR_ENB_BTO_ERR_EN_Pos (4)
#define OTG_FS_ERR_ENB_BTO_ERR_EN (0x01U << OTG_FS_ERR_ENB_BTO_ERR_EN_Pos)
#define OTG_FS_ERR_ENB_DMA_ERR_EN_Pos (5)
#define OTG_FS_ERR_ENB_DMA_ERR_EN (0x01U << OTG_FS_ERR_ENB_DMA_ERR_EN_Pos)
#define OTG_FS_ERR_ENB_BTS_ERR_EN_Pos (7)
#define OTG_FS_ERR_ENB_BTS_ERR_EN (0x01U << OTG_FS_ERR_ENB_BTS_ERR_EN_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_STAT Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_STAT_ODD_Pos (2)
#define OTG_FS_STAT_ODD (0x01U << OTG_FS_STAT_ODD_Pos)
#define OTG_FS_STAT_TX_Pos (3)
#define OTG_FS_STAT_TX (0x01U << OTG_FS_STAT_TX_Pos)
#define OTG_FS_STAT_ENDP_Pos (4)
#define OTG_FS_STAT_ENDP (0x0FU << OTG_FS_STAT_ENDP_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_CTL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_CTL_USB_EN_SOF_EN_Pos (0)
#define OTG_FS_CTL_USB_EN_SOF_EN (0x01U << OTG_FS_CTL_USB_EN_SOF_EN_Pos)
#define OTG_FS_CTL_ODD_RST_Pos (1)
#define OTG_FS_CTL_ODD_RST (0x01U << OTG_FS_CTL_ODD_RST_Pos)
#define OTG_FS_CTL_RESUME_Pos (2)
#define OTG_FS_CTL_RESUME (0x01U << OTG_FS_CTL_RESUME_Pos)
#define OTG_FS_CTL_HOST_MODE_EN_Pos (3)
#define OTG_FS_CTL_HOST_MODE_EN (0x01U << OTG_FS_CTL_HOST_MODE_EN_Pos)
#define OTG_FS_CTL_RESET_Pos (4)
#define OTG_FS_CTL_RESET (0x01U << OTG_FS_CTL_RESET_Pos)
#define OTG_FS_CTL_TXDSUSPEND_TOKENBUSY_Pos (5)
#define OTG_FS_CTL_TXDSUSPEND_TOKENBUSY (0x01U << OTG_FS_CTL_TXDSUSPEND_TOKENBUSY_Pos)
#define OTG_FS_CTL_SE0_Pos (6)
#define OTG_FS_CTL_SE0 (0x01U << OTG_FS_CTL_SE0_Pos)
#define OTG_FS_CTL_JSTATE_Pos (7)
#define OTG_FS_CTL_JSTATE (0x01U << OTG_FS_CTL_JSTATE_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_ADDR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_ADDR_ADDR_Pos (0)
#define OTG_FS_ADDR_ADDR (0x7FU << OTG_FS_ADDR_ADDR_Pos)
#define OTG_FS_ADDR_LS_EN_Pos (7)
#define OTG_FS_ADDR_LS_EN (0x01U << OTG_FS_ADDR_LS_EN_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_BDT_PAGE_01 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_BDT_PAGE_01_BDT_BA_15_9_Pos (1)
#define OTG_FS_BDT_PAGE_01_BDT_BA_15_9 (0x7FU << OTG_FS_BDT_PAGE_01_BDT_BA_15_9_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_FRM_NUML Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_FRM_NUML_FRM_Pos (0)
#define OTG_FS_FRM_NUML_FRM (0xFFU << OTG_FS_FRM_NUML_FRM_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_FRM_NUMH Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_FRM_NUMH_FRM_Pos (0)
#define OTG_FS_FRM_NUMH_FRM (0x07U << OTG_FS_FRM_NUMH_FRM_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_TOKEN Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_TOKEN_TOKEN_ENDPT_Pos (0)
#define OTG_FS_TOKEN_TOKEN_ENDPT (0x0FU << OTG_FS_TOKEN_TOKEN_ENDPT_Pos)
#define OTG_FS_TOKEN_TOKEN_PID_Pos (4)
#define OTG_FS_TOKEN_TOKEN_PID (0x0FU << OTG_FS_TOKEN_TOKEN_PID_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_SOF_THLD Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_SOF_THLD_CNT_Pos (0)
#define OTG_FS_SOF_THLD_CNT (0xFFU << OTG_FS_SOF_THLD_CNT_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_BDT_PAGE_02 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_BDT_PAGE_02_BDT_BA_23_16_Pos (0)
#define OTG_FS_BDT_PAGE_02_BDT_BA_23_16 (0xFFU << OTG_FS_BDT_PAGE_02_BDT_BA_23_16_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_BDT_PAGE_03 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_BDT_PAGE_03_BDT_BA_31_24_Pos (0)
#define OTG_FS_BDT_PAGE_03_BDT_BA_31_24 (0xFFU << OTG_FS_BDT_PAGE_03_BDT_BA_31_24_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS_EP_CTL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_EP_CTL_EP_HSHK_Pos (0)
#define OTG_FS_EP_CTL_EP_HSHK (0x01U << OTG_FS_EP_CTL_EP_HSHK_Pos)
#define OTG_FS_EP_CTL_EP_STALL_Pos (1)
#define OTG_FS_EP_CTL_EP_STALL (0x01U << OTG_FS_EP_CTL_EP_STALL_Pos)
#define OTG_FS_EP_CTL_EP_TX_EN_Pos (2)
#define OTG_FS_EP_CTL_EP_TX_EN (0x01U << OTG_FS_EP_CTL_EP_TX_EN_Pos)
#define OTG_FS_EP_CTL_EP_RX_EN_Pos (3)
#define OTG_FS_EP_CTL_EP_RX_EN (0x01U << OTG_FS_EP_CTL_EP_RX_EN_Pos)
#define OTG_FS_EP_CTL_EP_CTL_DIS_Pos (4)
#define OTG_FS_EP_CTL_EP_CTL_DIS (0x01U << OTG_FS_EP_CTL_EP_CTL_DIS_Pos)
#define OTG_FS_EP_CTL_RETRY_DIS_Pos (6)
#define OTG_FS_EP_CTL_RETRY_DIS (0x01U << OTG_FS_EP_CTL_RETRY_DIS_Pos)
#define OTG_FS_EP_CTL_HOST_WO_HUB_Pos (7)
#define OTG_FS_EP_CTL_HOST_WO_HUB (0x01U << OTG_FS_EP_CTL_HOST_WO_HUB_Pos)
////////////////////////////////////////////////////////////////////////////////
/// @brief OTG_FS Buffer Descriptor Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define OTG_FS_BD_TOK_PID_Pos (2)
#define OTG_FS_BD_TOK_PID (0x0FU << OTG_FS_BD_TOK_PID_Pos)
#define OTG_FS_BD_DATA01_Pos (6)
#define OTG_FS_BD_DATA01 (0x01U << OTG_FS_BD_DATA01_Pos)
#define OTG_FS_BD_OWN_Pos (7)
#define OTG_FS_BD_OWN (0x01U << OTG_FS_BD_OWN_Pos)
#define OTG_FS_BD_BC_Pos (16)
#define OTG_FS_BD_BC (0x3FFU << OTG_FS_BD_BC_Pos)
#define OTG_FS_BD_ADDRESS_Pos (0)
#define OTG_FS_BD_ADDRESS (0xFFFFFFFFU << OTG_FS_BD_ADDRESS_Pos)
/**
* @}
*/
//#define OTG_FS_INT_STAT_RST ((uint32_t)0x01)
//#define OTG_FS_INT_STAT_ERROR ((uint32_t)0x02)
//#define OTG_FS_INT_STAT_SOF ((uint32_t)0x04)
//#define OTG_FS_INT_STAT_DNE ((uint32_t)0x08)
//#define OTG_FS_INT_STAT_SLEEP ((uint32_t)0x10)
//#define OTG_FS_INT_STAT_RESUME ((uint32_t)0x20)
//#define OTG_FS_INT_STAT_ATTACH ((uint32_t)0x40)
//#define OTG_FS_INT_STAT_STALL ((uint32_t)0x80)
//TEMP
#define USB_INT_STAT_RST 0x01
#define USB_INT_STAT_ERROR 0x02
#define USB_INT_STAT_SOF_TOK 0x04
#define USB_INT_STAT_TOK_DNE 0x08
#define USB_INT_STAT_SLEEP 0x10
#define USB_INT_STAT_RESUME 0x20
#define USB_INT_STAT_ATTACH 0x40
#define USB_INT_STAT_STALL 0x80
/*! @name PERID - Peripheral ID register */
#define USB_PERID_ID_MASK (0x3FU)
#define USB_PERID_ID_SHIFT (0U)
#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
/*! @name IDCOMP - Peripheral ID Complement register */
#define USB_IDCOMP_NID_MASK (0x3FU)
#define USB_IDCOMP_NID_SHIFT (0U)
#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
/*! @name REV - Peripheral Revision register */
#define USB_REV_REV_MASK (0xFFU)
#define USB_REV_REV_SHIFT (0U)
#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
/*! @name ADDINFO - Peripheral Additional Info register */
#define USB_ADDINFO_IEHOST_MASK (0x1U)
#define USB_ADDINFO_IEHOST_SHIFT (0U)
#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
/*! @name OTGISTAT - OTG Interrupt Status register */
#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
#define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
#define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
/*! @name OTGICR - OTG Interrupt Control register */
#define USB_OTGICR_LINESTATEEN_MASK (0x20U)
#define USB_OTGICR_LINESTATEEN_SHIFT (5U)
#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
#define USB_OTGICR_ONEMSECEN_MASK (0x40U)
#define USB_OTGICR_ONEMSECEN_SHIFT (6U)
#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
/*! @name OTGSTAT - OTG Status register */
#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
/*! @name OTGCTL - OTG Control register */
#define USB_OTGCTL_OTGEN_MASK (0x4U)
#define USB_OTGCTL_OTGEN_SHIFT (2U)
#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
#define USB_OTGCTL_DMLOW_MASK (0x10U)
#define USB_OTGCTL_DMLOW_SHIFT (4U)
#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
#define USB_OTGCTL_DPLOW_MASK (0x20U)
#define USB_OTGCTL_DPLOW_SHIFT (5U)
#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
#define USB_OTGCTL_DPHIGH_MASK (0x80U)
#define USB_OTGCTL_DPHIGH_SHIFT (7U)
#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
/*! @name ISTAT - Interrupt Status register */
#define USB_ISTAT_USBRST_MASK (0x1U)
#define USB_ISTAT_USBRST_SHIFT (0U)
#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
#define USB_ISTAT_ERROR_MASK (0x2U)
#define USB_ISTAT_ERROR_SHIFT (1U)
#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
#define USB_ISTAT_SOFTOK_MASK (0x4U)
#define USB_ISTAT_SOFTOK_SHIFT (2U)
#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
#define USB_ISTAT_TOKDNE_MASK (0x8U)
#define USB_ISTAT_TOKDNE_SHIFT (3U)
#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
#define USB_ISTAT_SLEEP_MASK (0x10U)
#define USB_ISTAT_SLEEP_SHIFT (4U)
#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
#define USB_ISTAT_RESUME_MASK (0x20U)
#define USB_ISTAT_RESUME_SHIFT (5U)
#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
#define USB_ISTAT_ATTACH_MASK (0x40U)
#define USB_ISTAT_ATTACH_SHIFT (6U)
#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
#define USB_ISTAT_STALL_MASK (0x80U)
#define USB_ISTAT_STALL_SHIFT (7U)
#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
/*! @name INTEN - Interrupt Enable register */
#define USB_INTEN_USBRSTEN_MASK (0x1U)
#define USB_INTEN_USBRSTEN_SHIFT (0U)
#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
#define USB_INTEN_ERROREN_MASK (0x2U)
#define USB_INTEN_ERROREN_SHIFT (1U)
#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
#define USB_INTEN_SOFTOKEN_MASK (0x4U)
#define USB_INTEN_SOFTOKEN_SHIFT (2U)
#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
#define USB_INTEN_TOKDNEEN_MASK (0x8U)
#define USB_INTEN_TOKDNEEN_SHIFT (3U)
#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
#define USB_INTEN_SLEEPEN_MASK (0x10U)
#define USB_INTEN_SLEEPEN_SHIFT (4U)
#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
#define USB_INTEN_RESUMEEN_MASK (0x20U)
#define USB_INTEN_RESUMEEN_SHIFT (5U)
#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
#define USB_INTEN_ATTACHEN_MASK (0x40U)
#define USB_INTEN_ATTACHEN_SHIFT (6U)
#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
#define USB_INTEN_STALLEN_MASK (0x80U)
#define USB_INTEN_STALLEN_SHIFT (7U)
#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
/*! @name ERRSTAT - Error Interrupt Status register */
#define USB_ERRSTAT_PIDERR_MASK (0x1U)
#define USB_ERRSTAT_PIDERR_SHIFT (0U)
#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
#define USB_ERRSTAT_CRC16_MASK (0x4U)
#define USB_ERRSTAT_CRC16_SHIFT (2U)
#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
#define USB_ERRSTAT_DFN8_MASK (0x8U)
#define USB_ERRSTAT_DFN8_SHIFT (3U)
#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
#define USB_ERRSTAT_BTOERR_MASK (0x10U)
#define USB_ERRSTAT_BTOERR_SHIFT (4U)
#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
#define USB_ERRSTAT_DMAERR_MASK (0x20U)
#define USB_ERRSTAT_DMAERR_SHIFT (5U)
#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
#define USB_ERRSTAT_OWNERR_MASK (0x40U)
#define USB_ERRSTAT_OWNERR_SHIFT (6U)
#define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK)
#define USB_ERRSTAT_BTSERR_MASK (0x80U)
#define USB_ERRSTAT_BTSERR_SHIFT (7U)
#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
/*! @name ERREN - Error Interrupt Enable register */
#define USB_ERREN_PIDERREN_MASK (0x1U)
#define USB_ERREN_PIDERREN_SHIFT (0U)
#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
#define USB_ERREN_CRC16EN_MASK (0x4U)
#define USB_ERREN_CRC16EN_SHIFT (2U)
#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
#define USB_ERREN_DFN8EN_MASK (0x8U)
#define USB_ERREN_DFN8EN_SHIFT (3U)
#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
#define USB_ERREN_BTOERREN_MASK (0x10U)
#define USB_ERREN_BTOERREN_SHIFT (4U)
#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
#define USB_ERREN_DMAERREN_MASK (0x20U)
#define USB_ERREN_DMAERREN_SHIFT (5U)
#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
#define USB_ERREN_OWNERREN_MASK (0x40U)
#define USB_ERREN_OWNERREN_SHIFT (6U)
#define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK)
#define USB_ERREN_BTSERREN_MASK (0x80U)
#define USB_ERREN_BTSERREN_SHIFT (7U)
#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
/*! @name STAT - Status register */
#define USB_STAT_ODD_MASK (0x4U)
#define USB_STAT_ODD_SHIFT (2U)
#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
#define USB_STAT_TX_MASK (0x8U)
#define USB_STAT_TX_SHIFT (3U)
#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
#define USB_STAT_ENDP_MASK (0xF0U)
#define USB_STAT_ENDP_SHIFT (4U)
#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
/*! @name CTL - Control register */
#define USB_CTL_USBENSOFEN_MASK (0x1U)
#define USB_CTL_USBENSOFEN_SHIFT (0U)
#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
#define USB_CTL_ODDRST_MASK (0x2U)
#define USB_CTL_ODDRST_SHIFT (1U)
#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
#define USB_CTL_RESUME_MASK (0x4U)
#define USB_CTL_RESUME_SHIFT (2U)
#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
#define USB_CTL_HOSTMODEEN_MASK (0x8U)
#define USB_CTL_HOSTMODEEN_SHIFT (3U)
#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
#define USB_CTL_RESET_MASK (0x10U)
#define USB_CTL_RESET_SHIFT (4U)
#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
#define USB_CTL_SE0_MASK (0x40U)
#define USB_CTL_SE0_SHIFT (6U)
#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
#define USB_CTL_JSTATE_MASK (0x80U)
#define USB_CTL_JSTATE_SHIFT (7U)
#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
/*! @name ADDR - Address register */
#define USB_ADDR_ADDR_MASK (0x7FU)
#define USB_ADDR_ADDR_SHIFT (0U)
#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
#define USB_ADDR_LSEN_MASK (0x80U)
#define USB_ADDR_LSEN_SHIFT (7U)
#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
/*! @name BDTPAGE1 - BDT Page register 1 */
#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
/*! @name FRMNUML - Frame Number register Low */
#define USB_FRMNUML_FRM_MASK (0xFFU)
#define USB_FRMNUML_FRM_SHIFT (0U)
#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
/*! @name FRMNUMH - Frame Number register High */
#define USB_FRMNUMH_FRM_MASK (0x7U)
#define USB_FRMNUMH_FRM_SHIFT (0U)
#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
/*! @name TOKEN - Token register */
#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
#define USB_TOKEN_TOKENPID_MASK (0xF0U)
#define USB_TOKEN_TOKENPID_SHIFT (4U)
#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
/*! @name SOFTHLD - SOF Threshold register */
#define USB_SOFTHLD_CNT_MASK (0xFFU)
#define USB_SOFTHLD_CNT_SHIFT (0U)
#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
/*! @name BDTPAGE2 - BDT Page Register 2 */
#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
/*! @name BDTPAGE3 - BDT Page Register 3 */
#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
/*! @name ENDPT - Endpoint Control register */
#define USB_ENDPT_EPHSHK_MASK (0x1U)
#define USB_ENDPT_EPHSHK_SHIFT (0U)
#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
#define USB_ENDPT_EPSTALL_MASK (0x2U)
#define USB_ENDPT_EPSTALL_SHIFT (1U)
#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
#define USB_ENDPT_EPTXEN_MASK (0x4U)
#define USB_ENDPT_EPTXEN_SHIFT (2U)
#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
#define USB_ENDPT_EPRXEN_MASK (0x8U)
#define USB_ENDPT_EPRXEN_SHIFT (3U)
#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
#define USB_ENDPT_RETRYDIS_MASK (0x40U)
#define USB_ENDPT_RETRYDIS_SHIFT (6U)
#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
#define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
#define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
/* The count of USB_ENDPT */
#define USB_ENDPT_COUNT (16U)
/*! @name USBCTRL - USB Control register */
#define USB_USBCTRL_UARTSEL_MASK (0x10U)
#define USB_USBCTRL_UARTSEL_SHIFT (4U)
#define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK)
#define USB_USBCTRL_UARTCHLS_MASK (0x20U)
#define USB_USBCTRL_UARTCHLS_SHIFT (5U)
#define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK)
#define USB_USBCTRL_PDE_MASK (0x40U)
#define USB_USBCTRL_PDE_SHIFT (6U)
#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
#define USB_USBCTRL_SUSP_MASK (0x80U)
#define USB_USBCTRL_SUSP_SHIFT (7U)
#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
/*! @name OBSERVE - USB OTG Observe register */
#define USB_OBSERVE_DMPD_MASK (0x10U)
#define USB_OBSERVE_DMPD_SHIFT (4U)
#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
#define USB_OBSERVE_DPPD_MASK (0x40U)
#define USB_OBSERVE_DPPD_SHIFT (6U)
#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
#define USB_OBSERVE_DPPU_MASK (0x80U)
#define USB_OBSERVE_DPPU_SHIFT (7U)
#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
/*! @name CONTROL - USB OTG Control register */
#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
/*! @name USBTRC0 - USB Transceiver Control register 0 */
#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
#define USB_USBTRC0_VREDG_DET_MASK (0x8U)
#define USB_USBTRC0_VREDG_DET_SHIFT (3U)
#define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK)
#define USB_USBTRC0_VFEDG_DET_MASK (0x10U)
#define USB_USBTRC0_VFEDG_DET_SHIFT (4U)
#define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK)
#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
#define USB_USBTRC0_USBRESET_MASK (0x80U)
#define USB_USBTRC0_USBRESET_SHIFT (7U)
#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
/*! @name USBFRMADJUST - Frame Adjust Register */
#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
/*! @name MISCCTRL - Miscellaneous Control register */
#define USB_MISCCTRL_SOFDYNTHLD_MASK (0x1U)
#define USB_MISCCTRL_SOFDYNTHLD_SHIFT (0U)
#define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK)
#define USB_MISCCTRL_SOFBUSSET_MASK (0x2U)
#define USB_MISCCTRL_SOFBUSSET_SHIFT (1U)
#define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK)
#define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U)
#define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U)
#define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK)
#define USB_MISCCTRL_VREDG_EN_MASK (0x8U)
#define USB_MISCCTRL_VREDG_EN_SHIFT (3U)
#define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK)
#define USB_MISCCTRL_VFEDG_EN_MASK (0x10U)
#define USB_MISCCTRL_VFEDG_EN_SHIFT (4U)
#define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK)
#define USB_MISCCTRL_STL_ADJ_EN_MASK (0x80U)
#define USB_MISCCTRL_STL_ADJ_EN_SHIFT (7U)
#define USB_MISCCTRL_STL_ADJ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK)
/*! @name STALL_IL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in IN direction */
#define USB_STALL_IL_DIS_STALL_I_DIS0_MASK (0x1U)
#define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT (0U)
#define USB_STALL_IL_DIS_STALL_I_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK)
#define USB_STALL_IL_DIS_STALL_I_DIS1_MASK (0x2U)
#define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT (1U)
#define USB_STALL_IL_DIS_STALL_I_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK)
#define USB_STALL_IL_DIS_STALL_I_DIS2_MASK (0x4U)
#define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT (2U)
#define USB_STALL_IL_DIS_STALL_I_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK)
#define USB_STALL_IL_DIS_STALL_I_DIS3_MASK (0x8U)
#define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT (3U)
#define USB_STALL_IL_DIS_STALL_I_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK)
#define USB_STALL_IL_DIS_STALL_I_DIS4_MASK (0x10U)
#define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT (4U)
#define USB_STALL_IL_DIS_STALL_I_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK)
#define USB_STALL_IL_DIS_STALL_I_DIS5_MASK (0x20U)
#define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT (5U)
#define USB_STALL_IL_DIS_STALL_I_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK)
#define USB_STALL_IL_DIS_STALL_I_DIS6_MASK (0x40U)
#define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT (6U)
#define USB_STALL_IL_DIS_STALL_I_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK)
#define USB_STALL_IL_DIS_STALL_I_DIS7_MASK (0x80U)
#define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT (7U)
#define USB_STALL_IL_DIS_STALL_I_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK)
/*! @name STALL_IH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in IN direction */
#define USB_STALL_IH_DIS_STALL_I_DIS8_MASK (0x1U)
#define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT (0U)
#define USB_STALL_IH_DIS_STALL_I_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK)
#define USB_STALL_IH_DIS_STALL_I_DIS9_MASK (0x2U)
#define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT (1U)
#define USB_STALL_IH_DIS_STALL_I_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK)
#define USB_STALL_IH_DIS_STALL_I_DIS10_MASK (0x4U)
#define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT (2U)
#define USB_STALL_IH_DIS_STALL_I_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK)
#define USB_STALL_IH_DIS_STALL_I_DIS11_MASK (0x8U)
#define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT (3U)
#define USB_STALL_IH_DIS_STALL_I_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK)
#define USB_STALL_IH_DIS_STALL_I_DIS12_MASK (0x10U)
#define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT (4U)
#define USB_STALL_IH_DIS_STALL_I_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK)
#define USB_STALL_IH_DIS_STALL_I_DIS13_MASK (0x20U)
#define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT (5U)
#define USB_STALL_IH_DIS_STALL_I_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK)
#define USB_STALL_IH_DIS_STALL_I_DIS14_MASK (0x40U)
#define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT (6U)
#define USB_STALL_IH_DIS_STALL_I_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK)
#define USB_STALL_IH_DIS_STALL_I_DIS15_MASK (0x80U)
#define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT (7U)
#define USB_STALL_IH_DIS_STALL_I_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK)
/*! @name STALL_OL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in OUT direction */
#define USB_STALL_OL_DIS_STALL_O_DIS0_MASK (0x1U)
#define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT (0U)
#define USB_STALL_OL_DIS_STALL_O_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK)
#define USB_STALL_OL_DIS_STALL_O_DIS1_MASK (0x2U)
#define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT (1U)
#define USB_STALL_OL_DIS_STALL_O_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK)
#define USB_STALL_OL_DIS_STALL_O_DIS2_MASK (0x4U)
#define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT (2U)
#define USB_STALL_OL_DIS_STALL_O_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK)
#define USB_STALL_OL_DIS_STALL_O_DIS3_MASK (0x8U)
#define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT (3U)
#define USB_STALL_OL_DIS_STALL_O_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK)
#define USB_STALL_OL_DIS_STALL_O_DIS4_MASK (0x10U)
#define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT (4U)
#define USB_STALL_OL_DIS_STALL_O_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK)
#define USB_STALL_OL_DIS_STALL_O_DIS5_MASK (0x20U)
#define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT (5U)
#define USB_STALL_OL_DIS_STALL_O_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK)
#define USB_STALL_OL_DIS_STALL_O_DIS6_MASK (0x40U)
#define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT (6U)
#define USB_STALL_OL_DIS_STALL_O_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK)
#define USB_STALL_OL_DIS_STALL_O_DIS7_MASK (0x80U)
#define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT (7U)
#define USB_STALL_OL_DIS_STALL_O_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK)
/*! @name STALL_OH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in OUT direction */
#define USB_STALL_OH_DIS_STALL_O_DIS8_MASK (0x1U)
#define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT (0U)
#define USB_STALL_OH_DIS_STALL_O_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK)
#define USB_STALL_OH_DIS_STALL_O_DIS9_MASK (0x2U)
#define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT (1U)
#define USB_STALL_OH_DIS_STALL_O_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK)
#define USB_STALL_OH_DIS_STALL_O_DIS10_MASK (0x4U)
#define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT (2U)
#define USB_STALL_OH_DIS_STALL_O_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK)
#define USB_STALL_OH_DIS_STALL_O_DIS11_MASK (0x8U)
#define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT (3U)
#define USB_STALL_OH_DIS_STALL_O_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK)
#define USB_STALL_OH_DIS_STALL_O_DIS12_MASK (0x10U)
#define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT (4U)
#define USB_STALL_OH_DIS_STALL_O_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK)
#define USB_STALL_OH_DIS_STALL_O_DIS13_MASK (0x20U)
#define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT (5U)
#define USB_STALL_OH_DIS_STALL_O_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK)
#define USB_STALL_OH_DIS_STALL_O_DIS14_MASK (0x40U)
#define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT (6U)
#define USB_STALL_OH_DIS_STALL_O_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK)
#define USB_STALL_OH_DIS_STALL_O_DIS15_MASK (0x80U)
#define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT (7U)
#define USB_STALL_OH_DIS_STALL_O_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK)
/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U)
#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U)
#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
#define USB0_BASE ((0x50000000))
#define USB_BASE_ADDRS { USB0_BASE }
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif //__REG_USB_OTG_FS_H
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h
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////////////////////////////////////////////////////////////////////////////////
/// @file reg_wwdg.h
/// @author AE TEAM
/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
/// MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __REG_WWDG_H
#define __REG_WWDG_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#include "types.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief WWDG Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) ///< Base Address: 0x40002C00
////////////////////////////////////////////////////////////////////////////////
/// @brief WWDG Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
#undef USENCOMBINEREGISTER
#undef USENNEWREGISTER
#undef USENOLDREGISTER
#define USENCOMBINEREGISTER
#ifdef USENCOMBINEREGISTER
typedef struct {
__IO u32 CR; ///< Control register offset: 0x00
union {
__IO u32 CFGR; ///< Configuration register offset: 0x04
__IO u32 CFR;
};
__IO u32 SR; ///< Status register offset: 0x08
} WWDG_TypeDef;
#endif
#ifdef USENNEWREGISTER
typedef struct {
__IO u32 CR; ///< Control register offset: 0x00
__IO u32 CFGR; ///< Configuration register offset: 0x04
__IO u32 SR; ///< Status register offset: 0x08
} WWDG_TypeDef;
#endif
#ifdef USENOLDREGISTER
typedef struct {
__IO u32 CR;
__IO u32 CFR;
__IO u32 SR;
} WWDG_TypeDef;
#endif
////////////////////////////////////////////////////////////////////////////////
/// @brief WWDG type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define WWDG ((WWDG_TypeDef*) WWDG_BASE)
////////////////////////////////////////////////////////////////////////////////
/// @brief WWDG_CR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define WWDG_CR_CNT_Pos (0)
#define WWDG_CR_CNT (0x7FU << WWDG_CR_CNT_Pos) ///< T[6:0] bits (7-Bit counter (MSB to LSB))
#define WWDG_CR_WDGA_Pos (7)
#define WWDG_CR_WDGA (0x01U << WWDG_CR_WDGA_Pos) ///< Activation bit
////////////////////////////////////////////////////////////////////////////////
/// @brief WWDG_CFR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define WWDG_CFGR_WINDOW_Pos (0)
#define WWDG_CFGR_WINDOW (0x7FU << WWDG_CFGR_WINDOW_Pos) ///< W[6:0] bits (7-bit window value)
#define WWDG_CFGR_WDGTB_Pos (7)
#define WWDG_CFGR_WDGTB (0x03U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base)
#define WWDG_CFGR_WDGTB_1 (0x00U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /1)
#define WWDG_CFGR_WDGTB_2 (0x01U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /2)
#define WWDG_CFGR_WDGTB_4 (0x02U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /4)
#define WWDG_CFGR_WDGTB_8 (0x03U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /8)
#define WWDG_CFGR_EWI_Pos (9)
#define WWDG_CFGR_EWI (0x01U << WWDG_CFGR_EWI_Pos) ///< Early Wakeup Interrupt
////////////////////////////////////////////////////////////////////////////////
/// @brief WWDG_SR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define WWDG_SR_EWIF_Pos (0)
#define WWDG_SR_EWIF (0x01U << WWDG_SR_EWIF_Pos) ///< Early Wakeup Interrupt Flag
/// @}
/// @}
/// @}
////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h
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////////////////////////////////////////////////////////////////////////////////
/// @file types.h
/// @author AE TEAM
/// @brief THIS FILE PROVIDES ALL THE TYPE FIRMWARE FUNCTIONS.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#ifndef __TYPES_H
#define __TYPES_H
// Files includes
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
#define __I volatile ///< Defines 'read only' permissions
#else
#define __I volatile const ///< Defines 'read only' permissions
#endif
#define __O volatile ///< Defines 'write only' permissions
#define __IO volatile ///< Defines 'read / write' permissions
typedef long long s64; ///< used for signed 64bit
typedef signed int s32;
typedef signed short s16;
typedef signed char s8;
typedef signed int const sc32; ///< Read Only
typedef signed short const sc16; ///< Read Only
typedef signed char const sc8; ///< Read Only
typedef volatile signed int vs32;
typedef volatile signed short vs16;
typedef volatile signed char vs8;
typedef volatile signed int const vsc32; ///< Read Only
typedef volatile signed short const vsc16; ///< Read Only
typedef volatile signed char const vsc8; ///< Read Only
typedef unsigned int u32;
typedef unsigned short u16;
typedef unsigned char u8;
typedef unsigned int const uc32; ///< Read Only
typedef unsigned short const uc16; ///< Read Only
typedef unsigned char const uc8; ///< Read Only
typedef volatile unsigned int vu32;
typedef volatile unsigned short vu16;
typedef volatile unsigned char vu8;
typedef volatile unsigned int const vuc32; ///< Read Only
typedef volatile unsigned short const vuc16; ///< Read Only
typedef volatile unsigned char const vuc8; ///< Read Only
typedef bool BOOL;
#ifndef NULL
#define NULL ((void *)0)
#endif
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
#define U8_MAX ((u8)255)
#define S8_MAX ((s8)127)
#define S8_MIN ((s8)-128)
#define U16_MAX ((u16)65535u)
#define S16_MAX ((s16)32767)
#define S16_MIN ((s16)-32768)
#define U32_MAX ((u32)4294967295uL)
#define S32_MAX ((s32)2147483647)
#define S32_MIN ((s32)-2147483648uL)
#define MAX(a,b)((a)>(b)?(a):(b))
#define MIN(a,b)((a)<(b)?(a):(b))
#define SET_BIT(reg, bit) ((reg) |= (bit))
#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit))
#define READ_BIT(reg, bit) ((reg) & (bit))
#define CLEAR_REG(reg) ((reg) = (0x0))
#define WRITE_REG(reg, value) ((reg) = (value))
#define READ_REG(reg) ((reg))
#define MODIFY_REG(reg, CLEARMASK, SETMASK) WRITE_REG((reg), (((READ_REG(reg)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(value) (__CLZ(__RBIT(value)))
#define LEFT_SHIFT_BIT(x) (1 << x)
#endif