Add MM32 SDK and USB driver
Signed-off-by: zhangslice <1304224508@qq.com>
This commit is contained in:
zhangslice
@@ -0,0 +1,440 @@
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/**
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******************************************************************************
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* @file startup_mm32m3ux_u_gcc.s
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* @author AE Team
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* @brief MM32 devices vector table for GCC toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M3 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m3
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2], #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call static constructors */
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bl __libc_init_array
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/* Call the application's entry point.*/
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bl main
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bx lr
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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* @param None
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* @retval None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M3. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack /* Top of Stack */
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.word Reset_Handler /* Reset Handler */
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.word NMI_Handler /*-14 NMI Handler */
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.word HardFault_Handler /*-13 Hard Fault Handler */
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.word MemManage_Handler /*-12 MPU Fault Handler */
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.word BusFault_Handler /*-11 Bus Fault Handler */
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.word UsageFault_Handler /*-10 Usage Fault Handler */
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.word 0 /*-9 Reserved */
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.word 0 /*-8 Reserved */
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.word 0 /*-7 Reserved */
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.word 0 /*-6 Reserved */
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.word SVC_Handler /*-5 SVCall Handler */
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.word DebugMon_Handler /*-4 Debug Monitor Handler */
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.word 0 /*-3 Reserved */
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.word PendSV_Handler /*-2 PendSV Handler */
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.word SysTick_Handler /*-1 SysTick Handler */
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/* External Interrupts */
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.word WWDG_IRQHandler /*0 Window Watchdog */
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.word PVD_IRQHandler /*1 PVD through EXTI Line detect */
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.word TAMPER_IRQHandler /*2 Tamper */
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.word RTC_IRQHandler /*3 RTC */
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.word FLASH_IRQHandler /*4 Flash */
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.word RCC_CRS_IRQHandler /*5 RCC */
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.word EXTI0_IRQHandler /*6 EXTI Line 0 */
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.word EXTI1_IRQHandler /*7 EXTI Line 1 */
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.word EXTI2_IRQHandler /*8 EXTI Line 2 */
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.word EXTI3_IRQHandler /*9 EXTI Line 3 */
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.word EXTI4_IRQHandler /*10 EXTI Line 4 */
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.word DMA1_Channel1_IRQHandler /*11 DMA1 Channel 1 */
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.word DMA1_Channel2_IRQHandler /*12 DMA1 Channel 2 */
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.word DMA1_Channel3_IRQHandler /*13 DMA1 Channel 3 */
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.word DMA1_Channel4_IRQHandler /*14 DMA1 Channel 4 */
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.word DMA1_Channel5_IRQHandler /*15 DMA1 Channel 5 */
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.word DMA1_Channel6_IRQHandler /*16 DMA1 Channel 6 */
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.word DMA1_Channel7_IRQHandler /*17 DMA1 Channel 7 */
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.word ADC1_2_IRQHandler /*18 ADC1 and ADC2 */
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.word FlashCache_IRQHandler /*19 FlashCache outage */
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.word 0 /*20 Reserved */
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.word CAN1_RX_IRQHandler /*21 CAN1_RX */
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.word 0 /*22 Reserved */
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.word EXTI9_5_IRQHandler /*23 EXTI Line 9..5 */
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.word TIM1_BRK_IRQHandler /*24 TIM1 Break */
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.word TIM1_UP_IRQHandler /*25 TIM1 Update */
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.word TIM1_TRG_COM_IRQHandler /*26 TIM1 Trigger and Commutation */
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.word TIM1_CC_IRQHandler /*27 TIM1 Capture Compare */
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.word TIM2_IRQHandler /*28 TIM2 */
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.word TIM3_IRQHandler /*29 TIM3 */
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.word TIM4_IRQHandler /*30 TIM4 */
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.word I2C1_IRQHandler /*31 I2C1 Event */
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.word 0 /*32 Reserved */
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.word I2C2_IRQHandler /*33 I2C2 Event */
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.word 0 /*34 Reserved */
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.word SPI1_IRQHandler /*35 SPI1 */
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.word SPI2_IRQHandler /*36 SPI2 */
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.word UART1_IRQHandler /*37 UART1 */
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.word UART2_IRQHandler /*38 UART2 */
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.word UART3_IRQHandler /*39 UART3 */
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.word EXTI15_10_IRQHandler /*40 EXTI Line 15..10 */
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.word RTCAlarm_IRQHandler /*41 RTC Alarm through EXTI Line 17 */
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.word OTG_FS_WKUP_IRQHandler /*42 USB OTG FS Wakeup through EXTI line */
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.word TIM8_BRK_IRQHandler /*43 TIM8 Break */
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.word TIM8_UP_IRQHandler /*44 TIM8 Update */
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.word TIM8_TRG_COM_IRQHandler /*45 TIM8 Trigger and Commutation */
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.word TIM8_CC_IRQHandler /*46 TIM8 Capture Compare */
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.word ADC3_IRQHandler /*47 ADC3 */
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.word 0 /*48 Reserved */
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.word SDIO_IRQHandler /*49 SDIO */
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.word TIM5_IRQHandler /*50 TIM5 */
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.word SPI3_IRQHandler /*51 SPI3 */
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.word UART4_IRQHandler /*52 UART4 */
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.word UART5_IRQHandler /*53 UART5 */
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.word TIM6_IRQHandler /*54 TIM6 */
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.word TIM7_IRQHandler /*55 TIM7 */
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.word DMA2_Channel1_IRQHandler /*56 DMA2 Channel 1 */
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.word DMA2_Channel2_IRQHandler /*57 DMA2 Channel 2 */
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.word DMA2_Channel3_IRQHandler /*58 DMA2 Channel 3 */
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.word DMA2_Channel4_IRQHandler /*59 DMA2 Channel 4 */
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.word DMA2_Channel5_IRQHandler /*60 DMA2 Channel 5 */
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.word ETH_IRQHandler /*61 Ethernet */
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.word 0 /*62 Reserved */
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.word 0 /*63 Reserved */
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.word COMP1_2_IRQHandler /*64 COMP1,COMP2 */
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.word 0 /*65 Reserved */
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.word 0 /*66 Reserved */
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.word OTG_FS_IRQHandler /*67 USB OTG_FullSpeed */
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.word 0 /*68 Reserved */
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.word 0 /*69 Reserved */
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.word 0 /*70 Reserved */
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.word UART6_IRQHandler /*71 UART6 */
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.word 0 /*72 Reserved */
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.word 0 /*73 Reserved */
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.word 0 /*74 Reserved */
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.word 0 /*75 Reserved */
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.word 0 /*76 Reserved */
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.word 0 /*77 Reserved */
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.word 0 /*78 Reserved */
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.word 0 /*79 Reserved */
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.word 0 /*80 Reserved */
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.word 0 /*81 Reserved */
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.word UART7_IRQHandler /*82 UART7 */
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.word UART8_IRQHandler /*83 UART8 */
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/*******************************************************************************
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*
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* Provide weak aliases for each Exception handler to the Default_Handler.
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* As they are weak aliases, any function with the same name will override
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* this definition.
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*
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*******************************************************************************/
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.weak NMI_Handler
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.thumb_set NMI_Handler ,Default_Handler
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.weak HardFault_Handler
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.thumb_set HardFault_Handler ,Default_Handler
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.weak MemManage_Handler
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.thumb_set MemManage_Handler ,Default_Handler
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.weak BusFault_Handler
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.thumb_set BusFault_Handler ,Default_Handler
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.weak UsageFault_Handler
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.thumb_set UsageFault_Handler ,Default_Handler
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.weak SVC_Handler
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.thumb_set SVC_Handler ,Default_Handler
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.weak DebugMon_Handler
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.thumb_set DebugMon_Handler ,Default_Handler
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.weak PendSV_Handler
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.thumb_set PendSV_Handler ,Default_Handler
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.weak SysTick_Handler
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.thumb_set SysTick_Handler ,Default_Handler
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.weak WWDG_IRQHandler
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.thumb_set WWDG_IRQHandler ,Default_Handler
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.weak PVD_IRQHandler
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.thumb_set PVD_IRQHandler ,Default_Handler
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.weak TAMPER_IRQHandler
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.thumb_set TAMPER_IRQHandler ,Default_Handler
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.weak RTC_IRQHandler
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.thumb_set RTC_IRQHandler ,Default_Handler
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.weak FLASH_IRQHandler
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.thumb_set FLASH_IRQHandler ,Default_Handler
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.weak RCC_CRS_IRQHandler
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.thumb_set RCC_CRS_IRQHandler ,Default_Handler
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.weak EXTI0_IRQHandler
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.thumb_set EXTI0_IRQHandler ,Default_Handler
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.weak EXTI1_IRQHandler
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.thumb_set EXTI1_IRQHandler ,Default_Handler
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.weak EXTI2_IRQHandler
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.thumb_set EXTI2_IRQHandler ,Default_Handler
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.weak EXTI3_IRQHandler
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.thumb_set EXTI3_IRQHandler ,Default_Handler
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.weak EXTI4_IRQHandler
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.thumb_set EXTI4_IRQHandler ,Default_Handler
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.weak DMA1_Channel1_IRQHandler
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.thumb_set DMA1_Channel1_IRQHandler ,Default_Handler
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.weak DMA1_Channel2_IRQHandler
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.thumb_set DMA1_Channel2_IRQHandler ,Default_Handler
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.weak DMA1_Channel3_IRQHandler
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.thumb_set DMA1_Channel3_IRQHandler ,Default_Handler
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.weak DMA1_Channel4_IRQHandler
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.thumb_set DMA1_Channel4_IRQHandler ,Default_Handler
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.weak DMA1_Channel5_IRQHandler
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.thumb_set DMA1_Channel5_IRQHandler ,Default_Handler
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.weak DMA1_Channel6_IRQHandler
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.thumb_set DMA1_Channel6_IRQHandler ,Default_Handler
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.weak DMA1_Channel7_IRQHandler
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.thumb_set DMA1_Channel7_IRQHandler ,Default_Handler
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.weak ADC1_2_IRQHandler
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.thumb_set ADC1_2_IRQHandler ,Default_Handler
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.weak FlashCache_IRQHandler
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.thumb_set FlashCache_IRQHandler ,Default_Handler
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.weak CAN1_RX_IRQHandler
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.thumb_set CAN1_RX_IRQHandler ,Default_Handler
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.weak EXTI9_5_IRQHandler
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.thumb_set EXTI9_5_IRQHandler ,Default_Handler
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.weak TIM1_BRK_IRQHandler
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.thumb_set TIM1_BRK_IRQHandler ,Default_Handler
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.weak TIM1_UP_IRQHandler
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.thumb_set TIM1_UP_IRQHandler ,Default_Handler
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.weak TIM1_TRG_COM_IRQHandler
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.thumb_set TIM1_TRG_COM_IRQHandler ,Default_Handler
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.weak TIM1_CC_IRQHandler
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.thumb_set TIM1_CC_IRQHandler ,Default_Handler
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.weak TIM2_IRQHandler
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.thumb_set TIM2_IRQHandler ,Default_Handler
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.weak TIM3_IRQHandler
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.thumb_set TIM3_IRQHandler ,Default_Handler
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.weak TIM4_IRQHandler
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.thumb_set TIM4_IRQHandler ,Default_Handler
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.weak I2C1_IRQHandler
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.thumb_set I2C1_IRQHandler ,Default_Handler
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.weak I2C2_IRQHandler
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.thumb_set I2C2_IRQHandler ,Default_Handler
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.weak SPI1_IRQHandler
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.thumb_set SPI1_IRQHandler ,Default_Handler
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.weak SPI2_IRQHandler
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.thumb_set SPI2_IRQHandler ,Default_Handler
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.weak UART1_IRQHandler
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.thumb_set UART1_IRQHandler ,Default_Handler
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.weak UART2_IRQHandler
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.thumb_set UART2_IRQHandler ,Default_Handler
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.weak UART3_IRQHandler
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.thumb_set UART3_IRQHandler ,Default_Handler
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.weak EXTI15_10_IRQHandler
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.thumb_set EXTI15_10_IRQHandler ,Default_Handler
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.weak RTCAlarm_IRQHandler
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.thumb_set RTCAlarm_IRQHandler ,Default_Handler
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.weak OTG_FS_WKUP_IRQHandler
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.thumb_set OTG_FS_WKUP_IRQHandler ,Default_Handler
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.weak TIM8_BRK_IRQHandler
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.thumb_set TIM8_BRK_IRQHandler ,Default_Handler
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.weak TIM8_UP_IRQHandler
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.thumb_set TIM8_UP_IRQHandler ,Default_Handler
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.weak TIM8_TRG_COM_IRQHandler
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.thumb_set TIM8_TRG_COM_IRQHandler ,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
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.thumb_set TIM8_CC_IRQHandler ,Default_Handler
|
||||
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||||
.weak ADC3_IRQHandler
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||||
.thumb_set ADC3_IRQHandler ,Default_Handler
|
||||
|
||||
.weak SDIO_IRQHandler
|
||||
.thumb_set SDIO_IRQHandler ,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler ,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler ,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler ,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler ,Default_Handler
|
||||
|
||||
.weak TIM6_IRQHandler
|
||||
.thumb_set TIM6_IRQHandler ,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler ,Default_Handler
|
||||
|
||||
.weak DMA2_Channel1_IRQHandler
|
||||
.thumb_set DMA2_Channel1_IRQHandler ,Default_Handler
|
||||
|
||||
.weak DMA2_Channel2_IRQHandler
|
||||
.thumb_set DMA2_Channel2_IRQHandler ,Default_Handler
|
||||
|
||||
.weak DMA2_Channel3_IRQHandler
|
||||
.thumb_set DMA2_Channel3_IRQHandler ,Default_Handler
|
||||
|
||||
.weak DMA2_Channel4_IRQHandler
|
||||
.thumb_set DMA2_Channel4_IRQHandler ,Default_Handler
|
||||
|
||||
.weak DMA2_Channel5_IRQHandler
|
||||
.thumb_set DMA2_Channel5_IRQHandler ,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler ,Default_Handler
|
||||
|
||||
.weak COMP1_2_IRQHandler
|
||||
.thumb_set COMP1_2_IRQHandler ,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler ,Default_Handler
|
||||
|
||||
.weak UART6_IRQHandler
|
||||
.thumb_set UART6_IRQHandler ,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler ,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler ,Default_Handler
|
||||
|
||||
|
||||
|
||||
|
||||
/****END OF FILE****/
|
||||
|
||||
@@ -0,0 +1,866 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @file SYSTEM_MM32.C
|
||||
/// @author AE TEAM
|
||||
/// @brief THIS FILE PROVIDES ALL THE SYSTEM FUNCTIONS.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/// @attention
|
||||
///
|
||||
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
///
|
||||
/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define to prevent recursive inclusion
|
||||
#define _SYSTEM_MM32_C_
|
||||
|
||||
// Files includes
|
||||
|
||||
/// @addtogroup CMSIS
|
||||
/// @{
|
||||
|
||||
#include "mm32_device.h"
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
/// Uncomment the line corresponding to the desired System clock (SYSCLK)
|
||||
/// frequency (after reset the HSI is used as SYSCLK source)
|
||||
///
|
||||
/// IMPORTANT NOTE:
|
||||
/// ==============
|
||||
/// 1. After each device reset the HSI is used as System clock source.
|
||||
///
|
||||
/// 2. Please make sure that the selected System clock doesn't exceed your device's
|
||||
/// maximum frequency.
|
||||
///
|
||||
/// 3. If none of the define below is enabled, the HSI is used as System clock
|
||||
/// source.
|
||||
///
|
||||
/// 4. The System clock configuration functions provided within this file assume that:
|
||||
/// - For Low, Medium and High density Value line devices an external 8MHz
|
||||
/// crystal is used to drive the System clock.
|
||||
/// - For Low, Medium and High density devices an external 8MHz crystal is
|
||||
/// used to drive the System clock.
|
||||
/// - For Connectivity line devices an external 25MHz crystal is used to drive
|
||||
/// the System clock.
|
||||
/// If you are using different crystal you have to adapt those functions accordingly.
|
||||
|
||||
//#define SYSCLK_FREQ_HSE HSE_VALUE //HSE_VALUE is define in reg_common.h
|
||||
//#define SYSCLK_FREQ_24MHz (HSE_VALUE*3) //24000000 based HSE_VALUE = 8000000
|
||||
//#define SYSCLK_FREQ_36MHz (HSE_VALUE*9/2) //36000000 based HSE_VALUE = 8000000
|
||||
//#define SYSCLK_FREQ_48MHz (HSE_VALUE*6) //48000000 based HSE_VALUE = 8000000
|
||||
//#define SYSCLK_FREQ_XXMHz (HSE_VALUE*6) //48000000 based HSE_VALUE = 8000000
|
||||
//#define SYSCLK_FREQ_XXMHz (HSE_VALUE*9) //72000000 based HSE_VALUE = 8000000
|
||||
//#define SYSCLK_FREQ_XXMHz (HSE_VALUE*12) //96000000 based HSE_VALUE = 8000000
|
||||
#define SYSCLK_FREQ_XXMHz (HSE_VALUE*12) //120000000 based HSE_VALUE = 8000000
|
||||
|
||||
#if defined(SYSCLK_FREQ_HSE) || defined(SYSCLK_FREQ_24MHz) || defined(SYSCLK_FREQ_36MHz) || defined(SYSCLK_FREQ_48MHz) || defined(SYSCLK_FREQ_XXMHz)
|
||||
|
||||
#if defined(HSE_VALUE) && (!(HSE_VALUE == 8000000))
|
||||
#warning redefine HSE_VALUE in reg_common.h Line 48 and ignore this warning
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
//#define SYSCLK_HSI_24MHz 24000000
|
||||
//#define SYSCLK_HSI_36MHz 36000000
|
||||
//#define SYSCLK_HSI_48MHz 48000000
|
||||
//#define SYSCLK_HSI_XXMHz 48000000
|
||||
//#define SYSCLK_HSI_XXMHz 72000000
|
||||
//#define SYSCLK_HSI_XXMHz 96000000
|
||||
#define SYSCLK_HSI_XXMHz 120000000
|
||||
/// Uncomment the following line if you need to relocate your vector Table in
|
||||
/// Internal SRAM.
|
||||
///#define VECT_TAB_SRAM
|
||||
#define VECT_TAB_OFFSET 0x0
|
||||
/// Vector Table base offset field.
|
||||
/// This value must be a multiple of 0x200.
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////
|
||||
///Clock Definitions
|
||||
///////////////////////////////////////////////////////////////
|
||||
#if defined SYSCLK_FREQ_HSE
|
||||
u32 SystemCoreClock = SYSCLK_FREQ_HSE;
|
||||
#elif defined SYSCLK_FREQ_24MHz
|
||||
u32 SystemCoreClock = SYSCLK_FREQ_24MHz;
|
||||
#elif defined SYSCLK_FREQ_36MHz
|
||||
u32 SystemCoreClock = SYSCLK_FREQ_36MHz;
|
||||
#elif defined SYSCLK_FREQ_48MHz
|
||||
u32 SystemCoreClock = SYSCLK_FREQ_48MHz;
|
||||
#elif defined SYSCLK_FREQ_XXMHz
|
||||
u32 SystemCoreClock = SYSCLK_FREQ_XXMHz;
|
||||
|
||||
|
||||
#elif defined SYSCLK_HSI_24MHz
|
||||
u32 SystemCoreClock = SYSCLK_HSI_24MHz;
|
||||
#elif defined SYSCLK_HSI_36MHz
|
||||
u32 SystemCoreClock = SYSCLK_HSI_36MHz;
|
||||
#elif defined SYSCLK_HSI_48MHz
|
||||
u32 SystemCoreClock = SYSCLK_HSI_48MHz;
|
||||
#elif defined SYSCLK_HSI_XXMHz
|
||||
u32 SystemCoreClock = SYSCLK_HSI_XXMHz;
|
||||
#else //HSI Selected as System Clock source
|
||||
u32 SystemCoreClock = HSI_VALUE;
|
||||
#endif
|
||||
|
||||
__I u8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
static void SetSysClock(void);
|
||||
|
||||
#if defined SYSCLK_FREQ_HSE
|
||||
static void SetSysClockToHSE(void);
|
||||
#elif defined SYSCLK_FREQ_24MHz
|
||||
static void SetSysClockTo24(void);
|
||||
#elif defined SYSCLK_FREQ_36MHz
|
||||
static void SetSysClockTo36(void);
|
||||
#elif defined SYSCLK_FREQ_48MHz
|
||||
static void SetSysClockTo48(void);
|
||||
#elif defined SYSCLK_FREQ_XXMHz
|
||||
static void SetSysClockToXX(void);
|
||||
|
||||
#elif defined SYSCLK_HSI_24MHz
|
||||
static void SetSysClockTo24_HSI(void);
|
||||
#elif defined SYSCLK_HSI_36MHz
|
||||
static void SetSysClockTo36_HSI(void);
|
||||
#elif defined SYSCLK_HSI_48MHz
|
||||
static void SetSysClockTo48_HSI(void);
|
||||
#elif defined SYSCLK_HSI_XXMHz
|
||||
static void SetSysClockToXX_HSI(void);
|
||||
#endif
|
||||
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
static void SystemInit_ExtMemCtl(void);
|
||||
#endif //DATA_IN_ExtSRAM
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
/// @brief Setup the microcontroller system
|
||||
/// Initialize the Embedded Flash Interface, the PLL and update the
|
||||
/// SystemCoreClock variable.
|
||||
/// @note This function should be used only after reset.
|
||||
/// @param None
|
||||
/// @retval None
|
||||
|
||||
void SystemInit (void)
|
||||
{
|
||||
//Reset the RCC clock configuration to the default reset state(for debug purpose)
|
||||
//Set HSION bit
|
||||
RCC->CR |= (u32)0x00000001;
|
||||
|
||||
//Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits
|
||||
RCC->CFGR &= (u32)0xF8FFC00C;
|
||||
|
||||
//Reset HSEON, CSSON and PLLON bits
|
||||
RCC->CR &= (u32)0xFEF6FFFF;
|
||||
|
||||
//Reset HSEBYP bit
|
||||
RCC->CR &= (u32)0xFFFBFFFF;
|
||||
|
||||
//Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits
|
||||
RCC->CFGR &= (u32)0xFF3CFFFF;
|
||||
RCC->CR &= (u32)0x008FFFFF;
|
||||
|
||||
//Disable all interrupts and clear pending bits
|
||||
RCC->CIR = 0x009F0000;
|
||||
//Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers
|
||||
//Configure the Flash Latency cycles and enable prefetch buffer
|
||||
SetSysClock();
|
||||
}
|
||||
|
||||
|
||||
/// @brief use to return the pllm&plln.
|
||||
/// @param pllclkSourceFrq : PLL source clock frquency;
|
||||
/// pllclkFrq : Target PLL clock frquency;
|
||||
/// plln : PLL factor PLLN
|
||||
/// pllm : PLL factor PLLM
|
||||
/// @retval amount of error
|
||||
u32 AutoCalPllFactor(u32 pllclkSourceFrq, u32 pllclkFrq, u8* plln, u8* pllm)
|
||||
{
|
||||
u32 n, m;
|
||||
u32 tempFrq;
|
||||
u32 minDiff = pllclkFrq;
|
||||
u8 flag = 0;
|
||||
for(m = 0; m < 4 ; m++) {
|
||||
for(n = 0; n < 64 ; n++) {
|
||||
tempFrq = pllclkSourceFrq * (n + 1) / (m + 1);
|
||||
tempFrq = (tempFrq > pllclkFrq) ? (tempFrq - pllclkFrq) : (pllclkFrq - tempFrq) ;
|
||||
|
||||
if(minDiff > tempFrq) {
|
||||
minDiff = tempFrq;
|
||||
*plln = n;
|
||||
*pllm = m;
|
||||
}
|
||||
if(minDiff == 0) {
|
||||
flag = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(flag != 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
return minDiff;
|
||||
}
|
||||
static void DELAY_xUs(u32 count)
|
||||
{
|
||||
u32 temp;
|
||||
SysTick->CTRL = 0x0; //disable systick function
|
||||
SysTick->LOAD = count * 8; //time count for 1us with HSI as SYSCLK
|
||||
SysTick->VAL = 0x00; //clear counter
|
||||
SysTick->CTRL = 0x5; //start discrease with Polling
|
||||
do {
|
||||
temp = SysTick->CTRL;
|
||||
} while((temp & 0x01) && !(temp & (1 << 16))); //wait time count done
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; //Close Counter
|
||||
SysTick->VAL = 0X00; //clear counter
|
||||
}
|
||||
/// @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
|
||||
/// @param None
|
||||
/// @retval None
|
||||
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
CACHE->CCR &= ~(0x3 << 3);
|
||||
CACHE->CCR |= 1;
|
||||
while((CACHE->SR & 0x3) != 2);
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
SetSysClockToHSE();
|
||||
#elif defined SYSCLK_FREQ_24MHz
|
||||
SetSysClockTo24();
|
||||
#elif defined SYSCLK_FREQ_36MHz
|
||||
SetSysClockTo36();
|
||||
#elif defined SYSCLK_FREQ_48MHz
|
||||
SetSysClockTo48();
|
||||
#elif defined SYSCLK_FREQ_XXMHz
|
||||
SetSysClockToXX();
|
||||
|
||||
#elif defined SYSCLK_HSI_24MHz
|
||||
SetSysClockTo24_HSI();
|
||||
#elif defined SYSCLK_HSI_36MHz
|
||||
SetSysClockTo36_HSI();
|
||||
#elif defined SYSCLK_HSI_48MHz
|
||||
SetSysClockTo48_HSI();
|
||||
#elif defined SYSCLK_HSI_XXMHz
|
||||
SetSysClockToXX_HSI();
|
||||
#endif
|
||||
|
||||
//If none of the define above is enabled, the HSI is used as System clock
|
||||
//source (default after reset)
|
||||
}
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
|
||||
/// @brief Selects HSE as System clock source and configure HCLK, PCLK2
|
||||
/// and PCLK1 prescalers.
|
||||
/// @note This function should be used only after reset.
|
||||
/// @param None
|
||||
/// @retval None
|
||||
|
||||
static void SetSysClockToHSE(void)
|
||||
{
|
||||
__IO u32 StartUpCounter = 0, HSEStatus = 0;
|
||||
s32 i;
|
||||
|
||||
//SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
|
||||
//Enable HSE
|
||||
RCC->CR |= ((u32)RCC_CR_HSEON);
|
||||
|
||||
//Wait till HSE is ready and if Time out is reached exit
|
||||
do {
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
|
||||
HSEStatus = (u32)0x01;
|
||||
i = 2000;
|
||||
while(i--);
|
||||
}
|
||||
else {
|
||||
HSEStatus = (u32)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (u32)0x01) {
|
||||
//Enable Prefetch Buffer
|
||||
FLASH->ACR |= FLASH_ACR_PRFTBE;
|
||||
|
||||
//Flash 0 wait state ,bit0~2
|
||||
FLASH->ACR &= ~0x07;
|
||||
//HCLK = SYSCLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
//PCLK2 = HCLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
|
||||
|
||||
//PCLK1 = HCLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1;
|
||||
|
||||
//Select HSE as system clock source
|
||||
RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (u32)RCC_CFGR_SW_HSE;
|
||||
|
||||
//Wait till HSE is used as system clock source
|
||||
while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x04) {
|
||||
}
|
||||
}
|
||||
else {
|
||||
//If HSE fails to start-up, the application will have wrong clock
|
||||
//configuration. User can add here some code to deal with this error
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_24MHz
|
||||
|
||||
/// @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
|
||||
/// and PCLK1 prescalers.
|
||||
/// @note This function should be used only after reset.
|
||||
/// @param None
|
||||
/// @retval None
|
||||
|
||||
static void SetSysClockTo24(void)
|
||||
{
|
||||
__IO u32 StartUpCounter = 0, HSEStatus = 0;
|
||||
s32 i;
|
||||
|
||||
//SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
|
||||
//Enable HSE
|
||||
RCC->CR |= ((u32)RCC_CR_HSEON);
|
||||
|
||||
//Wait till HSE is ready and if Time out is reached exit
|
||||
do {
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
|
||||
HSEStatus = (u32)0x01;
|
||||
i = 2000;
|
||||
while(i--);
|
||||
}
|
||||
else {
|
||||
HSEStatus = (u32)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (u32)0x01) {
|
||||
//Enable Prefetch Buffer
|
||||
FLASH->ACR |= FLASH_ACR_PRFTBE;
|
||||
//Flash 0 wait state ,bit0~2
|
||||
FLASH->ACR &= ~0x07;
|
||||
FLASH->ACR |= 0x01;
|
||||
//HCLK = SYSCLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
//PCLK2 = HCLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
|
||||
|
||||
//PCLK1 = HCLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1;
|
||||
|
||||
// PLL configuration: = (HSE ) * (2+1) = 24 MHz
|
||||
RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
|
||||
RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ;
|
||||
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWR;
|
||||
RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
|
||||
RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (2 << RCC_PLLCFGR_PLL_DP_Pos));
|
||||
//Enable PLL
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
//Wait till PLL is ready
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0) {
|
||||
}
|
||||
|
||||
//Select PLL as system clock source
|
||||
RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
|
||||
|
||||
//Wait till PLL is used as system clock source
|
||||
while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) {
|
||||
}
|
||||
}
|
||||
else {
|
||||
//If HSE fails to start-up, the application will have wrong clock
|
||||
//configuration. User can add here some code to deal with this error
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_36MHz
|
||||
|
||||
/// @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
|
||||
/// and PCLK1 prescalers.
|
||||
/// @note This function should be used only after reset.
|
||||
/// @param None
|
||||
/// @retval None
|
||||
|
||||
static void SetSysClockTo36(void)
|
||||
{
|
||||
s32 i;
|
||||
__IO u32 StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
//SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
|
||||
//Enable HSE
|
||||
RCC->CR |= ((u32)RCC_CR_HSEON);
|
||||
|
||||
//Wait till HSE is ready and if Time out is reached exit
|
||||
do {
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
|
||||
HSEStatus = (u32)0x01;
|
||||
i = 2000;
|
||||
while(i--);
|
||||
}
|
||||
else {
|
||||
HSEStatus = (u32)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (u32)0x01) {
|
||||
//Enable Prefetch Buffer
|
||||
FLASH->ACR |= FLASH_ACR_PRFTBE;
|
||||
|
||||
//Flash 0 wait state ,bit0~2
|
||||
FLASH->ACR &= ~0x07;
|
||||
FLASH->ACR |= 0x01;
|
||||
//HCLK = SYSCLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
//PCLK2 = HCLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
|
||||
|
||||
//PCLK1 = HCLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1;
|
||||
RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
|
||||
RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ;
|
||||
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWR;
|
||||
RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
|
||||
RCC->PLLCFGR |= ((1 << RCC_PLLCFGR_PLL_DN_Pos) | (8 << RCC_PLLCFGR_PLL_DP_Pos));
|
||||
//Enable PLL
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
//Wait till PLL is ready
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0) {
|
||||
}
|
||||
|
||||
//Select PLL as system clock source
|
||||
RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
|
||||
|
||||
//Wait till PLL is used as system clock source
|
||||
while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) {
|
||||
}
|
||||
}
|
||||
else {
|
||||
//If HSE fails to start-up, the application will have wrong clock
|
||||
//configuration. User can add here some code to deal with this error
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_48MHz
|
||||
|
||||
/// @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
|
||||
/// and PCLK1 prescalers.
|
||||
/// @note This function should be used only after reset.
|
||||
/// @param None
|
||||
/// @retval None
|
||||
|
||||
static void SetSysClockTo48(void)
|
||||
{
|
||||
__IO u32 StartUpCounter = 0, HSEStatus = 0;
|
||||
s32 i;
|
||||
//SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
|
||||
//Enable HSE
|
||||
RCC->CR |= ((u32)RCC_CR_HSEON);
|
||||
|
||||
//Wait till HSE is ready and if Time out is reached exit
|
||||
do {
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
|
||||
HSEStatus = (u32)0x01;
|
||||
i = 2000;
|
||||
while(i--);
|
||||
}
|
||||
else {
|
||||
HSEStatus = (u32)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (u32)0x01) {
|
||||
//Enable Prefetch Buffer
|
||||
FLASH->ACR |= FLASH_ACR_PRFTBE;
|
||||
//Flash 0 wait state ,bit0~2
|
||||
FLASH->ACR &= ~0x07;
|
||||
FLASH->ACR |= 0x02;
|
||||
//HCLK = SYSCLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
//PCLK2 = HCLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
|
||||
|
||||
//PCLK1 = HCLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2;
|
||||
|
||||
// PLL configuration: = (HSE ) * (5+1) = 48MHz
|
||||
RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
|
||||
RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ;
|
||||
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWR;
|
||||
RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
|
||||
RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (5 << RCC_PLLCFGR_PLL_DP_Pos));
|
||||
//Enable PLL
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
//Wait till PLL is ready
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0) {
|
||||
}
|
||||
|
||||
//Select PLL as system clock source
|
||||
RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
|
||||
|
||||
//Wait till PLL is used as system clock source
|
||||
while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) {
|
||||
}
|
||||
}
|
||||
else {
|
||||
//If HSE fails to start-up, the application will have wrong clock
|
||||
//configuration. User can add here some code to deal with this error
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_XXMHz
|
||||
|
||||
/// @brief Sets System clock frequency to XXMHz and configure HCLK, PCLK2
|
||||
/// and PCLK1 prescalers.
|
||||
/// @note This function should be used only after reset.
|
||||
/// @param None
|
||||
/// @retval None
|
||||
|
||||
static void SetSysClockToXX(void)
|
||||
{
|
||||
__IO u32 temp, tn, tm;//j,
|
||||
__IO u32 StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
u8 plln, pllm;
|
||||
|
||||
RCC->CR |= RCC_CR_HSION;
|
||||
while(!(RCC->CR & RCC_CR_HSIRDY));
|
||||
//PLL SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
|
||||
//Enable HSE
|
||||
RCC->CR |= ((u32)RCC_CR_HSEON);
|
||||
|
||||
DELAY_xUs(5);
|
||||
|
||||
if(SystemCoreClock > 96000000) {
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWR;
|
||||
PWR->CR &= ~(3 << 14);
|
||||
PWR->CR |= 3 << 14;
|
||||
}
|
||||
//Wait till HSE is ready and if Time out is reached exit
|
||||
while(1) {
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
if(HSEStatus != 0)
|
||||
break;
|
||||
StartUpCounter++;
|
||||
if(StartUpCounter >= (10 * HSE_STARTUP_TIMEOUT))
|
||||
return;
|
||||
}
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSERDY) == RESET) {
|
||||
//If HSE fails to start-up, the application will have wrong clock
|
||||
//configuration. User can add here some code to deal with this error
|
||||
HSEStatus = (u32)0x00;
|
||||
return;
|
||||
}
|
||||
|
||||
HSEStatus = (u32)0x01;
|
||||
DELAY_xUs(5);
|
||||
|
||||
SystemCoreClock = SYSCLK_FREQ_XXMHz;
|
||||
//Enable Prefetch Buffer
|
||||
FLASH->ACR |= FLASH_ACR_PRFTBE;
|
||||
//Flash 0 wait state ,bit0~2
|
||||
FLASH->ACR &= ~FLASH_ACR_LATENCY;
|
||||
temp = (SystemCoreClock - 1) / 24000000;
|
||||
FLASH->ACR |= (temp & FLASH_ACR_LATENCY);
|
||||
RCC->CFGR &= (~RCC_CFGR_HPRE) & ( ~RCC_CFGR_PPRE1) & (~RCC_CFGR_PPRE2);
|
||||
|
||||
//HCLK = AHB = FCLK = SYSCLK divided by 4
|
||||
RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV4;
|
||||
|
||||
//PCLK2 = APB2 = HCLK divided by 1, APB2 is high APB CLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
|
||||
|
||||
if(SystemCoreClock > 72000000) {
|
||||
//PCLK1 = APB1 = HCLK divided by 4, APB1 is low APB CLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV4;
|
||||
}
|
||||
else if(SystemCoreClock > 36000000) {
|
||||
//PCLK1 = APB1 = HCLK divided by 2, APB1 is low APB CLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2;
|
||||
}
|
||||
|
||||
AutoCalPllFactor(HSE_VALUE, SystemCoreClock, &plln, &pllm);
|
||||
|
||||
RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
|
||||
RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ;
|
||||
|
||||
tm = (((u32)pllm) & 0x07);
|
||||
tn = (((u32)plln) & 0x7F);
|
||||
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWR;
|
||||
RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
|
||||
RCC->PLLCFGR |= ((tn << RCC_PLLCFGR_PLL_DN_Pos) | (tm << RCC_PLLCFGR_PLL_DP_Pos));
|
||||
//Enable PLL
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
//Wait till PLL is ready
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0) {
|
||||
__ASM ("nop") ;//__NOP();
|
||||
}
|
||||
//Select PLL as system clock source
|
||||
RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
|
||||
|
||||
//Wait till PLL is used as system clock source
|
||||
while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)RCC_CFGR_SWS_PLL) {
|
||||
__ASM ("nop") ;//__NOP();
|
||||
}
|
||||
|
||||
DELAY_xUs(1);
|
||||
// set HCLK = AHB = FCLK = SYSCLK divided by 2
|
||||
RCC->CFGR &= (~(RCC_CFGR_PPRE_0));
|
||||
DELAY_xUs(1);
|
||||
|
||||
// set HCLK = AHB = FCLK = SYSCLK divided by 1
|
||||
RCC->CFGR &= (~(RCC_CFGR_PPRE_3));
|
||||
|
||||
DELAY_xUs(1);
|
||||
|
||||
}
|
||||
#elif defined SYSCLK_HSI_24MHz
|
||||
void SetSysClockTo24_HSI(void)
|
||||
{
|
||||
u8 temp = 0;
|
||||
|
||||
RCC->CR |= RCC_CR_HSION;
|
||||
|
||||
while(!(RCC->CR & RCC_CR_HSIRDY));
|
||||
FLASH->ACR = FLASH_ACR_PRFTBE;
|
||||
|
||||
RCC->CFGR = RCC_CFGR_PPRE1_2;
|
||||
// PLL configuration: = (HSI = 8M ) * (2+1)/(0+1) = 24 MHz
|
||||
RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
|
||||
RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ;
|
||||
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWR;
|
||||
RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
|
||||
RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (2 << RCC_PLLCFGR_PLL_DP_Pos));
|
||||
|
||||
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
while(!(RCC->CR & RCC_CR_PLLRDY));
|
||||
|
||||
RCC->CFGR &= ~RCC_CFGR_SW;
|
||||
|
||||
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
||||
|
||||
while(temp != 0x02) {
|
||||
temp = RCC->CFGR >> 2;
|
||||
temp &= 0x03;
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_HSI_36MHz
|
||||
void SetSysClockTo36_HSI(void)
|
||||
{
|
||||
u8 temp = 0;
|
||||
|
||||
RCC->CR |= RCC_CR_HSION;
|
||||
|
||||
while(!(RCC->CR & RCC_CR_HSIRDY));
|
||||
FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_PRFTBE;
|
||||
RCC->CFGR = RCC_CFGR_PPRE1_2;
|
||||
// PLL configuration: = (HSI = 8M ) * (8+1)/(1+1) = 36 MHz
|
||||
RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
|
||||
RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ;
|
||||
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWR;
|
||||
RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
|
||||
RCC->PLLCFGR |= ((1 << RCC_PLLCFGR_PLL_DN_Pos) | (8 << RCC_PLLCFGR_PLL_DP_Pos));
|
||||
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
while(!(RCC->CR & RCC_CR_PLLRDY));
|
||||
|
||||
RCC->CFGR &= ~ RCC_CFGR_SW;
|
||||
|
||||
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
||||
|
||||
while(temp != 0x02) {
|
||||
temp = RCC->CFGR >> 2;
|
||||
temp &= 0x03;
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_HSI_48MHz
|
||||
void SetSysClockTo48_HSI(void)
|
||||
{
|
||||
u8 temp = 0;
|
||||
|
||||
RCC->CR |= RCC_CR_HSION;
|
||||
|
||||
while(!(RCC->CR & RCC_CR_HSIRDY));
|
||||
FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_PRFTBE;
|
||||
RCC->CFGR = RCC_CFGR_PPRE1_2;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// PLL configuration: = (HSI = 8M ) * (5+1)/(0+1) = 36 MHz
|
||||
RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
|
||||
RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ;
|
||||
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWR;
|
||||
RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
|
||||
RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (5 << RCC_PLLCFGR_PLL_DP_Pos));
|
||||
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
while(!(RCC->CR & RCC_CR_PLLRDY));
|
||||
|
||||
RCC->CFGR &= ~RCC_CFGR_SW;
|
||||
|
||||
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
||||
|
||||
while(temp != 0x02) {
|
||||
temp = RCC->CFGR >> 2;
|
||||
temp &= 0x03;
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_HSI_XXMHz
|
||||
|
||||
|
||||
static void SetSysClockToXX_HSI(void)
|
||||
{
|
||||
__IO u32 temp, tn, tm;
|
||||
u8 plln, pllm;
|
||||
|
||||
RCC->CR |= RCC_CR_HSION;
|
||||
while(!(RCC->CR & RCC_CR_HSIRDY));
|
||||
|
||||
if(SystemCoreClock > 96000000) {
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWR;
|
||||
PWR->CR &= ~(3 << 14);
|
||||
PWR->CR |= 3 << 14;
|
||||
}
|
||||
|
||||
|
||||
|
||||
SystemCoreClock = SYSCLK_HSI_XXMHz;
|
||||
//Enable Prefetch Buffer
|
||||
FLASH->ACR |= FLASH_ACR_PRFTBE;
|
||||
//Flash 0 wait state ,bit0~2
|
||||
FLASH->ACR &= ~FLASH_ACR_LATENCY;
|
||||
|
||||
temp = (SystemCoreClock - 1) / 24000000;
|
||||
|
||||
FLASH->ACR |= (temp & FLASH_ACR_LATENCY);
|
||||
|
||||
|
||||
RCC->CFGR &= (~RCC_CFGR_HPRE) & ( ~RCC_CFGR_PPRE1) & (~RCC_CFGR_PPRE2);
|
||||
//HCLK = AHB = FCLK = SYSCLK divided by 4
|
||||
RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV4;
|
||||
|
||||
//PCLK2 = APB2 = HCLK divided by 1, APB2 is high APB CLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
|
||||
|
||||
if(SystemCoreClock > 72000000) {
|
||||
//PCLK1 = APB1 = HCLK divided by 4, APB1 is low APB CLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV4;
|
||||
}
|
||||
else if(SystemCoreClock > 36000000) {
|
||||
//PCLK1 = APB1 = HCLK divided by 2, APB1 is low APB CLK
|
||||
RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2;
|
||||
}
|
||||
|
||||
|
||||
|
||||
AutoCalPllFactor(HSI_VALUE_PLL_ON, SystemCoreClock, &plln, &pllm);
|
||||
|
||||
RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
|
||||
RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC);
|
||||
|
||||
tm = (((u32)pllm) & 0x07);
|
||||
tn = (((u32)plln) & 0x7F);
|
||||
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWR;
|
||||
RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
|
||||
RCC->PLLCFGR |= ((tn << RCC_PLLCFGR_PLL_DN_Pos) | (tm << RCC_PLLCFGR_PLL_DP_Pos));
|
||||
//Enable PLL
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
//Wait till PLL is ready
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0) {
|
||||
__ASM ("nop") ;//__NOP();
|
||||
}
|
||||
//Select PLL as system clock source
|
||||
RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
|
||||
|
||||
//Wait till PLL is used as system clock source
|
||||
while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)RCC_CFGR_SWS_PLL) {
|
||||
__ASM ("nop") ;//__NOP();
|
||||
}
|
||||
|
||||
DELAY_xUs(1);
|
||||
// set HCLK = AHB = FCLK = SYSCLK divided by 2
|
||||
RCC->CFGR &= (~(RCC_CFGR_PPRE_0));
|
||||
DELAY_xUs(1);
|
||||
|
||||
// set HCLK = AHB = FCLK = SYSCLK divided by 1
|
||||
RCC->CFGR &= (~(RCC_CFGR_PPRE_3));
|
||||
|
||||
DELAY_xUs(1);
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
/// @}
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user