rename subfolder source to src
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hathach
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/**************************************************************************/
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/*!
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@file ehci.h
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@author hathach (tinyusb.org)
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@section LICENSE
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||||
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||||
Software License Agreement (BSD License)
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||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
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All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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||||
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||||
This file is part of the tinyusb stack.
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*/
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/**************************************************************************/
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||||
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/** \ingroup Group_HCD
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* @{
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* \defgroup EHCI
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* \brief EHCI driver. All documents sources mentioned here (eg section 3.5) is referring to EHCI Specs unless state otherwise
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* @{ */
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#ifndef _TUSB_EHCI_H_
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#define _TUSB_EHCI_H_
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#include "common/tusb_common.h"
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#include "../hcd.h"
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/* Abbreviation
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* HC: Host Controller
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* HCD: Host Controller Driver
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* QHD: Queue Head for non-ISO transfer
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* QTD: Queue Transfer Descriptor for non-ISO transfer
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* ITD: Iso Transfer Descriptor for highspeed
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* SITD: Split ISO Transfer Descriptor for full-speed
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* SMASK: Start Split mask for Slipt Transaction
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* CMASK: Complete Split mask for Slipt Transaction
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* RO: Read Only
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* R/WC: Read, Write to Clear
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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//--------------------------------------------------------------------+
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// EHCI CONFIGURATION & CONSTANTS
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//--------------------------------------------------------------------+
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#define HOST_HCD_XFER_INTERRUPT // TODO interrupt is used widely, should always be enalbed
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#define EHCI_PERIODIC_LIST (defined HOST_HCD_XFER_INTERRUPT || defined HOST_HCD_XFER_ISOCHRONOUS)
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#define EHCI_CFG_FRAMELIST_SIZE_BITS 7 /// Framelist Size (NXP specific) (0:1024) - (1:512) - (2:256) - (3:128) - (4:64) - (5:32) - (6:16) - (7:8)
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#define EHCI_FRAMELIST_SIZE (1024 >> EHCI_CFG_FRAMELIST_SIZE_BITS)
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// TODO merge OHCI with EHCI
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enum {
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EHCI_MAX_ITD = 4,
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EHCI_MAX_SITD = 16
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};
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//------------- Validation -------------//
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VERIFY_STATIC(EHCI_CFG_FRAMELIST_SIZE_BITS <= 7, "incorrect value");
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//--------------------------------------------------------------------+
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// EHCI Data Structure
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//--------------------------------------------------------------------+
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enum ehci_queue_element_type_{
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EHCI_QUEUE_ELEMENT_ITD = 0 , ///< 0
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EHCI_QUEUE_ELEMENT_QHD , ///< 1
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EHCI_QUEUE_ELEMENT_SITD , ///< 2
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EHCI_QUEUE_ELEMENT_FSTN ///< 3
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};
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/// EHCI PID
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enum tusb_pid_{
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EHCI_PID_OUT = 0 ,
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EHCI_PID_IN ,
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EHCI_PID_SETUP
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};
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/// Link pointer
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typedef union {
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uint32_t address;
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struct {
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uint32_t terminate : 1;
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uint32_t type : 2;
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};
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}ehci_link_t;
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/// Queue Element Transfer Descriptor (section 3.5)
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typedef struct {
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/// Word 0: Next QTD Pointer
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ehci_link_t next;
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/// Word 1: Alternate Next QTD Pointer (not used)
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union{
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ehci_link_t alternate;
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struct {
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uint32_t : 5;
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uint32_t used : 1;
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uint32_t : 10;
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uint32_t expected_bytes : 16;
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};
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};
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/// Word 2: qTQ Token
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volatile uint32_t pingstate_err : 1 ; ///< If the QH.EPSfield indicates a High-speed device and the PID_Codeindicates an OUT endpoint, then this is the state bit for the Ping protocol. 0b=OUT 1b=PING
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volatile uint32_t non_hs_split_state : 1 ; ///< This bit is ignored by the host controller unless the QH.EPSfield indicates a full- or low-speed endpoint. When a Full- or Low-speed device, the host controller uses this bit to track the state of the split-transaction. The functional requirements of the host controller for managing this state bit and the split transaction protocol depends on whether the endpoint is in the periodic or asynchronous schedule. 0b=Start Split 1b=Complete Split
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volatile uint32_t non_hs_period_missed_uframe : 1 ; ///< This bit is ignored unless the QH.EPSfield indicates a full- or low-speed endpoint and the queue head is in the periodic list. This bit is set when the host controller detected that a host-induced hold-off caused the host controller to miss a required complete-split transaction. If the host controller sets this bit to a one, then it remains a one for the duration of the transfer.
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volatile uint32_t xact_err : 1 ; ///< Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.)
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volatile uint32_t babble_err : 1 ; ///< Set to a 1 by the Host Controller during status update when a babble is detected during the transaction. In addition to setting this bit, the Host Controller also sets the Haltedbit to a 1
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volatile uint32_t buffer_err : 1 ; ///< Set to a 1 by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (underrun)
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volatile uint32_t halted : 1 ; ///< Set to a 1 by the Host Controller during status updates to indicate that a serious error has occurred at the device/endpoint addressed by this qTD. This can be caused by babble, the error counter counting down to zero, or reception of the STALL handshake from the device during a transaction. Any time that a transaction results in the Halted bit being set to a one, the Active bit is also set to 0
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volatile uint32_t active : 1 ; ///< Set to 1 by software to enable the execution of transactions by the Host Controller
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uint32_t pid : 2 ; ///< This field is an encoding of the token which should be used for transactions associated with this transfer descriptor. 00=OUT 01=IN 10=SETUP
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volatile uint32_t cerr : 2 ; ///< Error Counter, This field is a 2-bit down counter that keeps track of the number of consecutive Errors detected while executing this qTD
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volatile uint32_t current_page : 3 ; ///< This field is used as an index into the qTD buffer pointer list
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uint32_t int_on_complete : 1 ; ///< If this bit is set to a one, it specifies that when this qTD is completed, the Host Controller should issue an interrupt at the next interrupt threshold
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volatile uint32_t total_bytes : 15 ; ///< This field specifies the total number of bytes to be moved with this transfer descriptor
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volatile uint32_t data_toggle : 1 ; ///< This is the data toggle sequence bit
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uint32_t : 0 ; // padding to the end of current storage unit
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// End of Word 2
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/// Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
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uint32_t buffer[5];
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} ehci_qtd_t; // XXX qtd is used to declare overlay in ehci_qhd_t -> cannot be declared with ATTR_ALIGNED(32)
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VERIFY_STATIC( sizeof(ehci_qtd_t) == 32, "size is not correct" );
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/// Queue Head (section 3.6)
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typedef struct ATTR_ALIGNED(32) {
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/// Word 0: Queue Head Horizontal Link Pointer
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ehci_link_t next;
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/// Word 1 : Endpoint Characteristics
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uint32_t device_address : 7 ; ///< This field selects the specific device serving as the data source or sink
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uint32_t non_hs_period_inactive_next_xact : 1 ; ///< This bit is used by system software to request that the host controller set the Active bit to zero. See Section 4.12.2.5 for full operational details
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uint32_t endpoint_number : 4 ; ///< This 4-bit field selects the particular endpoint number on the device serving as the data source or sink.
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uint32_t endpoint_speed : 2 ; ///< This is the speed of the associated endpoint 00b=Full 01b=Low 10b=High 11b=Reserved
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uint32_t data_toggle_control : 1 ; ///< This bit specifies where the host controller should get the initial data toggle on an overlay transition. 0b=Ignore DT bit of qTD, 1b=Use DT bit of qTD
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uint32_t head_list_flag : 1 ; ///< This bit is set by System Software to mark a queue head as being the head of the reclamation list. See Section 4.8 for operational model
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uint32_t max_package_size : 11 ; ///< This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize)
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uint32_t non_hs_control_endpoint : 1 ; ///< If the QH.EPSfield indicates the endpoint is not a high-speed device, and the endpoint is an control endpoint, then software must set this bit to a one. Otherwise it should always set this bit to a zero.
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uint32_t nak_count_reload : 4 ; ///< This field contains a value, which is used by the host controller to reload the Nak Counter field.
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uint32_t : 0 ; // padding to the end of current storage unit
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// End of Word 1
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/// Word 2 : Endpoint Capabilities
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uint32_t interrupt_smask : 8 ; ///< This field is used for all endpoint speeds. Software should set this field to a zero when the queue head is on the asynchronous schedule. A non-zero value in this field indicates an interrupt endpoint
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uint32_t non_hs_interrupt_cmask : 8 ; ///< This field is ignored by the host controller unless the EPSfield indicates this device is a low- or full-speed device and this queue head is in the periodic list. This field (along with the Activeand SplitX-statefields) is used to determine during which micro-frames the host controller should execute a complete-split transaction
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uint32_t hub_address : 7 ; ///< This field is ignored by the host controller unless the EPSfield indicates a full- or low-speed device. The value is the USB device address of the USB 2.0 Hub below which the full- or low-speed device associated with this endpoint is attached. This field is used in the split-transaction protocol. See Section 4.12.
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uint32_t hub_port : 7 ; ///< This field is ignored by the host controller unless the EPSfield indicates a full- or low-speed device. The value is the port number identifier on the USB 2.0 Hub (for hub at device address Hub Addrbelow), below which the full- or low-speed device associated with this endpoint is attached. This information is used in the split-transaction protocol. See Section 4.12.
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uint32_t mult : 2 ; ///< This field is a multiplier used to key the host controller as the number of successive packets the host controller may submit to the endpoint in the current execution. 00b=Reserved 01b,10b,11b= 1 (2, 3) Transaction for this endpoint/micro frame
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uint32_t : 0 ; // padding to the end of current storage unit
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// End of Word 2
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/// Word 3: Current qTD Pointer
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volatile uint32_t qtd_addr;
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/// Word 4-11: Transfer Overlay
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volatile ehci_qtd_t qtd_overlay;
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//--------------------------------------------------------------------+
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/// Due to the fact QHD is 32 bytes aligned but occupies only 48 bytes
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/// thus there are 16 bytes padding free that we can make use of.
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//--------------------------------------------------------------------+
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uint8_t used;
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uint8_t is_removing;
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uint8_t pid_non_control;
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uint8_t class_code;
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uint16_t total_xferred_bytes; // number of bytes xferred until a qtd with ioc bit set
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uint8_t interval_ms; // polling interval in frames (or milisecond)
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uint8_t reserved;
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ehci_qtd_t * volatile p_qtd_list_head; // head of the scheduled TD list
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ehci_qtd_t * volatile p_qtd_list_tail; // tail of the scheduled TD list
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} ehci_qhd_t;
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VERIFY_STATIC( sizeof(ehci_qhd_t) == 64, "size is not correct" );
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/// Highspeed Isochronous Transfer Descriptor (section 3.3)
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typedef struct ATTR_ALIGNED(32) {
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/// Word 0: Next Link Pointer
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ehci_link_t next;
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/// Word 1-8: iTD Transaction Status and Control List
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struct {
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// iTD Control
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volatile uint32_t offset : 12 ; ///< This field is a value that is an offset, expressed in bytes, from the beginning of a buffer.
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volatile uint32_t page_select : 3 ; ///< These bits are set by software to indicate which of the buffer page pointers the offset field in this slot should be concatenated to produce the starting memory address for this transaction. The valid range of values for this field is 0 to 6
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uint32_t int_on_complete : 1 ; ///< If this bit is set to a one, it specifies that when this transaction completes, the Host Controller should issue an interrupt at the next interrupt threshold
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volatile uint32_t length : 12 ; ///< For an OUT, this field is the number of data bytes the host controller will send during the transaction. The host controller is not required to update this field to reflect the actual number of bytes transferred during the transfer
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///< For an IN, the initial value of the field is the number of bytes the host expects the endpoint to deliver. During the status update, the host controller writes back the number of bytes successfully received. The value in this register is the actual byte count
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// iTD Status
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volatile uint32_t error : 1 ; ///< Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit may only be set for isochronous IN transactions.
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volatile uint32_t babble_err : 1 ; ///< Set to a 1 by the Host Controller during status update when a babble is detected during the transaction
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volatile uint32_t buffer_err : 1 ; ///< Set to a 1 by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (underrun).
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volatile uint32_t active : 1 ; ///< Set to 1 by software to enable the execution of an isochronous transaction by the Host Controller
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} xact[8];
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///Word 9-15 Buffer Page Pointer List (Plus)
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uint32_t BufferPointer[7];
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// // FIXME: Store meta data into buffer pointer reserved for saving memory
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// /*---------- HCD Area ----------*/
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// uint32_t used;
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// uint32_t IhdIdx;
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// uint32_t reserved[6];
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} ehci_itd_t;
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VERIFY_STATIC( sizeof(ehci_itd_t) == 64, "size is not correct" );
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/// Split (Full-Speed) Isochronous Transfer Descriptor
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typedef struct ATTR_ALIGNED(32) {
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/// Word 0: Next Link Pointer
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ehci_link_t next;
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/// Word 1: siTD Endpoint Characteristics
|
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uint32_t device_address : 7; ///< This field selects the specific device serving as the data source or sink.
|
||||
uint32_t : 1; ///< reserved
|
||||
uint32_t endpoint_number : 4; ///< This 4-bit field selects the particular endpoint number on the device serving as the data source or sink.
|
||||
uint32_t : 4; ///< This field is reserved and should be set to zero.
|
||||
uint32_t hub_address : 7; ///< This field holds the device address of the transaction translators’ hub.
|
||||
uint32_t : 1; ///< reserved
|
||||
uint32_t port_number : 7; ///< This field is the port number of the recipient transaction translator.
|
||||
uint32_t direction : 1; ///< 0 = OUT; 1 = IN. This field encodes whether the full-speed transaction should be an IN or OUT.
|
||||
uint32_t : 0; // padding to the end of current storage unit
|
||||
// End of Word 1
|
||||
|
||||
/// Word 2: Micro-frame Schedule Control
|
||||
uint8_t interrupt_smask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute complete-split transactions
|
||||
uint8_t non_hs_interrupt_cmask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute start-split transactions.
|
||||
uint16_t reserved ; ///< reserved
|
||||
// End of Word 2
|
||||
|
||||
/// Word 3: siTD Transfer Status and Control
|
||||
// Status [7:0] TODO indentical to qTD Token'status --> refractor later
|
||||
volatile uint32_t : 1 ; // reserved
|
||||
volatile uint32_t split_state : 1 ;
|
||||
volatile uint32_t missed_uframe : 1 ;
|
||||
volatile uint32_t xact_err : 1 ;
|
||||
volatile uint32_t babble_err : 1 ;
|
||||
volatile uint32_t buffer_err : 1 ;
|
||||
volatile uint32_t error : 1 ;
|
||||
volatile uint32_t active : 1 ;
|
||||
// Micro-frame Schedule Control
|
||||
volatile uint32_t cmask_progress : 8 ; ///< This field is used by the host controller to record which split-completes have been executed. See Section 4.12.3.3.2 for behavioral requirements.
|
||||
volatile uint32_t total_bytes : 10 ; ///< This field is initialized by software to the total number of bytes expected in this transfer. Maximum value is 1023
|
||||
volatile uint32_t : 4 ; ///< reserved
|
||||
volatile uint32_t page_select : 1 ; ///< Used to indicate which data page pointer should be concatenated with the CurrentOffsetfield to construct a data buffer pointer
|
||||
uint32_t int_on_complete : 1 ; ///< Do not interrupt when transaction is complete. 1 = Do interrupt when transaction is complete
|
||||
uint32_t : 0 ; // padding to the end of current storage unit
|
||||
// End of Word 3
|
||||
|
||||
/// Word 4-5: Buffer Pointer List
|
||||
uint32_t buffer[2]; // buffer[1] TP: Transaction Position - T-Count: Transaction Count
|
||||
|
||||
// union{
|
||||
// uint32_t BufferPointer1;
|
||||
// struct {
|
||||
// volatile uint32_t TCount : 3;
|
||||
// volatile uint32_t TPosition : 2;
|
||||
// };
|
||||
// };
|
||||
|
||||
/*---------- Word 6 ----------*/
|
||||
ehci_link_t back;
|
||||
|
||||
/// SITD is 32-byte aligned but occupies only 28 --> 4 bytes for storing extra data
|
||||
uint8_t used;
|
||||
uint8_t ihd_idx;
|
||||
uint8_t reserved2[2];
|
||||
} ehci_sitd_t;
|
||||
|
||||
VERIFY_STATIC( sizeof(ehci_sitd_t) == 32, "size is not correct" );
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// EHCI Operational Register
|
||||
//--------------------------------------------------------------------+
|
||||
enum ehci_interrupt_mask_{
|
||||
EHCI_INT_MASK_USB = BIT_(0),
|
||||
EHCI_INT_MASK_ERROR = BIT_(1),
|
||||
EHCI_INT_MASK_PORT_CHANGE = BIT_(2),
|
||||
|
||||
EHCI_INT_MASK_FRAMELIST_ROLLOVER = BIT_(3),
|
||||
EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR = BIT_(4),
|
||||
EHCI_INT_MASK_ASYNC_ADVANCE = BIT_(5),
|
||||
EHCI_INT_MASK_NXP_SOF = BIT_(7),
|
||||
|
||||
EHCI_INT_MASK_NXP_ASYNC = BIT_(18),
|
||||
EHCI_INT_MASK_NXP_PERIODIC = BIT_(19),
|
||||
|
||||
EHCI_INT_MASK_ALL =
|
||||
EHCI_INT_MASK_USB | EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE |
|
||||
EHCI_INT_MASK_FRAMELIST_ROLLOVER | EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR |
|
||||
EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_NXP_SOF |
|
||||
EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_NXP_PERIODIC
|
||||
};
|
||||
|
||||
enum ehci_usbcmd_pos_ {
|
||||
EHCI_USBCMD_POS_RUN_STOP = 0,
|
||||
EHCI_USBCMD_POS_FRAMELIST_SZIE = 2,
|
||||
EHCI_USBCMD_POS_PERIOD_ENABLE = 4,
|
||||
EHCI_USBCMD_POS_ASYNC_ENABLE = 5,
|
||||
EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB = 15,
|
||||
EHCI_USBCMD_POS_INTERRUPT_THRESHOLD = 16
|
||||
};
|
||||
|
||||
enum ehci_portsc_change_mask_{
|
||||
EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE = BIT_(1),
|
||||
EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE = BIT_(3),
|
||||
EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE = BIT_(5),
|
||||
|
||||
EHCI_PORTSC_MASK_ALL =
|
||||
EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE |
|
||||
EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE |
|
||||
EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE
|
||||
};
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
uint32_t usb_cmd ; ///< The Command Register indicates the command to be executed by the serial bus host controller. Writing to the register causes a command to be executed
|
||||
struct {
|
||||
uint32_t run_stop : 1 ; ///< Default 0b. 1=Run. 0=Stop. When set to a 1, the Host Controller proceeds with execution of the schedule. The Host Controller continues execution as long as this bit is set to a 1. When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts. The Host Controller must halt within 16 micro-frames after software clears the Run bit. The HC Halted bit in the status register indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state. Software must not write a one to this field unless the host controller is in the Halted state (i.e. HCHaltedin the USBSTS register is a one). Doing so will yield undefined results.
|
||||
uint32_t reset : 1 ; ///< his control bit is used by software to reset the host controller. The effects of this on Root Hub registers are similar to a Chip Hardware Reset. When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports.This bit is set to zero by the Host Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. Software should not set this bit to a one when the HCHaltedbit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior.
|
||||
uint32_t framelist_size : 2 ; ///< This field is R/W only if Programmable Frame List Flagin the HCCPARAMS registers is set to a one. This field specifies the size of the frame list.00b 1024 elements (4096 bytes) Default value 01b 512 elements (2048 bytes) 10b 256 elements (1024 bytes)
|
||||
uint32_t periodic_enable : 1 ; ///< This bit controls whether the host controller skips processing the Periodic Schedule. Values mean: 0b Do not process the Periodic Schedule 1b Use the PERIODICLISTBASE register to access the Periodic Schedule.
|
||||
uint32_t async_enable : 1 ; ///< This bit controls whether the host controller skips processing the Asynchronous Schedule. Values mean: 0b Do not process the Asynchronous Schedule 1b Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
|
||||
uint32_t advacne_async : 1 ; ///< This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ringthe doorbell. When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Async Advancestatus bit in the USBSTS register. If the Interrupt on Async Advance Enablebit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold. See Section 4.8.2 for operational details. The host controller sets this bit to a zero after it has set the Interrupt on Async Advance status bit in the USBSTS register to a one. Software should not write a one to this bit when the asynchronous schedule is disabled. Doing so will yield undefined results.
|
||||
uint32_t light_reset : 1 ; ///< This control bit is not required. If implemented, it allows the driver to reset the EHCI controller without affecting the state of the ports or the relationship to the companion host controllers. For example, the PORSTC registers should not be reset to their default values and the CF bit setting should not go to zero (retaining port ownership relationships). A host software read of this bit as zero indicates the Light Host Controller Reset has completed and it is safe for host software to re-initialize the host controller. A host software read of this bit as a one indicates the Light Host Controller Reset has not yet completed.
|
||||
uint32_t async_park : 2 ; ///< It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. See Section 4.10.3.2 for full operational details. Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enableis a one as this will result in undefined behavior.
|
||||
uint32_t : 1 ; ///< reserved
|
||||
uint32_t async_park_enable : 1 ; ///< Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled.
|
||||
uint32_t : 3 ; ///< reserved
|
||||
uint32_t nxp_framelist_size_msb : 1 ; ///< NXP customized : Bit 2 of the Frame List Size bits \n 011b: 128 elements \n 100b: 64 elements \n 101b: 32 elements \n 110b: 16 elements \n 111b: 8 elements
|
||||
uint32_t int_threshold : 8 ; ///< Default 08h. This field is used by system software to select the maximum rate at which the host controller will issue interrupts. The only valid values are defined below. If software writes an invalid value to this register, the results are undefined. Value Maximum Interrupt Interval 00h Reserved 01h 1 micro-frame 02h 2 micro-frames 04h 4 micro-frames 08h 8 micro-frames (default, equates to 1 ms) 10h 16 micro-frames (2 ms) 20h 32 micro-frames (4 ms) 40h 64 micro-frames (8 ms) Refer to Section 4.15 for interrupts affected by this register. Any other value in this register yields undefined results. Software modifications to this bit while HCHalted bit is equal to zero results in undefined behavior.
|
||||
uint32_t : 0 ; // padding to the boundary of storage unit
|
||||
}usb_cmd_bit;
|
||||
};
|
||||
|
||||
union {
|
||||
uint32_t usb_sts ; ///< This register indicates pending interrupts and various states of the Host Controller. The status resulting from a transaction on the serial bus is not indicated in this register. Software sets a bit to 0 in this register by writing a 1 to it. See Section 4.15 for additional information concerning USB interrupt conditions.
|
||||
struct {
|
||||
uint32_t usb : 1 ; ///< R/WC The Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set. \n The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes).
|
||||
uint32_t usb_error : 1 ; ///< R/WC The Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow). If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set. See Section 4.15.1 for a list of the USB errors that will result in this bit being set to a one.
|
||||
uint32_t port_change_detect : 1 ; ///< R/WC The Host Controller sets this bit to a one when any port for which the Port Ownerbit is set to zero (see Section 2.3.9) has a change bit transition from a zero to a one or a Force Port Resumebit transition from a zero to a one as a result of a J-K transition detected on a suspended port.
|
||||
uint32_t framelist_rollover : 1 ; ///< R/WC The Host Controller sets this bit to a one when the Frame List Index(see Section 2.3.4) rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Sizefield of the USBCMD register) is 1024, the Frame Index Registerrolls over every time FRINDEX[13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles.
|
||||
uint32_t pci_host_system_error : 1 ; ///< R/WC (not used by NXP) The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. In a PCI system, conditions that set this bit to 1 include PCI Parity error, PCI Master Abort, and PCI Target Abort. When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs.
|
||||
uint32_t async_advance : 1 ; ///< R/WC 0=Default. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source.
|
||||
uint32_t : 1 ; ///< These bits are reserved and should be set to zero.
|
||||
uint32_t nxp_int_sof : 1 ; ///< R/WC NXP customized: this bit will be set every 125us and can be used by host controller driver as a time base.
|
||||
uint32_t : 4 ; ///< These bits are reserved and should be set to zero.
|
||||
uint32_t hc_halted : 1 ; ///< Read-Only 1=Default. This bit is a zero whenever the Run/Stop bit is a one. The Host Controller sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. internal error).
|
||||
uint32_t reclamation : 1 ; ///< Read-Only 0=Default. This is a read-only status bit, which is used to detect an empty asynchronous schedule. The operational model of empty schedule detection is described in Section 4.8.3. The valid transitions for this bit are described in Section 4.8.6.
|
||||
uint32_t period_schedule_status : 1 ; ///< Read-Only The bit reports the current real status of the Periodic Schedule. If this bit is a zero then the status of the Periodic Schedule is disabled. If this bit is a one then the status of the Periodic Schedule is enabled
|
||||
uint32_t async_schedule_status : 1 ; ///< Read-Only 0=Default. The bit reports the current real status of the Asynchronous Schedule. If this bit is a zero then the status of the Asynchronous Schedule is disabled. If this bit is a one then the status of the Asynchronous Schedule is enabled.
|
||||
uint32_t : 2 ; ///< reseved
|
||||
uint32_t nxp_int_async : 1 ; ///< R/WC NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set andthe TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected andthe packet is on the asynchronous schedule.
|
||||
uint32_t nxp_int_period : 1 ; ///< R/WC NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set andthe TD was from the periodic schedule.
|
||||
uint32_t : 12 ; ///< reserved
|
||||
uint32_t : 0 ; // padding to the boundary of storage unit
|
||||
}usb_sts_bit;
|
||||
};
|
||||
|
||||
union{
|
||||
uint32_t usb_int_enable ; ///< This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are disabled in this register still appear in the USBSTS to allow the software to poll for events.
|
||||
struct {
|
||||
uint32_t usb : 1 ; ///< When this bit is a one, and the USBINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINTbit.
|
||||
uint32_t usb_error : 1 ; ///< When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINTbit.
|
||||
uint32_t port_change_detect : 1 ; ///< When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detectbit.
|
||||
uint32_t framelist_rollover : 1 ; ///< When this bit is a one, and the Frame List Rolloverbit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit.
|
||||
uint32_t pci_host_system_error : 1 ; ///< (not used by NXP) When this bit is a one, and the Host System Error Statusbit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Host System Error bit.
|
||||
uint32_t async_advance : 1 ; ///< When this bit is a one, and the Interrupt on Async Advancebit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advancebit.
|
||||
uint32_t : 1 ; ///< reserved
|
||||
uint32_t nxp_int_sof : 1 ; ///< NXP customized: if this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 micro sec and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register.
|
||||
uint32_t : 10 ; ///< reserved
|
||||
uint32_t nxp_int_async : 1 ; ///< NXP customized: When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit.
|
||||
uint32_t nxp_int_period : 1 ; ///< NXP customized: When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit.
|
||||
uint32_t : 12 ; ///< reserved
|
||||
uint32_t : 0 ; // padding to the boundary of storage unit
|
||||
}usb_int_enable_bit;
|
||||
};
|
||||
|
||||
uint32_t frame_index ; ///< This register is used by the host controller to index into the periodic frame list. The register updates every 125 microseconds (once each micro-frame). Bits [N:3] are used to select a particular entry in the Periodic Frame List during periodic schedule execution. The number of bits used for the index depends on the size of the frame list as set by system software in the Frame List Sizefield in the USBCMD register
|
||||
uint32_t ctrl_ds_seg ; ///< (not used by NXP) This 32-bit register corresponds to the most significant address bits [63:32] for all EHCI data structures. If the 64-bit Addressing Capabilityfield in HCCPARAMS is a zero, then this register is not used
|
||||
uint32_t periodic_list_base ; ///< This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. System software loads this register prior to starting the schedule execution by the Host Controller (see 4.1). The memory structure referenced by this physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this register are combined with the Frame Index Register (FRINDEX) to enable the Host Controller to step through the Periodic Frame List in sequence.
|
||||
uint32_t async_list_base ; ///< This 32-bit register contains the address of the next asynchronous queue head to be executed. Bits [4:0] of this register cannot be modified by system software and will always return a zero when read. The memory structure referenced by this physical memory pointer is assumed to be 32-byte (cache line) aligned
|
||||
uint32_t tt_control ; ///< nxp embedded transaction translator (reserved by EHCI specs)
|
||||
uint32_t reserved[8] ; ///< reserved by EHCI specs
|
||||
uint32_t config_flag ; ///< (not used by NXP) configured flag register
|
||||
|
||||
union {
|
||||
uint32_t portsc ; ///< port status and control
|
||||
struct {
|
||||
uint32_t current_connect_status : 1; ///< RO 1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. This field is zero if Port Power is zero.
|
||||
uint32_t connect_status_change : 1; ///< R/WC 1=Change in Current Connect Status. 0=No change. Default = 0. Indicates a change has occurred in the port's Current Connect Status. The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be "setting" an already-set bit (i.e., the bit will remain set). Software sets this bit to 0 by writing a 1 to it. This field is zero if Port Power is zero.
|
||||
uint32_t port_enable : 1; ///< 1=Enable. 0=Disable. Default = 0. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. Note that the bit status does not change until the port state actually changes.
|
||||
uint32_t port_enable_change : 1; ///< R/WC 1=Port enabled/disabled status has changed. 0=No change. Default = 0. For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error). Software clears this bit by writing a 1 to it. This field is zero if Port Power is zero.
|
||||
uint32_t over_current_active : 1; ///< RO Default = 0. 1=This port currently has an over-current condition. 0=This port does not have an over-current condition. This bit will automatically transition from a one to a zero when the over current condition is removed.
|
||||
uint32_t over_current_change : 1; ///< R/WC Default = 0. 1=This bit gets set to a one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position.
|
||||
uint32_t force_port_resume : 1; ///< 1= Resume detected/driven on port. 0=No resume (K-state) detected/driven on port. Default = 0. This functionality defined for manipulating this bit depends on the value of the Suspendbit. For example, if the port is not suspended (Suspendand Enabledbits are a one) and software transitions this bit to a one, then the effects on the bus are undefined. Software sets this bit to a 1 to drive resume signaling. The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detectbit in the USBSTS register is also set to a one. If software sets this bit to a one, the host controller must not set the Port Change Detectbit.
|
||||
uint32_t suspend : 1; ///< 1=Port in suspend state. 0=Port not in suspend state. Default = 0. Port Enabled Bit and Suspend bit of this register define the port states as follows: Bits [Port Enabled, Suspend] Port State 0X Disable 10 Enable 11 Suspend When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. A write of zero to this bit is ignored by the host controller. The host controller will unconditionally set this bit to a zero when: •Software sets the Force Port Resumebit to a zero (from a one). •Software sets the Port Resetbit to a one (from a zero).
|
||||
uint32_t port_reset : 1; ///< 1=Port is in Reset. 0=Port is not in Reset. Default = 0. When software writes a one to this bit (from a zero)
|
||||
uint32_t nxp_highspeed_status : 1; ///< NXP customized: 0=connected to the port is not in High-speed mode, 1=connected to the port is in High-speed mode
|
||||
uint32_t line_status : 2; ///< hese bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence. This field is valid only when the port enable bit is zero and the current connect status bit is set to a one. The encoding of the bits are: 00b SE0, 10b J-state, 01b K-state, 11b undefined
|
||||
uint32_t port_power : 1; ///< 0= power off, 1= power on, Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).
|
||||
uint32_t port_owner : 1; ///< (not used by NXP)
|
||||
uint32_t port_indicator_control : 2; ///< Writing to this field effects the value of the pins USB0_IND1 and USB0_IND0. 00b: Port indication is off, 01b: Amber, 10b: green, 11b: undefined
|
||||
uint32_t port_test_control : 4; ///< When this field is zero, the port is NOT operating in a test mode. A non-zero value indicates that it is operating in test mode
|
||||
uint32_t wake_on_connect_enable : 1; ///< Default = 0b. Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. See Section 4.3 for effects of this bit on resume event behavior. Refer to Section 4.3.1 for operational model.
|
||||
uint32_t wake_on_disconnect_enable : 1; ///< Default = 0b. Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. See Section 4.3 for effects of this bit on resume event behavior. Refer to Section 4.3.1 for operational model.
|
||||
uint32_t wake_on_over_current_enable : 1; ///< Default = 0b. Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. See Section 4.3 for effects of this bit on resume event behavior. Refer to Section 4.3.1 for operational model.
|
||||
uint32_t nxp_phy_clock_disable : 1; ///< NXP customized: the PHY can be put into Low Power Suspend – Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0: enable PHY clock, 1: disable PHY clock
|
||||
uint32_t nxp_port_force_fullspeed : 1; ///< NXP customized: Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allowsthe port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device.
|
||||
uint32_t : 1;
|
||||
uint32_t nxp_port_speed : 2; ///< NXP customized: This register field indicates the speed atwhich the port is operating. For HS mode operation in the host controllerand HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. 0x0: Fullspeed, 0x1: Lowspeed, 0x2: Highspeed
|
||||
uint32_t : 0; // padding to the boundary of storage unit
|
||||
}portsc_bit;
|
||||
};
|
||||
}ehci_registers_t;
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// EHCI Data Organization
|
||||
//--------------------------------------------------------------------+
|
||||
typedef struct {
|
||||
//------------- Static Async/Period List Head, Each for one controller -------------//
|
||||
ehci_qhd_t async_head[CONTROLLER_HOST_NUMBER]; /// head qhd of async list, also is used as control endpoint for address 0
|
||||
|
||||
#if EHCI_PERIODIC_LIST
|
||||
// for NXP ECHI, only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist)
|
||||
// [0] : 1ms, [1] : 2ms, [2] : 4ms, [3] : 8 ms
|
||||
ehci_qhd_t period_head_arr[CONTROLLER_HOST_NUMBER][4];
|
||||
#endif
|
||||
|
||||
//------------- Data for Address 0 (use async head as its queue head) -------------//
|
||||
ehci_qtd_t addr0_qtd[3];
|
||||
|
||||
struct {
|
||||
struct {
|
||||
ehci_qhd_t qhd;
|
||||
ehci_qtd_t qtd[3];
|
||||
}control;
|
||||
|
||||
ehci_qhd_t qhd[HCD_MAX_ENDPOINT] ; ///< Queue Head Pool
|
||||
ehci_qtd_t qtd[HCD_MAX_XFER] ATTR_ALIGNED(32) ; ///< Queue Element Transfer Pool
|
||||
// ehci_itd_t itd[EHCI_MAX_ITD] ; ///< Iso Transfer Pool
|
||||
// ehci_sitd_t sitd[EHCI_MAX_SITD] ; ///< Split (FS) Isochronous Transfer Pool
|
||||
}device[CFG_TUSB_HOST_DEVICE_MAX];
|
||||
}ehci_data_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_EHCI_H_ */
|
||||
|
||||
/** @} */
|
||||
/** @} */
|
||||
|
||||
@@ -0,0 +1,44 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file hcd.c
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#include "hcd.h"
|
||||
|
||||
#if MODE_HOST_SUPPORTED
|
||||
|
||||
|
||||
#endif
|
||||
+129
@@ -0,0 +1,129 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file hcd.h
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
/** \ingroup group_usbh
|
||||
* \defgroup Group_HCD Host Controller Driver (HCD)
|
||||
* @{ */
|
||||
|
||||
#ifndef _TUSB_HCD_H_
|
||||
#define _TUSB_HCD_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <common/tusb_common.h>
|
||||
|
||||
#if MODE_HOST_SUPPORTED
|
||||
// Max number of endpoints per device
|
||||
enum {
|
||||
HCD_MAX_ENDPOINT = CFG_TUSB_HOST_HUB + CFG_TUSB_HOST_HID_KEYBOARD + CFG_TUSB_HOST_HID_MOUSE + CFG_TUSB_HOST_HID_GENERIC +
|
||||
CFG_TUSB_HOST_MSC*2 + CFG_TUSB_HOST_CDC*3,
|
||||
|
||||
HCD_MAX_XFER = HCD_MAX_ENDPOINT*2,
|
||||
};
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO CONSTANT TYPEDEF
|
||||
//--------------------------------------------------------------------+
|
||||
typedef struct {
|
||||
uint8_t dev_addr;
|
||||
uint8_t xfer_type;
|
||||
uint8_t index;
|
||||
uint8_t reserved;
|
||||
} pipe_handle_t;
|
||||
|
||||
static inline bool pipehandle_is_valid(pipe_handle_t pipe_hdl) ATTR_CONST ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;
|
||||
static inline bool pipehandle_is_valid(pipe_handle_t pipe_hdl)
|
||||
{
|
||||
return pipe_hdl.dev_addr > 0;
|
||||
}
|
||||
|
||||
static inline bool pipehandle_is_equal(pipe_handle_t x, pipe_handle_t y) ATTR_CONST ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;
|
||||
static inline bool pipehandle_is_equal(pipe_handle_t x, pipe_handle_t y)
|
||||
{
|
||||
return (x.dev_addr == y.dev_addr) && (x.xfer_type == y.xfer_type) && (x.index == y.index);
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// USBH-HCD API
|
||||
//--------------------------------------------------------------------+
|
||||
tusb_error_t hcd_init(void) ATTR_WARN_UNUSED_RESULT;
|
||||
void hal_hcd_isr(uint8_t hostid);
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// PIPE API
|
||||
//--------------------------------------------------------------------+
|
||||
// TODO control xfer should be used via usbh layer
|
||||
tusb_error_t hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size) ATTR_WARN_UNUSED_RESULT;
|
||||
tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[]) ATTR_WARN_UNUSED_RESULT;
|
||||
tusb_error_t hcd_pipe_control_close(uint8_t dev_addr) ATTR_WARN_UNUSED_RESULT;
|
||||
|
||||
pipe_handle_t hcd_pipe_open(uint8_t dev_addr, tusb_desc_endpoint_t const * endpoint_desc, uint8_t class_code) ATTR_WARN_UNUSED_RESULT;
|
||||
tusb_error_t hcd_pipe_queue_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t total_bytes) ATTR_WARN_UNUSED_RESULT; // only queue, not transferring yet
|
||||
tusb_error_t hcd_pipe_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete) ATTR_WARN_UNUSED_RESULT;
|
||||
tusb_error_t hcd_pipe_close(pipe_handle_t pipe_hdl) /*ATTR_WARN_UNUSED_RESULT*/;
|
||||
|
||||
bool hcd_pipe_is_busy(pipe_handle_t pipe_hdl) ATTR_PURE;
|
||||
bool hcd_pipe_is_error(pipe_handle_t pipe_hdl) ATTR_PURE;
|
||||
bool hcd_pipe_is_stalled(pipe_handle_t pipe_hdl) ATTR_PURE; // stalled also counted as error
|
||||
|
||||
uint8_t hcd_pipe_get_endpoint_addr(pipe_handle_t pipe_hdl) ATTR_PURE;
|
||||
tusb_error_t hcd_pipe_clear_stall(pipe_handle_t pipe_hdl);
|
||||
|
||||
#if 0
|
||||
tusb_error_t hcd_pipe_cancel()ATTR_WARN_UNUSED_RESULT;
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// PORT API
|
||||
//--------------------------------------------------------------------+
|
||||
/// return the current connect status of roothub port
|
||||
bool hcd_port_connect_status(uint8_t hostid) ATTR_PURE ATTR_WARN_UNUSED_RESULT; // TODO make inline if possible
|
||||
void hcd_port_reset(uint8_t hostid);
|
||||
tusb_speed_t hcd_port_speed_get(uint8_t hostid) ATTR_PURE ATTR_WARN_UNUSED_RESULT; // TODO make inline if possible
|
||||
void hcd_port_unplug(uint8_t hostid); // called by usbh to instruct hcd that it can execute unplug procedure
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_HCD_H_ */
|
||||
|
||||
/// @}
|
||||
+251
@@ -0,0 +1,251 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file hub.c
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#include "tusb_option.h"
|
||||
|
||||
#if (MODE_HOST_SUPPORTED && CFG_TUSB_HOST_HUB)
|
||||
|
||||
#define _TINY_USB_SOURCE_FILE_
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// INCLUDE
|
||||
//--------------------------------------------------------------------+
|
||||
#include "hub.h"
|
||||
#include "usbh_hub.h"
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO CONSTANT TYPEDEF
|
||||
//--------------------------------------------------------------------+
|
||||
typedef struct {
|
||||
pipe_handle_t pipe_status;
|
||||
uint8_t interface_number;
|
||||
uint8_t port_number;
|
||||
uint8_t status_change; // data from status change interrupt endpoint
|
||||
}usbh_hub_t;
|
||||
|
||||
CFG_TUSB_ATTR_USBRAM STATIC_VAR usbh_hub_t hub_data[CFG_TUSB_HOST_DEVICE_MAX];
|
||||
ATTR_ALIGNED(4) CFG_TUSB_ATTR_USBRAM STATIC_VAR uint8_t hub_enum_buffer[sizeof(descriptor_hub_desc_t)];
|
||||
|
||||
//OSAL_SEM_DEF(hub_enum_semaphore);
|
||||
//static osal_semaphore_handle_t hub_enum_sem_hdl;
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// HUB
|
||||
//--------------------------------------------------------------------+
|
||||
tusb_error_t hub_port_clear_feature_subtask(uint8_t hub_addr, uint8_t hub_port, uint8_t feature)
|
||||
{
|
||||
tusb_error_t error;
|
||||
|
||||
OSAL_SUBTASK_BEGIN
|
||||
|
||||
STASK_ASSERT(HUB_FEATURE_PORT_CONNECTION_CHANGE <= feature &&
|
||||
feature <= HUB_FEATURE_PORT_RESET_CHANGE);
|
||||
|
||||
//------------- Clear Port Feature request -------------//
|
||||
STASK_INVOKE(
|
||||
usbh_control_xfer_subtask( hub_addr, bm_request_type(TUSB_DIR_OUT, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_OTHER),
|
||||
HUB_REQUEST_CLEAR_FEATURE, feature, hub_port,
|
||||
0, NULL ),
|
||||
error
|
||||
);
|
||||
STASK_ASSERT_ERR( error );
|
||||
|
||||
//------------- Get Port Status to check if feature is cleared -------------//
|
||||
STASK_INVOKE(
|
||||
usbh_control_xfer_subtask( hub_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_OTHER),
|
||||
HUB_REQUEST_GET_STATUS, 0, hub_port,
|
||||
4, hub_enum_buffer ),
|
||||
error
|
||||
);
|
||||
STASK_ASSERT_ERR( error );
|
||||
|
||||
//------------- Check if feature is cleared -------------//
|
||||
hub_port_status_response_t * p_port_status;
|
||||
p_port_status = (hub_port_status_response_t *) hub_enum_buffer;
|
||||
|
||||
STASK_ASSERT( !BIT_TEST_(p_port_status->status_change.value, feature-16) );
|
||||
|
||||
OSAL_SUBTASK_END
|
||||
}
|
||||
|
||||
tusb_error_t hub_port_reset_subtask(uint8_t hub_addr, uint8_t hub_port)
|
||||
{
|
||||
enum { RESET_DELAY = 200 }; // USB specs say only 50ms but many devices require much longer
|
||||
tusb_error_t error;
|
||||
|
||||
OSAL_SUBTASK_BEGIN
|
||||
|
||||
//------------- Set Port Reset -------------//
|
||||
STASK_INVOKE(
|
||||
usbh_control_xfer_subtask( hub_addr, bm_request_type(TUSB_DIR_OUT, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_OTHER),
|
||||
HUB_REQUEST_SET_FEATURE, HUB_FEATURE_PORT_RESET, hub_port,
|
||||
0, NULL ),
|
||||
error
|
||||
);
|
||||
STASK_ASSERT_ERR( error );
|
||||
|
||||
osal_task_delay(RESET_DELAY); // TODO Hub wait for Status Endpoint on Reset Change
|
||||
|
||||
//------------- Get Port Status to check if port is enabled, powered and reset_change -------------//
|
||||
STASK_INVOKE(
|
||||
usbh_control_xfer_subtask( hub_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_OTHER),
|
||||
HUB_REQUEST_GET_STATUS, 0, hub_port,
|
||||
4, hub_enum_buffer ),
|
||||
error
|
||||
);
|
||||
STASK_ASSERT_ERR( error );
|
||||
|
||||
hub_port_status_response_t * p_port_status;
|
||||
p_port_status = (hub_port_status_response_t *) hub_enum_buffer;
|
||||
|
||||
STASK_ASSERT ( p_port_status->status_change.reset && p_port_status->status_current.connect_status &&
|
||||
p_port_status->status_current.port_power && p_port_status->status_current.port_enable);
|
||||
|
||||
OSAL_SUBTASK_END
|
||||
}
|
||||
|
||||
// can only get the speed RIGHT AFTER hub_port_reset_subtask call
|
||||
tusb_speed_t hub_port_get_speed(void)
|
||||
{
|
||||
hub_port_status_response_t * p_port_status = (hub_port_status_response_t *) hub_enum_buffer;
|
||||
return (p_port_status->status_current.high_speed_device_attached) ? TUSB_SPEED_HIGH :
|
||||
(p_port_status->status_current.low_speed_device_attached ) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// CLASS-USBH API (don't require to verify parameters)
|
||||
//--------------------------------------------------------------------+
|
||||
void hub_init(void)
|
||||
{
|
||||
memclr_(hub_data, CFG_TUSB_HOST_DEVICE_MAX*sizeof(usbh_hub_t));
|
||||
// hub_enum_sem_hdl = osal_semaphore_create( OSAL_SEM_REF(hub_enum_semaphore) );
|
||||
}
|
||||
|
||||
tusb_error_t hub_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length)
|
||||
{
|
||||
tusb_error_t error;
|
||||
|
||||
OSAL_SUBTASK_BEGIN
|
||||
|
||||
// not support multiple TT yet
|
||||
if ( p_interface_desc->bInterfaceProtocol > 1 ) return TUSB_ERROR_HUB_FEATURE_NOT_SUPPORTED;
|
||||
|
||||
//------------- Open Interrupt Status Pipe -------------//
|
||||
tusb_desc_endpoint_t const *p_endpoint;
|
||||
p_endpoint = (tusb_desc_endpoint_t const *) descriptor_next( (uint8_t const*) p_interface_desc );
|
||||
|
||||
STASK_ASSERT(TUSB_DESC_ENDPOINT == p_endpoint->bDescriptorType);
|
||||
STASK_ASSERT(TUSB_XFER_INTERRUPT == p_endpoint->bmAttributes.xfer);
|
||||
|
||||
hub_data[dev_addr-1].pipe_status = hcd_pipe_open(dev_addr, p_endpoint, TUSB_CLASS_HUB);
|
||||
STASK_ASSERT( pipehandle_is_valid(hub_data[dev_addr-1].pipe_status) );
|
||||
hub_data[dev_addr-1].interface_number = p_interface_desc->bInterfaceNumber;
|
||||
|
||||
(*p_length) = sizeof(tusb_desc_interface_t) + sizeof(tusb_desc_endpoint_t);
|
||||
|
||||
//------------- Get Hub Descriptor -------------//
|
||||
STASK_INVOKE(
|
||||
usbh_control_xfer_subtask( dev_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_DEVICE),
|
||||
HUB_REQUEST_GET_DESCRIPTOR, 0, 0,
|
||||
sizeof(descriptor_hub_desc_t), hub_enum_buffer ),
|
||||
error
|
||||
);
|
||||
STASK_ASSERT_ERR(error);
|
||||
|
||||
// only care about this field in hub descriptor
|
||||
hub_data[dev_addr-1].port_number = ((descriptor_hub_desc_t*) hub_enum_buffer)->bNbrPorts;
|
||||
|
||||
//------------- Set Port_Power on all ports -------------//
|
||||
static uint8_t i;
|
||||
for(i=1; i <= hub_data[dev_addr-1].port_number; i++)
|
||||
{
|
||||
STASK_INVOKE(
|
||||
usbh_control_xfer_subtask( dev_addr, bm_request_type(TUSB_DIR_OUT, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_OTHER),
|
||||
HUB_REQUEST_SET_FEATURE, HUB_FEATURE_PORT_POWER, i,
|
||||
0, NULL ),
|
||||
error
|
||||
);
|
||||
}
|
||||
|
||||
//------------- Queue the initial Status endpoint transfer -------------//
|
||||
STASK_ASSERT_ERR ( hcd_pipe_xfer(hub_data[dev_addr-1].pipe_status, &hub_data[dev_addr-1].status_change, 1, true) );
|
||||
|
||||
OSAL_SUBTASK_END
|
||||
}
|
||||
|
||||
// is the response of interrupt endpoint polling
|
||||
void hub_isr(pipe_handle_t pipe_hdl, tusb_event_t event, uint32_t xferred_bytes)
|
||||
{
|
||||
(void) xferred_bytes; // TODO can be more than 1 for hub with lots of ports
|
||||
|
||||
usbh_hub_t * p_hub = &hub_data[pipe_hdl.dev_addr-1];
|
||||
|
||||
if ( event == TUSB_EVENT_XFER_COMPLETE )
|
||||
{
|
||||
for (uint8_t port=1; port <= p_hub->port_number; port++)
|
||||
{ // TODO HUB ignore bit0 hub_status_change
|
||||
if ( BIT_TEST_(p_hub->status_change, port) )
|
||||
{
|
||||
usbh_hub_port_plugged_isr(pipe_hdl.dev_addr, port);
|
||||
break; // handle one port at a time, next port if any will be handled in the next cycle
|
||||
}
|
||||
}
|
||||
// NOTE: next status transfer is queued by usbh.c after handling this request
|
||||
}
|
||||
else
|
||||
{
|
||||
// TODO [HUB] check if hub is still plugged before polling status endpoint since failed usually mean hub unplugged
|
||||
// TU_ASSERT ( TUSB_ERROR_NONE == hcd_pipe_xfer(pipe_hdl, &p_hub->status_change, 1, true) );
|
||||
}
|
||||
}
|
||||
|
||||
void hub_close(uint8_t dev_addr)
|
||||
{
|
||||
(void) hcd_pipe_close(hub_data[dev_addr-1].pipe_status);
|
||||
memclr_(&hub_data[dev_addr-1], sizeof(usbh_hub_t));
|
||||
|
||||
// osal_semaphore_reset(hub_enum_sem_hdl);
|
||||
}
|
||||
|
||||
tusb_error_t hub_status_pipe_queue(uint8_t dev_addr)
|
||||
{
|
||||
return hcd_pipe_xfer(hub_data[dev_addr-1].pipe_status, &hub_data[dev_addr-1].status_change, 1, true);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
+210
@@ -0,0 +1,210 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file hub.h
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
/** \ingroup group_class
|
||||
* \defgroup ClassDriver_Hub Hub (Host only)
|
||||
* \details Like most PC's OS, Hub support is completely hidden from Application. In fact, application cannot determine whether
|
||||
* a device is mounted directly via roothub or via a hub's port. All Hub-related procedures are performed and managed
|
||||
* by tinyusb stack. Unless you are trying to develop the stack itself, there are nothing else can be used by Application.
|
||||
* \note Due to my laziness, only 1-level of Hub is supported. In other way, the stack cannot mount a hub via another hub.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _TUSB_HUB_H_
|
||||
#define _TUSB_HUB_H_
|
||||
|
||||
#include <common/tusb_common.h>
|
||||
#include "usbh.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//D1...D0: Logical Power Switching Mode
|
||||
//00: Ganged power switching (all ports’power at
|
||||
//once)
|
||||
//01: Individual port power switching
|
||||
//1X: Reserved. Used only on 1.0 compliant hubs
|
||||
//that implement no power switching
|
||||
//D2: Identifies a Compound Device
|
||||
//0: Hub is not part of a compound device.
|
||||
//1: Hub is part of a compound device.
|
||||
//D4...D3: Over-current Protection Mode
|
||||
//00: Global Over-current Protection. The hub
|
||||
//reports over-current as a summation of all
|
||||
//ports’current draw, without a breakdown of
|
||||
//individual port over-current status.
|
||||
//01: Individual Port Over-current Protection. The
|
||||
//hub reports over-current on a per-port basis.
|
||||
//Each port has an over-current status.
|
||||
//1X: No Over-current Protection. This option is
|
||||
//allowed only for bus-powered hubs that do not
|
||||
//implement over-current protection.
|
||||
//
|
||||
//D6...D5: TT Think TIme
|
||||
//00: TT requires at most 8 FS bit times of inter
|
||||
//transaction gap on a full-/low-speed
|
||||
//downstream bus.
|
||||
//01: TT requires at most 16 FS bit times.
|
||||
//10: TT requires at most 24 FS bit times.
|
||||
//11: TT requires at most 32 FS bit times.
|
||||
//D7: Port Indicators Supported
|
||||
//0: Port Indicators are not supported on its
|
||||
//downstream facing ports and the
|
||||
//PORT_INDICATOR request has no effect.
|
||||
//1: Port Indicators are supported on its
|
||||
//downstream facing ports and the
|
||||
//PORT_INDICATOR request controls the
|
||||
//indicators. See Section 11.5.3.
|
||||
//D15...D8: Reserved
|
||||
|
||||
typedef struct ATTR_PACKED{
|
||||
uint8_t bLength ; ///< Size of descriptor
|
||||
uint8_t bDescriptorType ; ///< Other_speed_Configuration Type
|
||||
uint8_t bNbrPorts;
|
||||
uint16_t wHubCharacteristics;
|
||||
uint8_t bPwrOn2PwrGood;
|
||||
uint8_t bHubContrCurrent;
|
||||
uint8_t DeviceRemovable; // bitmap each bit for a port (from bit1)
|
||||
uint8_t PortPwrCtrlMask; // just for compatibility, should be 0xff
|
||||
} descriptor_hub_desc_t;
|
||||
|
||||
VERIFY_STATIC( sizeof(descriptor_hub_desc_t) == 9, "size is not correct");
|
||||
|
||||
enum {
|
||||
HUB_REQUEST_GET_STATUS = 0 ,
|
||||
HUB_REQUEST_CLEAR_FEATURE = 1 ,
|
||||
|
||||
HUB_REQUEST_SET_FEATURE = 3 ,
|
||||
|
||||
HUB_REQUEST_GET_DESCRIPTOR = 6 ,
|
||||
HUB_REQUEST_SET_DESCRIPTOR = 7 ,
|
||||
HUB_REQUEST_CLEAR_TT_BUFFER = 8 ,
|
||||
HUB_REQUEST_RESET_TT = 9 ,
|
||||
HUB_REQUEST_GET_TT_STATE = 10 ,
|
||||
HUB_REQUEST_STOP_TT = 11
|
||||
};
|
||||
|
||||
enum {
|
||||
HUB_FEATURE_HUB_LOCAL_POWER_CHANGE = 0,
|
||||
HUB_FEATURE_HUB_OVER_CURRENT_CHANGE
|
||||
};
|
||||
|
||||
enum{
|
||||
HUB_FEATURE_PORT_CONNECTION = 0,
|
||||
HUB_FEATURE_PORT_ENABLE = 1,
|
||||
HUB_FEATURE_PORT_SUSPEND = 2,
|
||||
HUB_FEATURE_PORT_OVER_CURRENT = 3,
|
||||
HUB_FEATURE_PORT_RESET = 4,
|
||||
|
||||
HUB_FEATURE_PORT_POWER = 8,
|
||||
HUB_FEATURE_PORT_LOW_SPEED = 9,
|
||||
|
||||
HUB_FEATURE_PORT_CONNECTION_CHANGE = 16,
|
||||
HUB_FEATURE_PORT_ENABLE_CHANGE = 17,
|
||||
HUB_FEATURE_PORT_SUSPEND_CHANGE = 18,
|
||||
HUB_FEATURE_PORT_OVER_CURRENT_CHANGE = 19,
|
||||
HUB_FEATURE_PORT_RESET_CHANGE = 20,
|
||||
HUB_FEATURE_PORT_TEST = 21,
|
||||
HUB_FEATURE_PORT_INDICATOR = 22
|
||||
};
|
||||
|
||||
// data in response of HUB_REQUEST_GET_STATUS, wIndex = 0 (hub)
|
||||
typedef struct {
|
||||
union{
|
||||
struct ATTR_PACKED {
|
||||
uint16_t local_power_source : 1;
|
||||
uint16_t over_current : 1;
|
||||
uint16_t : 14;
|
||||
};
|
||||
|
||||
uint16_t value;
|
||||
} status, status_change;
|
||||
} hub_status_response_t;
|
||||
|
||||
VERIFY_STATIC( sizeof(hub_status_response_t) == 4, "size is not correct");
|
||||
|
||||
// data in response of HUB_REQUEST_GET_STATUS, wIndex = Port num
|
||||
typedef struct {
|
||||
union {
|
||||
struct ATTR_PACKED {
|
||||
uint16_t connect_status : 1;
|
||||
uint16_t port_enable : 1;
|
||||
uint16_t suspend : 1;
|
||||
uint16_t over_current : 1;
|
||||
uint16_t reset : 1;
|
||||
|
||||
uint16_t : 3;
|
||||
uint16_t port_power : 1;
|
||||
uint16_t low_speed_device_attached : 1;
|
||||
uint16_t high_speed_device_attached : 1;
|
||||
uint16_t port_test_mode : 1;
|
||||
uint16_t port_indicator_control : 1;
|
||||
uint16_t : 0;
|
||||
};
|
||||
|
||||
uint16_t value;
|
||||
} status_current, status_change;
|
||||
} hub_port_status_response_t;
|
||||
|
||||
VERIFY_STATIC( sizeof(hub_port_status_response_t) == 4, "size is not correct");
|
||||
|
||||
tusb_error_t hub_port_reset_subtask(uint8_t hub_addr, uint8_t hub_port);
|
||||
tusb_error_t hub_port_clear_feature_subtask(uint8_t hub_addr, uint8_t hub_port, uint8_t feature);
|
||||
tusb_speed_t hub_port_get_speed(void);
|
||||
tusb_error_t hub_status_pipe_queue(uint8_t dev_addr);
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// USBH-CLASS DRIVER API
|
||||
//--------------------------------------------------------------------+
|
||||
#ifdef _TINY_USB_SOURCE_FILE_
|
||||
|
||||
void hub_init(void);
|
||||
tusb_error_t hub_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length) ATTR_WARN_UNUSED_RESULT;
|
||||
void hub_isr(pipe_handle_t pipe_hdl, tusb_event_t event, uint32_t xferred_bytes);
|
||||
void hub_close(uint8_t dev_addr);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_HUB_H_ */
|
||||
|
||||
/** @} */
|
||||
@@ -0,0 +1,710 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file ohci.c
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#include <common/tusb_common.h>
|
||||
|
||||
#if MODE_HOST_SUPPORTED && (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X)
|
||||
//--------------------------------------------------------------------+
|
||||
// INCLUDE
|
||||
//--------------------------------------------------------------------+
|
||||
#include "hal/hal.h"
|
||||
#include "osal/osal.h"
|
||||
#include "common/timeout_timer.h"
|
||||
|
||||
#include "../hcd.h"
|
||||
#include "../usbh_hcd.h"
|
||||
#include "ohci.h"
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO CONSTANT TYPEDEF
|
||||
//--------------------------------------------------------------------+
|
||||
#define OHCI_REG ((ohci_registers_t *) LPC_USB_BASE)
|
||||
|
||||
enum {
|
||||
OHCI_CONTROL_FUNCSTATE_RESET = 0,
|
||||
OHCI_CONTROL_FUNCSTATE_RESUME,
|
||||
OHCI_CONTROL_FUNCSTATE_OPERATIONAL,
|
||||
OHCI_CONTROL_FUNCSTATE_SUSPEND
|
||||
};
|
||||
|
||||
enum {
|
||||
OHCI_CONTROL_CONTROL_BULK_RATIO = 3, ///< This specifies the service ratio between Control and Bulk EDs. 0 = 1:1, 3 = 4:1
|
||||
OHCI_CONTROL_LIST_PERIODIC_ENABLE_MASK = BIT_(2),
|
||||
OHCI_CONTROL_LIST_ISOCHRONOUS_ENABLE_MASK = BIT_(3),
|
||||
OHCI_CONTROL_LIST_CONTROL_ENABLE_MASK = BIT_(4),
|
||||
OHCI_CONTROL_LIST_BULK_ENABLE_MASK = BIT_(5),
|
||||
};
|
||||
|
||||
enum {
|
||||
OHCI_FMINTERVAL_FI = 0x2EDF, // 7.3.1 nominal (reset) value
|
||||
OHCI_FMINTERVAL_FSMPS = (6*(OHCI_FMINTERVAL_FI-210)) / 7, // 5.4 calculated based on maximum overhead + bit stuffing
|
||||
};
|
||||
|
||||
enum {
|
||||
OHCI_PERIODIC_START = 0x3E67
|
||||
};
|
||||
|
||||
#ifdef __CC_ARM
|
||||
#pragma diag_suppress 66 // Suppress Keil warnings #66-D: enumeration value is out of "int" range
|
||||
#endif
|
||||
|
||||
enum {
|
||||
OHCI_INT_SCHEDULING_OVERUN_MASK = BIT_(0),
|
||||
OHCI_INT_WRITEBACK_DONEHEAD_MASK = BIT_(1),
|
||||
OHCI_INT_SOF_MASK = BIT_(2),
|
||||
OHCI_INT_RESUME_DETECTED_MASK = BIT_(3),
|
||||
OHCI_INT_UNRECOVERABLE_ERROR_MASK = BIT_(4),
|
||||
OHCI_INT_FRAME_OVERFLOW_MASK = BIT_(5),
|
||||
OHCI_INT_RHPORT_STATUS_CHANGE_MASK = BIT_(6),
|
||||
|
||||
OHCI_INT_OWNERSHIP_CHANGE_MASK = BIT_(30),
|
||||
OHCI_INT_MASTER_ENABLE_MASK = BIT_(31),
|
||||
};
|
||||
|
||||
#ifdef __CC_ARM
|
||||
#pragma diag_default 66 // return Keil 66 to normal severity
|
||||
#endif
|
||||
|
||||
enum {
|
||||
OHCI_RHPORT_CURRENT_CONNECT_STATUS_MASK = BIT_(0),
|
||||
OHCI_RHPORT_PORT_ENABLE_STATUS_MASK = BIT_(1),
|
||||
OHCI_RHPORT_PORT_SUSPEND_STATUS_MASK = BIT_(2),
|
||||
OHCI_RHPORT_PORT_OVER_CURRENT_INDICATOR_MASK = BIT_(3),
|
||||
OHCI_RHPORT_PORT_RESET_STATUS_MASK = BIT_(4), ///< write '1' to reset port
|
||||
|
||||
OHCI_RHPORT_PORT_POWER_STATUS_MASK = BIT_(8),
|
||||
OHCI_RHPORT_LOW_SPEED_DEVICE_ATTACHED_MASK = BIT_(9),
|
||||
|
||||
OHCI_RHPORT_CONNECT_STATUS_CHANGE_MASK = BIT_(16),
|
||||
OHCI_RHPORT_PORT_ENABLE_CHANGE_MASK = BIT_(17),
|
||||
OHCI_RHPORT_PORT_SUSPEND_CHANGE_MASK = BIT_(18),
|
||||
OHCI_RHPORT_OVER_CURRENT_CHANGE_MASK = BIT_(19),
|
||||
OHCI_RHPORT_PORT_RESET_CHANGE_MASK = BIT_(20),
|
||||
|
||||
OHCI_RHPORT_ALL_CHANGE_MASK = OHCI_RHPORT_CONNECT_STATUS_CHANGE_MASK | OHCI_RHPORT_PORT_ENABLE_CHANGE_MASK |
|
||||
OHCI_RHPORT_PORT_SUSPEND_CHANGE_MASK | OHCI_RHPORT_OVER_CURRENT_CHANGE_MASK | OHCI_RHPORT_PORT_RESET_CHANGE_MASK
|
||||
};
|
||||
|
||||
enum {
|
||||
OHCI_CCODE_NO_ERROR = 0,
|
||||
OHCI_CCODE_CRC = 1,
|
||||
OHCI_CCODE_BIT_STUFFING = 2,
|
||||
OHCI_CCODE_DATA_TOGGLE_MISMATCH = 3,
|
||||
OHCI_CCODE_STALL = 4,
|
||||
OHCI_CCODE_DEVICE_NOT_RESPONDING = 5,
|
||||
OHCI_CCODE_PID_CHECK_FAILURE = 6,
|
||||
OHCI_CCODE_UNEXPECTED_PID = 7,
|
||||
OHCI_CCODE_DATA_OVERRUN = 8,
|
||||
OHCI_CCODE_DATA_UNDERRUN = 9,
|
||||
OHCI_CCODE_BUFFER_OVERRUN = 12,
|
||||
OHCI_CCODE_BUFFER_UNDERRUN = 13,
|
||||
OHCI_CCODE_NOT_ACCESSED = 14,
|
||||
};
|
||||
|
||||
enum {
|
||||
OHCI_INT_ON_COMPLETE_YES = 0,
|
||||
OHCI_INT_ON_COMPLETE_NO = BIN8(111)
|
||||
};
|
||||
//--------------------------------------------------------------------+
|
||||
// INTERNAL OBJECT & FUNCTION DECLARATION
|
||||
//--------------------------------------------------------------------+
|
||||
CFG_TUSB_ATTR_USBRAM ATTR_ALIGNED(256) STATIC_VAR ohci_data_t ohci_data;
|
||||
|
||||
static ohci_ed_t * const p_ed_head[] =
|
||||
{
|
||||
[TUSB_XFER_CONTROL] = &ohci_data.control[0].ed,
|
||||
[TUSB_XFER_BULK ] = &ohci_data.bulk_head_ed,
|
||||
[TUSB_XFER_INTERRUPT] = &ohci_data.period_head_ed,
|
||||
[TUSB_XFER_ISOCHRONOUS] = NULL // TODO Isochronous
|
||||
};
|
||||
|
||||
static void ed_list_insert(ohci_ed_t * p_pre, ohci_ed_t * p_ed);
|
||||
static void ed_list_remove(ohci_ed_t * p_head, ohci_ed_t * p_ed);
|
||||
|
||||
static ohci_ed_t * ed_list_find_previous(ohci_ed_t const * p_head, ohci_ed_t const * p_ed);
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// USBH-HCD API
|
||||
//--------------------------------------------------------------------+
|
||||
// Initialization according to 5.1.1.4
|
||||
tusb_error_t hcd_init(void)
|
||||
{
|
||||
//------------- Data Structure init -------------//
|
||||
memclr_(&ohci_data, sizeof(ohci_data_t));
|
||||
for(uint8_t i=0; i<32; i++)
|
||||
{ // assign all interrupt pointes to period head ed
|
||||
ohci_data.hcca.interrupt_table[i] = (uint32_t) &ohci_data.period_head_ed;
|
||||
}
|
||||
|
||||
ohci_data.control[0].ed.skip = 1;
|
||||
ohci_data.bulk_head_ed.skip = 1;
|
||||
ohci_data.period_head_ed.skip = 1;
|
||||
|
||||
// reset controller
|
||||
OHCI_REG->command_status_bit.controller_reset = 1;
|
||||
while( OHCI_REG->command_status_bit.controller_reset ) {} // should not take longer than 10 us
|
||||
|
||||
//------------- init ohci registers -------------//
|
||||
OHCI_REG->control_head_ed = (uint32_t) &ohci_data.control[0].ed;
|
||||
OHCI_REG->bulk_head_ed = (uint32_t) &ohci_data.bulk_head_ed;
|
||||
OHCI_REG->hcca = (uint32_t) &ohci_data.hcca;
|
||||
|
||||
OHCI_REG->interrupt_disable = OHCI_REG->interrupt_enable; // disable all interrupts
|
||||
OHCI_REG->interrupt_status = OHCI_REG->interrupt_status; // clear current set bits
|
||||
OHCI_REG->interrupt_enable = OHCI_INT_WRITEBACK_DONEHEAD_MASK | OHCI_INT_RESUME_DETECTED_MASK |
|
||||
OHCI_INT_UNRECOVERABLE_ERROR_MASK | /*OHCI_INT_FRAME_OVERFLOW_MASK |*/ OHCI_INT_RHPORT_STATUS_CHANGE_MASK |
|
||||
OHCI_INT_MASTER_ENABLE_MASK;
|
||||
|
||||
OHCI_REG->control |= OHCI_CONTROL_CONTROL_BULK_RATIO | OHCI_CONTROL_LIST_CONTROL_ENABLE_MASK |
|
||||
OHCI_CONTROL_LIST_BULK_ENABLE_MASK | OHCI_CONTROL_LIST_PERIODIC_ENABLE_MASK; // TODO Isochronous
|
||||
|
||||
OHCI_REG->frame_interval = (OHCI_FMINTERVAL_FSMPS << 16) | OHCI_FMINTERVAL_FI;
|
||||
OHCI_REG->periodic_start = (OHCI_FMINTERVAL_FI * 9) / 10; // Periodic start is 90% of frame interval
|
||||
|
||||
OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_OPERATIONAL; // make HC's state to operational state TODO use this to suspend (save power)
|
||||
OHCI_REG->rh_status_bit.local_power_status_change = 1; // set global power for ports
|
||||
|
||||
return TUSB_ERROR_NONE;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// PORT API
|
||||
//--------------------------------------------------------------------+
|
||||
void hcd_port_reset(uint8_t hostid)
|
||||
{
|
||||
OHCI_REG->rhport_status[0] = OHCI_RHPORT_PORT_RESET_STATUS_MASK;
|
||||
}
|
||||
|
||||
bool hcd_port_connect_status(uint8_t hostid)
|
||||
{
|
||||
return OHCI_REG->rhport_status_bit[0].current_connect_status;
|
||||
}
|
||||
|
||||
tusb_speed_t hcd_port_speed_get(uint8_t hostid)
|
||||
{
|
||||
return OHCI_REG->rhport_status_bit[0].low_speed_device_attached ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
|
||||
}
|
||||
|
||||
// TODO refractor abtract later
|
||||
void hcd_port_unplug(uint8_t hostid)
|
||||
{
|
||||
// TODO OHCI
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Controller API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// CONTROL PIPE API
|
||||
//--------------------------------------------------------------------+
|
||||
static inline tusb_xfer_type_t ed_get_xfer_type(ohci_ed_t const * const p_ed) ATTR_PURE ATTR_ALWAYS_INLINE;
|
||||
static inline tusb_xfer_type_t ed_get_xfer_type(ohci_ed_t const * const p_ed)
|
||||
{
|
||||
return (p_ed->endpoint_number == 0 ) ? TUSB_XFER_CONTROL :
|
||||
(p_ed->is_iso ) ? TUSB_XFER_ISOCHRONOUS :
|
||||
(p_ed->is_interrupt_xfer ) ? TUSB_XFER_INTERRUPT : TUSB_XFER_BULK;
|
||||
}
|
||||
|
||||
static void ed_init(ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t max_packet_size, uint8_t endpoint_addr, uint8_t xfer_type, uint8_t interval)
|
||||
{
|
||||
// address 0 is used as async head, which always on the list --> cannot be cleared
|
||||
if (dev_addr != 0)
|
||||
{
|
||||
memclr_(p_ed, sizeof(ohci_ed_t));
|
||||
}
|
||||
|
||||
p_ed->device_address = dev_addr;
|
||||
p_ed->endpoint_number = endpoint_addr & 0x0F;
|
||||
p_ed->direction = (xfer_type == TUSB_XFER_CONTROL) ? OHCI_PID_SETUP : ( (endpoint_addr & TUSB_DIR_IN_MASK) ? OHCI_PID_IN : OHCI_PID_OUT );
|
||||
p_ed->speed = usbh_devices[dev_addr].speed;
|
||||
p_ed->is_iso = (xfer_type == TUSB_XFER_ISOCHRONOUS) ? 1 : 0;
|
||||
p_ed->max_package_size = max_packet_size;
|
||||
|
||||
p_ed->used = 1;
|
||||
p_ed->is_interrupt_xfer = (xfer_type == TUSB_XFER_INTERRUPT ? 1 : 0);
|
||||
}
|
||||
|
||||
static void gtd_init(ohci_gtd_t* p_td, void* data_ptr, uint16_t total_bytes)
|
||||
{
|
||||
memclr_(p_td, sizeof(ohci_gtd_t));
|
||||
|
||||
p_td->used = 1;
|
||||
p_td->expected_bytes = total_bytes;
|
||||
|
||||
p_td->buffer_rounding = 1; // less than queued length is not a error
|
||||
p_td->delay_interrupt = OHCI_INT_ON_COMPLETE_NO;
|
||||
p_td->condition_code = OHCI_CCODE_NOT_ACCESSED;
|
||||
|
||||
p_td->current_buffer_pointer = data_ptr;
|
||||
p_td->buffer_end = total_bytes ? (((uint8_t*) data_ptr) + total_bytes-1) : NULL;
|
||||
}
|
||||
|
||||
tusb_error_t hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
|
||||
{
|
||||
ohci_ed_t* const p_ed = &ohci_data.control[dev_addr].ed;
|
||||
|
||||
ed_init(p_ed, dev_addr, max_packet_size, 0, TUSB_XFER_CONTROL, 0); // TODO binterval of control is ignored
|
||||
|
||||
if ( dev_addr != 0 )
|
||||
{ // insert to control head
|
||||
ed_list_insert( p_ed_head[TUSB_XFER_CONTROL], p_ed);
|
||||
}else
|
||||
{
|
||||
p_ed->skip = 0; // addr0 is used as static control head --> only need to clear skip bit
|
||||
}
|
||||
|
||||
return TUSB_ERROR_NONE;
|
||||
}
|
||||
|
||||
tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[])
|
||||
{
|
||||
ohci_ed_t* const p_ed = &ohci_data.control[dev_addr].ed;
|
||||
|
||||
ohci_gtd_t *p_setup = &ohci_data.control[dev_addr].gtd[0];
|
||||
ohci_gtd_t *p_data = p_setup + 1;
|
||||
ohci_gtd_t *p_status = p_setup + 2;
|
||||
|
||||
//------------- SETUP Phase -------------//
|
||||
gtd_init(p_setup, (void*) p_request, 8);
|
||||
p_setup->index = dev_addr;
|
||||
p_setup->pid = OHCI_PID_SETUP;
|
||||
p_setup->data_toggle = BIN8(10); // DATA0
|
||||
p_setup->next_td = (uint32_t) p_data;
|
||||
|
||||
//------------- DATA Phase -------------//
|
||||
if (p_request->wLength > 0)
|
||||
{
|
||||
gtd_init(p_data, data, p_request->wLength);
|
||||
p_data->index = dev_addr;
|
||||
p_data->pid = p_request->bmRequestType_bit.direction ? OHCI_PID_IN : OHCI_PID_OUT;
|
||||
p_data->data_toggle = BIN8(11); // DATA1
|
||||
}else
|
||||
{
|
||||
p_data = p_setup;
|
||||
}
|
||||
p_data->next_td = (uint32_t) p_status;
|
||||
|
||||
//------------- STATUS Phase -------------//
|
||||
gtd_init(p_status, NULL, 0); // zero-length data
|
||||
p_status->index = dev_addr;
|
||||
p_status->pid = p_request->bmRequestType_bit.direction ? OHCI_PID_OUT : OHCI_PID_IN; // reverse direction of data phase
|
||||
p_status->data_toggle = BIN8(11); // DATA1
|
||||
p_status->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
|
||||
|
||||
//------------- Attach TDs list to Control Endpoint -------------//
|
||||
p_ed->td_head.address = (uint32_t) p_setup;
|
||||
|
||||
OHCI_REG->command_status_bit.control_list_filled = 1;
|
||||
|
||||
return TUSB_ERROR_NONE;
|
||||
}
|
||||
|
||||
tusb_error_t hcd_pipe_control_close(uint8_t dev_addr)
|
||||
{
|
||||
ohci_ed_t* const p_ed = &ohci_data.control[dev_addr].ed;
|
||||
|
||||
if ( dev_addr == 0 )
|
||||
{ // addr0 serves as static head --> only set skip bitx
|
||||
p_ed->skip = 1;
|
||||
}else
|
||||
{
|
||||
ed_list_remove( p_ed_head[ ed_get_xfer_type(p_ed)], p_ed );
|
||||
|
||||
// TODO refractor to be USBH
|
||||
usbh_devices[dev_addr].state = TUSB_DEVICE_STATE_UNPLUG;
|
||||
}
|
||||
|
||||
return TUSB_ERROR_NONE;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// BULK/INT/ISO PIPE API
|
||||
//--------------------------------------------------------------------+
|
||||
static inline uint8_t ed_get_index(ohci_ed_t const * const p_ed) ATTR_PURE ATTR_ALWAYS_INLINE;
|
||||
static inline uint8_t ed_get_index(ohci_ed_t const * const p_ed)
|
||||
{
|
||||
return p_ed - ohci_data.device[p_ed->device_address-1].ed;
|
||||
}
|
||||
|
||||
static inline ohci_ed_t * ed_from_pipe_handle(pipe_handle_t pipe_hdl) ATTR_PURE ATTR_ALWAYS_INLINE;
|
||||
static inline ohci_ed_t * ed_from_pipe_handle(pipe_handle_t pipe_hdl)
|
||||
{
|
||||
return &ohci_data.device[pipe_hdl.dev_addr-1].ed[pipe_hdl.index];
|
||||
}
|
||||
|
||||
static inline ohci_ed_t * ed_find_free(uint8_t dev_addr) ATTR_PURE ATTR_ALWAYS_INLINE;
|
||||
static inline ohci_ed_t * ed_find_free(uint8_t dev_addr)
|
||||
{
|
||||
for(uint8_t i = 0; i < HCD_MAX_ENDPOINT; i++)
|
||||
{
|
||||
if ( !ohci_data.device[dev_addr-1].ed[i].used )
|
||||
{
|
||||
return &ohci_data.device[dev_addr-1].ed[i];
|
||||
}
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static ohci_ed_t * ed_list_find_previous(ohci_ed_t const * p_head, ohci_ed_t const * p_ed)
|
||||
{
|
||||
uint32_t max_loop = HCD_MAX_ENDPOINT*CFG_TUSB_HOST_DEVICE_MAX;
|
||||
|
||||
ohci_ed_t const * p_prev = p_head;
|
||||
|
||||
TU_ASSERT(p_prev, NULL);
|
||||
|
||||
while ( align16(p_prev->next_ed) != 0 && /* not reach null */
|
||||
align16(p_prev->next_ed) != (uint32_t) p_ed && /* not found yet */
|
||||
max_loop > 0)
|
||||
{
|
||||
p_prev = (ohci_ed_t const *) align16(p_prev->next_ed);
|
||||
max_loop--;
|
||||
}
|
||||
|
||||
return ( align16(p_prev->next_ed) == (uint32_t) p_ed ) ? (ohci_ed_t*) p_prev : NULL;
|
||||
}
|
||||
|
||||
static void ed_list_insert(ohci_ed_t * p_pre, ohci_ed_t * p_ed)
|
||||
{
|
||||
p_ed->next_ed |= p_pre->next_ed; // to reserve 4 lsb bits
|
||||
p_pre->next_ed = (p_pre->next_ed & 0x0FUL) | ((uint32_t) p_ed);
|
||||
}
|
||||
|
||||
static void ed_list_remove(ohci_ed_t * p_head, ohci_ed_t * p_ed)
|
||||
{
|
||||
ohci_ed_t * const p_prev = ed_list_find_previous(p_head, p_ed);
|
||||
|
||||
p_prev->next_ed = (p_prev->next_ed & 0x0fUL) | align16(p_ed->next_ed);
|
||||
// point the removed ED's next pointer to list head to make sure HC can always safely move away from this ED
|
||||
p_ed->next_ed = (uint32_t) p_head;
|
||||
p_ed->used = 0; // free ED
|
||||
}
|
||||
|
||||
pipe_handle_t hcd_pipe_open(uint8_t dev_addr, tusb_desc_endpoint_t const * p_endpoint_desc, uint8_t class_code)
|
||||
{
|
||||
pipe_handle_t const null_handle = { .dev_addr = 0, .xfer_type = 0, .index = 0 };
|
||||
|
||||
// TODO iso support
|
||||
TU_ASSERT(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS, null_handle );
|
||||
|
||||
//------------- Prepare Queue Head -------------//
|
||||
ohci_ed_t * const p_ed = ed_find_free(dev_addr);
|
||||
TU_ASSERT(p_ed, null_handle);
|
||||
|
||||
ed_init( p_ed, dev_addr, p_endpoint_desc->wMaxPacketSize.size, p_endpoint_desc->bEndpointAddress,
|
||||
p_endpoint_desc->bmAttributes.xfer, p_endpoint_desc->bInterval );
|
||||
p_ed->td_tail.class_code = class_code;
|
||||
|
||||
ed_list_insert( p_ed_head[p_endpoint_desc->bmAttributes.xfer], p_ed );
|
||||
|
||||
return (pipe_handle_t)
|
||||
{
|
||||
.dev_addr = dev_addr,
|
||||
.xfer_type = p_endpoint_desc->bmAttributes.xfer,
|
||||
.index = ed_get_index(p_ed)
|
||||
};
|
||||
}
|
||||
|
||||
static ohci_gtd_t * gtd_find_free(uint8_t dev_addr)
|
||||
{
|
||||
for(uint8_t i=0; i < HCD_MAX_XFER; i++)
|
||||
{
|
||||
if (!ohci_data.device[dev_addr-1].gtd[i].used)
|
||||
{
|
||||
return &ohci_data.device[dev_addr-1].gtd[i];
|
||||
}
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd)
|
||||
{
|
||||
// tail is always NULL
|
||||
if ( align16(p_ed->td_head.address) == 0 )
|
||||
{ // TD queue is empty --> head = TD
|
||||
p_ed->td_head.address |= (uint32_t) p_gtd;
|
||||
}
|
||||
else
|
||||
{ // TODO currently only support queue up to 2 TD each endpoint at a time
|
||||
((ohci_gtd_t*) align16(p_ed->td_head.address))->next_td = (uint32_t) p_gtd;
|
||||
}
|
||||
}
|
||||
|
||||
static tusb_error_t pipe_queue_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete)
|
||||
{
|
||||
ohci_ed_t* const p_ed = ed_from_pipe_handle(pipe_hdl);
|
||||
|
||||
if ( !p_ed->is_iso )
|
||||
{
|
||||
ohci_gtd_t * const p_gtd = gtd_find_free(pipe_hdl.dev_addr);
|
||||
TU_ASSERT(p_gtd, TUSB_ERROR_EHCI_NOT_ENOUGH_QTD); // TODO refractor error code
|
||||
|
||||
gtd_init(p_gtd, buffer, total_bytes);
|
||||
p_gtd->index = pipe_hdl.index;
|
||||
if ( int_on_complete ) p_gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
|
||||
|
||||
td_insert_to_ed(p_ed, p_gtd);
|
||||
}else
|
||||
{
|
||||
TU_ASSERT_ERR(TUSB_ERROR_NOT_SUPPORTED_YET);
|
||||
}
|
||||
|
||||
return TUSB_ERROR_NONE;
|
||||
}
|
||||
|
||||
tusb_error_t hcd_pipe_queue_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t total_bytes)
|
||||
{
|
||||
return pipe_queue_xfer(pipe_hdl, buffer, total_bytes, false);
|
||||
}
|
||||
|
||||
tusb_error_t hcd_pipe_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete)
|
||||
{
|
||||
TU_ASSERT_ERR( pipe_queue_xfer(pipe_hdl, buffer, total_bytes, true) );
|
||||
|
||||
tusb_xfer_type_t xfer_type = ed_get_xfer_type( ed_from_pipe_handle(pipe_hdl) );
|
||||
|
||||
if (TUSB_XFER_BULK == xfer_type) OHCI_REG->command_status_bit.bulk_list_filled = 1;
|
||||
|
||||
return TUSB_ERROR_NONE;
|
||||
}
|
||||
|
||||
/// pipe_close should only be called as a part of unmount/safe-remove process
|
||||
// endpoints are tied to an address, which only reclaim after a long delay when enumerating
|
||||
// thus there is no need to make sure ED is not in HC's cahed as it will not for sure
|
||||
tusb_error_t hcd_pipe_close(pipe_handle_t pipe_hdl)
|
||||
{
|
||||
ohci_ed_t * const p_ed = ed_from_pipe_handle(pipe_hdl);
|
||||
|
||||
ed_list_remove( p_ed_head[ ed_get_xfer_type(p_ed)], p_ed );
|
||||
|
||||
return TUSB_ERROR_FAILED;
|
||||
}
|
||||
|
||||
bool hcd_pipe_is_busy(pipe_handle_t pipe_hdl)
|
||||
{
|
||||
ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);
|
||||
return align16(p_ed->td_head.address) != align16(p_ed->td_tail.address);
|
||||
}
|
||||
|
||||
bool hcd_pipe_is_error(pipe_handle_t pipe_hdl)
|
||||
{
|
||||
ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);
|
||||
return p_ed->td_head.halted;
|
||||
}
|
||||
|
||||
bool hcd_pipe_is_stalled(pipe_handle_t pipe_hdl)
|
||||
{
|
||||
ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);
|
||||
return p_ed->td_head.halted && p_ed->is_stalled;
|
||||
}
|
||||
|
||||
uint8_t hcd_pipe_get_endpoint_addr(pipe_handle_t pipe_hdl)
|
||||
{
|
||||
ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);
|
||||
return p_ed->endpoint_number | (p_ed->direction == OHCI_PID_IN ? TUSB_DIR_IN_MASK : 0 );
|
||||
}
|
||||
|
||||
tusb_error_t hcd_pipe_clear_stall(pipe_handle_t pipe_hdl)
|
||||
{
|
||||
ohci_ed_t * const p_ed = ed_from_pipe_handle(pipe_hdl);
|
||||
|
||||
p_ed->is_stalled = 0;
|
||||
p_ed->td_tail.address &= 0x0Ful; // set tail pointer back to NULL
|
||||
|
||||
p_ed->td_head.toggle = 0; // reset data toggle
|
||||
p_ed->td_head.halted = 0;
|
||||
|
||||
if ( TUSB_XFER_BULK == ed_get_xfer_type(p_ed) ) OHCI_REG->command_status_bit.bulk_list_filled = 1;
|
||||
|
||||
return TUSB_ERROR_NONE;
|
||||
}
|
||||
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// OHCI Interrupt Handler
|
||||
//--------------------------------------------------------------------+
|
||||
static ohci_td_item_t* list_reverse(ohci_td_item_t* td_head)
|
||||
{
|
||||
ohci_td_item_t* td_reverse_head = NULL;
|
||||
|
||||
while(td_head != NULL)
|
||||
{
|
||||
uint32_t next = td_head->next_td;
|
||||
|
||||
// make current's item become reverse's first item
|
||||
td_head->next_td = (uint32_t) td_reverse_head;
|
||||
td_reverse_head = td_head;
|
||||
|
||||
td_head = (ohci_td_item_t*) next; // advance to next item
|
||||
}
|
||||
|
||||
return td_reverse_head;
|
||||
}
|
||||
|
||||
static inline bool gtd_is_control(ohci_gtd_t const * const p_qtd) ATTR_CONST ATTR_ALWAYS_INLINE;
|
||||
static inline bool gtd_is_control(ohci_gtd_t const * const p_qtd)
|
||||
{
|
||||
return ((uint32_t) p_qtd) < ((uint32_t) ohci_data.device); // check ohci_data_t for memory layout
|
||||
}
|
||||
|
||||
static inline ohci_ed_t* gtd_get_ed(ohci_gtd_t const * const p_qtd) ATTR_PURE ATTR_ALWAYS_INLINE;
|
||||
static inline ohci_ed_t* gtd_get_ed(ohci_gtd_t const * const p_qtd)
|
||||
{
|
||||
if ( gtd_is_control(p_qtd) )
|
||||
{
|
||||
return &ohci_data.control[p_qtd->index].ed;
|
||||
}else
|
||||
{
|
||||
uint8_t dev_addr_idx = (((uint32_t)p_qtd) - ((uint32_t)ohci_data.device)) / sizeof(ohci_data.device[0]);
|
||||
|
||||
return &ohci_data.device[dev_addr_idx].ed[p_qtd->index];
|
||||
}
|
||||
}
|
||||
|
||||
static inline uint32_t gtd_xfer_byte_left(uint32_t buffer_end, uint32_t current_buffer) ATTR_CONST ATTR_ALWAYS_INLINE;
|
||||
static inline uint32_t gtd_xfer_byte_left(uint32_t buffer_end, uint32_t current_buffer)
|
||||
{ // 5.2.9 OHCI sample code
|
||||
return (align4k(buffer_end ^ current_buffer) ? 0x1000 : 0) +
|
||||
offset4k(buffer_end) - offset4k(current_buffer) + 1;
|
||||
}
|
||||
|
||||
static void done_queue_isr(uint8_t hostid)
|
||||
{
|
||||
uint8_t max_loop = (CFG_TUSB_HOST_DEVICE_MAX+1)*(HCD_MAX_XFER+OHCI_MAX_ITD);
|
||||
|
||||
// done head is written in reversed order of completion --> need to reverse the done queue first
|
||||
ohci_td_item_t* td_head = list_reverse ( (ohci_td_item_t*) align16(ohci_data.hcca.done_head) );
|
||||
|
||||
while( td_head != NULL && max_loop > 0)
|
||||
{
|
||||
// TODO check if td_head is iso td
|
||||
//------------- Non ISO transfer -------------//
|
||||
ohci_gtd_t * const p_qtd = (ohci_gtd_t *) td_head;
|
||||
tusb_event_t const event = (p_qtd->condition_code == OHCI_CCODE_NO_ERROR) ? TUSB_EVENT_XFER_COMPLETE :
|
||||
(p_qtd->condition_code == OHCI_CCODE_STALL) ? TUSB_EVENT_XFER_STALLED : TUSB_EVENT_XFER_ERROR;
|
||||
|
||||
p_qtd->used = 0; // free TD
|
||||
if ( (p_qtd->delay_interrupt == OHCI_INT_ON_COMPLETE_YES) || (event != TUSB_EVENT_XFER_COMPLETE) )
|
||||
{
|
||||
ohci_ed_t * const p_ed = gtd_get_ed(p_qtd);
|
||||
|
||||
uint32_t const xferred_bytes = p_qtd->expected_bytes - gtd_xfer_byte_left((uint32_t) p_qtd->buffer_end, (uint32_t) p_qtd->current_buffer_pointer);
|
||||
|
||||
// NOTE Assuming the current list is BULK and there is no other EDs in the list has queued TDs.
|
||||
// When there is a error resulting this ED is halted, and this EP still has other queued TD
|
||||
// --> the Bulk list only has this halted EP queueing TDs (remaining)
|
||||
// --> Bulk list will be considered as not empty by HC !!! while there is no attempt transaction on this list
|
||||
// --> HC will not process Control list (due to service ratio when Bulk list not empty)
|
||||
// To walk-around this, the halted ED will have TailP = HeadP (empty list condition), when clearing halt
|
||||
// the TailP must be set back to NULL for processing remaining TDs
|
||||
if ((event != TUSB_EVENT_XFER_COMPLETE))
|
||||
{
|
||||
p_ed->td_tail.address &= 0x0Ful;
|
||||
p_ed->td_tail.address |= align16(p_ed->td_head.address); // mark halted EP as empty queue
|
||||
if ( event == TUSB_EVENT_XFER_STALLED ) p_ed->is_stalled = 1;
|
||||
}
|
||||
|
||||
pipe_handle_t pipe_hdl =
|
||||
{
|
||||
.dev_addr = p_ed->device_address,
|
||||
.xfer_type = ed_get_xfer_type(p_ed),
|
||||
};
|
||||
|
||||
if ( pipe_hdl.xfer_type != TUSB_XFER_CONTROL) pipe_hdl.index = ed_get_index(p_ed);
|
||||
|
||||
usbh_xfer_isr(pipe_hdl, p_ed->td_tail.class_code, event, xferred_bytes);
|
||||
}
|
||||
|
||||
td_head = (ohci_td_item_t*) td_head->next_td;
|
||||
max_loop--;
|
||||
}
|
||||
}
|
||||
|
||||
void hal_hcd_isr(uint8_t hostid)
|
||||
{
|
||||
uint32_t const int_en = OHCI_REG->interrupt_enable;
|
||||
uint32_t const int_status = OHCI_REG->interrupt_status & int_en;
|
||||
|
||||
if (int_status == 0) return;
|
||||
|
||||
//------------- RootHub status -------------//
|
||||
if ( int_status & OHCI_INT_RHPORT_STATUS_CHANGE_MASK )
|
||||
{
|
||||
uint32_t const rhport_status = OHCI_REG->rhport_status[0] & OHCI_RHPORT_ALL_CHANGE_MASK;
|
||||
|
||||
// TODO dual port is not yet supported
|
||||
if ( rhport_status & OHCI_RHPORT_CONNECT_STATUS_CHANGE_MASK )
|
||||
{
|
||||
// TODO check if remote wake-up
|
||||
if ( OHCI_REG->rhport_status_bit[0].current_connect_status )
|
||||
{
|
||||
// TODO reset port immediately, without this controller will got 2-3 (debouncing connection status change)
|
||||
OHCI_REG->rhport_status[0] = OHCI_RHPORT_PORT_RESET_STATUS_MASK;
|
||||
usbh_hcd_rhport_plugged_isr(0);
|
||||
}else
|
||||
{
|
||||
usbh_hcd_rhport_unplugged_isr(0);
|
||||
}
|
||||
}
|
||||
|
||||
if ( rhport_status & OHCI_RHPORT_PORT_SUSPEND_CHANGE_MASK)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
OHCI_REG->rhport_status[0] = rhport_status; // acknowledge all interrupt
|
||||
}
|
||||
|
||||
//------------- Transfer Complete -------------//
|
||||
if ( int_status & OHCI_INT_WRITEBACK_DONEHEAD_MASK)
|
||||
{
|
||||
done_queue_isr(hostid);
|
||||
}
|
||||
|
||||
OHCI_REG->interrupt_status = int_status; // Acknowledge handled interrupt
|
||||
}
|
||||
//--------------------------------------------------------------------+
|
||||
// HELPER
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,310 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file ohci.h
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
/** \ingroup Group_HCD
|
||||
* @{
|
||||
* \defgroup OHCI
|
||||
* \brief OHCI driver. All documents sources mentioned here (eg section 3.5) is referring to OHCI Specs unless state otherwise
|
||||
* @{ */
|
||||
|
||||
#ifndef _TUSB_OHCI_H_
|
||||
#define _TUSB_OHCI_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "common/tusb_common.h"
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// OHCI CONFIGURATION & CONSTANTS
|
||||
//--------------------------------------------------------------------+
|
||||
#define HOST_HCD_XFER_INTERRUPT // TODO interrupt is used widely, should always be enalbed
|
||||
#define OHCI_PERIODIC_LIST (defined HOST_HCD_XFER_INTERRUPT || defined HOST_HCD_XFER_ISOCHRONOUS)
|
||||
|
||||
// TODO merge OHCI with EHCI
|
||||
enum {
|
||||
OHCI_MAX_ITD = 4
|
||||
};
|
||||
|
||||
enum {
|
||||
OHCI_PID_SETUP = 0,
|
||||
OHCI_PID_OUT,
|
||||
OHCI_PID_IN,
|
||||
};
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// OHCI Data Structure
|
||||
//--------------------------------------------------------------------+
|
||||
typedef struct {
|
||||
uint32_t interrupt_table[32];
|
||||
volatile uint16_t frame_number;
|
||||
volatile uint16_t frame_pad;
|
||||
volatile uint32_t done_head;
|
||||
uint8_t reserved[116+4]; // TODO try to make use of this area if possible, extra 4 byte to make the whole struct size = 256
|
||||
}ohci_hcca_t; // ATTR_ALIGNED(256)
|
||||
|
||||
VERIFY_STATIC( sizeof(ohci_hcca_t) == 256, "size is not correct" );
|
||||
|
||||
typedef struct {
|
||||
uint32_t reserved[2];
|
||||
volatile uint32_t next_td;
|
||||
uint32_t reserved2;
|
||||
}ohci_td_item_t;
|
||||
|
||||
|
||||
typedef struct ATTR_ALIGNED(16) {
|
||||
//------------- Word 0 -------------//
|
||||
uint32_t used : 1;
|
||||
uint32_t index : 4; // endpoint index the td belongs to, or device address in case of control xfer
|
||||
uint32_t expected_bytes : 13; // TODO available for hcd
|
||||
|
||||
uint32_t buffer_rounding : 1;
|
||||
uint32_t pid : 2;
|
||||
uint32_t delay_interrupt : 3;
|
||||
volatile uint32_t data_toggle : 2;
|
||||
volatile uint32_t error_count : 2;
|
||||
volatile uint32_t condition_code : 4;
|
||||
/*---------- End Word 1 ----------*/
|
||||
|
||||
//------------- Word 1 -------------//
|
||||
volatile uint8_t* current_buffer_pointer;
|
||||
|
||||
//------------- Word 2 -------------//
|
||||
volatile uint32_t next_td;
|
||||
|
||||
//------------- Word 3 -------------//
|
||||
uint8_t* buffer_end;
|
||||
} ohci_gtd_t;
|
||||
|
||||
VERIFY_STATIC( sizeof(ohci_gtd_t) == 16, "size is not correct" );
|
||||
|
||||
typedef struct ATTR_ALIGNED(16) {
|
||||
//------------- Word 0 -------------//
|
||||
uint32_t device_address : 7;
|
||||
uint32_t endpoint_number : 4;
|
||||
uint32_t direction : 2;
|
||||
uint32_t speed : 1;
|
||||
uint32_t skip : 1;
|
||||
uint32_t is_iso : 1;
|
||||
uint32_t max_package_size : 11;
|
||||
|
||||
uint32_t used : 1; // HCD
|
||||
uint32_t is_interrupt_xfer : 1;
|
||||
uint32_t is_stalled : 1;
|
||||
uint32_t : 2;
|
||||
|
||||
|
||||
//------------- Word 1 -------------//
|
||||
union {
|
||||
uint32_t address; // 4 lsb bits are free to use
|
||||
struct {
|
||||
uint32_t class_code : 4; // FIXME refractor to use interface number instead
|
||||
uint32_t : 28;
|
||||
};
|
||||
}td_tail;
|
||||
|
||||
//------------- Word 2 -------------//
|
||||
volatile union {
|
||||
uint32_t address;
|
||||
struct {
|
||||
uint32_t halted : 1;
|
||||
uint32_t toggle : 1;
|
||||
uint32_t : 30;
|
||||
};
|
||||
}td_head;
|
||||
|
||||
//------------- Word 3 -------------//
|
||||
uint32_t next_ed; // 4 lsb bits are free to use
|
||||
} ohci_ed_t;
|
||||
|
||||
VERIFY_STATIC( sizeof(ohci_ed_t) == 16, "size is not correct" );
|
||||
|
||||
typedef struct ATTR_ALIGNED(32) {
|
||||
/*---------- Word 1 ----------*/
|
||||
uint32_t starting_frame : 16;
|
||||
uint32_t : 5; // can be used
|
||||
uint32_t delay_interrupt : 3;
|
||||
uint32_t frame_count : 3;
|
||||
uint32_t : 1; // can be used
|
||||
volatile uint32_t condition_code : 4;
|
||||
/*---------- End Word 1 ----------*/
|
||||
|
||||
/*---------- Word 2 ----------*/
|
||||
uint32_t buffer_page0; // 12 lsb bits can be used
|
||||
|
||||
/*---------- Word 3 ----------*/
|
||||
volatile uint32_t next_td;
|
||||
|
||||
/*---------- Word 4 ----------*/
|
||||
uint32_t buffer_end;
|
||||
|
||||
/*---------- Word 5-8 ----------*/
|
||||
volatile uint16_t offset_packetstatus[8];
|
||||
} ochi_itd_t;
|
||||
|
||||
VERIFY_STATIC( sizeof(ochi_itd_t) == 32, "size is not correct" );
|
||||
|
||||
// structure with member alignment required from large to small
|
||||
typedef struct ATTR_ALIGNED(256) {
|
||||
ohci_hcca_t hcca;
|
||||
|
||||
ohci_ed_t bulk_head_ed; // static bulk head (dummy)
|
||||
ohci_ed_t period_head_ed; // static periodic list head (dummy)
|
||||
|
||||
// control endpoints has reserved resources
|
||||
struct {
|
||||
ohci_ed_t ed;
|
||||
ohci_gtd_t gtd[3]; // setup, data, status
|
||||
}control[CFG_TUSB_HOST_DEVICE_MAX+1];
|
||||
|
||||
struct {
|
||||
// ochi_itd_t itd[OHCI_MAX_ITD]; // itd requires alignment of 32
|
||||
ohci_ed_t ed[HCD_MAX_ENDPOINT];
|
||||
ohci_gtd_t gtd[HCD_MAX_XFER];
|
||||
}device[CFG_TUSB_HOST_DEVICE_MAX];
|
||||
|
||||
} ohci_data_t;
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// OHCI Operational Register
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// OHCI Data Organization
|
||||
//--------------------------------------------------------------------+
|
||||
typedef volatile struct
|
||||
{
|
||||
uint32_t revision;
|
||||
|
||||
union {
|
||||
uint32_t control;
|
||||
struct {
|
||||
uint32_t control_bulk_service_ratio : 2;
|
||||
uint32_t periodic_list_enable : 1;
|
||||
uint32_t isochronous_enable : 1;
|
||||
uint32_t control_list_enable : 1;
|
||||
uint32_t bulk_list_enable : 1;
|
||||
uint32_t hc_functional_state : 2;
|
||||
uint32_t interrupt_routing : 1;
|
||||
uint32_t remote_wakeup_connected : 1;
|
||||
uint32_t remote_wakeup_enale : 1;
|
||||
uint32_t : 0;
|
||||
}control_bit;
|
||||
};
|
||||
|
||||
union {
|
||||
uint32_t command_status;
|
||||
struct {
|
||||
uint32_t controller_reset : 1;
|
||||
uint32_t control_list_filled : 1;
|
||||
uint32_t bulk_list_filled : 1;
|
||||
uint32_t ownership_change_request : 1;
|
||||
uint32_t : 12;
|
||||
uint32_t scheduling_overrun_count : 2;
|
||||
}command_status_bit;
|
||||
};
|
||||
|
||||
uint32_t interrupt_status;
|
||||
uint32_t interrupt_enable;
|
||||
uint32_t interrupt_disable;
|
||||
|
||||
uint32_t hcca;
|
||||
uint32_t period_current_ed;
|
||||
uint32_t control_head_ed;
|
||||
uint32_t control_current_ed;
|
||||
uint32_t bulk_head_ed;
|
||||
uint32_t bulk_current_ed;
|
||||
uint32_t done_head;
|
||||
|
||||
uint32_t frame_interval;
|
||||
uint32_t frame_remaining;
|
||||
uint32_t frame_number;
|
||||
uint32_t periodic_start;
|
||||
uint32_t lowspeed_threshold;
|
||||
|
||||
uint32_t rh_descriptorA;
|
||||
uint32_t rh_descriptorB;
|
||||
|
||||
union {
|
||||
uint32_t rh_status;
|
||||
struct {
|
||||
uint32_t local_power_status : 1; // read Local Power Status; write: Clear Global Power
|
||||
uint32_t over_current_indicator : 1;
|
||||
uint32_t : 13;
|
||||
uint32_t device_remote_wakeup_enable : 1;
|
||||
uint32_t local_power_status_change : 1;
|
||||
uint32_t over_current_indicator_change : 1;
|
||||
uint32_t : 13;
|
||||
uint32_t clear_remote_wakeup_enable : 1;
|
||||
}rh_status_bit;
|
||||
};
|
||||
|
||||
union {
|
||||
uint32_t rhport_status[2]; // TODO NXP OHCI controller only has 2 ports
|
||||
struct {
|
||||
uint32_t current_connect_status : 1;
|
||||
uint32_t port_enable_status : 1;
|
||||
uint32_t port_suspend_status : 1;
|
||||
uint32_t port_over_current_indicator : 1;
|
||||
uint32_t port_reset_status : 1;
|
||||
uint32_t : 3;
|
||||
uint32_t port_power_status : 1;
|
||||
uint32_t low_speed_device_attached : 1;
|
||||
uint32_t : 6;
|
||||
uint32_t connect_status_change : 1;
|
||||
uint32_t port_enable_status_change : 1;
|
||||
uint32_t port_suspend_status_change : 1;
|
||||
uint32_t port_over_current_indicator_change : 1;
|
||||
uint32_t port_reset_status_change : 1;
|
||||
uint32_t : 0;
|
||||
}rhport_status_bit[2];
|
||||
};
|
||||
}ohci_registers_t;
|
||||
|
||||
VERIFY_STATIC( sizeof(ohci_registers_t) == 0x5c, "size is not correct");
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_OHCI_H_ */
|
||||
|
||||
/** @} */
|
||||
/** @} */
|
||||
+642
@@ -0,0 +1,642 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file usbd_host.c
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#include "common/tusb_common.h"
|
||||
|
||||
#if MODE_HOST_SUPPORTED
|
||||
|
||||
#define _TINY_USB_SOURCE_FILE_
|
||||
|
||||
#ifndef CFG_TUD_TASK_PRIO
|
||||
#define CFG_TUD_TASK_PRIO 0
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// INCLUDE
|
||||
//--------------------------------------------------------------------+
|
||||
#include "tusb.h"
|
||||
#include "hub.h"
|
||||
#include "usbh_hcd.h"
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO CONSTANT TYPEDEF
|
||||
//--------------------------------------------------------------------+
|
||||
static host_class_driver_t const usbh_class_drivers[] =
|
||||
{
|
||||
#if HOST_CLASS_HID
|
||||
[TUSB_CLASS_HID] = {
|
||||
.init = hidh_init,
|
||||
.open_subtask = hidh_open_subtask,
|
||||
.isr = hidh_isr,
|
||||
.close = hidh_close
|
||||
},
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_HOST_CDC
|
||||
[TUSB_CLASS_CDC] = {
|
||||
.init = cdch_init,
|
||||
.open_subtask = cdch_open_subtask,
|
||||
.isr = cdch_isr,
|
||||
.close = cdch_close
|
||||
},
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_HOST_MSC
|
||||
[TUSB_CLASS_MSC] = {
|
||||
.init = msch_init,
|
||||
.open_subtask = msch_open_subtask,
|
||||
.isr = msch_isr,
|
||||
.close = msch_close
|
||||
},
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_HOST_HUB
|
||||
[TUSB_CLASS_HUB] = {
|
||||
.init = hub_init,
|
||||
.open_subtask = hub_open_subtask,
|
||||
.isr = hub_isr,
|
||||
.close = hub_close
|
||||
},
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_HOST_CUSTOM_CLASS
|
||||
[TUSB_CLASS_MAPPED_INDEX_END-1] = {
|
||||
.init = cush_init,
|
||||
.open_subtask = cush_open_subtask,
|
||||
.isr = cush_isr,
|
||||
.close = cush_close
|
||||
}
|
||||
#endif
|
||||
};
|
||||
|
||||
enum { USBH_CLASS_DRIVER_COUNT = sizeof(usbh_class_drivers) / sizeof(host_class_driver_t) };
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// INTERNAL OBJECT & FUNCTION DECLARATION
|
||||
//--------------------------------------------------------------------+
|
||||
CFG_TUSB_ATTR_USBRAM usbh_device_info_t usbh_devices[CFG_TUSB_HOST_DEVICE_MAX+1]; // including zero-address
|
||||
|
||||
//------------- Enumeration Task Data -------------/
|
||||
enum { ENUM_QUEUE_DEPTH = 16 };
|
||||
|
||||
STATIC_VAR osal_queue_t enum_queue_hdl;
|
||||
CFG_TUSB_ATTR_USBRAM ATTR_ALIGNED(4) STATIC_VAR uint8_t enum_data_buffer[CFG_TUSB_HOST_ENUM_BUFFER_SIZE];
|
||||
|
||||
//------------- Reporter Task Data -------------//
|
||||
|
||||
//------------- Helper Function Prototypes -------------//
|
||||
static inline uint8_t get_new_address(void) ATTR_ALWAYS_INLINE;
|
||||
static inline uint8_t get_configure_number_for_device(tusb_desc_device_t* dev_desc) ATTR_ALWAYS_INLINE;
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// PUBLIC API (Parameter Verification is required)
|
||||
//--------------------------------------------------------------------+
|
||||
tusb_device_state_t tuh_device_get_state (uint8_t const dev_addr)
|
||||
{
|
||||
TU_ASSERT( dev_addr <= CFG_TUSB_HOST_DEVICE_MAX, TUSB_DEVICE_STATE_INVALID_PARAMETER);
|
||||
return (tusb_device_state_t) usbh_devices[dev_addr].state;
|
||||
}
|
||||
|
||||
uint32_t tuh_device_get_mounted_class_flag(uint8_t dev_addr)
|
||||
{
|
||||
return tuh_device_is_configured(dev_addr) ? usbh_devices[dev_addr].flag_supported_class : 0;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// CLASS-USBD API (don't require to verify parameters)
|
||||
//--------------------------------------------------------------------+
|
||||
tusb_error_t usbh_init(void)
|
||||
{
|
||||
memclr_(usbh_devices, sizeof(usbh_device_info_t)*(CFG_TUSB_HOST_DEVICE_MAX+1));
|
||||
|
||||
TU_ASSERT_ERR( hcd_init() );
|
||||
|
||||
//------------- Enumeration & Reporter Task init -------------//
|
||||
enum_queue_hdl = osal_queue_create( ENUM_QUEUE_DEPTH, sizeof(uint32_t) );
|
||||
TU_ASSERT(enum_queue_hdl, TUSB_ERROR_OSAL_QUEUE_FAILED);
|
||||
|
||||
osal_task_create(usbh_enumeration_task, "usbh", 200, NULL, CFG_TUD_TASK_PRIO);
|
||||
|
||||
//------------- Semaphore, Mutex for Control Pipe -------------//
|
||||
for(uint8_t i=0; i<CFG_TUSB_HOST_DEVICE_MAX+1; i++) // including address zero
|
||||
{
|
||||
usbh_device_info_t * const p_device = &usbh_devices[i];
|
||||
|
||||
p_device->control.sem_hdl = osal_semaphore_create(1, 0);
|
||||
TU_ASSERT(p_device->control.sem_hdl, TUSB_ERROR_OSAL_SEMAPHORE_FAILED);
|
||||
|
||||
p_device->control.mutex_hdl = osal_mutex_create();
|
||||
TU_ASSERT(p_device->control.mutex_hdl, TUSB_ERROR_OSAL_MUTEX_FAILED);
|
||||
}
|
||||
|
||||
//------------- class init -------------//
|
||||
for (uint8_t class_index = 1; class_index < USBH_CLASS_DRIVER_COUNT; class_index++)
|
||||
{
|
||||
if (usbh_class_drivers[class_index].init)
|
||||
{
|
||||
usbh_class_drivers[class_index].init();
|
||||
}
|
||||
}
|
||||
|
||||
return TUSB_ERROR_NONE;
|
||||
}
|
||||
|
||||
//------------- USBH control transfer -------------//
|
||||
// function called within a task, requesting os blocking services, subtask input parameter must be static/global variables or constant
|
||||
tusb_error_t usbh_control_xfer_subtask(uint8_t dev_addr, uint8_t bmRequestType, uint8_t bRequest,
|
||||
uint16_t wValue, uint16_t wIndex, uint16_t wLength, uint8_t* data)
|
||||
{
|
||||
static tusb_error_t error; // FIXME [CMSIS-RTX] use svc for OS API, error value changed after mutex release at the end of function
|
||||
|
||||
OSAL_SUBTASK_BEGIN
|
||||
|
||||
osal_mutex_wait(usbh_devices[dev_addr].control.mutex_hdl, OSAL_TIMEOUT_NORMAL, &error);
|
||||
STASK_ASSERT_ERR_HDLR(error, osal_mutex_release(usbh_devices[dev_addr].control.mutex_hdl));
|
||||
|
||||
usbh_devices[dev_addr].control.request = (tusb_control_request_t) {
|
||||
{.bmRequestType = bmRequestType},
|
||||
.bRequest = bRequest,
|
||||
.wValue = wValue,
|
||||
.wIndex = wIndex,
|
||||
.wLength = wLength
|
||||
};
|
||||
|
||||
#ifndef _TEST_
|
||||
usbh_devices[dev_addr].control.pipe_status = 0;
|
||||
#else
|
||||
usbh_devices[dev_addr].control.pipe_status = TUSB_EVENT_XFER_COMPLETE; // in Test project, mark as complete immediately
|
||||
#endif
|
||||
|
||||
error = hcd_pipe_control_xfer(dev_addr, &usbh_devices[dev_addr].control.request, data);
|
||||
if ( TUSB_ERROR_NONE == error ) osal_semaphore_wait(usbh_devices[dev_addr].control.sem_hdl, OSAL_TIMEOUT_NORMAL, &error);
|
||||
osal_mutex_release(usbh_devices[dev_addr].control.mutex_hdl);
|
||||
|
||||
STASK_ASSERT_ERR(error);
|
||||
if (TUSB_EVENT_XFER_STALLED == usbh_devices[dev_addr].control.pipe_status) STASK_RETURN(TUSB_ERROR_USBH_XFER_STALLED);
|
||||
if (TUSB_EVENT_XFER_ERROR == usbh_devices[dev_addr].control.pipe_status) STASK_RETURN(TUSB_ERROR_USBH_XFER_FAILED);
|
||||
|
||||
// STASK_ASSERT_HDLR(TUSB_ERROR_NONE == error &&
|
||||
// TUSB_EVENT_XFER_COMPLETE == usbh_devices[dev_addr].control.pipe_status,
|
||||
// tuh_device_mount_failed_cb(TUSB_ERROR_USBH_MOUNT_DEVICE_NOT_RESPOND, NULL) );
|
||||
|
||||
OSAL_SUBTASK_END
|
||||
}
|
||||
|
||||
tusb_error_t usbh_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size) ATTR_ALWAYS_INLINE;
|
||||
tusb_error_t usbh_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
|
||||
{
|
||||
osal_semaphore_reset( usbh_devices[dev_addr].control.sem_hdl );
|
||||
osal_mutex_reset( usbh_devices[dev_addr].control.mutex_hdl );
|
||||
|
||||
TU_ASSERT_ERR( hcd_pipe_control_open(dev_addr, max_packet_size) );
|
||||
|
||||
return TUSB_ERROR_NONE;
|
||||
}
|
||||
|
||||
static inline tusb_error_t usbh_pipe_control_close(uint8_t dev_addr) ATTR_ALWAYS_INLINE;
|
||||
static inline tusb_error_t usbh_pipe_control_close(uint8_t dev_addr)
|
||||
{
|
||||
TU_ASSERT_ERR( hcd_pipe_control_close(dev_addr) );
|
||||
|
||||
return TUSB_ERROR_NONE;
|
||||
}
|
||||
|
||||
// TODO [USBH] unify pipe status get
|
||||
//tusb_interface_status_t usbh_pipe_status_get(pipe_handle_t pipe_hdl)
|
||||
//{
|
||||
// return TUSB_INTERFACE_STATUS_BUSY;
|
||||
//}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// USBH-HCD ISR/Callback API
|
||||
//--------------------------------------------------------------------+
|
||||
// interrupt caused by a TD (with IOC=1) in pipe of class class_code
|
||||
void usbh_xfer_isr(pipe_handle_t pipe_hdl, uint8_t class_code, tusb_event_t event, uint32_t xferred_bytes)
|
||||
{
|
||||
uint8_t class_index = std_class_code_to_index(class_code);
|
||||
if (TUSB_XFER_CONTROL == pipe_hdl.xfer_type)
|
||||
{
|
||||
usbh_devices[ pipe_hdl.dev_addr ].control.pipe_status = event;
|
||||
// usbh_devices[ pipe_hdl.dev_addr ].control.xferred_bytes = xferred_bytes; not yet neccessary
|
||||
osal_semaphore_post( usbh_devices[ pipe_hdl.dev_addr ].control.sem_hdl );
|
||||
}else if (usbh_class_drivers[class_index].isr)
|
||||
{
|
||||
usbh_class_drivers[class_index].isr(pipe_hdl, event, xferred_bytes);
|
||||
}else
|
||||
{
|
||||
TU_ASSERT(false); // something wrong, no one claims the isr's source
|
||||
}
|
||||
}
|
||||
|
||||
void usbh_hub_port_plugged_isr(uint8_t hub_addr, uint8_t hub_port)
|
||||
{
|
||||
usbh_enumerate_t enum_entry =
|
||||
{
|
||||
.core_id = usbh_devices[hub_addr].core_id,
|
||||
.hub_addr = hub_addr,
|
||||
.hub_port = hub_port
|
||||
};
|
||||
|
||||
osal_queue_send(enum_queue_hdl, &enum_entry);
|
||||
}
|
||||
|
||||
void usbh_hcd_rhport_plugged_isr(uint8_t hostid)
|
||||
{
|
||||
usbh_enumerate_t enum_entry =
|
||||
{
|
||||
.core_id = hostid,
|
||||
.hub_addr = 0,
|
||||
.hub_port = 0
|
||||
};
|
||||
|
||||
osal_queue_send(enum_queue_hdl, &enum_entry);
|
||||
}
|
||||
|
||||
// a device unplugged on hostid, hub_addr, hub_port
|
||||
// return true if found and unmounted device, false if cannot find
|
||||
static void usbh_device_unplugged(uint8_t hostid, uint8_t hub_addr, uint8_t hub_port)
|
||||
{
|
||||
bool is_found = false;
|
||||
//------------- find the all devices (star-network) under port that is unplugged -------------//
|
||||
for (uint8_t dev_addr = 0; dev_addr <= CFG_TUSB_HOST_DEVICE_MAX; dev_addr ++)
|
||||
{
|
||||
if (usbh_devices[dev_addr].core_id == hostid &&
|
||||
(hub_addr == 0 || usbh_devices[dev_addr].hub_addr == hub_addr) && // hub_addr == 0 & hub_port == 0 means roothub
|
||||
(hub_port == 0 || usbh_devices[dev_addr].hub_port == hub_port) &&
|
||||
usbh_devices[dev_addr].state != TUSB_DEVICE_STATE_UNPLUG)
|
||||
{
|
||||
// TODO Hub multiple level
|
||||
for (uint8_t class_index = 1; class_index < USBH_CLASS_DRIVER_COUNT; class_index++)
|
||||
{
|
||||
if ((usbh_devices[dev_addr].flag_supported_class & BIT_(class_index)) &&
|
||||
usbh_class_drivers[class_index].close)
|
||||
{
|
||||
usbh_class_drivers[class_index].close(dev_addr);
|
||||
}
|
||||
}
|
||||
|
||||
// TODO refractor
|
||||
// set to REMOVING to allow HCD to clean up its cached data for this device
|
||||
// HCD must set this device's state to TUSB_DEVICE_STATE_UNPLUG when done
|
||||
usbh_devices[dev_addr].state = TUSB_DEVICE_STATE_REMOVING;
|
||||
usbh_devices[dev_addr].flag_supported_class = 0;
|
||||
|
||||
usbh_pipe_control_close(dev_addr);
|
||||
|
||||
|
||||
is_found = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (is_found) hcd_port_unplug(usbh_devices[0].core_id); // TODO hack
|
||||
|
||||
}
|
||||
|
||||
void usbh_hcd_rhport_unplugged_isr(uint8_t hostid)
|
||||
{
|
||||
usbh_enumerate_t enum_entry =
|
||||
{
|
||||
.core_id = hostid,
|
||||
.hub_addr = 0,
|
||||
.hub_port = 0
|
||||
};
|
||||
|
||||
osal_queue_send(enum_queue_hdl, &enum_entry);
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// ENUMERATION TASK
|
||||
//--------------------------------------------------------------------+
|
||||
static tusb_error_t enumeration_body_subtask(void);
|
||||
|
||||
// To enable the TASK_ASSERT style (quick return on false condition) in a real RTOS, a task must act as a wrapper
|
||||
// and is used mainly to call subtasks. Within a subtask return statement can be called freely, the task with
|
||||
// forever loop cannot have any return at all.
|
||||
void usbh_enumeration_task(void* param)
|
||||
{
|
||||
(void) param;
|
||||
|
||||
OSAL_TASK_BEGIN
|
||||
enumeration_body_subtask();
|
||||
OSAL_TASK_END
|
||||
}
|
||||
|
||||
tusb_error_t enumeration_body_subtask(void)
|
||||
{
|
||||
enum {
|
||||
POWER_STABLE_DELAY = 500,
|
||||
RESET_DELAY = 200 // USB specs say only 50ms but many devices require much longer
|
||||
};
|
||||
|
||||
tusb_error_t error;
|
||||
usbh_enumerate_t enum_entry;
|
||||
|
||||
// for OSAL_NONE local variable won't retain value after blocking service sem_wait/queue_recv
|
||||
static uint8_t new_addr;
|
||||
static uint8_t configure_selected = 1; // TODO move
|
||||
static uint8_t *p_desc = NULL; // TODO move
|
||||
|
||||
OSAL_SUBTASK_BEGIN
|
||||
|
||||
osal_queue_receive(enum_queue_hdl, &enum_entry, OSAL_TIMEOUT_WAIT_FOREVER, &error);
|
||||
STASK_ASSERT_ERR(error);
|
||||
|
||||
usbh_devices[0].core_id = enum_entry.core_id; // TODO refractor integrate to device_pool
|
||||
usbh_devices[0].hub_addr = enum_entry.hub_addr;
|
||||
usbh_devices[0].hub_port = enum_entry.hub_port;
|
||||
usbh_devices[0].state = TUSB_DEVICE_STATE_UNPLUG;
|
||||
|
||||
//------------- connected/disconnected directly with roothub -------------//
|
||||
if ( usbh_devices[0].hub_addr == 0)
|
||||
{
|
||||
if( hcd_port_connect_status(usbh_devices[0].core_id) )
|
||||
{ // connection event
|
||||
osal_task_delay(POWER_STABLE_DELAY); // wait until device is stable. Increase this if the first 8 bytes is failed to get
|
||||
|
||||
if ( !hcd_port_connect_status(usbh_devices[0].core_id) ) STASK_RETURN(TUSB_ERROR_NONE); // exit if device unplugged while delaying
|
||||
|
||||
hcd_port_reset( usbh_devices[0].core_id ); // port must be reset to have correct speed operation
|
||||
osal_task_delay(RESET_DELAY);
|
||||
|
||||
usbh_devices[0].speed = hcd_port_speed_get( usbh_devices[0].core_id );
|
||||
}
|
||||
else
|
||||
{ // disconnection event
|
||||
usbh_device_unplugged(usbh_devices[0].core_id, 0, 0);
|
||||
STASK_RETURN(TUSB_ERROR_NONE); // restart task
|
||||
}
|
||||
}
|
||||
#if CFG_TUSB_HOST_HUB
|
||||
//------------- connected/disconnected via hub -------------//
|
||||
else
|
||||
{
|
||||
//------------- Get Port Status -------------//
|
||||
STASK_INVOKE(
|
||||
usbh_control_xfer_subtask( usbh_devices[0].hub_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_OTHER),
|
||||
HUB_REQUEST_GET_STATUS, 0, usbh_devices[0].hub_port,
|
||||
4, enum_data_buffer ),
|
||||
error
|
||||
);
|
||||
// STASK_ASSERT_ERR( error );
|
||||
STASK_ASSERT_ERR_HDLR(error, hub_status_pipe_queue( usbh_devices[0].hub_addr) ); // TODO hub refractor
|
||||
|
||||
// Acknowledge Port Connection Change
|
||||
STASK_INVOKE( hub_port_clear_feature_subtask(usbh_devices[0].hub_addr, usbh_devices[0].hub_port, HUB_FEATURE_PORT_CONNECTION_CHANGE), error );
|
||||
|
||||
hub_port_status_response_t * p_port_status;
|
||||
p_port_status = ((hub_port_status_response_t *) enum_data_buffer);
|
||||
|
||||
if ( ! p_port_status->status_change.connect_status ) STASK_RETURN(TUSB_ERROR_NONE); // only handle connection change
|
||||
|
||||
if ( ! p_port_status->status_current.connect_status )
|
||||
{ // Disconnection event
|
||||
usbh_device_unplugged(usbh_devices[0].core_id, usbh_devices[0].hub_addr, usbh_devices[0].hub_port);
|
||||
|
||||
(void) hub_status_pipe_queue( usbh_devices[0].hub_addr ); // done with hub, waiting for next data on status pipe
|
||||
STASK_RETURN(TUSB_ERROR_NONE); // restart task
|
||||
}
|
||||
else
|
||||
{ // Connection Event
|
||||
STASK_INVOKE ( hub_port_reset_subtask(usbh_devices[0].hub_addr, usbh_devices[0].hub_port), error );
|
||||
// STASK_ASSERT_ERR( error );
|
||||
STASK_ASSERT_ERR_HDLR(error, hub_status_pipe_queue( usbh_devices[0].hub_addr) ); // TODO hub refractor
|
||||
|
||||
usbh_devices[0].speed = hub_port_get_speed();
|
||||
|
||||
// Acknowledge Port Reset Change
|
||||
STASK_INVOKE( hub_port_clear_feature_subtask(usbh_devices[0].hub_addr, usbh_devices[0].hub_port, HUB_FEATURE_PORT_RESET_CHANGE), error );
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
STASK_ASSERT_ERR( usbh_pipe_control_open(0, 8) );
|
||||
usbh_devices[0].state = TUSB_DEVICE_STATE_ADDRESSED;
|
||||
|
||||
//------------- Get first 8 bytes of device descriptor to get Control Endpoint Size -------------//
|
||||
STASK_INVOKE(
|
||||
usbh_control_xfer_subtask( 0, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_STANDARD, TUSB_REQ_RCPT_DEVICE),
|
||||
TUSB_REQ_GET_DESCRIPTOR, (TUSB_DESC_DEVICE << 8), 0,
|
||||
8, enum_data_buffer ),
|
||||
error
|
||||
);
|
||||
|
||||
//------------- Reset device again before Set Address -------------//
|
||||
if (usbh_devices[0].hub_addr == 0)
|
||||
{ // connected directly to roothub
|
||||
STASK_ASSERT_ERR(error); // TODO some slow device is observed to fail the very fist controller xfer, can try more times
|
||||
hcd_port_reset( usbh_devices[0].core_id ); // reset port after 8 byte descriptor
|
||||
osal_task_delay(RESET_DELAY);
|
||||
}
|
||||
#if CFG_TUSB_HOST_HUB
|
||||
else
|
||||
{ // connected via a hub
|
||||
STASK_ASSERT_ERR_HDLR(error, hub_status_pipe_queue( usbh_devices[0].hub_addr) ); // TODO hub refractor
|
||||
STASK_INVOKE ( hub_port_reset_subtask(usbh_devices[0].hub_addr, usbh_devices[0].hub_port), error );
|
||||
|
||||
if ( TUSB_ERROR_NONE == error )
|
||||
{ // Acknowledge Port Reset Change if Reset Successful
|
||||
STASK_INVOKE( hub_port_clear_feature_subtask(usbh_devices[0].hub_addr, usbh_devices[0].hub_port, HUB_FEATURE_PORT_RESET_CHANGE), error );
|
||||
}
|
||||
|
||||
(void) hub_status_pipe_queue( usbh_devices[0].hub_addr ); // done with hub, waiting for next data on status pipe
|
||||
}
|
||||
#endif
|
||||
|
||||
//------------- Set new address -------------//
|
||||
new_addr = get_new_address();
|
||||
STASK_ASSERT(new_addr <= CFG_TUSB_HOST_DEVICE_MAX); // TODO notify application we reach max devices
|
||||
|
||||
STASK_INVOKE(
|
||||
usbh_control_xfer_subtask( 0, bm_request_type(TUSB_DIR_OUT, TUSB_REQ_TYPE_STANDARD, TUSB_REQ_RCPT_DEVICE),
|
||||
TUSB_REQ_SET_ADDRESS, new_addr, 0,
|
||||
0, NULL ),
|
||||
error
|
||||
);
|
||||
STASK_ASSERT_ERR(error);
|
||||
|
||||
//------------- update port info & close control pipe of addr0 -------------//
|
||||
usbh_devices[new_addr].core_id = usbh_devices[0].core_id;
|
||||
usbh_devices[new_addr].hub_addr = usbh_devices[0].hub_addr;
|
||||
usbh_devices[new_addr].hub_port = usbh_devices[0].hub_port;
|
||||
usbh_devices[new_addr].speed = usbh_devices[0].speed;
|
||||
usbh_devices[new_addr].state = TUSB_DEVICE_STATE_ADDRESSED;
|
||||
|
||||
usbh_pipe_control_close(0);
|
||||
usbh_devices[0].state = TUSB_DEVICE_STATE_UNPLUG;
|
||||
|
||||
// open control pipe for new address
|
||||
STASK_ASSERT_ERR ( usbh_pipe_control_open(new_addr, ((tusb_desc_device_t*) enum_data_buffer)->bMaxPacketSize0 ) );
|
||||
|
||||
//------------- Get full device descriptor -------------//
|
||||
STASK_INVOKE(
|
||||
usbh_control_xfer_subtask( new_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_STANDARD, TUSB_REQ_RCPT_DEVICE),
|
||||
TUSB_REQ_GET_DESCRIPTOR, (TUSB_DESC_DEVICE << 8), 0,
|
||||
18, enum_data_buffer ),
|
||||
error
|
||||
);
|
||||
STASK_ASSERT_ERR(error);
|
||||
|
||||
// update device info TODO alignment issue
|
||||
usbh_devices[new_addr].vendor_id = ((tusb_desc_device_t*) enum_data_buffer)->idVendor;
|
||||
usbh_devices[new_addr].product_id = ((tusb_desc_device_t*) enum_data_buffer)->idProduct;
|
||||
usbh_devices[new_addr].configure_count = ((tusb_desc_device_t*) enum_data_buffer)->bNumConfigurations;
|
||||
|
||||
configure_selected = get_configure_number_for_device((tusb_desc_device_t*) enum_data_buffer);
|
||||
STASK_ASSERT(configure_selected <= usbh_devices[new_addr].configure_count); // TODO notify application when invalid configuration
|
||||
|
||||
//------------- Get 9 bytes of configuration descriptor -------------//
|
||||
STASK_INVOKE(
|
||||
usbh_control_xfer_subtask( new_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_STANDARD, TUSB_REQ_RCPT_DEVICE),
|
||||
TUSB_REQ_GET_DESCRIPTOR, (TUSB_DESC_CONFIGURATION << 8) | (configure_selected - 1), 0,
|
||||
9, enum_data_buffer ),
|
||||
error
|
||||
);
|
||||
STASK_ASSERT_ERR(error);
|
||||
STASK_ASSERT_HDLR( CFG_TUSB_HOST_ENUM_BUFFER_SIZE >= ((tusb_desc_configuration_t*)enum_data_buffer)->wTotalLength,
|
||||
tuh_device_mount_failed_cb(TUSB_ERROR_USBH_MOUNT_CONFIG_DESC_TOO_LONG, NULL) );
|
||||
|
||||
//------------- Get full configuration descriptor -------------//
|
||||
STASK_INVOKE(
|
||||
usbh_control_xfer_subtask( new_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_STANDARD, TUSB_REQ_RCPT_DEVICE),
|
||||
TUSB_REQ_GET_DESCRIPTOR, (TUSB_DESC_CONFIGURATION << 8) | (configure_selected - 1), 0,
|
||||
CFG_TUSB_HOST_ENUM_BUFFER_SIZE, enum_data_buffer ),
|
||||
error
|
||||
);
|
||||
STASK_ASSERT_ERR(error);
|
||||
|
||||
// update configuration info
|
||||
usbh_devices[new_addr].interface_count = ((tusb_desc_configuration_t*) enum_data_buffer)->bNumInterfaces;
|
||||
|
||||
//------------- Set Configure -------------//
|
||||
STASK_INVOKE(
|
||||
usbh_control_xfer_subtask( new_addr, bm_request_type(TUSB_DIR_OUT, TUSB_REQ_TYPE_STANDARD, TUSB_REQ_RCPT_DEVICE),
|
||||
TUSB_REQ_SET_CONFIGURATION, configure_selected, 0,
|
||||
0, NULL ),
|
||||
error
|
||||
);
|
||||
STASK_ASSERT_ERR(error);
|
||||
|
||||
usbh_devices[new_addr].state = TUSB_DEVICE_STATE_CONFIGURED;
|
||||
|
||||
//------------- TODO Get String Descriptors -------------//
|
||||
|
||||
//------------- parse configuration & install drivers -------------//
|
||||
p_desc = enum_data_buffer + sizeof(tusb_desc_configuration_t);
|
||||
|
||||
// parse each interfaces
|
||||
while( p_desc < enum_data_buffer + ((tusb_desc_configuration_t*)enum_data_buffer)->wTotalLength )
|
||||
{
|
||||
// skip until we see interface descriptor
|
||||
if ( TUSB_DESC_INTERFACE != p_desc[DESCRIPTOR_OFFSET_TYPE] )
|
||||
{
|
||||
p_desc += p_desc[DESCRIPTOR_OFFSET_LENGTH]; // skip the descriptor, increase by the descriptor's length
|
||||
}else
|
||||
{
|
||||
static uint8_t class_index; // has to be static as it is used to call class's open_subtask
|
||||
|
||||
class_index = std_class_code_to_index( ((tusb_desc_interface_t*) p_desc)->bInterfaceClass );
|
||||
STASK_ASSERT( class_index != 0 ); // class_index == 0 means corrupted data, abort enumeration
|
||||
|
||||
if (usbh_class_drivers[class_index].open_subtask &&
|
||||
!(class_index == TUSB_CLASS_HUB && usbh_devices[new_addr].hub_addr != 0))
|
||||
{ // supported class, TODO Hub disable multiple level
|
||||
static uint16_t length;
|
||||
length = 0;
|
||||
|
||||
STASK_INVOKE ( // parameters in task/sub_task must be static storage (static or global)
|
||||
usbh_class_drivers[class_index].open_subtask( new_addr, (tusb_desc_interface_t*) p_desc, &length ),
|
||||
error
|
||||
);
|
||||
|
||||
if (error == TUSB_ERROR_NONE)
|
||||
{
|
||||
STASK_ASSERT( length >= sizeof(tusb_desc_interface_t) );
|
||||
usbh_devices[new_addr].flag_supported_class |= BIT_(class_index);
|
||||
p_desc += length;
|
||||
}else // Interface open failed, for example a subclass is not supported
|
||||
{
|
||||
p_desc += p_desc[DESCRIPTOR_OFFSET_LENGTH]; // skip this interface, the rest will be skipped by the above loop
|
||||
}
|
||||
} else // unsupported class (not enable or yet implemented)
|
||||
{
|
||||
p_desc += p_desc[DESCRIPTOR_OFFSET_LENGTH]; // skip this interface, the rest will be skipped by the above loop
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
tuh_device_mount_succeed_cb(new_addr);
|
||||
|
||||
OSAL_SUBTASK_END
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// REPORTER TASK & ITS DATA
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// INTERNAL HELPER
|
||||
//--------------------------------------------------------------------+
|
||||
static inline uint8_t get_new_address(void)
|
||||
{
|
||||
uint8_t addr;
|
||||
for (addr=1; addr <= CFG_TUSB_HOST_DEVICE_MAX; addr++)
|
||||
{
|
||||
if (usbh_devices[addr].state == TUSB_DEVICE_STATE_UNPLUG)
|
||||
break;
|
||||
}
|
||||
return addr;
|
||||
}
|
||||
|
||||
static inline uint8_t get_configure_number_for_device(tusb_desc_device_t* dev_desc)
|
||||
{
|
||||
uint8_t config_num = 1;
|
||||
|
||||
// invoke callback to ask user which configuration to select
|
||||
if (tuh_device_attached_cb)
|
||||
{
|
||||
config_num = min8_of(1, tuh_device_attached_cb(dev_desc) );
|
||||
}
|
||||
|
||||
return config_num;
|
||||
}
|
||||
|
||||
#endif
|
||||
+116
@@ -0,0 +1,116 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file usbh.h
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
/** \ingroup group_usbh USB Host Core (USBH)
|
||||
* @{ */
|
||||
|
||||
#ifndef _TUSB_USBH_H_
|
||||
#define _TUSB_USBH_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// INCLUDE
|
||||
//--------------------------------------------------------------------+
|
||||
#include "osal/osal.h" // TODO refractor move to common.h ?
|
||||
#include "hcd.h"
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO CONSTANT TYPEDEF
|
||||
//--------------------------------------------------------------------+
|
||||
typedef enum tusb_interface_status_{
|
||||
TUSB_INTERFACE_STATUS_READY = 0,
|
||||
TUSB_INTERFACE_STATUS_BUSY,
|
||||
TUSB_INTERFACE_STATUS_COMPLETE,
|
||||
TUSB_INTERFACE_STATUS_ERROR,
|
||||
TUSB_INTERFACE_STATUS_INVALID_PARA
|
||||
} tusb_interface_status_t;
|
||||
|
||||
typedef struct {
|
||||
void (* const init) (void);
|
||||
tusb_error_t (* const open_subtask)(uint8_t, tusb_desc_interface_t const *, uint16_t*);
|
||||
void (* const isr) (pipe_handle_t, tusb_event_t, uint32_t);
|
||||
void (* const close) (uint8_t);
|
||||
} host_class_driver_t;
|
||||
//--------------------------------------------------------------------+
|
||||
// INTERNAL OBJECT & FUNCTION DECLARATION
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// APPLICATION API
|
||||
//--------------------------------------------------------------------+
|
||||
//tusb_error_t tusbh_configuration_set (uint8_t dev_addr, uint8_t configure_number) ATTR_WARN_UNUSED_RESULT;
|
||||
tusb_device_state_t tuh_device_get_state (uint8_t dev_addr) ATTR_WARN_UNUSED_RESULT ATTR_PURE;
|
||||
static inline bool tuh_device_is_configured(uint8_t dev_addr) ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT ATTR_PURE;
|
||||
static inline bool tuh_device_is_configured(uint8_t dev_addr)
|
||||
{
|
||||
return tuh_device_get_state(dev_addr) == TUSB_DEVICE_STATE_CONFIGURED;
|
||||
}
|
||||
uint32_t tuh_device_get_mounted_class_flag(uint8_t dev_addr);
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// APPLICATION CALLBACK
|
||||
//--------------------------------------------------------------------+
|
||||
ATTR_WEAK uint8_t tuh_device_attached_cb (tusb_desc_device_t const *p_desc_device) ATTR_WARN_UNUSED_RESULT;
|
||||
ATTR_WEAK void tuh_device_mount_succeed_cb (uint8_t dev_addr);
|
||||
ATTR_WEAK void tuh_device_mount_failed_cb(tusb_error_t error, tusb_desc_device_t const *p_desc_device); // TODO refractor remove desc_device
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// CLASS-USBH & INTERNAL API
|
||||
//--------------------------------------------------------------------+
|
||||
#ifdef _TINY_USB_SOURCE_FILE_
|
||||
|
||||
|
||||
void usbh_enumeration_task(void* param);
|
||||
tusb_error_t usbh_init(void);
|
||||
|
||||
tusb_error_t usbh_control_xfer_subtask(uint8_t dev_addr, uint8_t bmRequestType, uint8_t bRequest,
|
||||
uint16_t wValue, uint16_t wIndex, uint16_t wLength, uint8_t* data);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_USBH_H_ */
|
||||
|
||||
/** @} */
|
||||
@@ -0,0 +1,114 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file usbh_hcd.h
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
/** \ingroup Group_HCD
|
||||
* @{ */
|
||||
|
||||
#ifndef _TUSB_USBH_HCD_H_
|
||||
#define _TUSB_USBH_HCD_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// INCLUDE
|
||||
//--------------------------------------------------------------------+
|
||||
#include "common/tusb_common.h"
|
||||
#include "osal/osal.h"
|
||||
|
||||
#ifdef _TEST_
|
||||
#include "hcd.h"
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// USBH-HCD common data structure
|
||||
//--------------------------------------------------------------------+
|
||||
typedef struct ATTR_ALIGNED(4){
|
||||
uint8_t core_id;
|
||||
uint8_t hub_addr;
|
||||
uint8_t hub_port;
|
||||
uint8_t reserve;
|
||||
} usbh_enumerate_t;
|
||||
|
||||
typedef struct {
|
||||
//------------- port -------------//
|
||||
uint8_t core_id;
|
||||
uint8_t hub_addr;
|
||||
uint8_t hub_port;
|
||||
uint8_t speed;
|
||||
|
||||
//------------- device descriptor -------------//
|
||||
uint16_t vendor_id;
|
||||
uint16_t product_id;
|
||||
uint8_t configure_count; // bNumConfigurations alias
|
||||
|
||||
//------------- configuration descriptor -------------//
|
||||
uint8_t interface_count; // bNumInterfaces alias
|
||||
|
||||
//------------- device -------------//
|
||||
volatile uint8_t state; // device state, value from enum tusbh_device_state_t
|
||||
uint32_t flag_supported_class; // a bitmap of supported class
|
||||
|
||||
//------------- control pipe -------------//
|
||||
struct {
|
||||
volatile uint8_t pipe_status;
|
||||
// uint8_t xferred_bytes; TODO not yet necessary
|
||||
tusb_control_request_t request;
|
||||
|
||||
osal_semaphore_t sem_hdl; // used to synchronize with HCD when control xfer complete
|
||||
osal_mutex_t mutex_hdl; // used to exclusively occupy control pipe
|
||||
} control;
|
||||
} usbh_device_info_t;
|
||||
|
||||
extern usbh_device_info_t usbh_devices[CFG_TUSB_HOST_DEVICE_MAX+1]; // including zero-address
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// callback from HCD ISR
|
||||
//--------------------------------------------------------------------+
|
||||
void usbh_xfer_isr(pipe_handle_t pipe_hdl, uint8_t class_code, tusb_event_t event, uint32_t xferred_bytes);
|
||||
void usbh_hcd_rhport_plugged_isr(uint8_t hostid);
|
||||
void usbh_hcd_rhport_unplugged_isr(uint8_t hostid);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_USBH_HCD_H_ */
|
||||
|
||||
/** @} */
|
||||
@@ -0,0 +1,64 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file usbh_hub.h
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
/** \ingroup group_usbh
|
||||
* @{ */
|
||||
|
||||
#ifndef _TUSB_USBH_HUB_H_
|
||||
#define _TUSB_USBH_HUB_H_
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// INCLUDE
|
||||
//--------------------------------------------------------------------+
|
||||
#include "common/tusb_common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
void usbh_hub_port_plugged_isr(uint8_t hub_addr, uint8_t hub_port);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_USBH_HUB_H_ */
|
||||
|
||||
/** @} */
|
||||
Reference in New Issue
Block a user