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Merge remote-tracking branch 'origin' into msp430f5529

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This commit is contained in:
William D. Jones
2019-10-02 23:18:49 -04:00
parent b0b737b42a e59742f200
commit 5ee1070c16
82 changed files with 7267 additions and 573 deletions
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src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+1 -1
View File
@@ -293,7 +293,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
break;
case TUSB_XFER_ISOCHRONOUS:
TU_ASSERT((epnum % 3) == 3 && (epnum != 15));
TU_ASSERT((epnum % 3) == 0 && (epnum != 0) && (epnum != 15));
break;
default:
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+217 -176
View File
@@ -30,13 +30,10 @@
/**********************************************
* This driver has been tested with the following MCUs:
*
*
* STM32F070RB
*
* - F070, F072, L053
*
* It also should work with minimal changes for any ST MCU with an "USB A"/"PCD"/"HCD" peripheral. This
* covers:
* covers:
*
* F04x, F072, F078, 070x6/B 1024 byte buffer
* F102, F103 512 byte buffer; no internal D+ pull-up (maybe many more changes?)
@@ -46,9 +43,13 @@
* L1 512 byte buffer
* L4x2, L4x3 1024 byte buffer
*
* To use this driver, you must:
* - Enable USB clock; Perhaps use __HAL_RCC_USB_CLK_ENABLE();
* - (Optionally configure GPIO HAL to tell it the USB driver is using the USB pins)
* - call tusb_init();
* - periodically call tusb_task();
*
* Assumptions of the driver:
* - dcd_fs_irqHandler() is called by the USB interrupt handler
* - USB clock enabled before usb_init() is called; Perhaps use __HAL_RCC_USB_CLK_ENABLE();
* - You are not using CAN (it must share the packet buffer)
* - APB clock is >= 10 MHz
* - On some boards, series resistors are required, but not on others.
@@ -59,7 +60,6 @@
* Current driver limitations (i.e., a list of features for you to add):
* - STALL handled, but not tested.
* - Does it work? No clue.
* - Only tested on F070RB; other models will have an #error during compilation
* - All EP BTABLE buffers are created as max 64 bytes.
* - Smaller can be requested, but it has to be an even number.
* - No isochronous endpoints
@@ -74,7 +74,7 @@
* - No DMA
* - No provision to control the D+ pull-up using GPIO on devices without an internal pull-up.
* - Minimal error handling
* - Perhaps error interrupts sholud be reported to the stack, or cause a device reset?
* - Perhaps error interrupts should be reported to the stack, or cause a device reset?
* - Assumes a single USB peripheral; I think that no hardware has multiple so this is fine.
* - Add a callback for enabling/disabling the D+ PU on devices without an internal PU.
* - F3 models use three separate interrupts. I think we could only use the LP interrupt for
@@ -103,14 +103,17 @@
#include "tusb_option.h"
#if defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || \
defined(STM32F103xE) || defined(STM32F103xG)
#define STM32F1_FSDEV
#endif
#if (TUSB_OPT_DEVICE_ENABLED) && ( \
((CFG_TUSB_MCU) == OPT_MCU_STM32F0) || \
(((CFG_TUSB_MCU) == OPT_MCU_STM32F1) && ( \
defined(stm32f102x6) || defined(stm32f102xb) || \
defined(stm32f103x6) || defined(stm32f103xb) || \
defined(stm32f103xe) || defined(stm32f103xg) \
)) || \
((CFG_TUSB_MCU) == OPT_MCU_STM32F3) \
(CFG_TUSB_MCU == OPT_MCU_STM32F0 ) || \
(CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_FSDEV)) || \
(CFG_TUSB_MCU == OPT_MCU_STM32F3 ) || \
(CFG_TUSB_MCU == OPT_MCU_STM32L0 ) \
)
// In order to reduce the dependance on HAL, we undefine this.
@@ -144,22 +147,12 @@
* Checks, structs, defines, function definitions, etc.
*/
#if ((MAX_EP_COUNT) > 8)
# error Only 8 endpoints supported on the hardware
#endif
TU_VERIFY_STATIC((MAX_EP_COUNT) <= STFSDEV_EP_COUNT, "Only 8 endpoints supported on the hardware");
#if (((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_LENGTH))>(PMA_LENGTH))
# error BTABLE does not fit in PMA RAM
#endif
#if (((DCD_STM32_BTABLE_BASE) % 8) != 0)
// per STM32F3 reference manual
#error BTABLE must be aligned to 8 bytes
#endif
// Max size of a USB FS packet is 64...
#define MAX_PACKET_SIZE 64
TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_LENGTH))<=(PMA_LENGTH),
"BTABLE does not fit in PMA RAM");
TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) % 8) == 0, "BTABLE base must be aligned to 8 bytes");
// One of these for every EP IN & OUT, uses a bit of RAM....
typedef struct
@@ -167,24 +160,37 @@ typedef struct
uint8_t * buffer;
uint16_t total_len;
uint16_t queued_len;
uint16_t max_packet_size;
} xfer_ctl_t;
static xfer_ctl_t xfer_status[MAX_EP_COUNT][2];
#define XFER_CTL_BASE(_epnum, _dir) &xfer_status[_epnum][_dir]
static xfer_ctl_t xfer_status[MAX_EP_COUNT][2];
static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t epnum, uint32_t dir)
{
return &xfer_status[epnum][dir];
}
static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
static uint8_t newDADDR; // Used to set the new device address during the CTR IRQ handler
static uint8_t remoteWakeCountdown; // When wake is requested
// EP Buffers assigned from end of memory location, to minimize their chance of crashing
// into the stack.
static uint16_t ep_buf_ptr;
static void dcd_handle_bus_reset(void);
static void dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes);
static void dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes);
static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes);
static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes);
static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix);
static uint16_t dcd_ep_ctr_handler(void);
// Using a function due to better type checks
// This seems better than having to do type casts everywhere else
static inline void reg16_clear_bits(__IO uint16_t *reg, uint16_t mask) {
*reg = (uint16_t)(*reg & ~mask);
}
void dcd_init (uint8_t rhport)
{
(void)rhport;
@@ -204,7 +210,7 @@ void dcd_init (uint8_t rhport)
{
asm("NOP");
}
USB->CNTR &= ~(USB_CNTR_PDWN);// Remove powerdown
reg16_clear_bits(&USB->CNTR, USB_CNTR_PDWN);// Remove powerdown
// Wait startup time, for F042 and F070, this is <= 1 us.
for(uint32_t i = 0; i<200; i++) // should be a few us
{
@@ -214,21 +220,22 @@ void dcd_init (uint8_t rhport)
USB->BTABLE = DCD_STM32_BTABLE_BASE;
USB->ISTR &= ~(USB_ISTR_ALL_EVENTS); // Clear pending interrupts
reg16_clear_bits(&USB->ISTR, USB_ISTR_ALL_EVENTS); // Clear pending interrupts
// Clear all EPREG
for(uint16_t i=0; i<8; i++)
// Reset endpoints to disabled
for(uint32_t i=0; i<STFSDEV_EP_COUNT; i++)
{
EPREG(0) = 0u;
// This doesn't clear all bits since some bits are "toggle", but does set the type to DISABLED.
pcd_set_endpoint(USB,i,0u);
}
// Initialize the BTABLE for EP0 at this point (though setting up the EP0R is unneeded)
// This is actually not necessary, but helps debugging to start with a blank RAM area
for(uint16_t i=0;i<(DCD_STM32_BTABLE_LENGTH>>1); i++)
for(uint32_t i=0;i<(DCD_STM32_BTABLE_LENGTH>>1); i++)
{
pma[PMA_STRIDE*(DCD_STM32_BTABLE_BASE + i)] = 0u;
}
USB->CNTR |= USB_CNTR_RESETM | USB_CNTR_SOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM;
USB->CNTR |= USB_CNTR_RESETM | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM;
dcd_handle_bus_reset();
// And finally enable pull-up, which may trigger the RESET IRQ if the host is connected.
@@ -245,16 +252,21 @@ void dcd_init (uint8_t rhport)
void dcd_int_enable (uint8_t rhport)
{
(void)rhport;
#if defined(STM32F0)
NVIC_SetPriority(USB_IRQn, 0);
// Member here forces write to RAM before allowing ISR to execute
__DSB();
__ISB();
#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0
NVIC_EnableIRQ(USB_IRQn);
#elif defined(STM32F3)
NVIC_SetPriority(USB_HP_CAN_TX_IRQn, 0);
NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0);
NVIC_SetPriority(USBWakeUp_IRQn, 0);
#elif CFG_TUSB_MCU == OPT_MCU_STM32F3
NVIC_EnableIRQ(USB_HP_CAN_TX_IRQn);
NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn);
NVIC_EnableIRQ(USBWakeUp_IRQn);
#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
NVIC_EnableIRQ(USB_HP_CAN1_TX_IRQn);
NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
NVIC_EnableIRQ(USBWakeUp_IRQn);
#else
#error Unknown arch in USB driver
#endif
}
@@ -262,15 +274,22 @@ void dcd_int_enable (uint8_t rhport)
void dcd_int_disable(uint8_t rhport)
{
(void)rhport;
#if defined(STM32F0)
#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0
NVIC_DisableIRQ(USB_IRQn);
#elif defined(STM32F3)
#elif CFG_TUSB_MCU == OPT_MCU_STM32F3
NVIC_DisableIRQ(USB_HP_CAN_TX_IRQn);
NVIC_DisableIRQ(USB_LP_CAN_RX0_IRQn);
NVIC_DisableIRQ(USBWakeUp_IRQn);
#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
NVIC_DisableIRQ(USB_HP_CAN1_TX_IRQn);
NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn);
NVIC_DisableIRQ(USBWakeUp_IRQn);
#else
#error Unknown arch in USB driver
#error Unknown arch in USB driver
#endif
// CMSIS has a membar after disabling interrupts
}
// Receive Set Address request, mcu port must also include status IN response
@@ -297,6 +316,9 @@ void dcd_set_config (uint8_t rhport, uint8_t config_num)
void dcd_remote_wakeup(uint8_t rhport)
{
(void) rhport;
USB->CNTR |= (uint16_t) USB_CNTR_RESUME;
remoteWakeCountdown = 4u; // required to be 1 to 15 ms, ESOF should trigger every 1ms.
}
// I'm getting a weird warning about missing braces here that I don't
@@ -319,7 +341,9 @@ static const tusb_desc_endpoint_t ep0IN_desc =
.bEndpointAddress = 0x80
};
#if defined(__GNUC__) && (__GNUC__ >= 7)
#pragma GCC diagnostic pop
#endif
static void dcd_handle_bus_reset(void)
{
@@ -327,23 +351,22 @@ static void dcd_handle_bus_reset(void)
USB->DADDR = 0u; // disable USB peripheral by clearing the EF flag
// Clear all EPREG (or maybe this is automatic? I'm not sure)
for(uint16_t i=0; i<8; i++)
for(uint32_t i=0; i<STFSDEV_EP_COUNT; i++)
{
EPREG(0) = 0u;
pcd_set_endpoint(USB,i,0u);
}
ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8*MAX_EP_COUNT; // 8 bytes per endpoint (two TX and two RX words, each)
dcd_edpt_open (0, &ep0OUT_desc);
dcd_edpt_open (0, &ep0IN_desc);
newDADDR = 0;
newDADDR = 0u;
USB->DADDR = USB_DADDR_EF; // Set enable flag, and leaving the device address as zero.
PCD_SET_EP_RX_STATUS(USB, 0, USB_EP_RX_VALID); // And start accepting SETUP on EP0
}
// FIXME: Defined to return uint16 so that ASSERT can be used, even though a return value is not needed.
static uint16_t dcd_ep_ctr_handler(void)
{
uint16_t count=0U;
uint32_t count=0U;
uint8_t EPindex;
__IO uint16_t wIstr;
__IO uint16_t wEPVal = 0U;
@@ -365,9 +388,9 @@ static uint16_t dcd_ep_ctr_handler(void)
{
/* DIR = 0 => IN int */
/* DIR = 0 implies that (EP_CTR_TX = 1) always */
PCD_CLEAR_TX_EP_CTR(USB, 0);
pcd_clear_tx_ep_ctr(USB, 0);
xfer_ctl_t * xfer = XFER_CTL_BASE(EPindex,TUSB_DIR_IN);
xfer_ctl_t * xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_IN);
if((xfer->total_len == xfer->queued_len))
{
@@ -375,13 +398,13 @@ static uint16_t dcd_ep_ctr_handler(void)
if((newDADDR != 0) && ( xfer->total_len == 0U))
{
// Delayed setting of the DADDR after the 0-len DATA packet acking the request is sent.
USB->DADDR &= ~USB_DADDR_ADD;
USB->DADDR |= newDADDR;
reg16_clear_bits(&USB->DADDR, USB_DADDR_ADD);
USB->DADDR = (uint16_t)(USB->DADDR | newDADDR); // leave the enable bit set
newDADDR = 0;
}
if(xfer->total_len == 0) // Probably a status message?
{
PCD_CLEAR_RX_DTOG(USB,EPindex);
pcd_clear_rx_dtog(USB,EPindex);
}
}
else
@@ -394,10 +417,10 @@ static uint16_t dcd_ep_ctr_handler(void)
/* DIR = 1 & CTR_RX => SETUP or OUT int */
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
xfer_ctl_t *xfer = XFER_CTL_BASE(EPindex,TUSB_DIR_OUT);
xfer_ctl_t *xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_OUT);
//ep = &hpcd->OUT_ep[0];
wEPVal = PCD_GET_ENDPOINT(USB, EPindex);
wEPVal = pcd_get_endpoint(USB, EPindex);
if ((wEPVal & USB_EP_SETUP) != 0U) // SETUP
{
@@ -405,69 +428,67 @@ static uint16_t dcd_ep_ctr_handler(void)
// user memory, to allow for the 32-bit access that memcpy performs.
uint8_t userMemBuf[8];
/* Get SETUP Packet*/
count = PCD_GET_EP_RX_CNT(USB, EPindex);
//TU_ASSERT_ERR(count == 8);
dcd_read_packet_memory(userMemBuf, *PCD_EP_RX_ADDRESS_PTR(USB,EPindex), 8);
count = pcd_get_ep_rx_cnt(USB, EPindex);
if(count == 8) // Setup packet should always be 8 bytes. If not, ignore it, and try again.
{
// Must reset EP to NAK (in case it had been stalling) (though, maybe too late here)
pcd_set_ep_rx_status(USB,0u,USB_EP_RX_NAK);
pcd_set_ep_tx_status(USB,0u,USB_EP_TX_NAK);
dcd_read_packet_memory(userMemBuf, *pcd_ep_rx_address_ptr(USB,EPindex), 8);
dcd_event_setup_received(0, (uint8_t*)userMemBuf, true);
}
/* SETUP bit kept frozen while CTR_RX = 1*/
dcd_event_setup_received(0, (uint8_t*)userMemBuf, true);
PCD_CLEAR_RX_EP_CTR(USB, EPindex);
pcd_clear_rx_ep_ctr(USB, EPindex);
}
else if ((wEPVal & USB_EP_CTR_RX) != 0U) // OUT
{
PCD_CLEAR_RX_EP_CTR(USB, EPindex);
pcd_clear_rx_ep_ctr(USB, EPindex);
/* Get Control Data OUT Packet */
count = PCD_GET_EP_RX_CNT(USB,EPindex);
count = pcd_get_ep_rx_cnt(USB,EPindex);
if (count != 0U)
{
dcd_read_packet_memory(xfer->buffer, *PCD_EP_RX_ADDRESS_PTR(USB,EPindex), count);
dcd_read_packet_memory(xfer->buffer, *pcd_ep_rx_address_ptr(USB,EPindex), count);
xfer->queued_len = (uint16_t)(xfer->queued_len + count);
}
/* Process Control Data OUT status Packet*/
if(EPindex == 0 && xfer->total_len == 0)
{
PCD_CLEAR_EP_KIND(USB,0); // Good, so allow non-zero length packets now.
}
dcd_event_xfer_complete(0, EPindex, xfer->total_len, XFER_RESULT_SUCCESS, true);
PCD_SET_EP_RX_CNT(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
if(EPindex == 0 && xfer->total_len == 0)
pcd_set_ep_rx_cnt(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
if(EPindex == 0u && xfer->total_len == 0u)
{
PCD_SET_EP_RX_STATUS(USB, EPindex, USB_EP_RX_VALID);// Await next SETUP
pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID);// Await next SETUP
}
}
}
}
else /* Decode and service non control endpoints interrupt */
{
/* process related endpoint register */
wEPVal = PCD_GET_ENDPOINT(USB, EPindex);
wEPVal = pcd_get_endpoint(USB, EPindex);
if ((wEPVal & USB_EP_CTR_RX) != 0U) // OUT
{
/* clear int flag */
PCD_CLEAR_RX_EP_CTR(USB, EPindex);
pcd_clear_rx_ep_ctr(USB, EPindex);
xfer_ctl_t * xfer = XFER_CTL_BASE(EPindex,TUSB_DIR_OUT);
xfer_ctl_t * xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_OUT);
//ep = &hpcd->OUT_ep[EPindex];
count = PCD_GET_EP_RX_CNT(USB, EPindex);
count = pcd_get_ep_rx_cnt(USB, EPindex);
if (count != 0U)
{
dcd_read_packet_memory(&(xfer->buffer[xfer->queued_len]),
*PCD_EP_RX_ADDRESS_PTR(USB,EPindex), count);
*pcd_ep_rx_address_ptr(USB,EPindex), count);
}
/*multi-packet on the NON control OUT endpoint */
xfer->queued_len = (uint16_t)(xfer->queued_len + count);
if ((count < 64) || (xfer->queued_len == xfer->total_len))
if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
{
/* RX COMPLETE */
dcd_event_xfer_complete(0, EPindex, xfer->queued_len, XFER_RESULT_SUCCESS, true);
@@ -476,14 +497,14 @@ static uint16_t dcd_ep_ctr_handler(void)
}
else
{
uint16_t remaining = (uint16_t)(xfer->total_len - xfer->queued_len);
if(remaining >=64) {
PCD_SET_EP_RX_CNT(USB, EPindex,64);
uint32_t remaining = (uint32_t)xfer->total_len - (uint32_t)xfer->queued_len;
if(remaining >= xfer->max_packet_size) {
pcd_set_ep_rx_cnt(USB, EPindex,xfer->max_packet_size);
} else {
PCD_SET_EP_RX_CNT(USB, EPindex,remaining);
pcd_set_ep_rx_cnt(USB, EPindex,remaining);
}
PCD_SET_EP_RX_STATUS(USB, EPindex, USB_EP_RX_VALID);
pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID);
}
} /* if((wEPVal & EP_CTR_RX) */
@@ -491,9 +512,9 @@ static uint16_t dcd_ep_ctr_handler(void)
if ((wEPVal & USB_EP_CTR_TX) != 0U) // IN
{
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(USB, EPindex);
pcd_clear_tx_ep_ctr(USB, EPindex);
xfer_ctl_t * xfer = XFER_CTL_BASE(EPindex,TUSB_DIR_IN);
xfer_ctl_t * xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_IN);
if (xfer->queued_len != xfer->total_len) // data remaining in transfer?
{
@@ -507,46 +528,71 @@ static uint16_t dcd_ep_ctr_handler(void)
return 0;
}
void dcd_fs_irqHandler(void) {
static void dcd_fs_irqHandler(void) {
uint16_t int_status = USB->ISTR;
// unused IRQs: (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_WKUP | USB_ISTR_SUSP | USB_ISTR_ESOF | USB_ISTR_L1REQ )
uint32_t int_status = USB->ISTR;
//const uint32_t handled_ints = USB_ISTR_CTR | USB_ISTR_RESET | USB_ISTR_WKUP
// | USB_ISTR_SUSP | USB_ISTR_SOF | USB_ISTR_ESOF;
// unused IRQs: (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_L1REQ )
// The ST driver loops here on the CTR bit, but that loop has been moved into the
// dcd_ep_ctr_handler(), so less need to loop here. The other interrupts shouldn't
// be triggered repeatedly.
if(int_status & USB_ISTR_RESET) {
// USBRST is start of reset.
reg16_clear_bits(&USB->ISTR, USB_ISTR_RESET);
dcd_handle_bus_reset();
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
return; // Don't do the rest of the things here; perhaps they've been cleared?
}
if (int_status & USB_ISTR_CTR)
{
/* servicing of the endpoint correct transfer interrupt */
/* clear of the CTR flag into the sub */
dcd_ep_ctr_handler();
USB->ISTR &= ~USB_ISTR_CTR;
}
if(int_status & USB_ISTR_RESET) {
// USBRST is start of reset.
USB->ISTR &= ~USB_ISTR_RESET;
dcd_handle_bus_reset();
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
reg16_clear_bits(&USB->ISTR, USB_ISTR_CTR);
}
if (int_status & USB_ISTR_WKUP)
{
USB->CNTR &= ~USB_CNTR_LPMODE;
USB->CNTR &= ~USB_CNTR_FSUSP;
USB->ISTR &= ~USB_ISTR_WKUP;
reg16_clear_bits(&USB->CNTR, USB_CNTR_LPMODE);
reg16_clear_bits(&USB->CNTR, USB_CNTR_FSUSP);
reg16_clear_bits(&USB->ISTR, USB_ISTR_WKUP);
dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
}
if (int_status & USB_ISTR_SUSP)
{
/* Suspend is asserted for both suspend and unplug events. without Vbus monitoring,
* these events cannot be differentiated, so we only trigger suspend. */
/* Force low-power mode in the macrocell */
USB->CNTR |= USB_CNTR_FSUSP;
USB->CNTR |= USB_CNTR_LPMODE;
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
USB->ISTR &= ~USB_ISTR_SUSP;
reg16_clear_bits(&USB->ISTR, USB_ISTR_SUSP);
dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
}
if(int_status & USB_ISTR_SOF) {
USB->ISTR &= ~USB_ISTR_SOF;
reg16_clear_bits(&USB->ISTR, USB_ISTR_SOF);
dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
}
if(int_status & USB_ISTR_ESOF) {
if(remoteWakeCountdown == 1u)
{
USB->CNTR &= (uint16_t)(~USB_CNTR_RESUME);
}
if(remoteWakeCountdown > 0u)
{
remoteWakeCountdown--;
}
reg16_clear_bits(&USB->ISTR, USB_ISTR_ESOF);
}
}
//--------------------------------------------------------------------+
@@ -561,47 +607,57 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
(void)rhport;
uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
const uint16_t epMaxPktSize = p_endpoint_desc->wMaxPacketSize.size;
// Isochronous not supported (yet), and some other driver assumptions.
TU_ASSERT(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
TU_ASSERT(p_endpoint_desc->wMaxPacketSize.size <= MAX_PACKET_SIZE);
TU_ASSERT(epnum < MAX_EP_COUNT);
TU_ASSERT((p_endpoint_desc->wMaxPacketSize.size %2) == 0);
// __IO uint16_t * const epreg = &(EPREG(epnum));
TU_ASSERT(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
TU_ASSERT(epnum < MAX_EP_COUNT);
// Set type
switch(p_endpoint_desc->bmAttributes.xfer) {
case TUSB_XFER_CONTROL:
PCD_SET_EPTYPE(USB, epnum, USB_EP_CONTROL); break;
case TUSB_XFER_ISOCHRONOUS:
PCD_SET_EPTYPE(USB, epnum, USB_EP_ISOCHRONOUS); break;
pcd_set_eptype(USB, epnum, USB_EP_CONTROL);
break;
#if (0)
case TUSB_XFER_ISOCHRONOUS: // FIXME: Not yet supported
pcd_set_eptype(USB, epnum, USB_EP_ISOCHRONOUS); break;
break;
#endif
case TUSB_XFER_BULK:
PCD_SET_EPTYPE(USB, epnum, USB_EP_BULK); break;
pcd_set_eptype(USB, epnum, USB_EP_BULK);
break;
case TUSB_XFER_INTERRUPT:
PCD_SET_EPTYPE(USB, epnum, USB_EP_INTERRUPT); break;
pcd_set_eptype(USB, epnum, USB_EP_INTERRUPT);
break;
default:
TU_ASSERT(false);
return false;
}
PCD_SET_EP_ADDRESS(USB, epnum, epnum);
PCD_CLEAR_EP_KIND(USB,0); // Be normal, for now, instead of only accepting zero-byte packets
pcd_set_ep_address(USB, epnum, epnum);
// Be normal, for now, instead of only accepting zero-byte packets (on control endpoint)
// or being double-buffered (bulk endpoints)
pcd_clear_ep_kind(USB,0);
if(dir == TUSB_DIR_IN)
{
*PCD_EP_TX_ADDRESS_PTR(USB, epnum) = ep_buf_ptr;
PCD_SET_EP_RX_CNT(USB, epnum, p_endpoint_desc->wMaxPacketSize.size);
PCD_CLEAR_TX_DTOG(USB, epnum);
PCD_SET_EP_TX_STATUS(USB,epnum,USB_EP_TX_NAK);
*pcd_ep_tx_address_ptr(USB, epnum) = ep_buf_ptr;
pcd_set_ep_tx_cnt(USB, epnum, p_endpoint_desc->wMaxPacketSize.size);
pcd_clear_tx_dtog(USB, epnum);
pcd_set_ep_tx_status(USB,epnum,USB_EP_TX_NAK);
}
else
{
*PCD_EP_RX_ADDRESS_PTR(USB, epnum) = ep_buf_ptr;
PCD_SET_EP_RX_CNT(USB, epnum, p_endpoint_desc->wMaxPacketSize.size);
PCD_CLEAR_RX_DTOG(USB, epnum);
PCD_SET_EP_RX_STATUS(USB, epnum, USB_EP_RX_NAK);
*pcd_ep_rx_address_ptr(USB, epnum) = ep_buf_ptr;
pcd_set_ep_rx_cnt(USB, epnum, p_endpoint_desc->wMaxPacketSize.size);
pcd_clear_rx_dtog(USB, epnum);
pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK);
}
xfer_ctl_ptr(epnum, dir)->max_packet_size = epMaxPktSize;
ep_buf_ptr = (uint16_t)(ep_buf_ptr + p_endpoint_desc->wMaxPacketSize.size); // increment buffer pointer
return true;
@@ -613,15 +669,16 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
{
uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);
if(len > 64u) // max packet size for FS transfer
if(len > xfer->max_packet_size) // max packet size for FS transfer
{
len = 64u;
len = xfer->max_packet_size;
}
dcd_write_packet_memory(*PCD_EP_TX_ADDRESS_PTR(USB,ep_ix), &(xfer->buffer[xfer->queued_len]), len);
uint16_t oldAddr = *pcd_ep_tx_address_ptr(USB,ep_ix);
dcd_write_packet_memory(oldAddr, &(xfer->buffer[xfer->queued_len]), len);
xfer->queued_len = (uint16_t)(xfer->queued_len + len);
PCD_SET_EP_TX_CNT(USB,ep_ix,len);
PCD_SET_EP_TX_STATUS(USB, ep_ix, USB_EP_TX_VALID);
pcd_set_ep_tx_cnt(USB,ep_ix,len);
pcd_set_ep_tx_status(USB, ep_ix, USB_EP_TX_VALID);
}
bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
@@ -631,7 +688,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
uint8_t const epnum = tu_edpt_number(ep_addr);
uint8_t const dir = tu_edpt_dir(ep_addr);
xfer_ctl_t * xfer = XFER_CTL_BASE(epnum,dir);
xfer_ctl_t * xfer = xfer_ctl_ptr(epnum,dir);
xfer->buffer = buffer;
xfer->total_len = total_bytes;
@@ -644,15 +701,14 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
if (epnum == 0 && buffer == NULL)
{
xfer->buffer = (uint8_t*)_setup_packet;
PCD_SET_EP_KIND(USB,0); // Expect a zero-byte INPUT
}
if(total_bytes > 64)
if(total_bytes > xfer->max_packet_size)
{
PCD_SET_EP_RX_CNT(USB,epnum,64);
pcd_set_ep_rx_cnt(USB,epnum,xfer->max_packet_size);
} else {
PCD_SET_EP_RX_CNT(USB,epnum,total_bytes);
pcd_set_ep_rx_cnt(USB,epnum,total_bytes);
}
PCD_SET_EP_RX_STATUS(USB, epnum, USB_EP_RX_VALID);
pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_VALID);
}
else // IN
{
@@ -665,41 +721,35 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
{
(void)rhport;
if (ep_addr == 0) { // CTRL EP0 (OUT for setup)
PCD_SET_EP_TX_STATUS(USB,ep_addr, USB_EP_TX_STALL);
if (ep_addr & 0x80)
{ // IN
pcd_set_ep_tx_status(USB, ep_addr & 0x7F, USB_EP_TX_STALL);
}
if (ep_addr & 0x80) { // IN
ep_addr &= 0x7F;
PCD_SET_EP_TX_STATUS(USB,ep_addr, USB_EP_TX_STALL);
} else { // OUT
PCD_SET_EP_RX_STATUS(USB,ep_addr, USB_EP_RX_STALL);
else
{ // OUT
pcd_set_ep_rx_status(USB, ep_addr, USB_EP_RX_STALL);
}
}
void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
{
(void)rhport;
if (ep_addr == 0)
{
PCD_SET_EP_TX_STATUS(USB,ep_addr, USB_EP_TX_NAK);
}
if (ep_addr & 0x80)
{ // IN
ep_addr &= 0x7F;
PCD_SET_EP_TX_STATUS(USB,ep_addr, USB_EP_TX_NAK);
pcd_set_ep_tx_status(USB,ep_addr, USB_EP_TX_NAK);
/* Reset to DATA0 if clearing stall condition. */
PCD_CLEAR_TX_DTOG(USB,ep_addr);
pcd_clear_tx_dtog(USB,ep_addr);
}
else
{ // OUT
/* Reset to DATA0 if clearing stall condition. */
PCD_CLEAR_RX_DTOG(USB,ep_addr);
pcd_clear_rx_dtog(USB,ep_addr);
PCD_SET_EP_RX_STATUS(USB,ep_addr, USB_EP_RX_VALID);
pcd_set_ep_rx_status(USB,ep_addr, USB_EP_RX_NAK);
}
}
@@ -714,19 +764,13 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
static void dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes)
static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes)
{
uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1U;
uint32_t i;
uint16_t temp1, temp2;
const uint8_t * srcVal;
#ifdef DEBUG
if(((dst%2) != 0) ||
(dst < DCD_STM32_BTABLE_BASE) ||
dst >= (DCD_STM32_BTABLE_BASE + DCD_STM32_BTABLE_LENGTH))
while(1) TU_BREAKPOINT();
#endif
// The GCC optimizer will combine access to 32-bit sizes if we let it. Force
// it volatile so that it won't do that.
__IO uint16_t *pdwVal;
@@ -743,6 +787,7 @@ static void dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si
pdwVal += PMA_STRIDE;
srcVal++;
}
return true;
}
/**
@@ -751,7 +796,7 @@ static void dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
static void dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes)
static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes)
{
uint32_t n = (uint32_t)wNBytes >> 1U;
uint32_t i;
@@ -760,13 +805,6 @@ static void dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN
__IO const uint16_t *pdwVal;
uint32_t temp;
#ifdef DEBUG
if((src%2) != 0 ||
(src < DCD_STM32_BTABLE_BASE) ||
src >= (DCD_STM32_BTABLE_BASE + DCD_STM32_BTABLE_LENGTH))
while(1) TU_BREAKPOINT();
#endif
pdwVal = &pma[PMA_STRIDE*(src>>1)];
uint8_t *dstVal = (uint8_t*)dst;
@@ -784,17 +822,18 @@ static void dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN
pdwVal += PMA_STRIDE;
*dstVal++ = ((temp >> 0) & 0xFF);
}
return true;
}
// Interrupt handlers
#if (CFG_TUSB_MCU) == (OPT_MCU_STM32F0)
#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0
void USB_IRQHandler(void)
{
dcd_fs_irqHandler();
}
#elif (CFG_TUSB_MCU) == (OPT_MCU_STM32F1)
#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
void USB_HP_IRQHandler(void)
{
dcd_fs_irqHandler();
@@ -826,14 +865,16 @@ void USB_LP_CAN_RX0_IRQHandler(void)
{
dcd_fs_irqHandler();
}
// USB wakeup interrupt (Channel 42): Triggered by the wakeup event from the USB
// Suspend mode.
void USBWakeUp_IRQHandler(void)
{
dcd_fs_irqHandler();
}
#else
#error Which IRQ handler do you need?
#error Which IRQ handler do you need?
#endif
#endif
src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+250 -142
View File
@@ -41,51 +41,58 @@
#ifndef PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_
#define PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_
#if defined(STM32F042x6) | \
defined(STM32F070x6) | defined(STM32F070xB) | \
defined(STM32F072xB) | \
#if defined(STM32F042x6) || \
defined(STM32F070x6) || defined(STM32F070xB) || \
defined(STM32F072xB) || \
defined(STM32F078xx)
#include "stm32f0xx.h"
#define PMA_LENGTH 1024
// F0x2 models are crystal-less
// All have internal D+ pull-up
// 070RB: 2 x 16 bits/word memory LPM Support, BCD Support
// PMA dedicated to USB (no sharing with CAN)
#elif defined(STM32F102x6) | defined(STM32F102x6) | \
defined(STM32F103x6) | defined(STM32F103xB) | \
defined(STM32F103xE) | defined(STM32F103xB)
#include "stm32f1xx.h"
#define PMA_LENGTH 512u
// NO internal Pull-ups
// *B, and *C: 2 x 16 bits/word
#error The F102/F103 driver is expected not to work, but it might? Try it?
#include "stm32f0xx.h"
#define PMA_LENGTH (1024u)
// F0x2 models are crystal-less
// All have internal D+ pull-up
// 070RB: 2 x 16 bits/word memory LPM Support, BCD Support
// PMA dedicated to USB (no sharing with CAN)
#elif defined(STM32F302xB) | defined(STM32F302xC) | \
defined(STM32F303xB) | defined(STM32F303xC) | \
#elif defined(STM32F1_FSDEV)
#include "stm32f1xx.h"
#define PMA_LENGTH (512u)
// NO internal Pull-ups
// *B, and *C: 2 x 16 bits/word
// F1 names this differently from the rest
#define USB_CNTR_LPMODE USB_CNTR_LP_MODE
#elif defined(STM32F302xB) || defined(STM32F302xC) || \
defined(STM32F303xB) || defined(STM32F303xC) || \
defined(STM32F373xC)
#include "stm32f3xx.h"
#define PMA_LENGTH 512u
// NO internal Pull-ups
// *B, and *C: 1 x 16 bits/word
// PMA dedicated to USB (no sharing with CAN)
#elif defined(STM32F302x6) | defined(STM32F302x8) | \
defined(STM32F302xD) | defined(STM32F302xE) | \
defined(STM32F303xD) | defined(STM32F303xE) | \
#include "stm32f3xx.h"
#define PMA_LENGTH 1024u
// NO internal Pull-ups
// *6, *8, *D, and *E: 2 x 16 bits/word LPM Support
// When CAN clock is enabled, USB can use first 768 bytes ONLY.
#include "stm32f3xx.h"
#define PMA_LENGTH (512u)
// NO internal Pull-ups
// *B, and *C: 1 x 16 bits/word
// PMA dedicated to USB (no sharing with CAN)
#elif defined(STM32F302x6) || defined(STM32F302x8) || \
defined(STM32F302xD) || defined(STM32F302xE) || \
defined(STM32F303xD) || defined(STM32F303xE)
#include "stm32f3xx.h"
#define PMA_LENGTH (1024u)
// NO internal Pull-ups
// *6, *8, *D, and *E: 2 x 16 bits/word LPM Support
// When CAN clock is enabled, USB can use first 768 bytes ONLY.
#elif CFG_TUSB_MCU == OPT_MCU_STM32L0
#include "stm32l0xx.h"
#define PMA_LENGTH (1024u)
#else
#error You are using an untested or unimplemented STM32 variant. Please update the driver.
// This includes L0x2, L0x3, L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4
#error You are using an untested or unimplemented STM32 variant. Please update the driver.
// This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4
#endif
// For purposes of accessing the packet
#if ((PMA_LENGTH) == 512u)
# define PMA_STRIDE (2u)
#define PMA_STRIDE (2u)
#elif ((PMA_LENGTH) == 1024u)
# define PMA_STRIDE (1u)
#define PMA_STRIDE (1u)
#endif
// And for type-safety create a new macro for the volatile address of PMAADDR
@@ -93,32 +100,75 @@
// Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden)
static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
/* SetENDPOINT */
#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*((__IO uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue))
/* GetENDPOINT */
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*((__IO uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U)))))
#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
(((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & ((uint32_t)(USB_EP_T_MASK))) | ((uint32_t)(wType))) | USB_EP_CTR_RX | USB_EP_CTR_TX)))
#define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD)
// prototypes
static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);
static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);
static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue);
/* SetENDPOINT */
static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue)
{
__O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpNum*2u);
*reg = (uint16_t)wRegValue;
}
/* GetENDPOINT */
static inline uint16_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpNum) {
__I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpNum*2u);
return *reg;
}
static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wType)
{
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
regVal &= (uint32_t)USB_EP_T_MASK;
regVal |= wType;
regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; // These clear on write0, so must set high
pcd_set_endpoint(USBx, bEpNum, regVal);
}
static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpNum)
{
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
regVal &= USB_EP_T_FIELD;
return regVal;
}
/**
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))
static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum)
{
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
regVal &= 0x7FFFu & USB_EPREG_MASK;
pcd_set_endpoint(USBx, bEpNum, regVal);
}
static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum)
{
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
regVal &= regVal & 0xFF7FU & USB_EPREG_MASK;
pcd_set_endpoint(USBx, bEpNum,regVal);
}
/**
* @brief gets counter of the tx buffer.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval Counter value
*/
#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT_PTR((USBx), (bEpNum))) & 0x3ffU)
#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT_PTR((USBx), (bEpNum))) & 0x3ffU)
static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpNum)
{
__I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpNum);
return *regPtr & 0x3ffU;
}
static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum)
{
__I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpNum);
return *regPtr & 0x3ffU;
}
/**
* @brief Sets counter of rx buffer with no. of blocks.
@@ -127,38 +177,30 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
* @param wNBlocks no. of Blocks.
* @retval None
*/
#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
(wNBlocks) = (uint32_t)((wCount) >> 5U);\
if(((wCount) & 0x1fU) == 0U)\
{ \
(wNBlocks)--;\
} \
*pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | (uint16_t)0x8000U); \
}/* PCD_CALC_BLK32 */
#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
(wNBlocks) = (uint32_t)((wCount) >> 1U); \
if(((wCount) & 0x1U) != 0U)\
{ \
(wNBlocks)++;\
} \
*pdwReg = (uint16_t)((wNBlocks) << 10U);\
}/* PCD_CALC_BLK2 */
#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
uint32_t wNBlocks;\
if((wCount) > 62U) \
{ \
PCD_CALC_BLK32((dwReg),(wCount),wNBlocks) \
} \
else \
{ \
PCD_CALC_BLK2((dwReg),(wCount),wNBlocks) \
} \
}/* PCD_SET_EP_CNT_RX_REG */
static inline void pcd_set_ep_cnt_rx_reg(__O uint16_t * pdwReg, size_t wCount) {
uint32_t wNBlocks;
if(wCount > 62u)
{
wNBlocks = wCount >> 5u;
if((wCount & 0x1fU) == 0u)
{
wNBlocks--;
}
wNBlocks = wNBlocks << 10u;
wNBlocks |= 0x8000u; // Mark block size as 32byte
*pdwReg = (uint16_t)wNBlocks;
}
else
{
wNBlocks = wCount >> 1u;
if((wCount & 0x1U) != 0u)
{
wNBlocks++;
}
*pdwReg = (uint16_t)((wNBlocks) << 10u);
}
}
/**
@@ -168,23 +210,52 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
* @param bAddr Address.
* @retval None
*/
#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
USB_EP_CTR_RX|USB_EP_CTR_TX|(((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK) | (bAddr))
static inline void pcd_set_ep_address(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t bAddr)
{
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
regVal &= USB_EPREG_MASK;
regVal |= bAddr;
regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
pcd_set_endpoint(USBx, bEpNum,regVal);
}
#define PCD_BTABLE_WORD_PTR(USBx,x) (&(pma[PMA_STRIDE*((((USBx)->BTABLE)>>1) + x)]))
static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x)
{
size_t total_word_offset = (((USBx)->BTABLE)>>1) + x;
total_word_offset *= PMA_STRIDE;
return &(pma[total_word_offset]);
}
// Pointers to the PMA table entries (using the ARM address space)
#define PCD_EP_TX_ADDRESS_PTR(USBx, bEpNum) (PCD_BTABLE_WORD_PTR(USBx,(bEpNum)*4u + 0u))
#define PCD_EP_TX_CNT_PTR(USBx, bEpNum) (PCD_BTABLE_WORD_PTR(USBx,(bEpNum)*4u + 1u))
static inline __IO uint16_t* pcd_ep_tx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
{
return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 0u);
}
static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
{
return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 1u);
}
#define PCD_EP_RX_ADDRESS_PTR(USBx, bEpNum) (PCD_BTABLE_WORD_PTR(USBx,(bEpNum)*4u + 2u))
#define PCD_EP_RX_CNT_PTR(USBx, bEpNum) (PCD_BTABLE_WORD_PTR(USBx,(bEpNum)*4u + 3u))
static inline __IO uint16_t* pcd_ep_rx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
{
return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 2u);
}
#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT_PTR((USBx), (bEpNum)) = (wCount))
#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) do {\
__IO uint16_t *pdwReg =PCD_EP_RX_CNT_PTR((USBx),(bEpNum)); \
PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
} while(0)
static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
{
return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 3u);
}
static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount)
{
*pcd_ep_tx_cnt_ptr(USBx, bEpNum) = (uint16_t)wCount;
}
static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount)
{
__IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpNum));
pcd_set_ep_cnt_rx_reg(pdwReg, wCount);
}
/**
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
@@ -193,21 +264,24 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
* @param wState new state
* @retval None
*/
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
\
_wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_DTOGMASK);\
/* toggle first bit ? */ \
if((USB_EPTX_DTOG1 & (wState))!= 0U)\
{ \
_wRegVal ^=(uint16_t) USB_EPTX_DTOG1; \
} \
/* toggle second bit ? */ \
if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
{ \
_wRegVal ^=(uint16_t) USB_EPTX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX));\
} /* PCD_SET_EP_TX_STATUS */
static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wState)
{
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
regVal &= USB_EPTX_DTOGMASK;
/* toggle first bit ? */
if((USB_EPTX_DTOG1 & (wState))!= 0U)
{
regVal ^= USB_EPTX_DTOG1;
}
/* toggle second bit ? */
if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U)
{
regVal ^= USB_EPTX_DTOG2;
}
regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
pcd_set_endpoint(USBx, bEpNum, regVal);
} /* pcd_set_ep_tx_status */
/**
* @brief sets the status for rx transfer (bits STAT_TX[1:0])
@@ -216,22 +290,25 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
* @param wState new state
* @retval None
*/
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
register uint16_t _wRegVal; \
\
_wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_DTOGMASK);\
/* toggle first bit ? */ \
if((USB_EPRX_DTOG1 & (wState))!= 0U) \
{ \
_wRegVal ^= (uint16_t) USB_EPRX_DTOG1; \
} \
/* toggle second bit ? */ \
if((USB_EPRX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
{ \
_wRegVal ^= (uint16_t) USB_EPRX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
} /* PCD_SET_EP_RX_STATUS */
static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wState)
{
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
regVal &= USB_EPRX_DTOGMASK;
/* toggle first bit ? */
if((USB_EPRX_DTOG1 & wState)!= 0U)
{
regVal ^= USB_EPRX_DTOG1;
}
/* toggle second bit ? */
if((USB_EPRX_DTOG2 & wState)!= 0U)
{
regVal ^= USB_EPRX_DTOG2;
}
regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
pcd_set_endpoint(USBx, bEpNum, regVal);
} /* pcd_set_ep_rx_status */
/**
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
@@ -239,10 +316,21 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
static inline void pcd_rx_dtog(USB_TypeDef * USBx, uint32_t bEpNum)
{
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
regVal &= USB_EPREG_MASK;
regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX;
pcd_set_endpoint(USBx, bEpNum, regVal);
}
static inline void pcd_tx_dtog(USB_TypeDef * USBx, uint32_t bEpNum)
{
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
regVal &= USB_EPREG_MASK;
regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX;
pcd_set_endpoint(USBx, bEpNum, regVal);
}
/**
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
@@ -250,14 +338,24 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\
{ \
PCD_RX_DTOG((USBx),(bEpNum));\
}
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_TX) != 0)\
{\
PCD_TX_DTOG((USBx),(bEpNum));\
}
static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx, uint32_t bEpNum)
{
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
if((regVal & USB_EP_DTOG_RX) != 0)
{
pcd_rx_dtog(USBx,bEpNum);
}
}
static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx, uint32_t bEpNum)
{
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
if((regVal & USB_EP_DTOG_TX) != 0)
{
pcd_tx_dtog(USBx,bEpNum);
}
}
/**
* @brief set & clear EP_KIND bit.
@@ -265,14 +363,22 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
(USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) | USB_EP_KIND) & USB_EPREG_MASK))))
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
(USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPKIND_MASK)))))
#define EPREG(n) (((__IO uint16_t*)USB_BASE)[n*2])
static inline void pcd_set_ep_kind(USB_TypeDef * USBx, uint32_t bEpNum)
{
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
regVal |= USB_EP_KIND;
regVal &= USB_EPREG_MASK;
regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
pcd_set_endpoint(USBx, bEpNum, regVal);
}
static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpNum)
{
uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
regVal &= USB_EPKIND_MASK;
regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
pcd_set_endpoint(USBx, bEpNum, regVal);
}
// This checks if the device has "LPM"
#if defined(USB_ISTR_L1REQ)
@@ -284,5 +390,7 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
#define USB_ISTR_ALL_EVENTS (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_WKUP | USB_ISTR_SUSP | \
USB_ISTR_RESET | USB_ISTR_SOF | USB_ISTR_ESOF | USB_ISTR_L1REQ_FORCED )
// Number of endpoints in hardware
#define STFSDEV_EP_COUNT (8u)
#endif /* PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ */
src/portable/st/synopsys/dcd_synopsys.c
+49 -26
View File
@@ -27,29 +27,47 @@
#include "tusb_option.h"
#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_STM32F4 || \
CFG_TUSB_MCU == OPT_MCU_STM32H7 || \
CFG_TUSB_MCU == OPT_MCU_STM32F7)
#if defined (STM32L475xx) || defined (STM32L476xx) || \
defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \
defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define STM32L4_SYNOPSYS
#endif
#if TUSB_OPT_DEVICE_ENABLED && \
( CFG_TUSB_MCU == OPT_MCU_STM32F2 || \
CFG_TUSB_MCU == OPT_MCU_STM32F4 || \
CFG_TUSB_MCU == OPT_MCU_STM32F7 || \
CFG_TUSB_MCU == OPT_MCU_STM32H7 || \
(CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)) \
)
// TODO Support OTG_HS
// EP_MAX : Max number of bi-directional endpoints including EP0
// EP_FIFO_SIZE : Size of dedicated USB SRAM
#if CFG_TUSB_MCU == OPT_MCU_STM32F4
#if CFG_TUSB_MCU == OPT_MCU_STM32F2
#include "stm32f2xx.h"
#define EP_MAX USB_OTG_FS_MAX_IN_ENDPOINTS
#define EP_FIFO_SIZE USB_OTG_FS_TOTAL_FIFO_SIZE
#elif CFG_TUSB_MCU == OPT_MCU_STM32F4
#include "stm32f4xx.h"
#define EP_MAX USB_OTG_FS_MAX_IN_ENDPOINTS
#define EP_FIFO_SIZE USB_OTG_FS_TOTAL_FIFO_SIZE
#define EP_MAX USB_OTG_FS_MAX_IN_ENDPOINTS
#define EP_FIFO_SIZE USB_OTG_FS_TOTAL_FIFO_SIZE
#elif CFG_TUSB_MCU == OPT_MCU_STM32H7
#include "stm32h7xx.h"
#define EP_MAX 9
#define EP_FIFO_SIZE 4096
#define EP_MAX 9
#define EP_FIFO_SIZE 4096
// TODO The official name of the USB FS peripheral on H7 is "USB2_OTG_FS".
#else
#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
#include "stm32f7xx.h"
#define EP_MAX 6
#define EP_FIFO_SIZE 1280
#define EP_MAX 6
#define EP_FIFO_SIZE 1280
#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
#include "stm32l4xx.h"
#define EP_MAX 6
#define EP_FIFO_SIZE 1280
#else
#error "Unsupported MCUs"
#endif
#include "device/dcd.h"
@@ -57,10 +75,10 @@
/*------------------------------------------------------------------*/
/* MACRO TYPEDEF CONSTANT ENUM
*------------------------------------------------------------------*/
#define DEVICE_BASE (USB_OTG_DeviceTypeDef *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_DEVICE_BASE)
#define OUT_EP_BASE (USB_OTG_OUTEndpointTypeDef *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_OUT_ENDPOINT_BASE)
#define IN_EP_BASE (USB_OTG_INEndpointTypeDef *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_IN_ENDPOINT_BASE)
#define FIFO_BASE(_x) (volatile uint32_t *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE)
#define DEVICE_BASE (USB_OTG_DeviceTypeDef *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_DEVICE_BASE)
#define OUT_EP_BASE (USB_OTG_OUTEndpointTypeDef *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_OUT_ENDPOINT_BASE)
#define IN_EP_BASE (USB_OTG_INEndpointTypeDef *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_IN_ENDPOINT_BASE)
#define FIFO_BASE(_x) ((volatile uint32_t *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE))
static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
static uint8_t _setup_offs; // We store up to 3 setup packets.
@@ -251,20 +269,21 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
// Unsupported endpoint numbers/size.
if((desc_edpt->wMaxPacketSize.size > 64) || (epnum > EP_MAX)) {
return false;
}
TU_ASSERT(desc_edpt->wMaxPacketSize.size <= 64);
TU_ASSERT(epnum < EP_MAX);
xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
xfer->max_size = desc_edpt->wMaxPacketSize.size;
if(dir == TUSB_DIR_OUT) {
if(dir == TUSB_DIR_OUT)
{
out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) | \
desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos | \
desc_edpt->wMaxPacketSize.size << USB_OTG_DOEPCTL_MPSIZ_Pos;
dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum));
} else {
}
else
{
// "USB Data FIFOs" section in reference manual
// Peripheral FIFO architecture
//
@@ -286,18 +305,22 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
// Since OUT FIFO = GRXFSIZ, FIFO 0 = 16, for simplicity, we equally allocated for the rest of endpoints
// - Size : (FIFO_SIZE/4 - GRXFSIZ - 16) / (EP_MAX-1)
// - Offset: GRXFSIZ + 16 + Size*(epnum-1)
// - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) | \
(epnum - 1) << USB_OTG_DIEPCTL_TXFNUM_Pos | \
epnum << USB_OTG_DIEPCTL_TXFNUM_Pos | \
desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos | \
(desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) | \
desc_edpt->wMaxPacketSize.size << USB_OTG_DIEPCTL_MPSIZ_Pos;
dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum));
// Both TXFD and TXSA are in unit of 32-bit words
// Both TXFD and TXSA are in unit of 32-bit words.
// IN FIFO 0 was configured during enumeration, hence the "+ 16".
uint16_t const allocated_size = (USB_OTG_FS->GRXFSIZ & 0x0000ffff) + 16;
uint16_t const fifo_size = (EP_FIFO_SIZE/4 - allocated_size) / (EP_MAX-1);
uint32_t const fifo_offset = allocated_size + fifo_size*(epnum-1);
// DIEPTXF starts at FIFO #1.
USB_OTG_FS->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | fifo_offset;
}