update dwc int enable/disable
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@@ -32,26 +32,38 @@
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#define __NOP() __asm volatile ("nop")
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// These numbers are the same for the whole GD32VF103 family.
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#define RHPORT_IRQn 86
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#define DWC2_REG_BASE 0x50000000UL
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#define EP_MAX 4
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#define EP_FIFO_SIZE 1280
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#define DWC2_REG_BASE 0x50000000UL
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#define RHPORT_IRQn 86
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// The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local
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// Interrupt Controller by Nuclei. It is nearly API compatible to the
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// NVIC used by ARM MCUs.
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#define ECLIC_INTERRUPT_ENABLE_BASE 0xD2001001UL
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#define NVIC_EnableIRQ __eclic_enable_interrupt
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#define NVIC_DisableIRQ __eclic_disable_interrupt
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TU_ATTR_ALWAYS_INLINE
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static inline void __eclic_enable_interrupt (uint32_t irq) {
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*(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 1;
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}
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TU_ATTR_ALWAYS_INLINE
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static inline void __eclic_disable_interrupt (uint32_t irq){
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*(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 0;
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}
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TU_ATTR_ALWAYS_INLINE
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static inline void dcd_dwc2_int_enable(uint8_t rhport)
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{
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(void) rhport;
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__eclic_enable_interrupt(RHPORT_IRQn);
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}
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TU_ATTR_ALWAYS_INLINE
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static inline void dcd_dwc2_int_disable (uint8_t rhport)
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{
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(void) rhport;
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__eclic_disable_interrupt(RHPORT_IRQn);
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}
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#endif /* DWC2_GD32_H_ */
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