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cdc_usbserial

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Jesus
2022-10-15 18:48:02 +02:00
parent b624664f52
commit 7441c5a4b2
21 changed files with 1865 additions and 3 deletions
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hw/bsp/samd21/family.c
+30
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@@ -182,6 +182,36 @@ static void uart_init(void)
SERCOM0->USART.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
while(SERCOM0->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
#endif
#if UART_SERCOM == 2
gpio_set_pin_function(PIN_PA14, PINMUX_PA14C_SERCOM2_PAD2);
gpio_set_pin_function(PIN_PA15, PINMUX_PA15C_SERCOM2_PAD3);
// setup clock (48MHz)
_pm_enable_bus_clock(PM_BUS_APBC, SERCOM2);
_gclk_enable_channel(SERCOM2_GCLK_ID_CORE, GCLK_CLKCTRL_GEN_GCLK0_Val);
SERCOM2->USART.CTRLA.bit.SWRST = 1; /* reset SERCOM & enable config */
while(SERCOM2->USART.SYNCBUSY.bit.SWRST);
SERCOM2->USART.CTRLA.reg = /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */
SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
// SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */
SERCOM_USART_CTRLA_DORD | /* LSB first */
SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */
SERCOM_USART_CTRLA_RXPO(3) | /* pad 3 */
SERCOM_USART_CTRLA_TXPO(1); /* pad 2 */
SERCOM2->USART.CTRLB.reg =
SERCOM_USART_CTRLB_TXEN | /* tx enabled */
SERCOM_USART_CTRLB_RXEN; /* rx enabled */
SERCOM2->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(0) | SERCOM_USART_BAUD_FRAC_BAUD(26);
SERCOM2->USART.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
while(SERCOM2->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
#endif
}
static inline void uart_send_buffer(uint8_t const *text, size_t len)