able to get pass enumeration

hw/mcu/nordic/nrf52/tusb_port/dcd_nrf52.c

@@ -48,10 +48,20 @@
 /*------------------------------------------------------------------*/
 /* MACRO TYPEDEF CONSTANT ENUM
  *------------------------------------------------------------------*/
+enum { MAX_PACKET_SIZE = 64 };
 
 /*------------------------------------------------------------------*/
 /* VARIABLE DECLARATION
  *------------------------------------------------------------------*/
+static struct
+{
+  struct
+  {
+    uint8_t* buffer;
+    uint16_t xfer_len;
+    uint8_t  dir;
+  }control;
+}_dcd_data;
 
 /*------------------------------------------------------------------*/
 /* Controller API
@@ -100,7 +110,7 @@ static void power_usb_event_handler(nrf_drv_power_usb_evt_t event)
         nrf_usbd_enable();
 
         // Enable HFCLK
-        nrf_drv_clock_handler_item_t clock_handler_item =
+        static nrf_drv_clock_handler_item_t clock_handler_item =
         {
             .event_handler = hfclk_ready
         };
@@ -128,8 +138,8 @@ static void power_usb_event_handler(nrf_drv_power_usb_evt_t event)
       nrf_usbd_isosplit_set(NRF_USBD_ISOSPLIT_Half);
 
       // Enable interrupt
-      NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk | USBD_INTEN_STARTED_Msk |
+      NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk | /*USBD_INTEN_STARTED_Msk |*/
-          USBD_INTEN_ENDEPIN0_Msk | USBD_INTEN_EP0DATADONE_Msk | USBD_INTEN_ENDEPOUT0_Msk | USBD_INTEN_EP0SETUP_Msk |
+          /*USBD_INTEN_ENDEPIN0_Msk |*/ USBD_INTEN_EP0DATADONE_Msk | USBD_INTEN_ENDEPOUT0_Msk | USBD_INTEN_EP0SETUP_Msk |
           USBD_INTEN_USBEVENT_Msk | USBD_INTEN_EPDATA_Msk | USBD_INTEN_ACCESSFAULT_Msk;
       //USBD_INTEN_SOF_Msk
 
@@ -188,7 +198,8 @@ void tusb_dcd_disconnect (uint8_t port)
 }
 void tusb_dcd_set_address (uint8_t port, uint8_t dev_addr)
 {
-
+  (void) port;
+  // address is automatically update by hw controller
 }
 void tusb_dcd_set_config (uint8_t port, uint8_t config_num)
 {
@@ -198,13 +209,62 @@ void tusb_dcd_set_config (uint8_t port, uint8_t config_num)
 /*------------------------------------------------------------------*/
 /* Control
  *------------------------------------------------------------------*/
-bool tusb_dcd_control_xfer (uint8_t port, tusb_dir_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
+
+static void control_xact_start(void)
 {
+  uint8_t xact_len = min16_of(_dcd_data.control.xfer_len, MAX_PACKET_SIZE);
+
+  if ( _dcd_data.control.dir == TUSB_DIR_OUT )
+  {
+
+  }else
+  {
+    // Each transaction is up to 64 bytes
+    NRF_USBD->EPIN[0].PTR        = (uint32_t) _dcd_data.control.buffer;
+    NRF_USBD->EPIN[0].MAXCNT     = xact_len;
+    NRF_USBD->TASKS_STARTEPIN[0] = 1;
+
+    _dcd_data.control.buffer   += xact_len;
+    _dcd_data.control.xfer_len -= xact_len;
+  }
+}
+
+static void control_xact_done(void)
+{
+  if ( _dcd_data.control.xfer_len > 0 )
+  {
+    control_xact_start();
+  }else
+  {
+    tusb_dcd_xfer_complete(0, 0, 0, true);
+  }
+}
+
+
+bool tusb_dcd_control_xfer (uint8_t port, tusb_dir_t dir, uint8_t * buffer, uint16_t length, bool int_on_complete)
+{
+  (void) port;
+
+  if ( length )
+  {
+    // Data Phase
+    _dcd_data.control.xfer_len = length;
+    _dcd_data.control.buffer   = buffer;
+    _dcd_data.control.dir      = (uint8_t) dir;
+
+    control_xact_start();
+  }else
+  {
+    // Status Phase
+    NRF_USBD->TASKS_EP0STATUS = 1;
+  }
+
   return true;
 }
 void tusb_dcd_control_stall (uint8_t port)
 {
-
+  (void) port;
+  NRF_USBD->TASKS_EP0STALL = 1;
 }
 
 /*------------------------------------------------------------------*/
@@ -254,6 +314,8 @@ void bus_reset(void)
 
   NRF_USBD->TASKS_STARTISOIN  = 0;
   NRF_USBD->TASKS_STARTISOOUT = 0;
+
+  varclr(&_dcd_data);
 }
 
 void USBD_IRQHandler(void)
@@ -382,6 +444,12 @@ void USBD_IRQHandler(void)
         NRF_USBD->WINDEXL, NRF_USBD->WINDEXH, NRF_USBD->WLENGTHL, NRF_USBD->WLENGTHH
     };
 
+    //NRF_USBD->TASKS_EP0STALL = 0; // clear stall upon receive new setup
     tusb_dcd_setup_received(0, setup);
   }
+
+  if ( int_status & USBD_INTEN_EP0DATADONE_Msk )
+  {
+    control_xact_done();
+  }
 }