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able to build with host msc

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This commit is contained in:
hathach
2018-12-07 12:56:42 +07:00
parent 9478c647e3
commit 89820a36a1
10 changed files with 202 additions and 78 deletions
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src/host/ehci/ehci.c
+2 -2
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@@ -294,7 +294,7 @@ tusb_error_t hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
return TUSB_ERROR_NONE;
}
tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[])
bool hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[])
{
ehci_qhd_t * const p_qhd = get_control_qhd(dev_addr);
@@ -332,7 +332,7 @@ tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t con
p_qhd->qtd_overlay.next.address = (uint32_t) p_setup;
return TUSB_ERROR_NONE;
return true;
}
tusb_error_t hcd_pipe_control_close(uint8_t dev_addr)
src/host/hcd.h
+1 -1
View File
@@ -128,7 +128,7 @@ void hcd_event_handler(hcd_event_t const* event, bool in_isr);
//--------------------------------------------------------------------+
// TODO control xfer should be used via usbh layer
tusb_error_t hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size) ATTR_WARN_UNUSED_RESULT;
tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[]) ATTR_WARN_UNUSED_RESULT;
bool hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[]) ATTR_WARN_UNUSED_RESULT;
tusb_error_t hcd_pipe_control_close(uint8_t dev_addr) ATTR_WARN_UNUSED_RESULT;
pipe_handle_t hcd_pipe_open(uint8_t dev_addr, tusb_desc_endpoint_t const * endpoint_desc, uint8_t class_code) ATTR_WARN_UNUSED_RESULT;
src/host/ohci/ohci.c
+2 -2
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@@ -291,7 +291,7 @@ tusb_error_t hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
return TUSB_ERROR_NONE;
}
tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[])
bool hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[])
{
ohci_ed_t* const p_ed = &ohci_data.control[dev_addr].ed;
@@ -331,7 +331,7 @@ tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t con
OHCI_REG->command_status_bit.control_list_filled = 1;
return TUSB_ERROR_NONE;
return true;
}
tusb_error_t hcd_pipe_control_close(uint8_t dev_addr)
src/host/usbh.c
+1 -1
View File
@@ -199,7 +199,7 @@ bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t* request, uint8
dev->control.request = *request;
dev->control.pipe_status = 0;
TU_ASSERT_ERR(hcd_pipe_control_xfer(dev_addr, &dev->control.request, data), false);
TU_ASSERT(hcd_pipe_control_xfer(dev_addr, &dev->control.request, data));
TU_ASSERT(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL));
osal_mutex_unlock(dev->control.mutex_hdl);