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able to build with host msc

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This commit is contained in:
hathach
2018-12-07 12:56:42 +07:00
parent 9478c647e3
commit 89820a36a1
10 changed files with 202 additions and 78 deletions
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tests/lpc18xx_43xx/test/host/ehci/test_ehci_usbh_hcd_integration.c
+2 -2
View File
@@ -100,7 +100,7 @@ void test_addr0_control_close(void)
TEST_ASSERT_STATUS( hcd_pipe_control_open(dev_addr, control_max_packet_size) );
TEST_ASSERT_STATUS( hcd_pipe_control_xfer(dev_addr,
TEST_ASSERT( hcd_pipe_control_xfer(dev_addr,
&(tusb_control_request_t) {
.bmRequestType_bit = { .direction = TUSB_DIR_HOST_TO_DEV, .type = TUSB_REQ_TYPE_STANDARD, .recipient = TUSB_REQ_RECIPIENT_DEVICE },
.bRequest = TUSB_REQ_SET_ADDRESS,
@@ -126,7 +126,7 @@ void test_isr_disconnect_then_async_advance_control_pipe(void)
{
TEST_ASSERT_STATUS( hcd_pipe_control_open(dev_addr, control_max_packet_size) );
TEST_ASSERT_STATUS( hcd_pipe_control_xfer(dev_addr,
TEST_ASSERT( hcd_pipe_control_xfer(dev_addr,
&(tusb_control_request_t) {
.bmRequestType_bit = { .direction = TUSB_DIR_HOST_TO_DEV, .type = TUSB_REQ_TYPE_STANDARD, .recipient = TUSB_REQ_RECIPIENT_DEVICE },
.bRequest = TUSB_REQ_SET_ADDRESS,
tests/lpc18xx_43xx/test/host/ehci/test_pipe_control_xfer.c
+6 -6
View File
@@ -149,7 +149,7 @@ void test_control_addr0_xfer_get_check_qhd_qtd_mapping(void)
TEST_ASSERT_STATUS( hcd_pipe_control_open(dev_addr, control_max_packet_size) );
//------------- Code Under TEST -------------//
TEST_ASSERT_STATUS( hcd_pipe_control_xfer(dev_addr, &request_get_dev_desc, xfer_data) );
TEST_ASSERT( hcd_pipe_control_xfer(dev_addr, &request_get_dev_desc, xfer_data) );
p_setup = &ehci_data.addr0_qtd[0];
p_data = &ehci_data.addr0_qtd[1];
@@ -171,7 +171,7 @@ void test_control_addr0_xfer_get_check_qhd_qtd_mapping(void)
void test_control_xfer_get(void)
{
//------------- Code Under TEST -------------//
TEST_ASSERT_STATUS( hcd_pipe_control_xfer(dev_addr, &request_get_dev_desc, xfer_data) );
TEST_ASSERT( hcd_pipe_control_xfer(dev_addr, &request_get_dev_desc, xfer_data) );
TEST_ASSERT_EQUAL_HEX( p_setup, p_control_qhd->qtd_overlay.next.address );
TEST_ASSERT_EQUAL_HEX( p_setup , p_control_qhd->p_qtd_list_head);
@@ -206,7 +206,7 @@ void test_control_xfer_get(void)
void test_control_xfer_set(void)
{
//------------- Code Under TEST -------------//
TEST_ASSERT_STATUS( hcd_pipe_control_xfer(dev_addr, &request_set_dev_addr, xfer_data) );
TEST_ASSERT( hcd_pipe_control_xfer(dev_addr, &request_set_dev_addr, xfer_data) );
TEST_ASSERT_EQUAL_HEX( p_setup, p_control_qhd->qtd_overlay.next.address );
TEST_ASSERT_EQUAL_HEX( p_setup , p_control_qhd->p_qtd_list_head);
@@ -226,7 +226,7 @@ void test_control_xfer_set(void)
void test_control_xfer_complete_isr(void)
{
TEST_ASSERT_STATUS( hcd_pipe_control_xfer(dev_addr, &request_get_dev_desc, xfer_data) );
TEST_ASSERT( hcd_pipe_control_xfer(dev_addr, &request_get_dev_desc, xfer_data) );
usbh_xfer_isr_Expect(((pipe_handle_t){.dev_addr = dev_addr}), 0, XFER_RESULT_SUCCESS, 18);
@@ -245,7 +245,7 @@ void test_control_xfer_complete_isr(void)
void test_control_xfer_error_isr(void)
{
TEST_ASSERT_STATUS( hcd_pipe_control_xfer(dev_addr, &request_get_dev_desc, xfer_data) );
TEST_ASSERT( hcd_pipe_control_xfer(dev_addr, &request_get_dev_desc, xfer_data) );
usbh_xfer_isr_Expect(((pipe_handle_t){.dev_addr = dev_addr}), 0, XFER_RESULT_FAILED, 0);
@@ -264,7 +264,7 @@ void test_control_xfer_error_isr(void)
void test_control_xfer_error_stall(void)
{
TEST_ASSERT_STATUS( hcd_pipe_control_xfer(dev_addr, &request_get_dev_desc, xfer_data) );
TEST_ASSERT( hcd_pipe_control_xfer(dev_addr, &request_get_dev_desc, xfer_data) );
usbh_xfer_isr_Expect(((pipe_handle_t){.dev_addr = dev_addr}), 0, XFER_RESULT_STALLED, 0);