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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef _TUSB_DCD_FOMU_H_
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#define _TUSB_DCD_FOMU_H_
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#include "common/tusb_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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// //--------------------------------------------------------------------+
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// // Register Interface
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// //--------------------------------------------------------------------+
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// //------------- USB Interrupt USBIntSt -------------//
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// //enum {
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// // DCD_USB_REQ_LOW_PRIO_MASK = TU_BIT(0),
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// // DCD_USB_REQ_HIGH_PRIO_MASK = TU_BIT(1),
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// // DCD_USB_REQ_DMA_MASK = TU_BIT(2),
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// // DCD_USB_REQ_NEED_CLOCK_MASK = TU_BIT(8),
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// // DCD_USB_REQ_ENABLE_MASK = TU_BIT(31)
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// //};
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// //------------- Device Interrupt USBDevInt -------------//
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// enum {
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// DEV_INT_FRAME_MASK = TU_BIT(0),
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// DEV_INT_ENDPOINT_FAST_MASK = TU_BIT(1),
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// DEV_INT_ENDPOINT_SLOW_MASK = TU_BIT(2),
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// DEV_INT_DEVICE_STATUS_MASK = TU_BIT(3),
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// DEV_INT_COMMAND_CODE_EMPTY_MASK = TU_BIT(4),
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// DEV_INT_COMMAND_DATA_FULL_MASK = TU_BIT(5),
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// DEV_INT_RX_ENDPOINT_PACKET_MASK = TU_BIT(6),
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// DEV_INT_TX_ENDPOINT_PACKET_MASK = TU_BIT(7),
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// DEV_INT_ENDPOINT_REALIZED_MASK = TU_BIT(8),
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// DEV_INT_ERROR_MASK = TU_BIT(9)
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// };
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// //------------- DMA Interrupt USBDMAInt-------------//
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// enum {
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// DMA_INT_END_OF_XFER_MASK = TU_BIT(0),
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// DMA_INT_NEW_DD_REQUEST_MASK = TU_BIT(1),
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// DMA_INT_ERROR_MASK = TU_BIT(2)
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// };
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// //------------- USBCtrl -------------//
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// enum {
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// USBCTRL_READ_ENABLE_MASK = TU_BIT(0),
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// USBCTRL_WRITE_ENABLE_MASK = TU_BIT(1),
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// };
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// //------------- USBRxPLen -------------//
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// enum {
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// USBRXPLEN_PACKET_LENGTH_MASK = (TU_BIT(10)-1),
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// USBRXPLEN_DATA_VALID_MASK = TU_BIT(10),
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// USBRXPLEN_PACKET_READY_MASK = TU_BIT(11),
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// };
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// //------------- SIE Command Code -------------//
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// typedef enum
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// {
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// SIE_CMDPHASE_WRITE = 1,
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// SIE_CMDPHASE_READ = 2,
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// SIE_CMDPHASE_COMMAND = 5
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// } sie_cmdphase_t;
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// enum {
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// // device commands
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// SIE_CMDCODE_SET_ADDRESS = 0xd0,
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// SIE_CMDCODE_CONFIGURE_DEVICE = 0xd8,
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// SIE_CMDCODE_SET_MODE = 0xf3,
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// SIE_CMDCODE_READ_FRAME_NUMBER = 0xf5,
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// SIE_CMDCODE_READ_TEST_REGISTER = 0xfd,
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// SIE_CMDCODE_DEVICE_STATUS = 0xfe,
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// SIE_CMDCODE_GET_ERROR = 0xff,
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// SIE_CMDCODE_READ_ERROR_STATUS = 0xfb,
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// // endpoint commands
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// SIE_CMDCODE_ENDPOINT_SELECT = 0x00, // + endpoint index
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// SIE_CMDCODE_ENDPOINT_SELECT_CLEAR_INTERRUPT = 0x40, // + endpoint index, should use USBEpIntClr instead
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// SIE_CMDCODE_ENDPOINT_SET_STATUS = 0x40, // + endpoint index
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// SIE_CMDCODE_BUFFER_CLEAR = 0xf2,
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// SIE_CMDCODE_BUFFER_VALIDATE = 0xfa
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// };
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// //------------- SIE Device Status (get/set from SIE_CMDCODE_DEVICE_STATUS) -------------//
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// enum {
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// SIE_DEV_STATUS_CONNECT_STATUS_MASK = TU_BIT(0),
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// SIE_DEV_STATUS_CONNECT_CHANGE_MASK = TU_BIT(1),
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// SIE_DEV_STATUS_SUSPEND_MASK = TU_BIT(2),
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// SIE_DEV_STATUS_SUSPEND_CHANGE_MASK = TU_BIT(3),
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// SIE_DEV_STATUS_RESET_MASK = TU_BIT(4)
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// };
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// //------------- SIE Select Endpoint Command -------------//
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// enum {
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// SIE_SELECT_ENDPOINT_FULL_EMPTY_MASK = TU_BIT(0), // 0: empty, 1 full. IN endpoint checks empty, OUT endpoint check full
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// SIE_SELECT_ENDPOINT_STALL_MASK = TU_BIT(1),
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// SIE_SELECT_ENDPOINT_SETUP_RECEIVED_MASK = TU_BIT(2), // clear by SIE_CMDCODE_ENDPOINT_SELECT_CLEAR_INTERRUPT
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// SIE_SELECT_ENDPOINT_PACKET_OVERWRITTEN_MASK = TU_BIT(3), // previous packet is overwritten by a SETUP packet
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// SIE_SELECT_ENDPOINT_NAK_MASK = TU_BIT(4), // last packet response is NAK (auto clear by an ACK)
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// SIE_SELECT_ENDPOINT_BUFFER1_FULL_MASK = TU_BIT(5),
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// SIE_SELECT_ENDPOINT_BUFFER2_FULL_MASK = TU_BIT(6)
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// };
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// typedef enum
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// {
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// SIE_SET_ENDPOINT_STALLED_MASK = TU_BIT(0),
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// SIE_SET_ENDPOINT_DISABLED_MASK = TU_BIT(5),
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// SIE_SET_ENDPOINT_RATE_FEEDBACK_MASK = TU_BIT(6),
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// SIE_SET_ENDPOINT_CONDITION_STALLED_MASK = TU_BIT(7),
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// }sie_endpoint_set_status_mask_t;
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// //------------- DMA Descriptor Status -------------//
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// enum {
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// DD_STATUS_NOT_SERVICED = 0,
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// DD_STATUS_BEING_SERVICED,
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// DD_STATUS_NORMAL,
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// DD_STATUS_DATA_UNDERUN, // short packet
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// DD_STATUS_DATA_OVERRUN,
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// DD_STATUS_SYSTEM_ERROR
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// };
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#ifdef __cplusplus
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}
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#endif
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#endif /* _TUSB_DCD_FOMU_H_ */
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