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clean all IAR ending warning

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This commit is contained in:
hathach
2014-03-12 14:59:57 +07:00
parent bb8602ce41
commit 92d28c96eb
14 changed files with 206 additions and 206 deletions
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demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/src/core_cm3.c
+23 -23
View File
@@ -8,9 +8,9 @@
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -60,7 +60,7 @@ __ASM uint32_t __REV16(uint32_t value)
rev16 r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
/** \brief Reverse byte order in signed short value
@@ -76,7 +76,7 @@ __ASM int32_t __REVSH(int32_t value)
revsh r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
/** \brief Remove the exclusive lock
@@ -89,7 +89,7 @@ __ASM void __CLREX(void)
{
clrex
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
@@ -117,7 +117,7 @@ __ASM uint32_t __get_CONTROL(void)
mrs r0, control
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
/** \brief Set Control Register
@@ -132,7 +132,7 @@ __ASM void __set_CONTROL(uint32_t control)
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
/** \brief Get ISPR Register
@@ -147,7 +147,7 @@ __ASM uint32_t __get_IPSR(void)
mrs r0, ipsr
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
/** \brief Get APSR Register
@@ -162,7 +162,7 @@ __ASM uint32_t __get_APSR(void)
mrs r0, apsr
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
/** \brief Get xPSR Register
@@ -177,7 +177,7 @@ __ASM uint32_t __get_xPSR(void)
mrs r0, xpsr
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
/** \brief Get Process Stack Pointer
@@ -192,7 +192,7 @@ __ASM uint32_t __get_PSP(void)
mrs r0, psp
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
/** \brief Set Process Stack Pointer
@@ -207,7 +207,7 @@ __ASM void __set_PSP(uint32_t topOfProcStack)
msr psp, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
/** \brief Get Main Stack Pointer
@@ -222,7 +222,7 @@ __ASM uint32_t __get_MSP(void)
mrs r0, msp
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
/** \brief Set Main Stack Pointer
@@ -237,7 +237,7 @@ __ASM void __set_MSP(uint32_t mainStackPointer)
msr msp, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
/** \brief Get Base Priority
@@ -252,7 +252,7 @@ __ASM uint32_t __get_BASEPRI(void)
mrs r0, basepri
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
/** \brief Set Base Priority
@@ -267,8 +267,8 @@ __ASM void __set_BASEPRI(uint32_t basePri)
msr basepri, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
@@ -281,7 +281,7 @@ __ASM uint32_t __get_PRIMASK(void)
mrs r0, primask
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
/** \brief Set Priority Mask
@@ -296,8 +296,8 @@ __ASM void __set_PRIMASK(uint32_t priMask)
msr primask, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
/** \brief Get Fault Mask
@@ -311,7 +311,7 @@ __ASM uint32_t __get_FAULTMASK(void)
mrs r0, faultmask
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
/** \brief Set the Fault Mask
@@ -326,7 +326,7 @@ __ASM void __set_FAULTMASK(uint32_t faultMask)
msr faultmask, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#endif /* __ARMCC_VERSION */
demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/src/system_LPC17xx.c
+9 -9
View File
@@ -9,9 +9,9 @@
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -376,7 +376,7 @@
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
@@ -389,7 +389,7 @@
/* F_cco0 = (2 * M * F_in) / N */
#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
#define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N)
#define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N)
#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
/* Determine core clock frequency according to settings */
@@ -398,7 +398,7 @@
#define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
#elif ((CLKSRCSEL_Val & 0x03) == 2)
#define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
#else
#else
#define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
#endif
#else
@@ -428,19 +428,19 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
switch (LPC_SC->CLKSRCSEL & 0x03) {
case 0: /* Int. RC oscillator => PLL0 */
case 3: /* Reserved, default to Int. RC */
SystemCoreClock = (IRC_OSC *
SystemCoreClock = (IRC_OSC *
((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
((LPC_SC->CCLKCFG & 0xFF)+ 1));
break;
case 1: /* Main oscillator => PLL0 */
SystemCoreClock = (OSC_CLK *
SystemCoreClock = (OSC_CLK *
((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
((LPC_SC->CCLKCFG & 0xFF)+ 1));
break;
case 2: /* RTC oscillator => PLL0 */
SystemCoreClock = (RTC_CLK *
SystemCoreClock = (RTC_CLK *
((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
((LPC_SC->CCLKCFG & 0xFF)+ 1));