able to build and run cdc device demo on lpc11uxx

This commit is contained in:
hathach
2013-11-13 12:40:11 +07:00
parent d8f32a79fc
commit 92d9c36dbc
15 changed files with 110 additions and 91 deletions
+2 -2
View File
@@ -121,12 +121,12 @@ tusb_error_t tusbd_hid_mouse_send(uint8_t coreid, hid_mouse_report_t const *p_re
//--------------------------------------------------------------------+
void hidd_init(void)
{
// TODO not implemented yet
}
void hidd_bus_reset(uint8_t coreid)
{
// TODO not implemented yet
}
tusb_error_t hidd_control_request(uint8_t coreid, tusb_control_request_t const * p_request)
+14 -3
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@@ -56,9 +56,10 @@ typedef struct {
endpoint_handle_t edpt_in, edpt_out;
// must be in USB ram
uint8_t max_lun;
msc_cmd_block_wrapper_t cbw;
msc_cmd_status_wrapper_t csw;
ATTR_USB_MIN_ALIGNMENT uint8_t max_lun;
ATTR_USB_MIN_ALIGNMENT msc_cmd_block_wrapper_t cbw;
ATTR_USB_MIN_ALIGNMENT msc_cmd_status_wrapper_t csw;
}mscd_interface_t;
STATIC_VAR mscd_interface_t mscd_data TUSB_CFG_ATTR_USBRAM;
@@ -69,6 +70,16 @@ STATIC_VAR mscd_interface_t mscd_data TUSB_CFG_ATTR_USBRAM;
//--------------------------------------------------------------------+
// USBD-CLASS API
//--------------------------------------------------------------------+
void mscd_init(void)
{
// TODO not implemented
}
void mscd_bus_reset(uint8_t coreid)
{
// TODO not implemented yet
}
tusb_error_t mscd_open(uint8_t coreid, tusb_descriptor_interface_t const * p_interface_desc, uint16_t *p_length)
{
ASSERT( ( MSC_SUBCLASS_SCSI == p_interface_desc->bInterfaceSubClass &&
+2
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@@ -58,6 +58,8 @@ msc_csw_status_t tusbd_msc_scsi_received_isr (uint8_t coreid, uint8_t lun, uint8
//--------------------------------------------------------------------+
#ifdef _TINY_USB_SOURCE_FILE_
void mscd_init(void);
void mscd_bus_reset(uint8_t coreid);
tusb_error_t mscd_open(uint8_t coreid, tusb_descriptor_interface_t const * p_interface_desc, uint16_t *p_length);
tusb_error_t mscd_control_request(uint8_t coreid, tusb_control_request_t const * p_request);
void mscd_isr(endpoint_handle_t edpt_hdl, tusb_event_t event, uint32_t xferred_bytes);
@@ -1,6 +1,6 @@
/**************************************************************************/
/*!
@file dcd_lpc13xx_12adc.c
@file dcd_lpc_11uxx_13uxx.c
@author hathach (tinyusb.org)
@section LICENSE
@@ -38,7 +38,7 @@
#include "tusb_option.h"
#if MODE_DEVICE_SUPPORTED && MCU == MCU_LPC13UXX
#if MODE_DEVICE_SUPPORTED && (MCU == MCU_LPC11UXX || MCU == MCU_LPC13UXX)
#define _TINY_USB_SOURCE_FILE_
//--------------------------------------------------------------------+
@@ -51,7 +51,7 @@
#include "dcd.h"
#include "usbd_dcd.h"
#include "dcd_lpc13uxx.h"
#include "dcd_lpc_11uxx_13uxx.h"
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
@@ -164,7 +164,6 @@ void dcd_controller_set_address(uint8_t coreid, uint8_t dev_addr)
LPC_USB->DEVCMDSTAT |= dev_addr;
}
tusb_error_t dcd_init(void)
{
LPC_USB->EPLISTSTART = (uint32_t) dcd_data.qhd;
@@ -226,7 +225,8 @@ void dcd_isr(uint8_t coreid)
}
LPC_USB->DEVCMDSTAT |= CMDSTAT_MASK_RESET_CHANGE | CMDSTAT_MASK_SUSPEND_CHANGE | CMDSTAT_MASK_CONNECT_CHANGE;
LPC_USB->DEVCMDSTAT |= CMDSTAT_MASK_RESET_CHANGE | CMDSTAT_MASK_CONNECT_CHANGE
/* CMDSTAT_MASK_SUSPEND_CHANGE | */;
}
//------------- Control Endpoint -------------//
@@ -325,8 +325,22 @@ static inline uint8_t edpt_phy2log(uint8_t physical_endpoint)
//--------------------------------------------------------------------+
// BULK/INTERRUPT/ISOCHRONOUS PIPE API
//--------------------------------------------------------------------+
tusb_error_t dcd_pipe_stall(endpoint_handle_t edpt_hdl)
{
ASSERT( !dcd_pipe_is_busy(edpt_hdl), TUSB_ERROR_INTERFACE_IS_BUSY); // endpoint must not in transferring
dcd_data.qhd[edpt_hdl.index][0].stall = 1;
return TUSB_ERROR_NONE;
}
tusb_error_t dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr)
{
uint8_t ep_id = edpt_addr2phy(edpt_addr);
dcd_data.qhd[ep_id][0].stall = 0;
dcd_data.qhd[ep_id][0].toggle_reset = 1;
return TUSB_ERROR_NONE;
}
@@ -371,10 +385,10 @@ bool dcd_pipe_is_busy(endpoint_handle_t edpt_hdl)
// return TUSB_ERROR_NONE;
//}
tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint16_t total_bytes)
{
}
//tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint16_t total_bytes)
//{
//
//}
tusb_error_t dcd_pipe_xfer(endpoint_handle_t edpt_hdl, void* buffer, uint16_t total_bytes, bool int_on_complete)
{
+8
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@@ -124,6 +124,14 @@ tusb_error_t usbd_init (void)
{
ASSERT_STATUS ( dcd_init() );
#if (TUSB_CFG_CONTROLLER_0_MODE & TUSB_MODE_DEVICE)
dcd_controller_connect(0);
#endif
#if (TUSB_CFG_CONTROLLER_1_MODE & TUSB_MODE_DEVICE)
dcd_controller_connect(1);
#endif
for (tusb_std_class_code_t class_code = TUSB_CLASS_AUDIO; class_code <= TUSB_CLASS_AUDIO_VIDEO; class_code++)
{
if ( usbd_class_drivers[class_code].init )
+1
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@@ -51,6 +51,7 @@ tusb_error_t hal_init(void)
address the wrong status in VBUSDebouncing bit in CmdStatus register. */
LPC_IOCON->PIO0_3 &= ~0x1F;
LPC_IOCON->PIO0_3 |= (0x01<<0); /* Secondary function VBUS */
LPC_IOCON->PIO0_6 &= ~0x07;
LPC_IOCON->PIO0_6 |= (0x01<<0); /* Secondary function SoftConn */
+4 -10
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@@ -36,12 +36,6 @@
*/
/**************************************************************************/
/** \file
* \brief TBD
*
* \note TBD
*/
/** \ingroup TBD
* \defgroup TBD
* \brief TBD
@@ -58,15 +52,15 @@
extern "C" {
#endif
static inline void hal_interrupt_enable(uint8_t controller_id)
static inline void hal_interrupt_enable(uint8_t coreid)
{
(void) controller_id; // discard compiler's warning
(void) coreid; // discard compiler's warning
NVIC_EnableIRQ(USB_IRQn);
}
static inline void hal_interrupt_disable(uint8_t controller_id)
static inline void hal_interrupt_disable(uint8_t coreid)
{
(void) controller_id; // discard compiler's warning
(void) coreid; // discard compiler's warning
NVIC_DisableIRQ(USB_IRQn);
}
-3
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@@ -57,9 +57,6 @@ tusb_error_t hal_init(void)
LPC_IOCON->PIO0_6 &= ~0x07;
LPC_IOCON->PIO0_6 |= (0x01<<0); /* Secondary function SoftConn */
dcd_controller_connect(0);
hal_interrupt_enable(0);
return TUSB_ERROR_NONE;
}
-6
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@@ -81,7 +81,6 @@ tusb_error_t hal_init(void)
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL0);
CGU_EnableEntity(CGU_CLKSRC_PLL0, ENABLE); /* Enable PLL after all setting is done */
// reset controller & set role
ASSERT_STATUS( hal_controller_reset(0) );
@@ -93,10 +92,7 @@ tusb_error_t hal_init(void)
#if TUSB_CFG_DEVICE_FULLSPEED // TODO for easy testing
LPC_USB0->PORTSC1_D |= (1<<24); // force full speed
#endif
dcd_controller_connect(0);
#endif
hal_interrupt_enable(0);
#endif
//------------- USB1 -------------//
@@ -114,11 +110,9 @@ tusb_error_t hal_init(void)
LPC_USB1->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
#else // TODO OTG
LPC_USB1->USBMODE_D = LPC43XX_USBMODE_DEVICE;
dcd_controller_connect(1);
#endif
LPC_USB1->PORTSC1_D |= (1<<24); // TODO abtract, force port to fullspeed
hal_interrupt_enable(1);
#endif
return TUSB_ERROR_NONE;
-4
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@@ -78,10 +78,6 @@
#define CAP_MODE_HOST
#endif
#if MCU == MCU_LPC43XX || MCU == MCU_LPC18XX || MCU == MCU_LPC11UXX || MCU == MCU_LPC13UXX
#define CAP_DEVICE_ROMDRIVER
#endif
//--------------------------------------------------------------------+
// Validation
//--------------------------------------------------------------------+
+8
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@@ -52,6 +52,14 @@ tusb_error_t tusb_init(void)
ASSERT_STATUS ( usbd_init() ); // device stack init
#endif
#if (TUSB_CFG_CONTROLLER_0_MODE)
hal_interrupt_enable(0);
#endif
#if (TUSB_CFG_CONTROLLER_1_MODE)
hal_interrupt_enable(1);
#endif
return TUSB_ERROR_NONE;
}
+2 -2
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@@ -51,8 +51,8 @@
/** \defgroup MCU_ MCU Selection
* \brief TUSB_CFG_MCU must be defined to one of these
* @{ */
#define MCU_LPC13UXX 1 ///< NXP LPC13xx 12 bit ADC family with USB on-chip Rom Driver (not supported yet)
#define MCU_LPC13XX_10ADC 2 ///< NXP LPC13xx 10 bit ADC family (not supported yet)
#define MCU_LPC13UXX 1 ///< NXP LPC13xx 12 bit ADC family with USB on-chip Rom Driver (not supported yet)
#define MCU_LPC13XX 2 ///< NXP LPC13xx 10 bit ADC family (not supported yet)
#define MCU_LPC11UXX 3 ///< NXP LPC11Uxx family (not supported yet)
#define MCU_LPC43XX 4 ///< NXP LPC43xx family
#define MCU_LPC18XX 5 ///< NXP LPC18xx family (not supported yet)