refractor
- rename some field in ehci_qhd/qtd_t - code test for open pipe
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@@ -146,7 +146,7 @@ void test_hcd_init_period_list(void)
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TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, framelist[list_idx].type);
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}
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TEST_ASSERT(period_head->smask)
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TEST_ASSERT(period_head->interrupt_smask)
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TEST_ASSERT_TRUE(period_head->next.terminate);
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TEST_ASSERT(period_head->qtd_overlay.halted);
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}
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@@ -101,11 +101,15 @@ void tearDown(void)
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{
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}
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void verify_open_qhd(ehci_qhd_t *p_qhd)
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void verify_open_qhd(ehci_qhd_t *p_qhd, uint8_t endpoint_addr, uint16_t max_packet_size)
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{
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TEST_ASSERT_EQUAL(dev_addr, p_qhd->device_address);
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TEST_ASSERT_FALSE(p_qhd->inactive_next_xact);
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TEST_ASSERT_EQUAL(0, p_qhd->nak_count_reload); // TODO NAK Reload disable
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TEST_ASSERT_EQUAL(endpoint_addr & 0x0F, p_qhd->endpoint_number);
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TEST_ASSERT_EQUAL(usbh_device_info_pool[dev_addr].speed, p_qhd->endpoint_speed);
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TEST_ASSERT_EQUAL(max_packet_size, p_qhd->max_package_size);
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TEST_ASSERT_EQUAL(0, p_qhd->nak_count_reload); // TDD NAK Reload disable
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TEST_ASSERT_EQUAL(hub_addr, p_qhd->hub_address);
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TEST_ASSERT_EQUAL(hub_port, p_qhd->hub_port);
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TEST_ASSERT_EQUAL(1, p_qhd->mult);
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@@ -124,13 +128,11 @@ void verify_open_qhd(ehci_qhd_t *p_qhd)
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//--------------------------------------------------------------------+
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void verify_control_open_qhd(ehci_qhd_t *p_qhd)
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{
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verify_open_qhd(p_qhd);
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verify_open_qhd(p_qhd, 0, control_max_packet_size);
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TEST_ASSERT_EQUAL(control_max_packet_size, p_qhd->max_package_size);
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TEST_ASSERT_EQUAL(0, p_qhd->endpoint_number);
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TEST_ASSERT_EQUAL(1, p_qhd->data_toggle_control);
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TEST_ASSERT_EQUAL(0, p_qhd->smask);
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TEST_ASSERT_EQUAL(0, p_qhd->cmask);
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TEST_ASSERT_EQUAL(0, p_qhd->interrupt_smask);
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TEST_ASSERT_EQUAL(0, p_qhd->non_hs_cmask);
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}
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void test_control_open_addr0_qhd_data(void)
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@@ -139,6 +141,7 @@ void test_control_open_addr0_qhd_data(void)
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ehci_qhd_t * const p_qhd = async_head;
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//------------- Code Under Test -------------//
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hcd_pipe_control_open(dev_addr, control_max_packet_size);
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verify_control_open_qhd(p_qhd);
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@@ -149,6 +152,7 @@ void test_control_open_qhd_data(void)
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{
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ehci_qhd_t * const p_qhd = &ehci_data.device[dev_addr].control.qhd;
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//------------- Code Under TEST -------------//
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hcd_pipe_control_open(dev_addr, control_max_packet_size);
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verify_control_open_qhd(p_qhd);
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@@ -166,9 +170,9 @@ void test_control_open_highspeed(void)
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usbh_device_info_pool[dev_addr].speed = TUSB_SPEED_HIGH;
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//------------- Code Under TEST -------------//
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hcd_pipe_control_open(dev_addr, control_max_packet_size);
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TEST_ASSERT_EQUAL(TUSB_SPEED_HIGH, p_qhd->endpoint_speed);
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TEST_ASSERT_FALSE(p_qhd->non_hs_control_endpoint);
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}
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@@ -178,9 +182,9 @@ void test_control_open_non_highspeed(void)
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usbh_device_info_pool[dev_addr].speed = TUSB_SPEED_FULL;
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//------------- Code Under TEST -------------//
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hcd_pipe_control_open(dev_addr, control_max_packet_size);
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TEST_ASSERT_EQUAL(TUSB_SPEED_FULL, p_qhd->endpoint_speed);
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TEST_ASSERT_TRUE(p_qhd->non_hs_control_endpoint);
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}
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@@ -189,18 +193,15 @@ void test_control_open_non_highspeed(void)
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//--------------------------------------------------------------------+
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void verify_bulk_open_qhd(ehci_qhd_t *p_qhd, tusb_descriptor_endpoint_t const * desc_endpoint)
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{
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verify_open_qhd(p_qhd);
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verify_open_qhd(p_qhd, desc_endpoint->bEndpointAddress, desc_endpoint->wMaxPacketSize);
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TEST_ASSERT_FALSE(p_qhd->head_list_flag);
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TEST_ASSERT_EQUAL(desc_endpoint->wMaxPacketSize, p_qhd->max_package_size);
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TEST_ASSERT_EQUAL(desc_endpoint->bEndpointAddress & 0x0F, p_qhd->endpoint_number);
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TEST_ASSERT_EQUAL(0, p_qhd->data_toggle_control);
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TEST_ASSERT_EQUAL(0, p_qhd->smask);
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TEST_ASSERT_EQUAL(0, p_qhd->cmask);
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TEST_ASSERT_EQUAL(0, p_qhd->interrupt_smask);
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TEST_ASSERT_EQUAL(0, p_qhd->non_hs_cmask);
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TEST_ASSERT_FALSE(p_qhd->non_hs_control_endpoint);
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TEST_ASSERT_EQUAL(usbh_device_info_pool[dev_addr].speed, p_qhd->endpoint_speed);
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// TEST_ASSERT_EQUAL(desc_endpoint->bInterval); TEST highspeed bulk/control OUT
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// TEST_ASSERT_EQUAL(desc_endpoint->bInterval); TDD highspeed bulk/control OUT
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TEST_ASSERT_EQUAL(desc_endpoint->bEndpointAddress & 0x80 ? EHCI_PID_IN : EHCI_PID_OUT, p_qhd->pid_non_control);
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@@ -216,6 +217,7 @@ void test_open_bulk_qhd_data(void)
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pipe_handle_t pipe_hdl;
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tusb_descriptor_endpoint_t const * desc_endpoint = &desc_ept_bulk_in;
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//------------- Code Under TEST -------------//
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pipe_hdl = hcd_pipe_open(dev_addr, desc_endpoint);
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p_qhd = &ehci_data.device[ pipe_hdl.dev_addr ].qhd[ pipe_hdl.index ];
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@@ -152,8 +152,8 @@ void test_qhd_structure(void)
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TEST_ASSERT_EQUAL( 28, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 1, nak_count_reload) );
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//------------- Word 2 -------------//
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TEST_ASSERT_EQUAL( 0, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, smask) );
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TEST_ASSERT_EQUAL( 8, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, cmask) );
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TEST_ASSERT_EQUAL( 0, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, interrupt_smask) );
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TEST_ASSERT_EQUAL( 8, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, non_hs_cmask) );
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TEST_ASSERT_EQUAL( 16, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, hub_address) );
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TEST_ASSERT_EQUAL( 23, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, hub_port) );
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TEST_ASSERT_EQUAL( 30, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, mult) );
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@@ -191,8 +191,8 @@ void test_sitd_structure(void)
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TEST_ASSERT_EQUAL( 31, BITFIELD_OFFSET_OF_UINT32(ehci_sitd_t, 1, direction) );
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//------------- Word 2 -------------//
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TEST_ASSERT_EQUAL( 4*2, offsetof(ehci_sitd_t, smask));
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TEST_ASSERT_EQUAL( 4*2+1, offsetof(ehci_sitd_t, cmask));
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TEST_ASSERT_EQUAL( 4*2, offsetof(ehci_sitd_t, interrupt_smask));
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TEST_ASSERT_EQUAL( 4*2+1, offsetof(ehci_sitd_t, non_hs_cmask));
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//------------- Word 3 -------------//
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TEST_ASSERT_EQUAL( 1, BITFIELD_OFFSET_OF_UINT32(ehci_sitd_t, 3, split_state) );
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