diff --git a/demos/device/device_os_none/.cproject b/demos/device/device_os_none/.cproject
index 65ba9500..4b6066b5 100644
--- a/demos/device/device_os_none/.cproject
+++ b/demos/device/device_os_none/.cproject
@@ -30,7 +30,7 @@
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@@ -62,7 +62,7 @@
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@@ -120,7 +120,7 @@
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@@ -152,7 +152,7 @@
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@@ -209,7 +209,7 @@
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@@ -244,7 +244,7 @@
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@@ -303,7 +303,7 @@
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@@ -335,7 +335,7 @@
-
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@@ -372,45 +372,49 @@
<?xml version="1.0" encoding="UTF-8"?>
<TargetConfig>
-<Properties property_0="" property_3="NXP" property_4="LPC11U37/401" property_count="5" version="1"/>
-<infoList vendor="NXP"><info chip="LPC11U37/401" match_id="0x00017C40" name="LPC11U37/401" stub="crt_emu_lpc11_13_nxp"><chip><name>LPC11U37/401</name>
-<family>LPC11Uxx</family>
+<Properties property_0="" property_3="NXP" property_4="LPC1347" property_count="5" version="1"/>
+<infoList vendor="NXP"><info chip="LPC1347" match_id="0x08020543" name="LPC1347" stub="crt_emu_lpc11_13_nxp"><chip><name>LPC1347</name>
+<family>LPC13xx (12bit ADC)</family>
<vendor>NXP (formerly Philips)</vendor>
<reset board="None" core="Real" sys="Real"/>
<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/>
<memory can_program="true" id="Flash" is_ro="true" type="Flash"/>
<memory id="RAM" type="RAM"/>
<memory id="Periph" is_volatile="true" type="Peripheral"/>
-<memoryInstance derived_from="Flash" id="MFlash128" location="0x0" size="0x20000"/>
+<memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/>
<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/>
<memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/>
-<prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x400" progwithcode="TRUE" size="0x20000"/>
-<peripheralInstance derived_from="CM0_NVIC" id="NVIC" location="0xe000e000"/>
-<peripheralInstance derived_from="LPC11U_GPIO" id="GPIO" location="0x50000000"/>
-<peripheralInstance derived_from="LPC11U_USBDEV" id="USB" location="0x40080000"/>
-<peripheralInstance derived_from="CM0_DCR" id="DCR" location="0xe000edf0"/>
-<peripheralInstance derived_from="LPC11U_GPIO_GROUP_INT" id="GPIOGROUP0INT" location="0x40060000"/>
-<peripheralInstance derived_from="LPC11U_GPIO_GROUP_INT" id="GPIOGROUP1INT" location="0x4005c000"/>
-<peripheralInstance derived_from="LPC11U_GPIO_INT" id="GPIOINT" location="0x4004c000"/>
-<peripheralInstance derived_from="LPC11_13_SSP" id="SSP1" location="0x40058000"/>
-<peripheralInstance derived_from="LPC11U_FMC" id="FMC" location="0x4003c000"/>
-<peripheralInstance derived_from="LPC11U_SYSCTL" id="SYSCTL" location="0x40048000"/>
-<peripheralInstance derived_from="LPC11U_IOCON" id="IOCON" location="0x40044000"/>
-<peripheralInstance derived_from="LPC11_13_SSP" id="SSP0" location="0x40040000"/>
-<peripheralInstance derived_from="LPC11_13_PMU" id="PMU" location="0x40038000"/>
-<peripheralInstance derived_from="LPC11_13_ADC" id="ADC" location="0x4001c000"/>
-<peripheralInstance derived_from="LPC11_13_TIMER32" id="TIMER1" location="0x40018000"/>
-<peripheralInstance derived_from="LPC11_13_TIMER32" id="TIMER0" location="0x40014000"/>
-<peripheralInstance derived_from="LPC11_13_TIMER16" id="TMR161" location="0x40010000"/>
-<peripheralInstance derived_from="LPC11_13_TIMER16" id="TMR160" location="0x4000c000"/>
-<peripheralInstance derived_from="LPC1xxx_UART_MODEM" id="UART0" location="0x40008000"/>
-<peripheralInstance derived_from="LPC11_13_WDT" id="WDT" location="0x40004000"/>
-<peripheralInstance derived_from="LPC11_13_I2C" id="I2C0" location="0x40000000"/>
+<memoryInstance derived_from="RAM" id="RamPeriph2" location="0x20000000" size="0x800"/>
+<prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/>
+<peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/>
+<peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/>
+<peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/>
+<peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/>
+<peripheralInstance derived_from="I2C" id="I2C" location="0x40000000"/>
+<peripheralInstance derived_from="WWDT" id="WWDT" location="0x40004000"/>
+<peripheralInstance derived_from="USART" id="USART" location="0x40008000"/>
+<peripheralInstance derived_from="CT16B0" id="CT16B0" location="0x4000c000"/>
+<peripheralInstance derived_from="CT16B1" id="CT16B1" location="0x40010000"/>
+<peripheralInstance derived_from="CT32B0" id="CT32B0" location="0x40014000"/>
+<peripheralInstance derived_from="CT32B1" id="CT32B1" location="0x40018000"/>
+<peripheralInstance derived_from="ADC" id="ADC" location="0x4001c000"/>
+<peripheralInstance derived_from="PMU" id="PMU" location="0x40038000"/>
+<peripheralInstance derived_from="FLASHCTRL" id="FLASHCTRL" location="0x4003c000"/>
+<peripheralInstance derived_from="SSP0" id="SSP0" location="0x40040000"/>
+<peripheralInstance derived_from="IOCON" id="IOCON" location="0x40044000"/>
+<peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x40048000"/>
+<peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x4004c000"/>
+<peripheralInstance derived_from="SSP1" id="SSP1" location="0x40058000"/>
+<peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x4005c000"/>
+<peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40060000"/>
+<peripheralInstance derived_from="RITIMER" id="RITIMER" location="0x40064000"/>
+<peripheralInstance derived_from="USB" id="USB" location="0x40080000"/>
+<peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x50000000"/>
</chip>
-<processor><name gcc_name="cortex-m0">Cortex-M0</name>
+<processor><name gcc_name="cortex-m3">Cortex-M3</name>
<family>Cortex-M</family>
</processor>
-<link href="nxp_lpc11_13_peripheral.xme" show="embed" type="simple"/>
+<link href="nxp_lpc13Uxx_peripheral.xme" show="embed" type="simple"/>
</info>
</infoList>
</TargetConfig>
diff --git a/demos/device/device_os_none/tusb_config.h b/demos/device/device_os_none/tusb_config.h
index cdb15e36..8fa5e315 100644
--- a/demos/device/device_os_none/tusb_config.h
+++ b/demos/device/device_os_none/tusb_config.h
@@ -86,8 +86,8 @@
#define TUSB_CFG_DEVICE_HID_KEYBOARD 0
#define TUSB_CFG_DEVICE_HID_MOUSE 0
#define TUSB_CFG_DEVICE_HID_GENERIC 0
-#define TUSB_CFG_DEVICE_MSC 0
-#define TUSB_CFG_DEVICE_CDC 1
+#define TUSB_CFG_DEVICE_MSC 1
+#define TUSB_CFG_DEVICE_CDC 0
//--------------------------------------------------------------------+
diff --git a/tinyusb/class/msc_device.c b/tinyusb/class/msc_device.c
index 6fc36fc0..f6990750 100644
--- a/tinyusb/class/msc_device.c
+++ b/tinyusb/class/msc_device.c
@@ -158,7 +158,7 @@ static bool read10_write10_data_xfer(mscd_interface_t* p_msc)
if ( 0 == xferred_block )
{ // xferred_block is zero will cause pipe is stalled & status in CSW set to failed
- p_csw->data_residue = __n2be(p_cbw->xfer_bytes);
+ p_csw->data_residue = p_cbw->xfer_bytes;
p_csw->status = MSC_CSW_STATUS_FAILED;
(void) dcd_pipe_stall(edpt_hdl);
@@ -239,6 +239,7 @@ tusb_error_t mscd_xfer_cb(endpoint_handle_t edpt_hdl, tusb_event_t event, uint32
}
//------------- Status Phase -------------//
+ // Either bulk in & out can be stalled in the data phase, dcd must make sure these queued transfer will be resumed after host clear stall
if (!is_waiting_read10_write10)
{
ASSERT_STATUS( dcd_pipe_xfer( p_msc->edpt_in , p_csw, sizeof(msc_cmd_status_wrapper_t), true) ); // need to be true for dcd to clean up qtd !!
diff --git a/tinyusb/device/dcd_lpc_11uxx_13uxx.c b/tinyusb/device/dcd_lpc_11uxx_13uxx.c
index 09ff7a58..b2681c40 100644
--- a/tinyusb/device/dcd_lpc_11uxx_13uxx.c
+++ b/tinyusb/device/dcd_lpc_11uxx_13uxx.c
@@ -144,6 +144,7 @@ static inline uint16_t addr_offset(void const * p_buffer)
static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_addr_offset, uint16_t total_bytes);
static void pipe_queue_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes);
+static void queue_xfer_in_next_td(uint8_t ep_id);
//--------------------------------------------------------------------+
// CONTROLLER API
@@ -315,11 +316,7 @@ void dcd_isr(uint8_t coreid)
//------------- Next TD is available -------------//
if ( dcd_data.next_td[ep_id].total_bytes != 0 )
{
- dcd_data.current_ioc |= ( dcd_data.next_ioc & BIT_(ep_id) ); // copy next IOC to current IOC
-
- pipe_queue_xfer(ep_id, dcd_data.next_td[ep_id].buff_addr_offset, dcd_data.next_td[ep_id].total_bytes);
-
- dcd_data.next_td[ep_id].total_bytes = 0; // clear this field as it is used to indicate next TD available
+ queue_xfer_in_next_td(ep_id);
}
}
}
@@ -370,13 +367,16 @@ static inline uint8_t edpt_phy2log(uint8_t physical_endpoint)
//--------------------------------------------------------------------+
tusb_error_t dcd_pipe_stall(endpoint_handle_t edpt_hdl)
{
-// ASSERT( !dcd_pipe_is_busy(edpt_hdl), TUSB_ERROR_INTERFACE_IS_BUSY); // endpoint must not in transferring
-
dcd_data.qhd[edpt_hdl.index][0].stall = dcd_data.qhd[edpt_hdl.index][1].stall = 1;
return TUSB_ERROR_NONE;
}
+bool dcd_pipe_is_stalled(endpoint_handle_t edpt_hdl)
+{
+ return dcd_data.qhd[edpt_hdl.index][0].stall || dcd_data.qhd[edpt_hdl.index][1].stall;
+}
+
tusb_error_t dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr)
{
uint8_t ep_id = edpt_addr2phy(edpt_addr);
@@ -387,6 +387,12 @@ tusb_error_t dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr)
dcd_data.qhd[ep_id][active_buffer].toggle_reset = 1;
dcd_data.qhd[ep_id][active_buffer].feedback_toggle = 0;
+ //------------- clear stall must carry on any previously queued transfer -------------//
+ if ( dcd_data.next_td[ep_id].total_bytes != 0 )
+ {
+ queue_xfer_in_next_td(ep_id);
+ }
+
return TUSB_ERROR_NONE;
}
@@ -460,6 +466,15 @@ static void pipe_queue_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t t
queue_xfer_to_buffer(ep_id, 0, buff_addr_offset, total_bytes);
}
+static void queue_xfer_in_next_td(uint8_t ep_id)
+{
+ dcd_data.current_ioc |= ( dcd_data.next_ioc & BIT_(ep_id) ); // copy next IOC to current IOC
+
+ pipe_queue_xfer(ep_id, dcd_data.next_td[ep_id].buff_addr_offset, dcd_data.next_td[ep_id].total_bytes);
+
+ dcd_data.next_td[ep_id].total_bytes = 0; // clear this field as it is used to indicate whehther next TD available
+}
+
tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint16_t total_bytes)
{
ASSERT( !dcd_pipe_is_busy(edpt_hdl), TUSB_ERROR_INTERFACE_IS_BUSY); // endpoint must not in transferring
@@ -473,8 +488,8 @@ tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint
tusb_error_t dcd_pipe_xfer(endpoint_handle_t edpt_hdl, void* buffer, uint16_t total_bytes, bool int_on_complete)
{
- if( dcd_pipe_is_busy(edpt_hdl) )
- { // save this transfer data to next td
+ if( dcd_pipe_is_busy(edpt_hdl) || dcd_pipe_is_stalled(edpt_hdl) )
+ { // save this transfer data to next td if pipe is busy or already been stalled
dcd_data.next_td[edpt_hdl.index].buff_addr_offset = addr_offset(buffer);
dcd_data.next_td[edpt_hdl.index].total_bytes = total_bytes;