Merge branch 'master' of https://github.com/hathach/tinyusb into stm32f4
This commit is contained in:
William D. Jones
+17
-30
@@ -52,38 +52,27 @@
|
||||
|
||||
#include "ansi_escape.h"
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// PRINTF TARGET DEFINE
|
||||
//--------------------------------------------------------------------+
|
||||
/** \defgroup group_printf Printf Retarget
|
||||
* \brief Retarget the standard stdio printf/getchar to other IOs
|
||||
* @{ */
|
||||
#define PRINTF_TARGET_SEMIHOST 1 ///< Using the semihost support from toolchain, requires no hardware but is the slowest
|
||||
#define PRINTF_TARGET_UART 2 ///< Using UART as stdio, this is the default for most of the board
|
||||
#define PRINTF_TARGET_SWO 3 ///< Using non-instructive serial wire output (SWO), is the best option since it does not slow down MCU but requires supported from debugger and IDE
|
||||
#define PRINTF_TARGET_NONE 4 ///< Using none at all.
|
||||
/** @} */
|
||||
|
||||
#define PRINTF(...) printf(__VA_ARGS__)
|
||||
|
||||
// NXP LPC
|
||||
#if defined BOARD_LPCXPRESSO11U14
|
||||
#include "lpcxpresso11u14/board_lpcxpresso11u14.h"
|
||||
#elif defined BOARD_LPCXPRESSO11U68
|
||||
#include "lpcxpresso11u68/board_lpcxpresso11u68.h"
|
||||
#elif defined BOARD_LPCXPRESSO1347
|
||||
#include "lpcxpresso1347/board_lpcxpresso1347.h"
|
||||
#elif defined BOARD_LPCXPRESSO11U68
|
||||
#include "lpcxpresso11u68/board_lpcxpresso11u68.h"
|
||||
#elif defined BOARD_LPCXPRESSO1769
|
||||
#include "lpcxpresso1769/board_lpcxpresso1769.h"
|
||||
#elif defined BOARD_NGX4330
|
||||
#include "ngx/board_ngx4330.h"
|
||||
#elif defined BOARD_MCB1800
|
||||
#include "mcb1800/board_mcb1800.h"
|
||||
#elif defined BOARD_EA4088QS
|
||||
#include "ea4088qs/board_ea4088qs.h"
|
||||
#elif defined BOARD_EA4357
|
||||
#include "ea4357/board_ea4357.h"
|
||||
#elif defined BOARD_MCB4300
|
||||
#include "keil/board_mcb4300.h"
|
||||
#elif defined BOARD_LPCLINK2
|
||||
#include "lpcxpresso/board_lpclink2.h"
|
||||
|
||||
// Nordic nRF
|
||||
#elif defined BOARD_PCA10056
|
||||
#include "pca10056/board_pca10056.h"
|
||||
|
||||
// Atmel SAM
|
||||
#elif defined BOARD_METRO_M4_EXPRESS
|
||||
#include "metro_m4_express/board_metro_m4_express.h"
|
||||
#elif defined BOARD_METRO_M0_EXPRESS
|
||||
@@ -104,20 +93,18 @@ void board_init(void);
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// LED
|
||||
// Board variant must defined following
|
||||
// - BOARD_LED_NUM : number of LEDs
|
||||
// - BOARD_LEDn : where n is 0,1 etc ...
|
||||
// Board layer use only 1 LED for indicator
|
||||
//--------------------------------------------------------------------+
|
||||
void board_led_control(uint32_t led_id, bool state);
|
||||
void board_led_control(bool state);
|
||||
|
||||
static inline void board_led_on(uint32_t led_id)
|
||||
static inline void board_led_on(void)
|
||||
{
|
||||
board_led_control(led_id, true);
|
||||
board_led_control(true);
|
||||
}
|
||||
|
||||
static inline void board_led_off(uint32_t led_id)
|
||||
static inline void board_led_off(void)
|
||||
{
|
||||
board_led_control(led_id, false);
|
||||
board_led_control(false);
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
@@ -0,0 +1,186 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file board_ea4088qs.c
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2018, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#ifdef BOARD_EA4088QS
|
||||
|
||||
#include "../board.h"
|
||||
#include "tusb.h"
|
||||
|
||||
#define LED_PORT 2
|
||||
#define LED_PIN 19
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
/* System oscillator rate and RTC oscillator rate */
|
||||
const uint32_t OscRateIn = 12000000;
|
||||
const uint32_t RTCOscRateIn = 32768;
|
||||
|
||||
/* Pin muxing configuration */
|
||||
static const PINMUX_GRP_T pinmuxing[] =
|
||||
{
|
||||
/* LEDs */
|
||||
{2, 19, (IOCON_FUNC0 | IOCON_MODE_INACT)},
|
||||
};
|
||||
|
||||
static const PINMUX_GRP_T pin_usb_mux[] =
|
||||
{
|
||||
// USB1 as Host
|
||||
{0, 29, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D+1
|
||||
{0, 30, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D-1
|
||||
{1, 18, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // UP LED1
|
||||
{1, 19, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // PPWR1
|
||||
// {2, 14, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // VBUS1
|
||||
// {2, 15, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // OVRCR1
|
||||
|
||||
// USB2 as Device
|
||||
{0, 31, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D+2
|
||||
{0, 13, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // UP LED
|
||||
{0, 14, (IOCON_FUNC3 | IOCON_MODE_INACT)}, // CONNECT2
|
||||
|
||||
/* VBUS is not connected on this board, so leave the pin at default setting. */
|
||||
/*Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);*/ /* USB VBUS */
|
||||
};
|
||||
|
||||
// Invoked by startup code
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Enable IOCON clock */
|
||||
Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
|
||||
Chip_SetupXtalClocking();
|
||||
}
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
SysTick_Config(SystemCoreClock / BOARD_TICKS_HZ);
|
||||
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||
NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
|
||||
#endif
|
||||
|
||||
Chip_GPIO_Init(LPC_GPIO);
|
||||
|
||||
//------------- LED -------------//
|
||||
Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
|
||||
|
||||
//------------- BUTTON -------------//
|
||||
// for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) GPIO_SetDir(buttons[i].port, TU_BIT(buttons[i].pin), 0);
|
||||
|
||||
|
||||
//------------- UART -------------//
|
||||
|
||||
//------------- USB -------------//
|
||||
// Port1 as Host, Port2: Device
|
||||
Chip_USB_Init();
|
||||
|
||||
enum {
|
||||
USBCLK = 0x1B // Host + Device + OTG + AHB
|
||||
};
|
||||
|
||||
LPC_USB->OTGClkCtrl = USBCLK;
|
||||
while ( (LPC_USB->OTGClkSt & USBCLK) != USBCLK ) {}
|
||||
|
||||
// USB1 = host, USB2 = device
|
||||
LPC_USB->StCtrl = 0x3;
|
||||
|
||||
Chip_IOCON_SetPinMuxing(LPC_IOCON, pin_usb_mux, sizeof(pin_usb_mux) / sizeof(PINMUX_GRP_T));
|
||||
}
|
||||
|
||||
|
||||
//------------- LED -------------//
|
||||
void board_led_control(bool state)
|
||||
{
|
||||
Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state);
|
||||
}
|
||||
|
||||
//------------- Buttons -------------//
|
||||
#if 0
|
||||
static bool button_read(uint8_t id)
|
||||
{
|
||||
// return !TU_BIT_TEST( GPIO_ReadValue(buttons[id].gpio_port), buttons[id].gpio_pin ); // button is active low
|
||||
}
|
||||
#endif
|
||||
|
||||
uint32_t board_buttons(void)
|
||||
{
|
||||
uint32_t result = 0;
|
||||
|
||||
// for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? TU_BIT(i) : 0);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
//------------- UART -------------//
|
||||
uint8_t board_uart_getchar(void)
|
||||
{
|
||||
//return UART_ReceiveByte(BOARD_UART_PORT);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void board_uart_putchar(uint8_t c)
|
||||
{
|
||||
//UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
|
||||
(void) c;
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
/* TUSB HAL MILLISECOND
|
||||
*------------------------------------------------------------------*/
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
|
||||
volatile uint32_t system_ticks = 0;
|
||||
|
||||
void SysTick_Handler (void)
|
||||
{
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t tusb_hal_millis(void)
|
||||
{
|
||||
return board_tick2ms(system_ticks);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,51 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file board_ea4088qs.h
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2018, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
#ifndef BOARD_EA4088QS_H_
|
||||
#define BOARD_EA4088QS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* BOARD_EA4088QS_H_ */
|
||||
+161
-32
@@ -36,11 +36,12 @@
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#include "bsp/board.h"
|
||||
#include "tusb.h"
|
||||
|
||||
#ifdef BOARD_EA4357
|
||||
|
||||
#include "../board.h"
|
||||
#include "pca9532.h"
|
||||
#include "tusb.h"
|
||||
|
||||
#define BOARD_UART_PORT LPC_USART0
|
||||
#define BOARD_UART_PIN_PORT 0x0f
|
||||
#define BOARD_UART_PIN_TX 10 // PF.10 : UART0_TXD
|
||||
@@ -88,39 +89,75 @@ uint32_t tusb_hal_millis(void)
|
||||
/*------------------------------------------------------------------*/
|
||||
/* BOARD API
|
||||
*------------------------------------------------------------------*/
|
||||
|
||||
/* System configuration variables used by chip driver */
|
||||
const uint32_t ExtRateIn = 0;
|
||||
const uint32_t OscRateIn = 12000000;
|
||||
|
||||
static const PINMUX_GRP_T pinmuxing[] =
|
||||
{
|
||||
// USB
|
||||
|
||||
/* I2S */
|
||||
{0x3, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC2)}, //I2S0_TX_CLK
|
||||
{0xC, 12, (SCU_PINIO_FAST | SCU_MODE_FUNC6)}, //I2S0_TX_SDA
|
||||
{0xC, 13, (SCU_PINIO_FAST | SCU_MODE_FUNC6)}, //I2S0_TX_WS
|
||||
{0x6, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC4)}, //I2S0_RX_SCK
|
||||
{0x6, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, //I2S0_RX_WS
|
||||
{0x6, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, //I2S0_RX_SDA
|
||||
};
|
||||
|
||||
/* Pin clock mux values, re-used structure, value in first index is meaningless */
|
||||
static const PINMUX_GRP_T pinclockmuxing[] =
|
||||
{
|
||||
{0, 0, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
|
||||
{0, 1, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
|
||||
{0, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
|
||||
{0, 3, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
|
||||
};
|
||||
|
||||
// Invoked by startup code
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Setup system level pin muxing */
|
||||
Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
|
||||
|
||||
/* Clock pins only, group field not used */
|
||||
for (int i = 0; i <(int) (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++)
|
||||
{
|
||||
Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
|
||||
}
|
||||
|
||||
Chip_SetupXtalClocking();
|
||||
}
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
CGU_Init();
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE // TODO may move to main.c
|
||||
SysTick_Config(CGU_GetPCLKFrequency(CGU_PERIPHERAL_M4CORE) / BOARD_TICKS_HZ); // 1 msec tick timer
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
SysTick_Config( SystemCoreClock / BOARD_TICKS_HZ );
|
||||
#endif
|
||||
|
||||
//------------- USB -------------//
|
||||
// USB0 Power: EA4357 channel B U20 GPIO26 active low (base board), P2_3 on LPC4357
|
||||
scu_pinmux(0x02, 3, MD_PUP | MD_EZI, FUNC7); // USB0 VBus Power
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
|
||||
scu_pinmux(0x09, 5, GPIO_PDN, FUNC4); // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.
|
||||
GPIO_SetDir(5, BIT_(18), 1);
|
||||
#endif
|
||||
|
||||
// USB1 Power: EA4357 channel A U20 is enabled by SJ5 connected to pad 1-2, no more action required
|
||||
// TODO Remove R170, R171, solder a pair of 15K to USB1 D+/D- to test with USB1 Host
|
||||
Chip_GPIO_Init(LPC_GPIO_PORT);
|
||||
|
||||
//------------- LED -------------//
|
||||
I2C_Init(LPC_I2C0, 100000);
|
||||
I2C_Cmd(LPC_I2C0, ENABLE);
|
||||
/* Init I2C */
|
||||
Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE);
|
||||
Chip_I2C_Init(I2C0);
|
||||
Chip_I2C_SetClockRate(I2C0, 100000);
|
||||
Chip_I2C_SetMasterEventHandler(I2C0, Chip_I2C_EventHandlerPolling);
|
||||
|
||||
pca9532_init();
|
||||
|
||||
#if 0
|
||||
//------------- BUTTON -------------//
|
||||
for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++)
|
||||
{
|
||||
scu_pinmux(buttons[i].mux_port, buttons[i].mux_pin, GPIO_NOPULL, FUNC0);
|
||||
GPIO_SetDir(buttons[i].gpio_port, BIT_(buttons[i].gpio_pin), 0);
|
||||
GPIO_SetDir(buttons[i].gpio_port, TU_BIT(buttons[i].gpio_pin), 0);
|
||||
}
|
||||
|
||||
#if 0
|
||||
//------------- UART -------------//
|
||||
scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_TX, MD_PDN, FUNC1);
|
||||
scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_RX, MD_PLN | MD_EZI | MD_ZI, FUNC1);
|
||||
@@ -134,33 +171,122 @@ void board_init(void)
|
||||
UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
|
||||
#endif
|
||||
|
||||
//------------- NAND Flash (K9FXX) Size = 128M, Page Size = 2K, Block Size = 128K, Number of Block = 1024 -------------//
|
||||
// nand_init();
|
||||
//------------- USB -------------//
|
||||
enum {
|
||||
USBMODE_DEVICE = 2,
|
||||
USBMODE_HOST = 3
|
||||
};
|
||||
|
||||
enum {
|
||||
USBMODE_VBUS_LOW = 0,
|
||||
USBMODE_VBUS_HIGH = 1
|
||||
};
|
||||
|
||||
/* USB0
|
||||
* For USB Device operation; insert jumpers in position 1-2 in JP17/JP18/JP19. GPIO28 controls USB
|
||||
* connect functionality and LED32 lights when the USB Device is connected. SJ4 has pads 1-2 shorted
|
||||
* by default. LED33 is controlled by GPIO27 and signals USB-up state. GPIO54 is used for VBUS
|
||||
* sensing.
|
||||
* For USB Host operation; insert jumpers in position 2-3 in JP17/JP18/JP19. USB Host power is
|
||||
* controlled via distribution switch U20 (found in schematic page 11). Signal GPIO26 is active low and
|
||||
* enables +5V on VBUS2. LED35 light whenever +5V is present on VBUS2. GPIO55 is connected to
|
||||
* status feedback from the distribution switch. GPIO54 is used for VBUS sensing. 15Kohm pull-down
|
||||
* resistors are always active
|
||||
*/
|
||||
#if CFG_TUSB_RHPORT0_MODE
|
||||
Chip_USB0_Init();
|
||||
|
||||
// Reset controller
|
||||
LPC_USB0->USBCMD_D |= 0x02;
|
||||
while( LPC_USB0->USBCMD_D & 0x02 ) {}
|
||||
|
||||
// Set mode
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
|
||||
LPC_USB0->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
|
||||
|
||||
LPC_USB0->PORTSC1_D |= (1<<24); // FIXME force full speed for debugging
|
||||
#else // TODO OTG
|
||||
LPC_USB0->USBMODE_D = USBMODE_DEVICE;
|
||||
LPC_USB0->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* USB1
|
||||
* When USB channel #1 is used as USB Host, 15Kohm pull-down resistors are needed on the USB data
|
||||
* signals. These are activated inside the USB OTG chip (U31), and this has to be done via the I2C
|
||||
* interface of GPIO52/GPIO53.
|
||||
* J20 is the connector to use when USB Host is used. In order to provide +5V to the external USB
|
||||
* device connected to this connector (J20), channel A of U20 must be enabled. It is enabled by default
|
||||
* since SJ5 is normally connected between pin 1-2. LED34 lights green when +5V is available on J20.
|
||||
* JP15 shall not be inserted. JP16 has no effect
|
||||
*
|
||||
* When USB channel #1 is used as USB Device, a 1.5Kohm pull-up resistor is needed on the USB DP
|
||||
* data signal. There are two methods to create this. JP15 is inserted and the pull-up resistor is always
|
||||
* enabled. Alternatively, the pull-up resistor is activated inside the USB OTG chip (U31), and this has to
|
||||
* be done via the I2C interface of GPIO52/GPIO53. In the latter case, JP15 shall not be inserted.
|
||||
* J19 is the connector to use when USB Device is used. Normally it should be a USB-B connector for
|
||||
* creating a USB Device interface, but the mini-AB connector can also be used in this case. The status
|
||||
* of VBUS can be read via U31.
|
||||
* JP16 shall not be inserted.
|
||||
*/
|
||||
#if CFG_TUSB_RHPORT1_MODE
|
||||
Chip_USB1_Init();
|
||||
|
||||
// Reset controller
|
||||
LPC_USB1->USBCMD_D |= 0x02;
|
||||
while( LPC_USB1->USBCMD_D & 0x02 ) {}
|
||||
|
||||
// Set mode
|
||||
#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
|
||||
LPC_USB1->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
|
||||
#else // TODO OTG
|
||||
LPC_USB1->USBMODE_D = USBMODE_DEVICE;
|
||||
#endif
|
||||
|
||||
// USB1 as fullspeed
|
||||
LPC_USB1->PORTSC1_D |= (1<<24);
|
||||
#endif
|
||||
|
||||
// USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board)
|
||||
Chip_SCU_PinMuxSet(2, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7);
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
|
||||
// P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.
|
||||
Chip_SCU_PinMuxSet(9, 5, SCU_MODE_PULLDOWN | SCU_MODE_FUNC4);
|
||||
Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 18);
|
||||
#endif
|
||||
|
||||
// USB1 Power: EA4357 channel A U20 is enabled by SJ5 connected to pad 1-2, no more action required
|
||||
// TODO Remove R170, R171, solder a pair of 15K to USB1 D+/D- to test with USB1 Host
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// LEDS
|
||||
//--------------------------------------------------------------------+
|
||||
void board_led_control(uint32_t id, bool state)
|
||||
// LED
|
||||
void board_led_control(bool state)
|
||||
{
|
||||
uint16_t on_mask = state ? (1 << id) : 0;
|
||||
uint16_t off_mask = state ? 0 : (1 << id);
|
||||
pca9532_setLeds( on_mask << 8, off_mask << 8 );
|
||||
if (state)
|
||||
{
|
||||
pca9532_setLeds( LED1, 0 );
|
||||
}else
|
||||
{
|
||||
pca9532_setLeds( 0, LED1);
|
||||
}
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// BUTTONS
|
||||
//--------------------------------------------------------------------+
|
||||
#if 0
|
||||
static bool button_read(uint8_t id)
|
||||
{
|
||||
return !BIT_TEST_( GPIO_ReadValue(buttons[id].gpio_port), buttons[id].gpio_pin ); // button is active low
|
||||
// return !TU_BIT_TEST( GPIO_ReadValue(buttons[id].gpio_port), buttons[id].gpio_pin ); // button is active low
|
||||
}
|
||||
#endif
|
||||
|
||||
uint32_t board_buttons(void)
|
||||
{
|
||||
uint32_t result = 0;
|
||||
|
||||
for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? BIT_(i) : 0);
|
||||
// for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? TU_BIT(i) : 0);
|
||||
|
||||
return result;
|
||||
}
|
||||
@@ -171,10 +297,13 @@ uint32_t board_buttons(void)
|
||||
uint8_t board_uart_getchar(void)
|
||||
{
|
||||
//return UART_ReceiveByte(BOARD_UART_PORT);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void board_uart_putchar(uint8_t c)
|
||||
{
|
||||
//UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
|
||||
(void) c;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -43,22 +43,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "LPC43xx.h"
|
||||
#include "lpc43xx_scu.h"
|
||||
#include "lpc43xx_cgu.h"
|
||||
#include "lpc43xx_gpio.h"
|
||||
#include "lpc43xx_uart.h"
|
||||
#include "lpc43xx_i2c.h"
|
||||
|
||||
|
||||
#include "oem_base_board/pca9532.h" // LEDs
|
||||
|
||||
#define BOARD_LED_NUM 1
|
||||
#define BOARD_LED0 0
|
||||
|
||||
|
||||
//#define CFG_PRINTF_TARGET PRINTF_TARGET_SWO
|
||||
#define CFG_PRINTF_TARGET PRINTF_TARGET_UART
|
||||
#include "chip.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -1,480 +0,0 @@
|
||||
/******************************************************************
|
||||
***** *****
|
||||
***** Name: cs8900.c *****
|
||||
***** Ver.: 1.0 *****
|
||||
***** Date: 07/05/2001 *****
|
||||
***** Auth: Andreas Dannenberg *****
|
||||
***** HTWK Leipzig *****
|
||||
***** university of applied sciences *****
|
||||
***** Germany *****
|
||||
***** Func: ethernet packet-driver for use with LAN- *****
|
||||
***** controller CS8900 from Crystal/Cirrus Logic *****
|
||||
***** *****
|
||||
***** NXP: Module modified for use with NXP *****
|
||||
***** lpc43xx EMAC Ethernet controller *****
|
||||
***** *****
|
||||
******************************************************************/
|
||||
|
||||
#include "../board.h"
|
||||
|
||||
#if BOARD == BOARD_EA4357
|
||||
|
||||
#include "emac.h"
|
||||
//#include "tcpip.h"
|
||||
#include "LPC43xx.h"
|
||||
#include "lpc43xx_scu.h"
|
||||
#include "lpc43xx_rgu.h"
|
||||
|
||||
#define TIMEOUT 100000
|
||||
|
||||
static unsigned short *rptr;
|
||||
static unsigned short *tptr;
|
||||
|
||||
static unsigned int TxDescIndex = 0;
|
||||
static unsigned int RxDescIndex = 0;
|
||||
|
||||
// Keil: function added to write PHY
|
||||
static void write_PHY (unsigned int PhyReg, unsigned short Value) {
|
||||
|
||||
unsigned int tout;
|
||||
|
||||
/* Write a data 'Value' to PHY register 'PhyReg'. */
|
||||
while(LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY); // Check GMII busy bit
|
||||
LPC_ETHERNET->MAC_MII_ADDR = (DP83848C_DEF_ADR<<11) | (PhyReg<<6) | GMII_WRITE;
|
||||
LPC_ETHERNET->MAC_MII_DATA = Value;
|
||||
LPC_ETHERNET->MAC_MII_ADDR |= GMII_BUSY; // Start PHY Write Cycle
|
||||
|
||||
/* Wait utill operation completed */
|
||||
for (tout = 0; tout < MII_WR_TOUT; tout++) {
|
||||
if ((LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY) == 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (tout == MII_WR_TOUT) // Trap the timeout
|
||||
while(1);
|
||||
}
|
||||
|
||||
|
||||
// Keil: function added to read PHY
|
||||
static unsigned short read_PHY (unsigned int PhyReg) {
|
||||
|
||||
unsigned int tout, val;
|
||||
|
||||
/* Read a PHY register 'PhyReg'. */
|
||||
while(LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY); // Check GMII busy bit
|
||||
LPC_ETHERNET->MAC_MII_ADDR = (DP83848C_DEF_ADR<<11) | (PhyReg<<6) | GMII_READ;
|
||||
LPC_ETHERNET->MAC_MII_ADDR |= GMII_BUSY; // Start PHY Read Cycle
|
||||
|
||||
/* Wait until operation completed */
|
||||
for (tout = 0; tout < MII_RD_TOUT; tout++) {
|
||||
if ((LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY) == 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (tout == MII_RD_TOUT) // Trap the timeout
|
||||
while(1);
|
||||
val = LPC_ETHERNET->MAC_MII_DATA;
|
||||
return (val);
|
||||
}
|
||||
|
||||
|
||||
// Keil: function added to initialize Rx Descriptors
|
||||
void rx_descr_init (void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < NUM_RX_DESC; i++) {
|
||||
RX_DESC_STAT(i) = OWN_BIT;
|
||||
RX_DESC_CTRL(i) = ETH_FRAG_SIZE;
|
||||
RX_BUFADDR(i) = RX_BUF(i);
|
||||
if (i == (NUM_RX_DESC-1)) // Last Descriptor?
|
||||
RX_DESC_CTRL(i) |= RX_END_RING;
|
||||
}
|
||||
|
||||
/* Set Starting address of RX Descriptor list */
|
||||
LPC_ETHERNET->DMA_REC_DES_ADDR = RX_DESC_BASE;
|
||||
}
|
||||
|
||||
|
||||
// Keil: function added to initialize Tx Descriptors
|
||||
void tx_descr_init (void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < NUM_TX_DESC; i++) { // Take it out!!!!
|
||||
TX_DESC_STAT(i) = 0;
|
||||
TX_DESC_CTRL(i) = 0;
|
||||
TX_BUFADDR(i) = 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < NUM_TX_DESC; i++) {
|
||||
TX_DESC_STAT(i) = TX_LAST_SEGM | TX_FIRST_SEGM;
|
||||
TX_DESC_CTRL(i) = 0;
|
||||
TX_BUFADDR(i) = TX_BUF(i);
|
||||
if (i == (NUM_TX_DESC-1)) // Last Descriptor?
|
||||
TX_DESC_STAT(i) |= TX_END_RING;
|
||||
}
|
||||
|
||||
/* Set Starting address of RX Descriptor list */
|
||||
LPC_ETHERNET->DMA_TRANS_DES_ADDR = TX_DESC_BASE;
|
||||
}
|
||||
|
||||
|
||||
|
||||
// configure port-pins for use with LAN-controller,
|
||||
// reset it and send the configuration-sequence
|
||||
|
||||
void Init_EMAC(void)
|
||||
{
|
||||
int id1, id2, tout, regv;
|
||||
unsigned phy_in_use = 0;
|
||||
|
||||
/* Ethernet pins configuration */
|
||||
#if MII
|
||||
scu_pinmux(0xC ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_MDC: PC_1 -> FUNC3
|
||||
scu_pinmux(0x1 ,17 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_MDIO: P1_17 -> FUNC3
|
||||
scu_pinmux(0x1 ,18 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD0: P1_18 -> FUNC3
|
||||
scu_pinmux(0x1 ,20 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD1: P1_20 -> FUNC3
|
||||
scu_pinmux(0x1 ,19 , (MD_PLN | MD_EZI | MD_ZI), FUNC0); // ENET_REF: P1_19 -> FUNC0 (default)
|
||||
|
||||
// scu_pinmux(0xC ,4 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TX_EN: PC_4 -> FUNC3
|
||||
scu_pinmux(0x0 ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC6); // ENET_TX_EN: P0_1 -> FUNC6
|
||||
|
||||
scu_pinmux(0x1 ,15 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXD0: P1_15 -> FUNC3
|
||||
scu_pinmux(0x0 ,0 , (MD_PLN | MD_EZI | MD_ZI), FUNC2); // ENET_RXD1: P0_0 -> FUNC2
|
||||
|
||||
// scu_pinmux(0x1 ,16 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_CRS: P1_16 -> FUNC3
|
||||
scu_pinmux(0x9 ,0 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_CRS: P9_0 -> FUNC5
|
||||
|
||||
// scu_pinmux(0xC ,9 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RX_ER: PC_9 -> FUNC3
|
||||
scu_pinmux(0x9 ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_RX_ER: P9_1 -> FUNC5
|
||||
|
||||
// scu_pinmux(0xC ,8 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXDV: PC_8 -> FUNC3
|
||||
scu_pinmux(0x1 ,16 , (MD_PLN | MD_EZI | MD_ZI), FUNC7); // ENET_RXDV: P1_16 -> FUNC7
|
||||
|
||||
#else
|
||||
scu_pinmux(0xC ,1 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_MDC: PC_1 -> FUNC3
|
||||
scu_pinmux(0x1 ,17 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_MDIO: P1_17 -> FUNC3
|
||||
scu_pinmux(0x1 ,18 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD0: P1_18 -> FUNC3
|
||||
scu_pinmux(0x1 ,20 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD1: P1_20 -> FUNC3
|
||||
scu_pinmux(0x1 ,19 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC0); // ENET_REF: P1_19 -> FUNC0 (default)
|
||||
// scu_pinmux(0xC ,4 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TX_EN: PC_4 -> FUNC3
|
||||
scu_pinmux(0x0 ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC6); // ENET_TX_EN: P0_1 -> FUNC6
|
||||
scu_pinmux(0x1 ,15 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXD0: P1_15 -> FUNC3
|
||||
scu_pinmux(0x0 ,0 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC2); // ENET_RXD1: P0_0 -> FUNC2
|
||||
// scu_pinmux(0x1 ,16 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_CRS: P1_16 -> FUNC3
|
||||
// scu_pinmux(0x9 ,0 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_CRS: P9_0 -> FUNC5
|
||||
// scu_pinmux(0xC ,9 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RX_ER: PC_9 -> FUNC3
|
||||
// scu_pinmux(0x9 ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_RX_ER: P9_1 -> FUNC5
|
||||
// scu_pinmux(0xC ,8 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXDV: PC_8 -> FUNC3
|
||||
scu_pinmux(0x1 ,16 , (MD_PLN | MD_EZI | MD_ZI), FUNC7); // ENET_RXDV: P1_16 -> FUNC7
|
||||
#endif
|
||||
|
||||
|
||||
#if MII /* Select MII interface */ // check MUXING for new Eagle...
|
||||
// scu_pinmux(0xC ,6 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXD2: PC_6 -> FUNC3
|
||||
scu_pinmux(0x9 ,3 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_RXD2: P9_3 -> FUNC5
|
||||
|
||||
// scu_pinmux(0xC ,7 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXD3: PC_7 -> FUNC3
|
||||
scu_pinmux(0x9 ,2 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_RXD3: P9_2 -> FUNC5
|
||||
|
||||
scu_pinmux(0xC ,0 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXLK: PC_0 -> FUNC3
|
||||
|
||||
// scu_pinmux(0xC ,2 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD2: PC_2 -> FUNC3
|
||||
scu_pinmux(0x9 ,4 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_TXD2: P9_4 -> FUNC5
|
||||
|
||||
// scu_pinmux(0xC ,3 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD3: PC_3 -> FUNC3
|
||||
scu_pinmux(0x9 ,5 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_TXD3: P9_5 -> FUNC5
|
||||
|
||||
// scu_pinmux(0xC ,5 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TX_ER: PC_5 -> FUNC3
|
||||
scu_pinmux(0xC ,5 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TX_ER: PC_5 -> FUNC3
|
||||
|
||||
// scu_pinmux(0x0 ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC2); // ENET_COL: P0_1 -> FUNC2
|
||||
scu_pinmux(0x9 ,6 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_COL: P9_6 -> FUNC5
|
||||
#else /* Select RMII interface */
|
||||
LPC_CREG->CREG6 |= RMII_SELECT;
|
||||
#endif
|
||||
|
||||
|
||||
RGU_SoftReset(RGU_SIG_ETHERNET);
|
||||
while(1){ // Confirm the reset happened
|
||||
if (LPC_RGU->RESET_ACTIVE_STATUS0 & (1<<ETHERNET_RST))
|
||||
break;
|
||||
}
|
||||
|
||||
LPC_ETHERNET->DMA_BUS_MODE |= DMA_SOFT_RESET; // Reset all GMAC Subsystem internal registers and logic
|
||||
while(LPC_ETHERNET->DMA_BUS_MODE & DMA_SOFT_RESET); // Wait for software reset completion
|
||||
|
||||
/* Put the DP83848C in reset mode */
|
||||
write_PHY (PHY_REG_BMCR, PHY_BMCR_RESET);
|
||||
|
||||
/* Wait for hardware reset to end. */
|
||||
for (tout = 0; tout < TIMEOUT; tout++) {
|
||||
regv = read_PHY (PHY_REG_BMCR);
|
||||
if (!(regv & PHY_BMCR_RESET)) {
|
||||
/* Reset complete */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if this is a DP83848C PHY. */
|
||||
id1 = read_PHY (PHY_REG_IDR1);
|
||||
id2 = read_PHY (PHY_REG_IDR2);
|
||||
if (((id1 << 16) | (id2 & 0xFFF0)) == DP83848C_ID) {
|
||||
phy_in_use = DP83848C_ID;
|
||||
}
|
||||
else if (((id1 << 16) | (id2 & 0xFFF0)) == LAN8720_ID) {
|
||||
phy_in_use = LAN8720_ID;
|
||||
}
|
||||
|
||||
if (phy_in_use != 0) {
|
||||
/* Configure the PHY device */
|
||||
#if !MII
|
||||
write_PHY (PHY_REG_RBR, 0x20);
|
||||
#endif
|
||||
|
||||
/* Use autonegotiation about the link speed. */
|
||||
write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
|
||||
/* Wait to complete Auto_Negotiation. */
|
||||
for (tout = 0; tout < TIMEOUT; tout++) {
|
||||
regv = read_PHY (PHY_REG_BMSR);
|
||||
if (regv & PHY_AUTO_NEG_DONE) {
|
||||
/* Autonegotiation Complete. */
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Check the link status. */
|
||||
for (tout = 0; tout < TIMEOUT; tout++) {
|
||||
regv = read_PHY (PHY_REG_STS);
|
||||
if (regv & LINK_VALID_STS) {
|
||||
/* Link is on. */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// Configure the EMAC with the established parameters
|
||||
switch (phy_in_use) {
|
||||
case DP83848C_ID:
|
||||
|
||||
/* Configure Full/Half Duplex mode. */
|
||||
if (regv & FULL_DUP_STS) {
|
||||
/* Full duplex is enabled. */
|
||||
LPC_ETHERNET->MAC_CONFIG |= MAC_DUPMODE;
|
||||
}
|
||||
|
||||
/* Configure 100MBit/10MBit mode. */
|
||||
if (~(regv & SPEED_10M_STS)) {
|
||||
/* 100MBit mode. */
|
||||
LPC_ETHERNET->MAC_CONFIG |= MAC_100MPS;
|
||||
}
|
||||
|
||||
// value = ReadFromPHY (PHY_REG_STS); /* PHY Extended Status Register */
|
||||
// // Now configure for full/half duplex mode
|
||||
// if (value & 0x0004) {
|
||||
// // We are in full duplex is enabled mode
|
||||
// LPC_ETHERNET->MAC2 |= MAC2_FULL_DUP;
|
||||
// LPC_ETHERNET->Command |= CR_FULL_DUP;
|
||||
// LPC_ETHERNET->IPGT = IPGT_FULL_DUP;
|
||||
// }
|
||||
// else {
|
||||
// // Otherwise we are in half duplex mode
|
||||
// LPC_ETHERNET->IPGT = IPGT_HALF_DUP;
|
||||
// }
|
||||
|
||||
// // Now configure 100MBit or 10MBit mode
|
||||
// if (value & 0x0002) {
|
||||
// // 10MBit mode
|
||||
// LPC_ETHERNET->SUPP = 0;
|
||||
// }
|
||||
// else {
|
||||
// // 100MBit mode
|
||||
// LPC_ETHERNET->SUPP = SUPP_SPEED;
|
||||
// }
|
||||
break;
|
||||
|
||||
case LAN8720_ID:
|
||||
|
||||
regv = read_PHY (PHY_REG_SCSR); /* PHY Extended Status Register */
|
||||
// Now configure for full/half duplex mode
|
||||
if (regv & (1<<4)) { /* bit 4: 1 = Full Duplex, 0 = Half Duplex */
|
||||
// We are in full duplex is enabled mode
|
||||
LPC_ETHERNET->MAC_CONFIG |= MAC_DUPMODE;
|
||||
}
|
||||
|
||||
// Now configure 100MBit or 10MBit mode
|
||||
if (regv & (1<<3)) { /* bit 3: 1 = 100Mbps, 0 = 10Mbps */
|
||||
// 100MBit mode
|
||||
LPC_ETHERNET->MAC_CONFIG |= MAC_100MPS;
|
||||
}
|
||||
|
||||
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
/* Set the Ethernet MAC Address registers */
|
||||
LPC_ETHERNET->MAC_ADDR0_HIGH = (MYMAC_6 << 8) | MYMAC_5;
|
||||
LPC_ETHERNET->MAC_ADDR0_LOW = (MYMAC_4 << 24) | (MYMAC_3 << 16) | (MYMAC_2 << 8) | MYMAC_1;
|
||||
|
||||
/* Initialize Descriptor Lists */
|
||||
rx_descr_init();
|
||||
tx_descr_init();
|
||||
|
||||
/* Configure Filter */
|
||||
LPC_ETHERNET->MAC_FRAME_FILTER = MAC_PROMISCUOUS | MAC_RECEIVEALL;
|
||||
|
||||
/* Enable Receiver and Transmitter */
|
||||
LPC_ETHERNET->MAC_CONFIG |= (MAC_TX_ENABLE | MAC_RX_ENABLE);
|
||||
|
||||
/* Enable interrupts */
|
||||
//LPC_ETHERNET->DMA_INT_EN = DMA_INT_NOR_SUM | DMA_INT_RECEIVE | DMA_INT_TRANSMIT;
|
||||
|
||||
/* Start Transmission & Receive processes */
|
||||
LPC_ETHERNET->DMA_OP_MODE |= (DMA_SS_TRANSMIT | DMA_SS_RECEIVE );
|
||||
|
||||
}
|
||||
|
||||
|
||||
// reads a word in little-endian byte order from RX_BUFFER
|
||||
|
||||
unsigned short ReadFrame_EMAC(void)
|
||||
{
|
||||
return (*rptr++);
|
||||
}
|
||||
|
||||
|
||||
// easyWEB internal function
|
||||
// help function to swap the byte order of a WORD
|
||||
|
||||
unsigned short SwapBytes(unsigned short Data)
|
||||
{
|
||||
return (Data >> 8) | (Data << 8);
|
||||
}
|
||||
|
||||
// reads a word in big-endian byte order from RX_FRAME_PORT
|
||||
// (useful to avoid permanent byte-swapping while reading
|
||||
// TCP/IP-data)
|
||||
|
||||
unsigned short ReadFrameBE_EMAC(void)
|
||||
{
|
||||
unsigned short ReturnValue;
|
||||
|
||||
ReturnValue = SwapBytes (*rptr++);
|
||||
return (ReturnValue);
|
||||
}
|
||||
|
||||
|
||||
// copies bytes from frame port to MCU-memory
|
||||
// NOTES: * an odd number of byte may only be transfered
|
||||
// if the frame is read to the end!
|
||||
// * MCU-memory MUST start at word-boundary
|
||||
|
||||
void CopyFromFrame_EMAC(void *Dest, unsigned short Size)
|
||||
{
|
||||
unsigned short * piDest; // Keil: Pointer added to correct expression
|
||||
|
||||
piDest = Dest; // Keil: Line added
|
||||
while (Size > 1) {
|
||||
*piDest++ = ReadFrame_EMAC();
|
||||
Size -= 2;
|
||||
}
|
||||
|
||||
if (Size) { // check for leftover byte...
|
||||
*(unsigned char *)piDest = (char)ReadFrame_EMAC();// the LAN-Controller will return 0
|
||||
} // for the highbyte
|
||||
}
|
||||
|
||||
// does a dummy read on frame-I/O-port
|
||||
// NOTE: only an even number of bytes is read!
|
||||
|
||||
void DummyReadFrame_EMAC(unsigned short Size) // discards an EVEN number of bytes
|
||||
{ // from RX-fifo
|
||||
while (Size > 1) {
|
||||
ReadFrame_EMAC();
|
||||
Size -= 2;
|
||||
}
|
||||
}
|
||||
|
||||
// Reads the length of the received ethernet frame and checks if the
|
||||
// destination address is a broadcast message or not
|
||||
// returns the frame length
|
||||
unsigned short StartReadFrame(void) {
|
||||
unsigned short RxLen;
|
||||
|
||||
if ((RX_DESC_STAT(RxDescIndex) & OWN_BIT) == 0) {
|
||||
RxLen = (RX_DESC_STAT(RxDescIndex) >> 16) & 0x03FFF;
|
||||
rptr = (unsigned short *)RX_BUFADDR(RxDescIndex);
|
||||
return(RxLen);
|
||||
}
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
void EndReadFrame(void) {
|
||||
|
||||
RX_DESC_STAT(RxDescIndex) = OWN_BIT;
|
||||
RxDescIndex++;
|
||||
if (RxDescIndex == NUM_RX_DESC)
|
||||
RxDescIndex = 0;
|
||||
}
|
||||
|
||||
unsigned int CheckFrameReceived(void) { // Packet received ?
|
||||
|
||||
if ((RX_DESC_STAT(RxDescIndex) & OWN_BIT) == 0)
|
||||
return(1);
|
||||
else
|
||||
return(0);
|
||||
}
|
||||
|
||||
// requests space in EMAC memory for storing an outgoing frame
|
||||
|
||||
void RequestSend(unsigned short FrameSize)
|
||||
{
|
||||
tptr = (unsigned short *)TX_BUFADDR(TxDescIndex);
|
||||
TX_DESC_CTRL(TxDescIndex) = FrameSize;
|
||||
}
|
||||
|
||||
// check if ethernet controller is ready to accept the
|
||||
// frame we want to send
|
||||
|
||||
unsigned int Rdy4Tx(void)
|
||||
{
|
||||
return (1); // the ethernet controller transmits much faster
|
||||
} // than the CPU can load its buffers
|
||||
|
||||
|
||||
// writes a word in little-endian byte order to TX_BUFFER
|
||||
void WriteFrame_EMAC(unsigned short Data)
|
||||
{
|
||||
*tptr++ = Data;
|
||||
}
|
||||
|
||||
// copies bytes from MCU-memory to frame port
|
||||
// NOTES: * an odd number of byte may only be transfered
|
||||
// if the frame is written to the end!
|
||||
// * MCU-memory MUST start at word-boundary
|
||||
|
||||
void CopyToFrame_EMAC(void *Source, unsigned int Size)
|
||||
{
|
||||
unsigned short * piSource;
|
||||
// unsigned int idx;
|
||||
|
||||
piSource = Source;
|
||||
Size = (Size + 1) & 0xFFFE; // round Size up to next even number
|
||||
while (Size > 0) {
|
||||
WriteFrame_EMAC(*piSource++);
|
||||
Size -= 2;
|
||||
}
|
||||
TX_DESC_STAT(TxDescIndex) |= OWN_BIT;
|
||||
LPC_ETHERNET->DMA_TRANS_POLL_DEMAND = 1; // Wake Up the DMA if it's in Suspended Mode
|
||||
TxDescIndex++;
|
||||
if (TxDescIndex == NUM_TX_DESC)
|
||||
TxDescIndex = 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,157 +0,0 @@
|
||||
#ifndef __EMAC_H
|
||||
#define __EMAC_H
|
||||
|
||||
|
||||
/* Configuration */
|
||||
|
||||
/* Interface Selection */
|
||||
#define MII 0 // =0 RMII - =1 MII
|
||||
|
||||
/* MAC Configuration */
|
||||
#define MYMAC_1 0x1EU /* our ethernet (MAC) address */
|
||||
#define MYMAC_2 0x30U /* (MUST be unique in LAN!) */
|
||||
#define MYMAC_3 0x6cU
|
||||
#define MYMAC_4 0xa2U
|
||||
#define MYMAC_5 0x45U
|
||||
#define MYMAC_6 0x5eU
|
||||
|
||||
|
||||
#define ETH_FRAG_SIZE 1536
|
||||
#define NUM_RX_DESC 3
|
||||
#define NUM_TX_DESC 3
|
||||
|
||||
/* End of Configuration */
|
||||
|
||||
|
||||
/* EMAC Descriptors and Buffers located in 16K SRAM */
|
||||
/* Rx Descriptors */
|
||||
#define RX_DESC_BASE 0x20008000
|
||||
#define RX_STAT_BASE RX_DESC_BASE
|
||||
#define RX_CTRL_BASE (RX_STAT_BASE + 4)
|
||||
#define RX_BUFADDR_BASE (RX_CTRL_BASE + 4)
|
||||
#define RX_NEXTDESC_BASE (RX_BUFADDR_BASE + 4)
|
||||
#define RX_BUF_BASE (RX_DESC_BASE + NUM_RX_DESC*16)
|
||||
|
||||
#define RX_DESC_STAT(i) (*(unsigned int *)(RX_STAT_BASE + 16*i))
|
||||
#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_CTRL_BASE + 16*i))
|
||||
#define RX_BUFADDR(i) (*(unsigned int *)(RX_BUFADDR_BASE + 16*i))
|
||||
#define RX_NEXTDESC(i) (*(unsigned int *)(RX_NEXTDESC_BASE + 16*i))
|
||||
#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)
|
||||
|
||||
/* Tx Descriptors */
|
||||
#define TX_DESC_BASE RX_BUF_BASE + (ETH_FRAG_SIZE * NUM_RX_DESC)
|
||||
#define TX_STAT_BASE TX_DESC_BASE
|
||||
#define TX_CTRL_BASE (TX_STAT_BASE + 4)
|
||||
#define TX_BUFADDR_BASE (TX_CTRL_BASE + 4)
|
||||
#define TX_NEXTDESC_BASE (TX_BUFADDR_BASE + 4)
|
||||
#define TX_BUF_BASE (TX_DESC_BASE + NUM_TX_DESC*16)
|
||||
|
||||
#define TX_DESC_STAT(i) (*(unsigned int *)(TX_STAT_BASE + 16*i))
|
||||
#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_CTRL_BASE + 16*i))
|
||||
#define TX_BUFADDR(i) (*(unsigned int *)(TX_BUFADDR_BASE + 16*i))
|
||||
#define TX_NEXTDESC(i) (*(unsigned int *)(TX_NEXTDESC_BASE + 16*i))
|
||||
#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i)
|
||||
|
||||
/* Descriptors Fields bits */
|
||||
#define OWN_BIT (1U<<31) /* Own bit in RDES0 & TDES0 */
|
||||
#define RX_END_RING (1<<15) /* Receive End of Ring bit in RDES1 */
|
||||
#define RX_NXTDESC_FLAG (1<<14) /* Second Address Chained bit in RDES1 */
|
||||
#define TX_LAST_SEGM (1<<29) /* Last Segment bit in TDES0 */
|
||||
#define TX_FIRST_SEGM (1<<28) /* First Segment bit in TDES0 */
|
||||
#define TX_END_RING (1<<21) /* Transmit End of Ring bit in TDES0 */
|
||||
#define TX_NXTDESC_FLAG (1<<20) /* Second Address Chained bit in TDES0 */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* EMAC Control and Status bits */
|
||||
#define MAC_RX_ENABLE (1<<2) /* Receiver Enable in MAC_CONFIG reg */
|
||||
#define MAC_TX_ENABLE (1<<3) /* Transmitter Enable in MAC_CONFIG reg */
|
||||
#define MAC_PADCRC_STRIP (1<<7) /* Automatic Pad-CRC Stripping in MAC_CONFIG reg */
|
||||
#define MAC_DUPMODE (1<<11) /* Duplex Mode in MAC_CONFIG reg */
|
||||
#define MAC_100MPS (1<<14) /* Speed is 100Mbps in MAC_CONFIG reg */
|
||||
#define MAC_PROMISCUOUS (1U<<0) /* Promiscuous Mode bit in MAC_FRAME_FILTER reg */
|
||||
#define MAC_DIS_BROAD (1U<<5) /* Disable Broadcast Frames bit in MAC_FRAME_FILTER reg */
|
||||
#define MAC_RECEIVEALL (1U<<31) /* Receive All bit in MAC_FRAME_FILTER reg */
|
||||
#define DMA_SOFT_RESET 0x01 /* Software Reset bit in DMA_BUS_MODE reg */
|
||||
#define DMA_SS_RECEIVE (1<<1) /* Start/Stop Receive bit in DMA_OP_MODE reg */
|
||||
#define DMA_SS_TRANSMIT (1<<13) /* Start/Stop Transmission bit in DMA_OP_MODE reg */
|
||||
#define DMA_INT_TRANSMIT (1<<0) /* Transmit Interrupt Enable bit in DMA_INT_EN reg */
|
||||
#define DMA_INT_OVERFLOW (1<<4) /* Overflow Interrupt Enable bit in DMA_INT_EN reg */
|
||||
#define DMA_INT_UNDERFLW (1<<5) /* Underflow Interrupt Enable bit in DMA_INT_EN reg */
|
||||
#define DMA_INT_RECEIVE (1<<6) /* Receive Interrupt Enable bit in DMA_INT_EN reg */
|
||||
#define DMA_INT_ABN_SUM (1<<15) /* Abnormal Interrupt Summary Enable bit in DMA_INT_EN reg */
|
||||
#define DMA_INT_NOR_SUM (1<<16) /* Normal Interrupt Summary Enable bit in DMA_INT_EN reg */
|
||||
|
||||
/* MII Management Command Register */
|
||||
#define GMII_READ (0<<1) /* GMII Read PHY */
|
||||
#define GMII_WRITE (1<<1) /* GMII Write PHY */
|
||||
#define GMII_BUSY 0x00000001 /* GMII is Busy / Start Read/Write */
|
||||
#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
|
||||
#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
|
||||
|
||||
/* MII Management Address Register */
|
||||
#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
|
||||
|
||||
/* DP83848C PHY Registers */
|
||||
#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
|
||||
#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
|
||||
#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
|
||||
#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
|
||||
#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
|
||||
#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
|
||||
#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
|
||||
#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
|
||||
|
||||
/* PHY Extended Registers */
|
||||
#define PHY_REG_STS 0x10 /* Status Register */
|
||||
#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
|
||||
#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
|
||||
#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
|
||||
#define PHY_REG_RECR 0x15 /* Receive Error Counter */
|
||||
#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
|
||||
#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
|
||||
#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
|
||||
#define PHY_REG_PHYCR 0x19 /* PHY Control Register */
|
||||
#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
|
||||
#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
|
||||
#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
|
||||
|
||||
/* PHY Control and Status bits */
|
||||
#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
|
||||
#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
|
||||
#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
|
||||
#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
|
||||
#define PHY_AUTO_NEG 0x1000 /* Select Auto Negotiation */
|
||||
#define PHY_AUTO_NEG_DONE 0x0020 /* AutoNegotiation Complete in BMSR PHY reg */
|
||||
#define PHY_BMCR_RESET 0x8000 /* Reset bit at BMCR PHY reg */
|
||||
#define LINK_VALID_STS 0x0001 /* Link Valid Status at REG_STS PHY reg */
|
||||
#define FULL_DUP_STS 0x0004 /* Full Duplex Status at REG_STS PHY reg */
|
||||
#define SPEED_10M_STS 0x0002 /* 10Mbps Status at REG_STS PHY reg */
|
||||
|
||||
#define DP83848C_DEF_ADR 0x01 /* Default PHY device address */
|
||||
#define DP83848C_ID 0x20005C90 /* PHY Identifier (without Rev. info */
|
||||
|
||||
#define LAN8720_ID 0x0007C0F0 /* PHY Identifier */
|
||||
#define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */
|
||||
|
||||
/* Misc */
|
||||
#define ETHERNET_RST 22 /* Reset Output for EMAC at RGU */
|
||||
#define RMII_SELECT 0x04 /* Select RMII in EMACCFG */
|
||||
|
||||
|
||||
/* Prototypes */
|
||||
void Init_EMAC(void);
|
||||
unsigned short ReadFrameBE_EMAC(void);
|
||||
void CopyToFrame_EMAC(void *Source, unsigned int Size);
|
||||
void CopyFromFrame_EMAC(void *Dest, unsigned short Size);
|
||||
void DummyReadFrame_EMAC(unsigned short Size);
|
||||
unsigned short StartReadFrame(void);
|
||||
void EndReadFrame(void);
|
||||
unsigned int CheckFrameReceived(void);
|
||||
void RequestSend(unsigned short FrameSize);
|
||||
unsigned int Rdy4Tx(void);
|
||||
|
||||
|
||||
#endif
|
||||
@@ -1,546 +0,0 @@
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright(C) 2011, Embedded Artists AB
|
||||
* All rights reserved.
|
||||
*
|
||||
******************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* Embedded Artists AB assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. Embedded Artists AB
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. Embedded Artists AB also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Includes
|
||||
*****************************************************************************/
|
||||
#include "../board.h"
|
||||
|
||||
#if BOARD == BOARD_EA4357
|
||||
|
||||
#include "lpc_types.h"
|
||||
#include "lpc43xx_scu.h"
|
||||
#include "lpc43xx_timer.h"
|
||||
#include "nand.h"
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Defines and typedefs
|
||||
*****************************************************************************/
|
||||
|
||||
#define K9F1G_CLE ((volatile uint8_t *)0x1D100000)
|
||||
#define K9F1G_ALE ((volatile uint8_t *)0x1D080000)
|
||||
#define K9F1G_DATA ((volatile uint8_t *)0x1D000000)
|
||||
|
||||
#define K9FXX_WAIT()
|
||||
|
||||
#define K9FXX_READ_1 0x00
|
||||
#define K9FXX_READ_2 0x30
|
||||
|
||||
#define K9FXX_SET_ADDR_A 0x00
|
||||
#define K9FXX_SET_ADDR_B 0x01
|
||||
#define K9FXX_SET_ADDR_C 0x50
|
||||
#define K9FXX_READ_ID 0x90
|
||||
#define K9FXX_RESET 0xff
|
||||
#define K9FXX_BLOCK_PROGRAM_1 0x80
|
||||
#define K9FXX_BLOCK_PROGRAM_2 0x10
|
||||
#define K9FXX_BLOCK_ERASE_1 0x60
|
||||
#define K9FXX_BLOCK_ERASE_2 0xd0
|
||||
#define K9FXX_READ_STATUS 0x70
|
||||
#define K9FXX_BUSY (1 << 6)
|
||||
#define K9FXX_OK (1 << 0)
|
||||
|
||||
#define ID_MARKER_CODE (0xEC)
|
||||
#define ID_SAMSUNG (0xF1)
|
||||
|
||||
#define ID_PAGE_SZ_1KB (0x00)
|
||||
#define ID_PAGE_SZ_2KB (0x01)
|
||||
#define ID_PAGE_SZ_4KB (0x02)
|
||||
#define ID_PAGE_SZ_8KB (0x03)
|
||||
|
||||
#define ID_BLOCK_SZ_64KB (0x00)
|
||||
#define ID_BLOCK_SZ_128KB (0x01)
|
||||
#define ID_BLOCK_SZ_256KB (0x02)
|
||||
#define ID_BLOCK_SZ_512KB (0x03)
|
||||
|
||||
#define ID_PAGE_SZ_1KB (0x00)
|
||||
#define ID_PAGE_SZ_2KB (0x01)
|
||||
#define ID_PAGE_SZ_4KB (0x02)
|
||||
#define ID_PAGE_SZ_8KB (0x03)
|
||||
|
||||
#define ID_REDUND_SZ_8 (0x00)
|
||||
#define ID_REDUND_SZ_16 (0x01)
|
||||
|
||||
|
||||
|
||||
/* This macro could be changed to check the ready pin */
|
||||
#define WAIT_READY() (TIM_Waitus(25))
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* External global variables
|
||||
*****************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
* Local variables
|
||||
*****************************************************************************/
|
||||
|
||||
static uint32_t pageSize = 0;
|
||||
static uint32_t blockSize = 0;
|
||||
static uint32_t reduntSize = 0;
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Local Functions
|
||||
*****************************************************************************/
|
||||
|
||||
static void pinConfig(void)
|
||||
{
|
||||
/* Set up EMC pin */
|
||||
scu_pinmux( 2 , 9 , MD_PLN_FAST , 3 );//A0
|
||||
scu_pinmux( 2 , 10 , MD_PLN_FAST , 3 );//A1
|
||||
scu_pinmux( 2 , 11 , MD_PLN_FAST , 3 );//A2
|
||||
scu_pinmux( 2 , 12 , MD_PLN_FAST , 3 );//A3
|
||||
scu_pinmux( 2 , 13 , MD_PLN_FAST , 3 );//A4
|
||||
scu_pinmux( 1 , 0 , MD_PLN_FAST , 2 );//A5
|
||||
scu_pinmux( 1 , 1 , MD_PLN_FAST , 2 );//A6
|
||||
scu_pinmux( 1 , 2 , MD_PLN_FAST , 2 );//A7
|
||||
scu_pinmux( 2 , 8 , MD_PLN_FAST , 3 );//A8
|
||||
scu_pinmux( 2 , 7 , MD_PLN_FAST , 3 );//A9
|
||||
scu_pinmux( 2 , 6 , MD_PLN_FAST , 2 );//A10
|
||||
scu_pinmux( 2 , 2 , MD_PLN_FAST , 2 );//A11
|
||||
scu_pinmux( 2 , 1 , MD_PLN_FAST , 2 );//A12
|
||||
scu_pinmux( 2 , 0 , MD_PLN_FAST , 2 );//A13
|
||||
scu_pinmux( 6 , 8 , MD_PLN_FAST , 1 );//A14
|
||||
scu_pinmux( 6 , 7 , MD_PLN_FAST , 1 );//A15
|
||||
scu_pinmux( 13 , 16 , MD_PLN_FAST , 2 );//A16
|
||||
scu_pinmux( 13 , 15 , MD_PLN_FAST , 2 );//A17
|
||||
scu_pinmux( 14 , 0 , MD_PLN_FAST , 3 );//A18
|
||||
scu_pinmux( 14 , 1 , MD_PLN_FAST , 3 );//A19
|
||||
scu_pinmux( 14 , 2 , MD_PLN_FAST , 3 );//A20
|
||||
scu_pinmux( 14 , 3 , MD_PLN_FAST , 3 );//A21
|
||||
scu_pinmux( 14 , 4 , MD_PLN_FAST , 3 );//A22
|
||||
scu_pinmux( 10 , 4 , MD_PLN_FAST , 3 );//A23
|
||||
|
||||
scu_pinmux( 1 , 7 , MD_PLN_FAST , 3 );//D0
|
||||
scu_pinmux( 1 , 8 , MD_PLN_FAST , 3 );//D1
|
||||
scu_pinmux( 1 , 9 , MD_PLN_FAST , 3 );//D2
|
||||
scu_pinmux( 1 , 10 , MD_PLN_FAST , 3 );//D3
|
||||
scu_pinmux( 1 , 11 , MD_PLN_FAST , 3 );//D4
|
||||
scu_pinmux( 1 , 12 , MD_PLN_FAST , 3 );//D5
|
||||
scu_pinmux( 1 , 13 , MD_PLN_FAST , 3 );//D6
|
||||
scu_pinmux( 1 , 14 , MD_PLN_FAST , 3 );//D7
|
||||
scu_pinmux( 5 , 4 , MD_PLN_FAST , 2 );//D8
|
||||
scu_pinmux( 5 , 5 , MD_PLN_FAST , 2 );//D9
|
||||
scu_pinmux( 5 , 6 , MD_PLN_FAST , 2 );//D10
|
||||
scu_pinmux( 5 , 7 , MD_PLN_FAST , 2 );//D11
|
||||
scu_pinmux( 5 , 0 , MD_PLN_FAST , 2 );//D12
|
||||
scu_pinmux( 5 , 1 , MD_PLN_FAST , 2 );//D13
|
||||
scu_pinmux( 5 , 2 , MD_PLN_FAST , 2 );//D14
|
||||
scu_pinmux( 5 , 3 , MD_PLN_FAST , 2 );//D15
|
||||
scu_pinmux( 13 , 2 , MD_PLN_FAST , 2 );//D16
|
||||
scu_pinmux( 13 , 3 , MD_PLN_FAST , 2 );//D17
|
||||
scu_pinmux( 13 , 4 , MD_PLN_FAST , 2 );//D18
|
||||
scu_pinmux( 13 , 5 , MD_PLN_FAST , 2 );//D19
|
||||
scu_pinmux( 13 , 6 , MD_PLN_FAST , 2 );//D20
|
||||
scu_pinmux( 13 , 7 , MD_PLN_FAST , 2 );//D21
|
||||
scu_pinmux( 13 , 8 , MD_PLN_FAST , 2 );//D22
|
||||
scu_pinmux( 13 , 9 , MD_PLN_FAST , 2 );//D23
|
||||
scu_pinmux( 14 , 5 , MD_PLN_FAST , 3 );//D24
|
||||
scu_pinmux( 14 , 6 , MD_PLN_FAST , 3 );//D25
|
||||
scu_pinmux( 14 , 7 , MD_PLN_FAST , 3 );//D26
|
||||
scu_pinmux( 14 , 8 , MD_PLN_FAST , 3 );//D27
|
||||
scu_pinmux( 14 , 9 , MD_PLN_FAST , 3 );//D28
|
||||
scu_pinmux( 14 , 10 , MD_PLN_FAST , 3 );//D29
|
||||
scu_pinmux( 14 , 11 , MD_PLN_FAST , 3 );//D30
|
||||
scu_pinmux( 14 , 12 , MD_PLN_FAST , 3 );//D31
|
||||
|
||||
scu_pinmux( 1 , 3 , MD_PLN_FAST , 3 );//OE
|
||||
scu_pinmux( 1 , 6 , MD_PLN_FAST , 3 );//WE
|
||||
|
||||
scu_pinmux( 1 , 4 , MD_PLN_FAST , 3 );//BLS0
|
||||
scu_pinmux( 6 , 6 , MD_PLN_FAST , 1 );//BLS1
|
||||
scu_pinmux( 13 , 13 , MD_PLN_FAST , 2 );//BLS2
|
||||
scu_pinmux( 13 , 10 , MD_PLN_FAST , 2 );//BLS3
|
||||
|
||||
scu_pinmux( 1 , 5 , MD_PLN_FAST , 3 );//CS0
|
||||
scu_pinmux( 6 , 3 , MD_PLN_FAST , 3 );//CS1
|
||||
scu_pinmux( 13 , 12 , MD_PLN_FAST , 2 );//CS2
|
||||
scu_pinmux( 13 , 11 , MD_PLN_FAST , 2 );//CS3
|
||||
}
|
||||
|
||||
|
||||
static uint32_t nandReadId(void)
|
||||
{
|
||||
uint8_t a, b, c, d;
|
||||
volatile uint8_t *pCLE;
|
||||
volatile uint8_t *pALE;
|
||||
volatile uint8_t *pData;
|
||||
|
||||
pCLE = K9F1G_CLE;
|
||||
pALE = K9F1G_ALE;
|
||||
pData = K9F1G_DATA;
|
||||
|
||||
*pCLE = K9FXX_READ_ID;
|
||||
*pALE = 0;
|
||||
|
||||
a = *pData;
|
||||
b = *pData;
|
||||
c = *pData;
|
||||
d = *pData;
|
||||
|
||||
|
||||
return (a << 24) | (b << 16) | (c << 8) | d;
|
||||
}
|
||||
|
||||
static uint8_t nandStatus(void)
|
||||
{
|
||||
uint8_t status = 0;
|
||||
volatile uint8_t *pCLE;
|
||||
volatile uint8_t *pALE;
|
||||
volatile uint8_t *pData;
|
||||
|
||||
pCLE = K9F1G_CLE;
|
||||
pALE = K9F1G_ALE;
|
||||
pData = K9F1G_DATA;
|
||||
|
||||
*pCLE = K9FXX_READ_STATUS;
|
||||
*pALE = 0;
|
||||
|
||||
status = *pData;
|
||||
|
||||
/* remove bits not used */
|
||||
return (status & 0xC1);
|
||||
}
|
||||
|
||||
static void nandWaitReady(void)
|
||||
{
|
||||
while( !(nandStatus() & (1<<6)) );
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Public Functions
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Initialize the NAND Flash
|
||||
*
|
||||
* Returns:
|
||||
* TRUE if initialization successful; otherwise FALSE
|
||||
*
|
||||
*****************************************************************************/
|
||||
uint32_t nand_init (void)
|
||||
{
|
||||
uint32_t nandId = 0;
|
||||
TIM_TIMERCFG_Type timerCfg;
|
||||
|
||||
// LPC_SC->PCONP |= 0x00000800;
|
||||
LPC_EMC->CONTROL = 0x00000001;
|
||||
LPC_EMC->CONFIG = 0x00000000;
|
||||
|
||||
pinConfig();
|
||||
|
||||
TIM_ConfigStructInit(TIM_TIMER_MODE, &timerCfg);
|
||||
TIM_Init(LPC_TIMER0, TIM_TIMER_MODE, &timerCfg);
|
||||
|
||||
LPC_EMC->STATICCONFIG1 = 0x00000080;
|
||||
|
||||
LPC_EMC->STATICWAITWEN1 = 0x00000002;
|
||||
LPC_EMC->STATICWAITOEN1 = 0x00000002;
|
||||
LPC_EMC->STATICWAITRD1 = 0x00000008;
|
||||
LPC_EMC->STATICWAITPAG1 = 0x0000001f;
|
||||
LPC_EMC->STATICWAITWR1 = 0x00000008;
|
||||
LPC_EMC->STATICWAITTURN1 = 0x0000000f;
|
||||
|
||||
nandId = nandReadId();
|
||||
|
||||
if ((nandId & 0xffff0000) !=
|
||||
(((uint32_t)(ID_MARKER_CODE) << 24) | ID_SAMSUNG << 16)) {
|
||||
/* unknown NAND chip */
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
pageSize = 1024 * (1 << (nandId & 0x03));
|
||||
blockSize = 64*1024 * (1 << ((nandId>>4) & 0x03));
|
||||
reduntSize = 8 * (1 << ((nandId >> 1) & 0x1));
|
||||
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Get the page size of the NAND flash
|
||||
*
|
||||
* Returns:
|
||||
* page size in bytes
|
||||
*
|
||||
*****************************************************************************/
|
||||
uint32_t nand_getPageSize(void)
|
||||
{
|
||||
return pageSize;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Get the block size of the NAND flash
|
||||
*
|
||||
* Returns:
|
||||
* block size in bytes
|
||||
*
|
||||
*****************************************************************************/
|
||||
uint32_t nand_getBlockSize(void)
|
||||
{
|
||||
return blockSize;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Get the redundant (spare) size per page
|
||||
*
|
||||
* Returns:
|
||||
* redundant/spare size in bytes
|
||||
*
|
||||
*****************************************************************************/
|
||||
uint32_t nand_getRedundantSize(void)
|
||||
{
|
||||
return reduntSize * (pageSize/512);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Check if a block is valid
|
||||
*
|
||||
* Returns:
|
||||
* TRUE if the block is valid; otherwise FALSE
|
||||
*
|
||||
*****************************************************************************/
|
||||
uint32_t nand_isBlockValid(uint32_t block)
|
||||
{
|
||||
uint32_t addr = 0;
|
||||
uint32_t page = 0;
|
||||
|
||||
volatile uint8_t *pCLE;
|
||||
volatile uint8_t *pALE;
|
||||
volatile uint8_t *pData;
|
||||
|
||||
|
||||
pCLE = K9F1G_CLE;
|
||||
pALE = K9F1G_ALE;
|
||||
pData = K9F1G_DATA;
|
||||
|
||||
if (block >= NAND_NUM_BLOCKS) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
addr = block * (blockSize/pageSize);
|
||||
|
||||
/*
|
||||
* Check page 0 and page 1 in each block. If the first byte
|
||||
* in the spare area (of either page 0 or page 1) is != 0xFF
|
||||
* the block is invalid.
|
||||
*/
|
||||
|
||||
nandWaitReady();
|
||||
|
||||
for (page = 0; page < 2; page++) {
|
||||
addr += page;
|
||||
|
||||
*pCLE = K9FXX_READ_1;
|
||||
*pALE = (uint8_t) (pageSize & 0x00FF);
|
||||
*pALE = (uint8_t)((pageSize & 0xFF00) >> 8);
|
||||
*pALE = (uint8_t)((addr & 0x00FF));
|
||||
*pALE = (uint8_t)((addr & 0xFF00) >> 8);
|
||||
*pCLE = K9FXX_READ_2;
|
||||
|
||||
WAIT_READY();
|
||||
|
||||
if (*pData != 0xFF) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Read a page from the NAND memory
|
||||
*
|
||||
* Params:
|
||||
* block - block number to read from
|
||||
* page - page with�n block to read from
|
||||
* pageBuf - data is copied to this buffer. The size must be at least
|
||||
* pageSize.
|
||||
*
|
||||
* Returns:
|
||||
* TRUE if read successful; otherwise FALSE
|
||||
*
|
||||
*****************************************************************************/
|
||||
uint32_t nand_readPage(uint32_t block, uint32_t page, uint8_t* pageBuf)
|
||||
{
|
||||
uint32_t i = 0;
|
||||
uint32_t addr = 0;
|
||||
|
||||
volatile uint8_t *pCLE;
|
||||
volatile uint8_t *pALE;
|
||||
volatile uint8_t *pData;
|
||||
|
||||
|
||||
pCLE = K9F1G_CLE;
|
||||
pALE = K9F1G_ALE;
|
||||
pData = K9F1G_DATA;
|
||||
|
||||
if (block >= NAND_NUM_BLOCKS) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if (page >= blockSize/pageSize) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
addr = block * (blockSize/pageSize) + page;
|
||||
|
||||
/*
|
||||
* Always reading from start of a page address.
|
||||
* This means that the column address is always 0.
|
||||
*/
|
||||
|
||||
*pCLE = K9FXX_READ_1;
|
||||
*pALE = 0;
|
||||
*pALE = 0;
|
||||
*pALE = (uint8_t)((addr & 0x00FF));
|
||||
*pALE = (uint8_t)((addr & 0xFF00) >> 8);
|
||||
*pCLE = K9FXX_READ_2;
|
||||
|
||||
WAIT_READY();
|
||||
|
||||
|
||||
for (i = 0; i < pageSize; i++) {
|
||||
*pageBuf++ = *pData;
|
||||
}
|
||||
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Write a page of data to the NAND memory
|
||||
*
|
||||
* Params:
|
||||
* block - block number to write to
|
||||
* page - page within block to write to
|
||||
* pageBuf - data is copied from this buffer. The size must be at least
|
||||
* pageSize.
|
||||
*
|
||||
* Returns:
|
||||
* TRUE if write successful; otherwise FALSE
|
||||
*
|
||||
*****************************************************************************/
|
||||
uint32_t nand_writePage(uint32_t block, uint32_t page, uint8_t* pageBuf)
|
||||
{
|
||||
uint32_t i = 0;
|
||||
uint32_t addr = 0;
|
||||
|
||||
volatile uint8_t *pCLE;
|
||||
volatile uint8_t *pALE;
|
||||
volatile uint8_t *pData;
|
||||
|
||||
|
||||
pCLE = K9F1G_CLE;
|
||||
pALE = K9F1G_ALE;
|
||||
pData = K9F1G_DATA;
|
||||
|
||||
if (block >= NAND_NUM_BLOCKS) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if (page >= blockSize/pageSize) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
addr = block * (blockSize/pageSize) + page;
|
||||
|
||||
/*
|
||||
* Always writing to start of a page address.
|
||||
* This means that the column address is always 0.
|
||||
*/
|
||||
|
||||
*pCLE = K9FXX_BLOCK_PROGRAM_1;
|
||||
*pALE = 0;
|
||||
*pALE = 0;
|
||||
*pALE = (uint8_t)((addr & 0x00FF));
|
||||
*pALE = (uint8_t)((addr & 0xFF00) >> 8);
|
||||
|
||||
|
||||
for (i = 0; i < pageSize; i++) {
|
||||
*pData = *pageBuf++;
|
||||
}
|
||||
|
||||
*pCLE = K9FXX_BLOCK_PROGRAM_2;
|
||||
|
||||
TIM_Waitus(700);
|
||||
nandWaitReady();
|
||||
|
||||
return ((nandStatus() & 0x01) != 0x01);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Erase a block
|
||||
*
|
||||
* Params:
|
||||
* block - block number to erase
|
||||
*
|
||||
* Returns:
|
||||
* TRUE if eras successful; otherwise FALSE
|
||||
*
|
||||
*****************************************************************************/
|
||||
uint32_t nand_eraseBlock(uint32_t block)
|
||||
{
|
||||
uint32_t addr = 0;
|
||||
|
||||
volatile uint8_t *pCLE;
|
||||
volatile uint8_t *pALE;
|
||||
|
||||
pCLE = K9F1G_CLE;
|
||||
pALE = K9F1G_ALE;
|
||||
|
||||
if (block >= NAND_NUM_BLOCKS) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
addr = block * (blockSize/pageSize);
|
||||
|
||||
*pCLE = K9FXX_BLOCK_ERASE_1;
|
||||
*pALE = (uint8_t)(addr & 0x00FF);
|
||||
*pALE = (uint8_t)((addr & 0xFF00) >> 8);
|
||||
*pCLE = K9FXX_BLOCK_ERASE_2;
|
||||
|
||||
TIM_Waitus(700);
|
||||
nandWaitReady();
|
||||
|
||||
return ((nandStatus() & 0x01) != 0x01);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,36 +0,0 @@
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright(C) 2011, Embedded Artists AB
|
||||
* All rights reserved.
|
||||
*
|
||||
******************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* Embedded Artists AB assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. Embedded Artists AB
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. Embedded Artists AB also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
*****************************************************************************/
|
||||
#ifndef __NAND_H
|
||||
#define __NAND_H
|
||||
|
||||
#define NAND_NUM_BLOCKS (1024)
|
||||
|
||||
extern uint32_t nand_init (void);
|
||||
extern uint32_t nand_getPageSize(void);
|
||||
extern uint32_t nand_getBlockSize(void);
|
||||
extern uint32_t nand_getRedundantSize(void);
|
||||
extern uint32_t nand_isBlockValid(uint32_t blockNum);
|
||||
uint32_t nand_readPage(uint32_t block, uint32_t page, uint8_t* pageBuf);
|
||||
uint32_t nand_writePage(uint32_t block, uint32_t page, uint8_t* pageBuf);
|
||||
uint32_t nand_eraseBlock(uint32_t block);
|
||||
|
||||
|
||||
#endif /* end __NAND_H */
|
||||
/****************************************************************************
|
||||
** End Of File
|
||||
*****************************************************************************/
|
||||
@@ -1,254 +0,0 @@
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright(C) 2011, Embedded Artists AB
|
||||
* All rights reserved.
|
||||
*
|
||||
******************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* Embedded Artists AB assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. Embedded Artists AB
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. Embedded Artists AB also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Includes
|
||||
*****************************************************************************/
|
||||
#include "../../board.h"
|
||||
|
||||
#if BOARD == BOARD_EA4357
|
||||
|
||||
#include "lpc_types.h"
|
||||
#include "lpc43xx_i2c.h"
|
||||
#include "acc.h"
|
||||
|
||||
/******************************************************************************
|
||||
* Defines and typedefs
|
||||
*****************************************************************************/
|
||||
#define I2C_PORT (LPC_I2C0)
|
||||
|
||||
#define ACC_I2C_ADDR (0x1D)
|
||||
|
||||
#define ACC_ADDR_XOUTL 0x00
|
||||
#define ACC_ADDR_XOUTH 0x01
|
||||
#define ACC_ADDR_YOUTL 0x02
|
||||
#define ACC_ADDR_YOUTX 0x03
|
||||
#define ACC_ADDR_ZOUTL 0x04
|
||||
#define ACC_ADDR_ZOUTH 0x05
|
||||
#define ACC_ADDR_XOUT8 0x06
|
||||
#define ACC_ADDR_YOUT8 0x07
|
||||
#define ACC_ADDR_ZOUT8 0x08
|
||||
#define ACC_ADDR_STATUS 0x09
|
||||
#define ACC_ADDR_DETSRC 0x0A
|
||||
#define ACC_ADDR_TOUT 0x0B
|
||||
#define ACC_ADDR_I2CAD 0x0D
|
||||
#define ACC_ADDR_USRINF 0x0E
|
||||
#define ACC_ADDR_WHOAMI 0x0F
|
||||
#define ACC_ADDR_XOFFL 0x10
|
||||
#define ACC_ADDR_XOFFH 0x11
|
||||
#define ACC_ADDR_YOFFL 0x12
|
||||
#define ACC_ADDR_YOFFH 0x13
|
||||
#define ACC_ADDR_ZOFFL 0x14
|
||||
#define ACC_ADDR_ZOFFH 0x15
|
||||
#define ACC_ADDR_MCTL 0x16
|
||||
#define ACC_ADDR_INTRST 0x17
|
||||
#define ACC_ADDR_CTL1 0x18
|
||||
#define ACC_ADDR_CTL2 0x19
|
||||
#define ACC_ADDR_LDTH 0x1A
|
||||
#define ACC_ADDR_PDTH 0x1B
|
||||
#define ACC_ADDR_PW 0x1C
|
||||
#define ACC_ADDR_LT 0x1D
|
||||
#define ACC_ADDR_TW 0x1E
|
||||
|
||||
#define ACC_MCTL_MODE(m) ((m) << 0)
|
||||
#define ACC_MCTL_GLVL(g) ((g) << 2)
|
||||
|
||||
|
||||
#define ACC_STATUS_DRDY 0x01
|
||||
#define ACC_STATUS_DOVR 0x02
|
||||
#define ACC_STATUS_PERR 0x04
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* External global variables
|
||||
*****************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
* Local variables
|
||||
*****************************************************************************/
|
||||
|
||||
static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len)
|
||||
{
|
||||
I2C_M_SETUP_Type i2cData;
|
||||
|
||||
i2cData.sl_addr7bit = addr;
|
||||
i2cData.tx_data = buf;
|
||||
i2cData.tx_length = len;
|
||||
i2cData.rx_data = NULL;
|
||||
i2cData.rx_length = 0;
|
||||
i2cData.retransmissions_max = 3;
|
||||
|
||||
return I2C_MasterTransferData(I2C_PORT, &i2cData, I2C_TRANSFER_POLLING);
|
||||
}
|
||||
|
||||
static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len)
|
||||
{
|
||||
I2C_M_SETUP_Type i2cData;
|
||||
|
||||
i2cData.sl_addr7bit = addr;
|
||||
i2cData.tx_data = NULL;
|
||||
i2cData.tx_length = 0;
|
||||
i2cData.rx_data = buf;
|
||||
i2cData.rx_length = len;
|
||||
i2cData.retransmissions_max = 3;
|
||||
|
||||
return I2C_MasterTransferData(I2C_PORT, &i2cData, I2C_TRANSFER_POLLING);
|
||||
}
|
||||
|
||||
|
||||
static uint8_t getStatus(void)
|
||||
{
|
||||
uint8_t buf[1];
|
||||
|
||||
buf[0] = ACC_ADDR_STATUS;
|
||||
I2CWrite(ACC_I2C_ADDR, buf, 1);
|
||||
I2CRead(ACC_I2C_ADDR, buf, 1);
|
||||
|
||||
return buf[0];
|
||||
}
|
||||
|
||||
static uint8_t getModeControl(void)
|
||||
{
|
||||
uint8_t buf[1];
|
||||
|
||||
buf[0] = ACC_ADDR_MCTL;
|
||||
I2CWrite(ACC_I2C_ADDR, buf, 1);
|
||||
I2CRead(ACC_I2C_ADDR, buf, 1);
|
||||
|
||||
return buf[0];
|
||||
}
|
||||
|
||||
static void setModeControl(uint8_t mctl)
|
||||
{
|
||||
uint8_t buf[2];
|
||||
|
||||
buf[0] = ACC_ADDR_MCTL;
|
||||
buf[1] = mctl;
|
||||
I2CWrite(ACC_I2C_ADDR, buf, 2);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Local Functions
|
||||
*****************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
* Public Functions
|
||||
*****************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Initialize the ISL29003 Device
|
||||
*
|
||||
*****************************************************************************/
|
||||
void acc_init (void)
|
||||
{
|
||||
|
||||
/* set to measurement mode by default */
|
||||
|
||||
setModeControl( (ACC_MCTL_MODE(ACC_MODE_MEASURE)
|
||||
| ACC_MCTL_GLVL(ACC_RANGE_2G) ));
|
||||
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Read accelerometer data
|
||||
*
|
||||
* Params:
|
||||
* [out] x - read x value
|
||||
* [out] y - read y value
|
||||
* [out] z - read z value
|
||||
*
|
||||
*****************************************************************************/
|
||||
void acc_read (int8_t *x, int8_t *y, int8_t *z)
|
||||
{
|
||||
uint8_t buf[1];
|
||||
|
||||
/* wait for ready flag */
|
||||
while ((getStatus() & ACC_STATUS_DRDY) == 0);
|
||||
|
||||
/*
|
||||
* Have experienced problems reading all registers
|
||||
* at once. Change to reading them one-by-one.
|
||||
*/
|
||||
buf[0] = ACC_ADDR_XOUT8;
|
||||
I2CWrite(ACC_I2C_ADDR, buf, 1);
|
||||
I2CRead(ACC_I2C_ADDR, buf, 1);
|
||||
|
||||
*x = (int8_t)buf[0];
|
||||
|
||||
buf[0] = ACC_ADDR_YOUT8;
|
||||
I2CWrite(ACC_I2C_ADDR, buf, 1);
|
||||
I2CRead(ACC_I2C_ADDR, buf, 1);
|
||||
|
||||
*y = (int8_t)buf[0];
|
||||
|
||||
buf[0] = ACC_ADDR_ZOUT8;
|
||||
I2CWrite(ACC_I2C_ADDR, buf, 1);
|
||||
I2CRead(ACC_I2C_ADDR, buf, 1);
|
||||
|
||||
*z = (int8_t)buf[0];
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Set the g-Range
|
||||
*
|
||||
* Params:
|
||||
* [in] range - the g-Range
|
||||
*
|
||||
*****************************************************************************/
|
||||
void acc_setRange(acc_range_t range)
|
||||
{
|
||||
uint8_t mctl = 0;
|
||||
|
||||
mctl = getModeControl();
|
||||
|
||||
mctl &= ~(0x03 << 2);
|
||||
mctl |= ACC_MCTL_GLVL(range);
|
||||
|
||||
setModeControl(mctl);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Set sensor mode
|
||||
*
|
||||
* Params:
|
||||
* [in] mode - the mode to set
|
||||
*
|
||||
*****************************************************************************/
|
||||
void acc_setMode(acc_mode_t mode)
|
||||
{
|
||||
uint8_t mctl = 0;
|
||||
|
||||
mctl = getModeControl();
|
||||
|
||||
mctl &= ~(0x03 << 0);
|
||||
mctl |= ACC_MCTL_MODE(mode);
|
||||
|
||||
setModeControl(mctl);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,49 +0,0 @@
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright(C) 2011, Embedded Artists AB
|
||||
* All rights reserved.
|
||||
*
|
||||
******************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* Embedded Artists AB assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. Embedded Artists AB
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. Embedded Artists AB also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
*****************************************************************************/
|
||||
#ifndef __ACC_H
|
||||
#define __ACC_H
|
||||
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ACC_MODE_STANDBY,
|
||||
ACC_MODE_MEASURE,
|
||||
ACC_MODE_LEVEL, /* level detection */
|
||||
ACC_MODE_PULSE, /* pulse detection */
|
||||
} acc_mode_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ACC_RANGE_8G,
|
||||
ACC_RANGE_2G,
|
||||
ACC_RANGE_4G,
|
||||
} acc_range_t;
|
||||
|
||||
|
||||
void acc_init (void);
|
||||
|
||||
void acc_read (int8_t *x, int8_t *y, int8_t *z);
|
||||
void acc_setRange(acc_range_t range);
|
||||
void acc_setMode(acc_mode_t mode);
|
||||
|
||||
|
||||
|
||||
#endif /* end __LIGHT_H */
|
||||
/****************************************************************************
|
||||
** End Of File
|
||||
*****************************************************************************/
|
||||
@@ -1,200 +0,0 @@
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright(C) 2011, Embedded Artists AB
|
||||
* All rights reserved.
|
||||
*
|
||||
******************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* Embedded Artists AB assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. Embedded Artists AB
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. Embedded Artists AB also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
*****************************************************************************/
|
||||
|
||||
/*
|
||||
* NOTE: I2C must have been initialized before calling any functions in this
|
||||
* file.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* Includes
|
||||
*****************************************************************************/
|
||||
#include "../../board.h"
|
||||
|
||||
#if BOARD == BOARD_EA4357
|
||||
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
#include "lpc_types.h"
|
||||
#include "lpc43xx_i2c.h"
|
||||
#include "base_eeprom.h"
|
||||
|
||||
/******************************************************************************
|
||||
* Defines and typedefs
|
||||
*****************************************************************************/
|
||||
|
||||
#define I2C_PORT (LPC_I2C0)
|
||||
|
||||
#ifndef MIN
|
||||
#define MIN(x, y) ((x) < (y) ? (x) : (y))
|
||||
#endif
|
||||
|
||||
#define EEPROM_I2C_ADDR (0x57)
|
||||
|
||||
#define EEPROM_PAGE_SIZE 32
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* External global variables
|
||||
*****************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
* Local variables
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Local Functions
|
||||
*****************************************************************************/
|
||||
|
||||
static void eepromDelay(void)
|
||||
{
|
||||
volatile int i = 0;
|
||||
for (i = 0; i <0x20000; i++);
|
||||
}
|
||||
|
||||
static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len)
|
||||
{
|
||||
I2C_M_SETUP_Type i2cData;
|
||||
|
||||
i2cData.sl_addr7bit = addr;
|
||||
i2cData.tx_data = buf;
|
||||
i2cData.tx_length = len;
|
||||
i2cData.rx_data = NULL;
|
||||
i2cData.rx_length = 0;
|
||||
i2cData.retransmissions_max = 3;
|
||||
|
||||
return I2C_MasterTransferData(I2C_PORT, &i2cData, I2C_TRANSFER_POLLING);
|
||||
}
|
||||
|
||||
static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len)
|
||||
{
|
||||
I2C_M_SETUP_Type i2cData;
|
||||
|
||||
i2cData.sl_addr7bit = addr;
|
||||
i2cData.tx_data = NULL;
|
||||
i2cData.tx_length = 0;
|
||||
i2cData.rx_data = buf;
|
||||
i2cData.rx_length = len;
|
||||
i2cData.retransmissions_max = 3;
|
||||
|
||||
return I2C_MasterTransferData(I2C_PORT, &i2cData, I2C_TRANSFER_POLLING);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Public Functions
|
||||
*****************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Initialize the EEPROM Driver
|
||||
*
|
||||
*****************************************************************************/
|
||||
void base_eeprom_init (void)
|
||||
{
|
||||
I2C_Cmd(I2C_PORT, ENABLE);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Read from the EEPROM
|
||||
*
|
||||
* Params:
|
||||
* [in] buf - read buffer
|
||||
* [in] offset - offset to start to read from
|
||||
* [in] len - number of bytes to read
|
||||
*
|
||||
* Returns:
|
||||
* number of read bytes or -1 in case of an error
|
||||
*
|
||||
*****************************************************************************/
|
||||
int16_t base_eeprom_read(uint8_t* buf, uint16_t offset, uint16_t len)
|
||||
{
|
||||
uint8_t addr = 0;
|
||||
int i = 0;
|
||||
uint8_t off[2];
|
||||
|
||||
if (len > BASE_EEPROM_TOTAL_SIZE || offset+len > BASE_EEPROM_TOTAL_SIZE) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
addr = EEPROM_I2C_ADDR;
|
||||
off[0] = ((offset >> 8) & 0xff);
|
||||
off[1] = (offset & 0xff);
|
||||
|
||||
I2CWrite((addr << 1), off, 2);
|
||||
for ( i = 0; i < 0x2000; i++);
|
||||
I2CRead((addr << 1), buf, len);
|
||||
|
||||
return len;
|
||||
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Write to the EEPROM
|
||||
*
|
||||
* Params:
|
||||
* [in] buf - data to write
|
||||
* [in] offset - offset to start to write to
|
||||
* [in] len - number of bytes to write
|
||||
*
|
||||
* Returns:
|
||||
* number of written bytes or -1 in case of an error
|
||||
*
|
||||
*****************************************************************************/
|
||||
int16_t base_eeprom_write(uint8_t* buf, uint16_t offset, uint16_t len)
|
||||
{
|
||||
uint8_t addr = 0;
|
||||
int16_t written = 0;
|
||||
uint16_t wLen = 0;
|
||||
uint16_t off = offset;
|
||||
uint8_t tmp[EEPROM_PAGE_SIZE+2];
|
||||
|
||||
if (len > BASE_EEPROM_TOTAL_SIZE || offset+len > BASE_EEPROM_TOTAL_SIZE) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
addr = EEPROM_I2C_ADDR;
|
||||
|
||||
wLen = EEPROM_PAGE_SIZE - (off % EEPROM_PAGE_SIZE);
|
||||
wLen = MIN(wLen, len);
|
||||
|
||||
while (len) {
|
||||
tmp[0] = ((off >> 8) & 0xff);
|
||||
tmp[1] = (off & 0xff);
|
||||
memcpy(&tmp[2], (void*)&buf[written], wLen);
|
||||
I2CWrite((addr << 1), tmp, wLen+2);
|
||||
|
||||
/* delay to wait for a write cycle */
|
||||
eepromDelay();
|
||||
|
||||
len -= wLen;
|
||||
written += wLen;
|
||||
off += wLen;
|
||||
|
||||
wLen = MIN(EEPROM_PAGE_SIZE, len);
|
||||
}
|
||||
|
||||
return written;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,31 +0,0 @@
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright(C) 2011, Embedded Artists AB
|
||||
* All rights reserved.
|
||||
*
|
||||
******************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* Embedded Artists AB assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. Embedded Artists AB
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. Embedded Artists AB also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
*****************************************************************************/
|
||||
#ifndef __BASE_EEPROM_H
|
||||
#define __BASE_EEPROM_H
|
||||
|
||||
#define BASE_EEPROM_TOTAL_SIZE 8192
|
||||
|
||||
void base_eeprom_init (void);
|
||||
int16_t base_eeprom_read(uint8_t* buf, uint16_t offset, uint16_t len);
|
||||
int16_t base_eeprom_write(uint8_t* buf, uint16_t offset, uint16_t len);
|
||||
|
||||
|
||||
#endif /* end __BASE_EEPROM_H */
|
||||
/****************************************************************************
|
||||
** End Of File
|
||||
*****************************************************************************/
|
||||
@@ -1,132 +0,0 @@
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright(C) 2011, Embedded Artists AB
|
||||
* All rights reserved.
|
||||
*
|
||||
******************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* Embedded Artists AB assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. Embedded Artists AB
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. Embedded Artists AB also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
*****************************************************************************/
|
||||
|
||||
/*
|
||||
* NOTE: I2C must have been initialized before calling any functions in this
|
||||
* file.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* Includes
|
||||
*****************************************************************************/
|
||||
#include "../../board.h"
|
||||
|
||||
#if BOARD == BOARD_EA4357
|
||||
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
#include "lpc_types.h"
|
||||
#include "lpc43xx_i2c.h"
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Defines and typedefs
|
||||
*****************************************************************************/
|
||||
|
||||
#define I2C_PORT (LPC_I2C0)
|
||||
|
||||
#define LM75A_I2C_ADDR (0x48)
|
||||
|
||||
#define LM75A_CMD_TEMP 0x00
|
||||
|
||||
#define I2CDEV LPC_I2C2
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* External global variables
|
||||
*****************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
* Local variables
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Local Functions
|
||||
*****************************************************************************/
|
||||
static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len)
|
||||
{
|
||||
I2C_M_SETUP_Type i2cData;
|
||||
|
||||
i2cData.sl_addr7bit = addr;
|
||||
i2cData.tx_data = buf;
|
||||
i2cData.tx_length = len;
|
||||
i2cData.rx_data = NULL;
|
||||
i2cData.rx_length = 0;
|
||||
i2cData.retransmissions_max = 3;
|
||||
|
||||
return I2C_MasterTransferData(I2C_PORT, &i2cData, I2C_TRANSFER_POLLING);
|
||||
}
|
||||
|
||||
static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len)
|
||||
{
|
||||
I2C_M_SETUP_Type i2cData;
|
||||
|
||||
i2cData.sl_addr7bit = addr;
|
||||
i2cData.tx_data = NULL;
|
||||
i2cData.tx_length = 0;
|
||||
i2cData.rx_data = buf;
|
||||
i2cData.rx_length = len;
|
||||
i2cData.retransmissions_max = 3;
|
||||
|
||||
return I2C_MasterTransferData(I2C_PORT, &i2cData, I2C_TRANSFER_POLLING);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Public Functions
|
||||
*****************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Initialize the EEPROM Driver
|
||||
*
|
||||
*****************************************************************************/
|
||||
void lm75a_init (void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Read the temperature
|
||||
*
|
||||
* Params: None
|
||||
*
|
||||
* Returns:
|
||||
* The measured temperature x 100, i.e. 26.50 degrees returned as 2650
|
||||
*
|
||||
*****************************************************************************/
|
||||
int32_t lm75a_readTemp(void)
|
||||
{
|
||||
uint8_t temp[2];
|
||||
int16_t t = 0;
|
||||
|
||||
I2CWrite(LM75A_I2C_ADDR, LM75A_CMD_TEMP, 1);
|
||||
I2CRead(LM75A_I2C_ADDR, temp, 2);
|
||||
|
||||
/* 11 MSB bits used. Celcius is calculated as Temp data * 1/8 */
|
||||
t = ((temp[0] << 8) | (temp[1]));
|
||||
|
||||
return ((t * 100) >> 8);
|
||||
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
@@ -1,29 +0,0 @@
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright(C) 2011, Embedded Artists AB
|
||||
* All rights reserved.
|
||||
*
|
||||
******************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* Embedded Artists AB assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. Embedded Artists AB
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. Embedded Artists AB also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
*****************************************************************************/
|
||||
#ifndef __LM75A_H
|
||||
#define __LM75A_H
|
||||
|
||||
|
||||
void lm75a_init (void);
|
||||
int32_t lm75a_readTemp(void);
|
||||
|
||||
|
||||
#endif /* end __LM75A_H */
|
||||
/****************************************************************************
|
||||
** End Of File
|
||||
*****************************************************************************/
|
||||
@@ -1,174 +0,0 @@
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright(C) 2011, Embedded Artists AB
|
||||
* All rights reserved.
|
||||
*
|
||||
******************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* Embedded Artists AB assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. Embedded Artists AB
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. Embedded Artists AB also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Includes
|
||||
*****************************************************************************/
|
||||
#include "../../board.h"
|
||||
|
||||
#if BOARD == BOARD_EA4357
|
||||
|
||||
#include "LPC43xx.h"
|
||||
#include "lpc_types.h"
|
||||
#include "lpc43xx_scu.h"
|
||||
#include "memreg.h"
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Defines and typedefs
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* External global variables
|
||||
*****************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
* Local variables
|
||||
*****************************************************************************/
|
||||
|
||||
static void pinConfig(void)
|
||||
{
|
||||
/* Set up EMC pin */
|
||||
scu_pinmux( 2 , 9 , MD_PLN_FAST , 3 );//A0
|
||||
scu_pinmux( 2 , 10 , MD_PLN_FAST , 3 );//A1
|
||||
scu_pinmux( 2 , 11 , MD_PLN_FAST , 3 );//A2
|
||||
scu_pinmux( 2 , 12 , MD_PLN_FAST , 3 );//A3
|
||||
scu_pinmux( 2 , 13 , MD_PLN_FAST , 3 );//A4
|
||||
scu_pinmux( 1 , 0 , MD_PLN_FAST , 2 );//A5
|
||||
scu_pinmux( 1 , 1 , MD_PLN_FAST , 2 );//A6
|
||||
scu_pinmux( 1 , 2 , MD_PLN_FAST , 2 );//A7
|
||||
scu_pinmux( 2 , 8 , MD_PLN_FAST , 3 );//A8
|
||||
scu_pinmux( 2 , 7 , MD_PLN_FAST , 3 );//A9
|
||||
scu_pinmux( 2 , 6 , MD_PLN_FAST , 2 );//A10
|
||||
scu_pinmux( 2 , 2 , MD_PLN_FAST , 2 );//A11
|
||||
scu_pinmux( 2 , 1 , MD_PLN_FAST , 2 );//A12
|
||||
scu_pinmux( 2 , 0 , MD_PLN_FAST , 2 );//A13
|
||||
scu_pinmux( 6 , 8 , MD_PLN_FAST , 1 );//A14
|
||||
scu_pinmux( 6 , 7 , MD_PLN_FAST , 1 );//A15
|
||||
scu_pinmux( 13 , 16 , MD_PLN_FAST , 2 );//A16
|
||||
scu_pinmux( 13 , 15 , MD_PLN_FAST , 2 );//A17
|
||||
scu_pinmux( 14 , 0 , MD_PLN_FAST , 3 );//A18
|
||||
scu_pinmux( 14 , 1 , MD_PLN_FAST , 3 );//A19
|
||||
scu_pinmux( 14 , 2 , MD_PLN_FAST , 3 );//A20
|
||||
scu_pinmux( 14 , 3 , MD_PLN_FAST , 3 );//A21
|
||||
scu_pinmux( 14 , 4 , MD_PLN_FAST , 3 );//A22
|
||||
scu_pinmux( 10 , 4 , MD_PLN_FAST , 3 );//A23
|
||||
|
||||
scu_pinmux( 1 , 7 , MD_PLN_FAST , 3 );//D0
|
||||
scu_pinmux( 1 , 8 , MD_PLN_FAST , 3 );//D1
|
||||
scu_pinmux( 1 , 9 , MD_PLN_FAST , 3 );//D2
|
||||
scu_pinmux( 1 , 10 , MD_PLN_FAST , 3 );//D3
|
||||
scu_pinmux( 1 , 11 , MD_PLN_FAST , 3 );//D4
|
||||
scu_pinmux( 1 , 12 , MD_PLN_FAST , 3 );//D5
|
||||
scu_pinmux( 1 , 13 , MD_PLN_FAST , 3 );//D6
|
||||
scu_pinmux( 1 , 14 , MD_PLN_FAST , 3 );//D7
|
||||
scu_pinmux( 5 , 4 , MD_PLN_FAST , 2 );//D8
|
||||
scu_pinmux( 5 , 5 , MD_PLN_FAST , 2 );//D9
|
||||
scu_pinmux( 5 , 6 , MD_PLN_FAST , 2 );//D10
|
||||
scu_pinmux( 5 , 7 , MD_PLN_FAST , 2 );//D11
|
||||
scu_pinmux( 5 , 0 , MD_PLN_FAST , 2 );//D12
|
||||
scu_pinmux( 5 , 1 , MD_PLN_FAST , 2 );//D13
|
||||
scu_pinmux( 5 , 2 , MD_PLN_FAST , 2 );//D14
|
||||
scu_pinmux( 5 , 3 , MD_PLN_FAST , 2 );//D15
|
||||
scu_pinmux( 13 , 2 , MD_PLN_FAST , 2 );//D16
|
||||
scu_pinmux( 13 , 3 , MD_PLN_FAST , 2 );//D17
|
||||
scu_pinmux( 13 , 4 , MD_PLN_FAST , 2 );//D18
|
||||
scu_pinmux( 13 , 5 , MD_PLN_FAST , 2 );//D19
|
||||
scu_pinmux( 13 , 6 , MD_PLN_FAST , 2 );//D20
|
||||
scu_pinmux( 13 , 7 , MD_PLN_FAST , 2 );//D21
|
||||
scu_pinmux( 13 , 8 , MD_PLN_FAST , 2 );//D22
|
||||
scu_pinmux( 13 , 9 , MD_PLN_FAST , 2 );//D23
|
||||
scu_pinmux( 14 , 5 , MD_PLN_FAST , 3 );//D24
|
||||
scu_pinmux( 14 , 6 , MD_PLN_FAST , 3 );//D25
|
||||
scu_pinmux( 14 , 7 , MD_PLN_FAST , 3 );//D26
|
||||
scu_pinmux( 14 , 8 , MD_PLN_FAST , 3 );//D27
|
||||
scu_pinmux( 14 , 9 , MD_PLN_FAST , 3 );//D28
|
||||
scu_pinmux( 14 , 10 , MD_PLN_FAST , 3 );//D29
|
||||
scu_pinmux( 14 , 11 , MD_PLN_FAST , 3 );//D30
|
||||
scu_pinmux( 14 , 12 , MD_PLN_FAST , 3 );//D31
|
||||
|
||||
scu_pinmux( 1 , 3 , MD_PLN_FAST , 3 );//OE
|
||||
scu_pinmux( 1 , 6 , MD_PLN_FAST , 3 );//WE
|
||||
|
||||
scu_pinmux( 1 , 4 , MD_PLN_FAST , 3 );//BLS0
|
||||
scu_pinmux( 6 , 6 , MD_PLN_FAST , 1 );//BLS1
|
||||
scu_pinmux( 13 , 13 , MD_PLN_FAST , 2 );//BLS2
|
||||
scu_pinmux( 13 , 10 , MD_PLN_FAST , 2 );//BLS3
|
||||
|
||||
scu_pinmux( 1 , 5 , MD_PLN_FAST , 3 );//CS0
|
||||
scu_pinmux( 6 , 3 , MD_PLN_FAST , 3 );//CS1
|
||||
scu_pinmux( 13 , 12 , MD_PLN_FAST , 2 );//CS2
|
||||
scu_pinmux( 13 , 11 , MD_PLN_FAST , 2 );//CS3
|
||||
|
||||
scu_pinmux( 6 , 4 , MD_PLN_FAST , 3 );//CAS
|
||||
scu_pinmux( 6 , 5 , MD_PLN_FAST , 3 );//RAS
|
||||
|
||||
scu_pinmux( 6 , 9 , MD_PLN_FAST , 3 );//DYCS0
|
||||
scu_pinmux( 6 , 1 , MD_PLN_FAST , 1 );//DYCS1
|
||||
scu_pinmux( 13 , 14 , MD_PLN_FAST , 2 );//DYCS2
|
||||
scu_pinmux( 15 , 14 , MD_PLN_FAST , 3 );//DYCS3
|
||||
|
||||
scu_pinmux( 6 , 11 , MD_PLN_FAST , 3 );//CKEOUT0
|
||||
scu_pinmux( 6 , 2 , MD_PLN_FAST , 1 );//CKEOUT1
|
||||
scu_pinmux( 13 , 1 , MD_PLN_FAST , 2 );//CKEOUT2
|
||||
scu_pinmux( 14 , 15 , MD_PLN_FAST , 3 );//CKEOUT3
|
||||
|
||||
scu_pinmux( 6 , 12 , MD_PLN_FAST , 3 );//DQMOUT0
|
||||
scu_pinmux( 6 , 10 , MD_PLN_FAST , 3 );//DQMOUT1
|
||||
scu_pinmux( 13 , 0 , MD_PLN_FAST , 2 );//DQMOUT2
|
||||
scu_pinmux( 14 , 13 , MD_PLN_FAST , 3 );//DQMOUT3
|
||||
}
|
||||
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Local Functions
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Public Functions
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Initialize the NOR Flash
|
||||
*
|
||||
*****************************************************************************/
|
||||
uint32_t memreg_init (void)
|
||||
{
|
||||
LPC_EMC->CONTROL = 0x00000001;
|
||||
LPC_EMC->CONFIG = 0x00000000;
|
||||
|
||||
pinConfig();
|
||||
|
||||
// Setup for 16-bit access
|
||||
LPC_EMC->STATICCONFIG2 = 0x00000001;
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,30 +0,0 @@
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright(C) 2011, Embedded Artists AB
|
||||
* All rights reserved.
|
||||
*
|
||||
******************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* Embedded Artists AB assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. Embedded Artists AB
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. Embedded Artists AB also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
*****************************************************************************/
|
||||
#ifndef __MEMREG_H
|
||||
#define __MEMREG_H
|
||||
|
||||
#define MEMREG_BASE 0x1e000000
|
||||
|
||||
|
||||
extern uint32_t memreg_init (void);
|
||||
|
||||
|
||||
#endif /* end __MEMREG_H */
|
||||
/****************************************************************************
|
||||
** End Of File
|
||||
*****************************************************************************/
|
||||
@@ -1,547 +0,0 @@
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright(C) 2011, Embedded Artists AB
|
||||
* All rights reserved.
|
||||
*
|
||||
******************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* Embedded Artists AB assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. Embedded Artists AB
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. Embedded Artists AB also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Includes
|
||||
*****************************************************************************/
|
||||
#include "../../board.h"
|
||||
|
||||
#if BOARD == BOARD_EA4357
|
||||
|
||||
#include "lpc_types.h"
|
||||
#include "lpc43xx_scu.h"
|
||||
#include "lpc43xx_timer.h"
|
||||
#include "norflash.h"
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Defines and typedefs
|
||||
*****************************************************************************/
|
||||
|
||||
#define CMD_SWID 0x90
|
||||
#define CMD_CFI_QRY 0x98
|
||||
#define CMD_ID_EXIT 0xF0
|
||||
|
||||
#define CMD_ERASE_BLOCK 0x0050
|
||||
#define CMD_ERASE_SECTOR 0x0030
|
||||
#define CMD_ERASE_CHIP 0x0010
|
||||
|
||||
#define MAN_ID_SST 0x00BF
|
||||
#define DEV_ID_SST39VF3201 0x235B
|
||||
|
||||
/******************************************************************************
|
||||
* External global variables
|
||||
*****************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
* Local variables
|
||||
*****************************************************************************/
|
||||
|
||||
static geometry_t chip_info;
|
||||
|
||||
/******************************************************************************
|
||||
* Local Functions
|
||||
*****************************************************************************/
|
||||
|
||||
static void pinConfig(void)
|
||||
{
|
||||
/* Set up EMC pin */
|
||||
scu_pinmux( 2 , 9 , MD_PLN_FAST , 3 );//A0
|
||||
scu_pinmux( 2 , 10 , MD_PLN_FAST , 3 );//A1
|
||||
scu_pinmux( 2 , 11 , MD_PLN_FAST , 3 );//A2
|
||||
scu_pinmux( 2 , 12 , MD_PLN_FAST , 3 );//A3
|
||||
scu_pinmux( 2 , 13 , MD_PLN_FAST , 3 );//A4
|
||||
scu_pinmux( 1 , 0 , MD_PLN_FAST , 2 );//A5
|
||||
scu_pinmux( 1 , 1 , MD_PLN_FAST , 2 );//A6
|
||||
scu_pinmux( 1 , 2 , MD_PLN_FAST , 2 );//A7
|
||||
scu_pinmux( 2 , 8 , MD_PLN_FAST , 3 );//A8
|
||||
scu_pinmux( 2 , 7 , MD_PLN_FAST , 3 );//A9
|
||||
scu_pinmux( 2 , 6 , MD_PLN_FAST , 2 );//A10
|
||||
scu_pinmux( 2 , 2 , MD_PLN_FAST , 2 );//A11
|
||||
scu_pinmux( 2 , 1 , MD_PLN_FAST , 2 );//A12
|
||||
scu_pinmux( 2 , 0 , MD_PLN_FAST , 2 );//A13
|
||||
scu_pinmux( 6 , 8 , MD_PLN_FAST , 1 );//A14
|
||||
scu_pinmux( 6 , 7 , MD_PLN_FAST , 1 );//A15
|
||||
scu_pinmux( 13 , 16 , MD_PLN_FAST , 2 );//A16
|
||||
scu_pinmux( 13 , 15 , MD_PLN_FAST , 2 );//A17
|
||||
scu_pinmux( 14 , 0 , MD_PLN_FAST , 3 );//A18
|
||||
scu_pinmux( 14 , 1 , MD_PLN_FAST , 3 );//A19
|
||||
scu_pinmux( 14 , 2 , MD_PLN_FAST , 3 );//A20
|
||||
scu_pinmux( 14 , 3 , MD_PLN_FAST , 3 );//A21
|
||||
scu_pinmux( 14 , 4 , MD_PLN_FAST , 3 );//A22
|
||||
scu_pinmux( 10 , 4 , MD_PLN_FAST , 3 );//A23
|
||||
|
||||
scu_pinmux( 1 , 7 , MD_PLN_FAST , 3 );//D0
|
||||
scu_pinmux( 1 , 8 , MD_PLN_FAST , 3 );//D1
|
||||
scu_pinmux( 1 , 9 , MD_PLN_FAST , 3 );//D2
|
||||
scu_pinmux( 1 , 10 , MD_PLN_FAST , 3 );//D3
|
||||
scu_pinmux( 1 , 11 , MD_PLN_FAST , 3 );//D4
|
||||
scu_pinmux( 1 , 12 , MD_PLN_FAST , 3 );//D5
|
||||
scu_pinmux( 1 , 13 , MD_PLN_FAST , 3 );//D6
|
||||
scu_pinmux( 1 , 14 , MD_PLN_FAST , 3 );//D7
|
||||
scu_pinmux( 5 , 4 , MD_PLN_FAST , 2 );//D8
|
||||
scu_pinmux( 5 , 5 , MD_PLN_FAST , 2 );//D9
|
||||
scu_pinmux( 5 , 6 , MD_PLN_FAST , 2 );//D10
|
||||
scu_pinmux( 5 , 7 , MD_PLN_FAST , 2 );//D11
|
||||
scu_pinmux( 5 , 0 , MD_PLN_FAST , 2 );//D12
|
||||
scu_pinmux( 5 , 1 , MD_PLN_FAST , 2 );//D13
|
||||
scu_pinmux( 5 , 2 , MD_PLN_FAST , 2 );//D14
|
||||
scu_pinmux( 5 , 3 , MD_PLN_FAST , 2 );//D15
|
||||
scu_pinmux( 13 , 2 , MD_PLN_FAST , 2 );//D16
|
||||
scu_pinmux( 13 , 3 , MD_PLN_FAST , 2 );//D17
|
||||
scu_pinmux( 13 , 4 , MD_PLN_FAST , 2 );//D18
|
||||
scu_pinmux( 13 , 5 , MD_PLN_FAST , 2 );//D19
|
||||
scu_pinmux( 13 , 6 , MD_PLN_FAST , 2 );//D20
|
||||
scu_pinmux( 13 , 7 , MD_PLN_FAST , 2 );//D21
|
||||
scu_pinmux( 13 , 8 , MD_PLN_FAST , 2 );//D22
|
||||
scu_pinmux( 13 , 9 , MD_PLN_FAST , 2 );//D23
|
||||
scu_pinmux( 14 , 5 , MD_PLN_FAST , 3 );//D24
|
||||
scu_pinmux( 14 , 6 , MD_PLN_FAST , 3 );//D25
|
||||
scu_pinmux( 14 , 7 , MD_PLN_FAST , 3 );//D26
|
||||
scu_pinmux( 14 , 8 , MD_PLN_FAST , 3 );//D27
|
||||
scu_pinmux( 14 , 9 , MD_PLN_FAST , 3 );//D28
|
||||
scu_pinmux( 14 , 10 , MD_PLN_FAST , 3 );//D29
|
||||
scu_pinmux( 14 , 11 , MD_PLN_FAST , 3 );//D30
|
||||
scu_pinmux( 14 , 12 , MD_PLN_FAST , 3 );//D31
|
||||
|
||||
scu_pinmux( 1 , 3 , MD_PLN_FAST , 3 );//OE
|
||||
scu_pinmux( 1 , 6 , MD_PLN_FAST , 3 );//WE
|
||||
|
||||
scu_pinmux( 1 , 4 , MD_PLN_FAST , 3 );//BLS0
|
||||
scu_pinmux( 6 , 6 , MD_PLN_FAST , 1 );//BLS1
|
||||
scu_pinmux( 13 , 13 , MD_PLN_FAST , 2 );//BLS2
|
||||
scu_pinmux( 13 , 10 , MD_PLN_FAST , 2 );//BLS3
|
||||
|
||||
scu_pinmux( 1 , 5 , MD_PLN_FAST , 3 );//CS0
|
||||
scu_pinmux( 6 , 3 , MD_PLN_FAST , 3 );//CS1
|
||||
scu_pinmux( 13 , 12 , MD_PLN_FAST , 2 );//CS2
|
||||
scu_pinmux( 13 , 11 , MD_PLN_FAST , 2 );//CS3
|
||||
}
|
||||
|
||||
#if 0
|
||||
static void getIdString(uint16_t idString[11])
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2aaa)) = 0x0055;
|
||||
*(GET_ADDR(0x5555)) = CMD_CFI_QRY;
|
||||
|
||||
for (i = 0; i < 11; i++) {
|
||||
idString[i] = *(GET_ADDR(0x10 + i));
|
||||
}
|
||||
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2aaa)) = 0x0055;
|
||||
*(GET_ADDR(0x5555)) = CMD_ID_EXIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void getGeoInfo(uint16_t info[14])
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2aaa)) = 0x0055;
|
||||
*(GET_ADDR(0x5555)) = CMD_CFI_QRY;
|
||||
|
||||
for (i = 0; i < 14; i++) {
|
||||
info[i] = *(GET_ADDR(0x27 + i));
|
||||
}
|
||||
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2aaa)) = 0x0055;
|
||||
*(GET_ADDR(0x5555)) = CMD_ID_EXIT;
|
||||
}
|
||||
|
||||
static uint32_t getProductId(void)
|
||||
{
|
||||
uint16_t manuid = 0;
|
||||
uint16_t devid = 0;
|
||||
uint32_t result = 0;
|
||||
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2aaa)) = 0x0055;
|
||||
*(GET_ADDR(0x5555)) = CMD_SWID;
|
||||
|
||||
manuid = *(GET_ADDR(0x00));
|
||||
devid = *(GET_ADDR(0x01));
|
||||
|
||||
result = ((manuid << 16) | devid);
|
||||
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2aaa)) = 0x0055;
|
||||
*(GET_ADDR(0x5555)) = CMD_ID_EXIT;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* When the SST39VF160x/320x are in the internal Program operation, any
|
||||
* attempt to read DQ7 will produce the complement of the true data. Once
|
||||
* the Program operation is completed, DQ7 will produce true data. Note
|
||||
* that even though DQ7 may have valid data immediately following the
|
||||
* completion of an internal Write operation, the remaining data outputs
|
||||
* may still be invalid: valid data on the entire data bus will appear in
|
||||
* subsequent successive Read cycles after an interval of 1 �s. During
|
||||
* internal Erase operation, any attempt to read DQ7 will produce a '0'.
|
||||
* Once the internal Erase operation is completed, DQ7 will produce a '1'.
|
||||
*
|
||||
* Parameters:
|
||||
* addr The device address
|
||||
* data The original (true) data
|
||||
* timeout Maximum number of loops to delay
|
||||
*
|
||||
* Returns:
|
||||
* TRUE if success
|
||||
*
|
||||
*****************************************************************************/
|
||||
static uint16_t check_data_polling(uint32_t addr, uint16_t data, uint32_t timeout)
|
||||
{
|
||||
volatile uint16_t *p = (uint16_t*) addr;
|
||||
uint16_t true_data = data & 0x80;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < timeout; i++)
|
||||
{
|
||||
if ( true_data == (*p &0x80) )
|
||||
{
|
||||
TIM_Waitus(1);
|
||||
return (TRUE);
|
||||
}
|
||||
}
|
||||
return (FALSE);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* During the internal Program or Erase operation, any consecutive attempts
|
||||
* to read DQ6 will produce alternating �1�s and �0�s, i.e., toggling
|
||||
* between 1 and 0. When the internal Program or Erase operation is
|
||||
* completed, the DQ6 bit will stop toggling. The device is then ready
|
||||
* for the next operation.
|
||||
*
|
||||
* Parameters:
|
||||
* addr The device address
|
||||
* timeout Maximum number of loops to delay
|
||||
*
|
||||
* Returns:
|
||||
* TRUE if success
|
||||
*
|
||||
*****************************************************************************/
|
||||
static uint16_t check_toggle_ready(uint32_t addr, uint32_t timeout)
|
||||
{
|
||||
volatile uint16_t *p = (uint16_t*) addr;
|
||||
uint16_t predata, currdata;
|
||||
int i;
|
||||
|
||||
predata = *p & 0x40;
|
||||
for (i = 0; i < timeout; i++)
|
||||
{
|
||||
currdata = *p & 0x40;
|
||||
if (predata == currdata)
|
||||
{
|
||||
TIM_Waitus(1);
|
||||
return (TRUE);
|
||||
}
|
||||
predata = currdata;
|
||||
}
|
||||
return (FALSE);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Public Functions
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Initialize the NOR Flash
|
||||
*
|
||||
*****************************************************************************/
|
||||
uint32_t norflash_init()
|
||||
{
|
||||
uint32_t prodId = 0;
|
||||
|
||||
// LPC_SC->PCONP |= 0x00000800;
|
||||
|
||||
LPC_EMC->CONTROL = 0x00000001;
|
||||
|
||||
LPC_EMC->CONFIG = 0x00000000;
|
||||
|
||||
//Disable Auto-Byte Addressing (on boards designed for LPC24xx)
|
||||
//LPC_SC->SCS |= 0x00000001;
|
||||
|
||||
pinConfig();
|
||||
|
||||
LPC_EMC->STATICCONFIG0 = 0x00000081;
|
||||
|
||||
LPC_EMC->STATICWAITWEN0 = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
|
||||
LPC_EMC->STATICWAITOEN0 = 0x00000003; /* ( n ) -> 0 clock cycles */
|
||||
LPC_EMC->STATICWAITRD0 = 0x00000006; /* ( n + 1 ) -> 7 clock cycles */
|
||||
LPC_EMC->STATICWAITPAG0 = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
|
||||
LPC_EMC->STATICWAITWR0 = 0x00000005; /* ( n + 2 ) -> 7 clock cycles */
|
||||
LPC_EMC->STATICWAITTURN0 = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
|
||||
|
||||
#if 0
|
||||
M32(0x40086400) = 3;//SFSP8_0, pin config P8_0, FUNC3, (PUP_DISABLE | PDN_DISABLE | INBUF_DISABLE | FILTER_ENABLE)
|
||||
M32(0x40086404) = 3;//SFSP8_1, pin config P8_1, FUNC3, (PUP_DISABLE | PDN_DISABLE | INBUF_DISABLE | FILTER_ENABLE)
|
||||
M32(0x40086408) = 3;//SFSP8_2, pin config P8_2, FUNC3, (PUP_DISABLE | PDN_DISABLE | INBUF_DISABLE | FILTER_ENABLE)
|
||||
M32(0x4008640C) = 3;//SFSP8_3, pin config P8_3, FUNC3, (PUP_DISABLE | PDN_DISABLE | SLEWRATE_SLOW | INBUF_DISABLE | FILTER_ENABLE)
|
||||
M32(0x40086410) = 3;//SFSP8_4, pin config P8_4, FUNC3, (PUP_DISABLE | PDN_DISABLE | SLEWRATE_SLOW | INBUF_DISABLE | FILTER_ENABLE)
|
||||
M32(0x40086414) = 3;//SFSP8_5, pin config P8_5, FUNC3, (PUP_DISABLE | PDN_DISABLE | SLEWRATE_SLOW | INBUF_DISABLE | FILTER_ENABLE)
|
||||
M32(0x40086418) = 3;//SFSP8_6, pin config P8_6, FUNC3, (PUP_DISABLE | PDN_DISABLE | SLEWRATE_SLOW | INBUF_DISABLE | FILTER_ENABLE)
|
||||
M32(0x4008641C) = 3;//SFSP8_7, pin config P8_7, FUNC3, (PUP_DISABLE | PDN_DISABLE | SLEWRATE_SLOW | INBUF_DISABLE | FILTER_ENABLE)
|
||||
#endif
|
||||
|
||||
prodId = getProductId();
|
||||
|
||||
if (prodId == ((MAN_ID_SST << 16) | DEV_ID_SST39VF3201)) {
|
||||
|
||||
uint16_t info[14];
|
||||
getGeoInfo(info);
|
||||
chip_info.device_size = 1 << info[0];
|
||||
chip_info.num_sectors = ((info[7] << 8) | info[6]) + 1;
|
||||
chip_info.sector_size = ((info[9] << 8) | info[8]) * 256;
|
||||
chip_info.num_blocks = ((info[11] << 8) | info[10]) + 1;
|
||||
chip_info.block_size = ((info[13] << 8) | info[12]) * 256;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
void norflash_getGeometry(geometry_t* geometry)
|
||||
{
|
||||
*geometry = chip_info;
|
||||
}
|
||||
|
||||
|
||||
uint32_t norflash_eraseSector(uint32_t addr)
|
||||
{
|
||||
volatile uint16_t* p;
|
||||
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2AAA)) = 0x0055;
|
||||
*(GET_ADDR(0x5555)) = 0x0080;
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2AAA)) = 0x0055;
|
||||
|
||||
p = (uint16_t*) addr;
|
||||
*p = CMD_ERASE_SECTOR;
|
||||
|
||||
return check_data_polling(addr, 0xffff, 500000);
|
||||
}
|
||||
|
||||
uint32_t norflash_eraseBlock(uint32_t addr)
|
||||
{
|
||||
volatile uint16_t* p;
|
||||
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2AAA)) = 0x0055;
|
||||
*(GET_ADDR(0x5555)) = 0x0080;
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2AAA)) = 0x0055;
|
||||
|
||||
p = (uint16_t*) addr;
|
||||
*p = CMD_ERASE_BLOCK;
|
||||
|
||||
return check_toggle_ready(addr, 500000);
|
||||
}
|
||||
|
||||
uint32_t norflash_eraseEntireChip(void)
|
||||
{
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2AAA)) = 0x0055;
|
||||
*(GET_ADDR(0x5555)) = 0x0080;
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2AAA)) = 0x0055;
|
||||
*(GET_ADDR(0x5555)) = CMD_ERASE_CHIP;
|
||||
|
||||
return check_toggle_ready(NORFLASH_BASE, 500000);
|
||||
}
|
||||
|
||||
uint32_t norflash_writeWord(uint32_t addr, uint16_t data)
|
||||
{
|
||||
volatile uint16_t *p;
|
||||
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2AAA)) = 0x0055;
|
||||
*(GET_ADDR(0x5555)) = 0x00A0;
|
||||
|
||||
p = (uint16_t*) addr;
|
||||
*p = data;
|
||||
|
||||
return check_toggle_ready(addr, 500000);
|
||||
}
|
||||
|
||||
uint32_t norflash_writeBuff(uint32_t addr, uint16_t* data, uint16_t len)
|
||||
{
|
||||
uint16_t i;
|
||||
for (i = 0; i < len; i++)
|
||||
{
|
||||
if (!norflash_writeWord(addr, data[i]))
|
||||
{
|
||||
return (FALSE);
|
||||
}
|
||||
}
|
||||
return (TRUE);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Reads the security information from the chip. For an explanation
|
||||
* see the user manual.
|
||||
*
|
||||
* Parameters:
|
||||
* SST_SecID The factory programmed security segment
|
||||
* User_SecID The user defined security segment
|
||||
*
|
||||
*****************************************************************************/
|
||||
void norflash_secid_read(uint16_t SST_SecID[8], uint16_t User_SecID[8])
|
||||
{
|
||||
uint16_t i;
|
||||
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2AAA)) = 0x0055;
|
||||
*(GET_ADDR(0x5555)) = 0x0088;
|
||||
|
||||
for (i = 0; i < 7; i++)
|
||||
{
|
||||
SST_SecID[i] = *(GET_ADDR(i)); // SST security is 0x00 - 0x07
|
||||
User_SecID[i] = *(GET_ADDR(i + 0x10)); // User security is 0x10 - 0x17
|
||||
}
|
||||
|
||||
// exit command
|
||||
*(GET_ADDR(0x5555)) = CMD_ID_EXIT;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Checks if the user defined security segment has been locked or not.
|
||||
* See the user manual for more information.
|
||||
*
|
||||
* Returns:
|
||||
* TRUE if the segment is locked
|
||||
*
|
||||
*****************************************************************************/
|
||||
uint32_t norflash_secid_getLockStatus(void)
|
||||
{
|
||||
uint16_t status;
|
||||
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2AAA)) = 0x0055;
|
||||
*(GET_ADDR(0x5555)) = 0x0088;
|
||||
|
||||
// read status
|
||||
status = *(GET_ADDR(0xff));
|
||||
status &= 0x0008;
|
||||
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2AAA)) = 0x0055;
|
||||
*(GET_ADDR(0x5555)) = CMD_ID_EXIT;
|
||||
|
||||
if (!status)
|
||||
return TRUE; // locked
|
||||
return FALSE; // not locked
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Lock the user security segment. CANNOT BE UNDONE.
|
||||
* See the user manual for more information.
|
||||
*
|
||||
* Returns:
|
||||
* TRUE if the segment is locked after programming
|
||||
*
|
||||
*****************************************************************************/
|
||||
uint32_t norflash_secid_lockOut()
|
||||
{
|
||||
// Code not verified. Use at own risk
|
||||
#if 0
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2AAA)) = 0x0055;
|
||||
*(GET_ADDR(0x5555)) = 0x0085;
|
||||
*(GET_ADDR(0x0 )) = 0x0000; // Write 0x0000 to any address
|
||||
|
||||
if (check_toggle_ready(GET_ADDR(0x0), 500000))
|
||||
{
|
||||
return norflash_secid_getLockStatus();
|
||||
}
|
||||
#endif
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Writes data to the user security segment (0x0010 - 0x0017).
|
||||
* See the user manual for more information.
|
||||
*
|
||||
* Parameters:
|
||||
* target Must be in the range 0x10 to 0x17
|
||||
* data The data to write
|
||||
* len The number of words to write
|
||||
*
|
||||
* Returns:
|
||||
* TRUE if the programming was successful
|
||||
*
|
||||
*****************************************************************************/
|
||||
uint32_t norflash_secid_writeWord(uint16_t target, uint16_t* data, uint16_t len)
|
||||
{
|
||||
// Code not verified. Use at own risk
|
||||
#if 0
|
||||
uint16_t i;
|
||||
|
||||
if ((target < 0x10) || (target > 0x17))
|
||||
return FALSE;
|
||||
|
||||
if ((len > 8) || ((target + len) > 0x17))
|
||||
return FALSE;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
{
|
||||
*(GET_ADDR(0x5555)) = 0x00AA;
|
||||
*(GET_ADDR(0x2AAA)) = 0x0055;
|
||||
*(GET_ADDR(0x5555)) = 0x00A5;
|
||||
*(GET_ADDR(target + i)) = data;
|
||||
|
||||
data++;
|
||||
|
||||
/* Read the toggle bit to detect end-of-programming for User Sec ID.
|
||||
Do Not use Data# Polling for User_SecID_Word_Program!! */
|
||||
if (!check_toggle_ready(GET_ADDR(target + i), 500000))
|
||||
return FALSE;
|
||||
}
|
||||
#endif
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,56 +0,0 @@
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright(C) 2011, Embedded Artists AB
|
||||
* All rights reserved.
|
||||
*
|
||||
******************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* Embedded Artists AB assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. Embedded Artists AB
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. Embedded Artists AB also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
*****************************************************************************/
|
||||
#ifndef __NORFLASH_H
|
||||
#define __NORFLASH_H
|
||||
|
||||
#define NORFLASH_SIZE 0x400000 /*Bytes or 0x200000 16bit words*/
|
||||
#define NORFLASH_BLOCK_SIZE 0x10000 /*Bytes, or 32K 16bit words*/
|
||||
#define NORFLASH_BASE 0x1C000000
|
||||
|
||||
//16 bit data
|
||||
#define GET_ADDR(addr) (volatile uint16_t *)(NORFLASH_BASE | ((addr) << 1))
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t device_size; /* Device size in bytes */
|
||||
uint32_t num_sectors; /* Number of sectors */
|
||||
uint32_t sector_size; /* Sector size in bytes */
|
||||
uint32_t num_blocks; /* Number of blocks */
|
||||
uint32_t block_size; /* Block size in bytes */
|
||||
} geometry_t;
|
||||
|
||||
extern uint32_t norflash_init(void);
|
||||
|
||||
extern void norflash_getGeometry(geometry_t* geometry);
|
||||
|
||||
extern uint32_t norflash_eraseBlock(uint32_t addr);
|
||||
extern uint32_t norflash_eraseSector(uint32_t addr);
|
||||
extern uint32_t norflash_eraseEntireChip(void);
|
||||
|
||||
extern uint32_t norflash_writeWord(uint32_t addr, uint16_t data);
|
||||
extern uint32_t norflash_writeBuff(uint32_t addr, uint16_t* data, uint16_t len);
|
||||
|
||||
extern void norflash_secid_read(uint16_t SST_SecID[8], uint16_t user_SecID[8]);
|
||||
extern uint32_t norflash_secid_getLockStatus(void);
|
||||
extern uint32_t norflash_secid_lockOut(void);
|
||||
extern uint32_t norflash_secid_writeWord(uint16_t target, uint16_t* data, uint16_t len);
|
||||
|
||||
#endif /* end __NORFLASH_H */
|
||||
/****************************************************************************
|
||||
** End Of File
|
||||
*****************************************************************************/
|
||||
@@ -1,159 +0,0 @@
|
||||
#include "../../board.h"
|
||||
|
||||
#if BOARD == BOARD_EA4357
|
||||
|
||||
#include "lpc43xx_i2c.h"
|
||||
#include "lpc43xx_scu.h"
|
||||
#include "uda1380.h"
|
||||
|
||||
//Uda1380 link to I2C0 only
|
||||
#define UDA1380_I2C LPC_I2C0
|
||||
|
||||
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Initialize Uda1380
|
||||
* @param[in] i2cClockFreq I2C clock frequency that Uda1380 operate
|
||||
* @param[in] i2sClockFreq I2S bit clock frequency
|
||||
* @return None
|
||||
**********************************************************************/
|
||||
int32_t Uda1380_Init(uint32_t i2cClockFreq, uint32_t i2sClockFreq)
|
||||
{
|
||||
int32_t ret;
|
||||
uint8_t clk;
|
||||
|
||||
// // Config Pin for I2C_SDA and I2C_SCL of I2C0
|
||||
// scu_pinmux( 2 , 3 , MD_PLN_FAST, FUNC1 );
|
||||
// scu_pinmux( 2 , 4 , MD_PLN_FAST, FUNC1 );
|
||||
|
||||
I2C_Init(UDA1380_I2C, i2cClockFreq);
|
||||
|
||||
/* Enable I2C1 operation */
|
||||
I2C_Cmd(UDA1380_I2C, ENABLE);
|
||||
|
||||
/* Reset */
|
||||
ret = Uda1380_WriteData(UDA1380_REG_L3, 0 );
|
||||
if(ret != UDA1380_FUNC_OK)
|
||||
return ret;
|
||||
|
||||
/* Write clock settings */
|
||||
ret = Uda1380_WriteData(UDA1380_REG_I2S,0 );
|
||||
if(ret != UDA1380_FUNC_OK)
|
||||
return ret;
|
||||
|
||||
ret = Uda1380_WriteData(UDA1380_REG_MSTRMUTE,0);
|
||||
if(ret != UDA1380_FUNC_OK)
|
||||
return ret;
|
||||
|
||||
ret = Uda1380_WriteData(UDA1380_REG_MIXSDO,0);
|
||||
if(ret != UDA1380_FUNC_OK)
|
||||
return ret;
|
||||
|
||||
#if UDA1380_SYSCLK_USED //Use SYSCLK
|
||||
ret = Uda1380_WriteData(UDA1380_REG_EVALCLK,
|
||||
EVALCLK_DEC_EN | EVALCLK_DAC_EN | EVALCLK_INT_EN | EVALCLK_DAC_SEL_SYSCLK );
|
||||
if(ret != UDA1380_FUNC_OK)
|
||||
return ret;
|
||||
|
||||
ret = Uda1380_WriteData(UDA1380_REG_PWRCTRL,
|
||||
PWR_PON_HP_EN | PWR_PON_DAC_EN | PWR_PON_BIAS_EN);
|
||||
if(ret != UDA1380_FUNC_OK)
|
||||
return ret;
|
||||
|
||||
#else //Use WSPLL
|
||||
if(i2sClockFreq >= 6250 && i2sClockFreq < 12500)
|
||||
clk = EVALCLK_WSPLL_SEL6_12K;
|
||||
else if(i2sClockFreq >= 12501 && i2sClockFreq < 25000)
|
||||
clk = EVALCLK_WSPLL_SEL12_25K;
|
||||
else if(i2sClockFreq >= 25001 && i2sClockFreq < 50000)
|
||||
clk = EVALCLK_WSPLL_SEL25_50K;
|
||||
else if(i2sClockFreq >= 50001 && i2sClockFreq < 100000)
|
||||
clk = EVALCLK_WSPLL_SEL50_100K;
|
||||
else
|
||||
clk= 0;
|
||||
|
||||
ret = Uda1380_WriteData(UDA1380_REG_EVALCLK,
|
||||
EVALCLK_DEC_EN | EVALCLK_DAC_EN | EVALCLK_INT_EN | EVALCLK_DAC_SEL_WSPLL | clk);
|
||||
if(ret != UDA1380_FUNC_OK)
|
||||
return ret;
|
||||
|
||||
ret = Uda1380_WriteData(UDA1380_REG_PWRCTRL,
|
||||
PWR_PON_PLL_EN | PWR_PON_HP_EN | PWR_PON_DAC_EN | PWR_PON_BIAS_EN);
|
||||
if(ret != UDA1380_FUNC_OK)
|
||||
return ret;
|
||||
#endif
|
||||
return UDA1380_FUNC_OK;
|
||||
}
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Write data to a register of Uda1380
|
||||
* @param[in] reg Register address
|
||||
* @param[out] data data value.
|
||||
* @return None
|
||||
**********************************************************************/
|
||||
int32_t Uda1380_WriteData(uint8_t reg, uint16_t data)
|
||||
{
|
||||
I2C_M_SETUP_Type i2cData;
|
||||
uint8_t i2cBuf[UDA1380_CMD_BUFF_SIZE];
|
||||
|
||||
i2cBuf[0] = reg;
|
||||
i2cBuf[1] = (data >> 8) & 0xFF;
|
||||
i2cBuf[2] = data & 0xFF;
|
||||
|
||||
i2cData.sl_addr7bit = UDA1380_SLAVE_ADDR;
|
||||
i2cData.tx_length = UDA1380_CMD_BUFF_SIZE;
|
||||
i2cData.tx_data = i2cBuf;
|
||||
i2cData.rx_data = NULL;
|
||||
i2cData.rx_length = 0;
|
||||
i2cData.retransmissions_max = 3;
|
||||
|
||||
if (I2C_MasterTransferData(UDA1380_I2C, &i2cData, I2C_TRANSFER_POLLING) == SUCCESS)
|
||||
{
|
||||
uint16_t dataTmp;
|
||||
if(Uda1380_ReadData(reg, &dataTmp) != UDA1380_FUNC_OK) {
|
||||
return UDA1380_FUNC_ERR;
|
||||
}
|
||||
if(dataTmp != data)
|
||||
return UDA1380_FUNC_ERR;
|
||||
|
||||
return UDA1380_FUNC_OK;
|
||||
}
|
||||
|
||||
return UDA1380_FUNC_ERR;
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief Read data stored in register of Uda1380
|
||||
* @param[in] reg Register address
|
||||
* @param[out] data point to the buffer which is used for storing data.
|
||||
* @return None
|
||||
**********************************************************************/
|
||||
int32_t Uda1380_ReadData(uint8_t reg, uint16_t *data)
|
||||
{
|
||||
I2C_M_SETUP_Type i2cData;
|
||||
uint8_t i2cBuf[UDA1380_CMD_BUFF_SIZE];
|
||||
|
||||
if(data == NULL)
|
||||
return UDA1380_FUNC_ERR;
|
||||
|
||||
i2cBuf[0] = reg;
|
||||
|
||||
i2cData.sl_addr7bit = UDA1380_SLAVE_ADDR;
|
||||
i2cData.tx_length = 1;
|
||||
i2cData.tx_data = i2cBuf;
|
||||
i2cData.rx_data = &i2cBuf[1];
|
||||
i2cData.rx_length = UDA1380_CMD_BUFF_SIZE - 1;
|
||||
i2cData.retransmissions_max = 3;
|
||||
|
||||
if (I2C_MasterTransferData(UDA1380_I2C, &i2cData, I2C_TRANSFER_POLLING) == SUCCESS)
|
||||
{
|
||||
*data = i2cBuf[1] << 8 | i2cBuf[2];
|
||||
return UDA1380_FUNC_OK;
|
||||
}
|
||||
|
||||
return UDA1380_FUNC_ERR;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,93 +0,0 @@
|
||||
#ifndef _UDA1380_H_
|
||||
#define _UDA1380_H_
|
||||
|
||||
#include "lpc_types.h"
|
||||
|
||||
#define UDA1380_SYSCLK_USED 0
|
||||
#define UDA1380_SLAVE_ADDR 0x1A
|
||||
#define UDA1380_CMD_BUFF_SIZE 3
|
||||
|
||||
/** UDA1380 Registers */
|
||||
#define UDA1380_REG_EVALCLK 0x00
|
||||
#define UDA1380_REG_I2S 0x01
|
||||
#define UDA1380_REG_PWRCTRL 0x02
|
||||
#define UDA1380_REG_ANAMIX 0x03
|
||||
#define UDA1380_REG_HEADAMP 0x04
|
||||
#define UDA1380_REG_MSTRVOL 0x10
|
||||
#define UDA1380_REG_MIXVOL 0x11
|
||||
#define UDA1380_REG_MODEBBT 0x12
|
||||
#define UDA1380_REG_MSTRMUTE 0x13
|
||||
#define UDA1380_REG_MIXSDO 0x14
|
||||
#define UDA1380_REG_DECVOL 0x20
|
||||
#define UDA1380_REG_PGA 0x21
|
||||
#define UDA1380_REG_ADC 0x22
|
||||
#define UDA1380_REG_AGC 0x23
|
||||
#define UDA1380_REG_L3 0x7f
|
||||
#define UDA1380_REG_HEADPHONE 0x18
|
||||
#define UDA1380_REG_DEC 0x28
|
||||
|
||||
// UDA1380_REG_EVALCLK bit defines
|
||||
#define EVALCLK_ADC_EN 0x0800 // Enable ADC clock
|
||||
#define EVALCLK_DEC_EN 0x0400 // Enable decimator clock
|
||||
#define EVALCLK_DAC_EN 0x0200 // Enable DAC clock
|
||||
#define EVALCLK_INT_EN 0x0100 // Enable interpolator clock
|
||||
#define EVALCLK_ADC_SEL_WSPLL 0x0020 // Select SYSCLK input for ADC clock
|
||||
#define EVALCLK_ADC_SEL_SYSCLK 0x0000 // Select WSPLL clock for ADC clock
|
||||
#define EVALCLK_DAC_SEL_WSPLL 0x0010 // Select SYSCLK input for DAC clock
|
||||
#define EVALCLK_DAC_SEL_SYSCLK 0x0000 // Select WSPLL clock for DAC clock
|
||||
#define EVALCLK_SYSDIV_SEL(n) ((n) << 2) // System clock input divider select
|
||||
#define EVALCLK_WSPLL_SEL6_12K 0x0000 // WSPLL input freq selection = 6.25 to 12.5K
|
||||
#define EVALCLK_WSPLL_SEL12_25K 0x0001 // WSPLL input freq selection = 12.5K to 25K
|
||||
#define EVALCLK_WSPLL_SEL25_50K 0x0002 // WSPLL input freq selection = 25K to 50K
|
||||
#define EVALCLK_WSPLL_SEL50_100K 0x0003 // WSPLL input freq selection = 50K to 100K
|
||||
|
||||
// UDA1380_REG_I2S
|
||||
#define I2S_SFORI_I2S 0x0000
|
||||
#define I2S_SFORI_LSB16 0x0100
|
||||
#define I2S_SFORI_LSB18 0x0200
|
||||
#define I2S_SFORI_LSB20 0x0300
|
||||
#define I2S_SFORI_MSB 0x0500
|
||||
#define I2S_SFORI_MASK 0x0700
|
||||
#define I2S_SFORO_I2S 0x0000
|
||||
#define I2S_SFORO_LSB16 0x0001
|
||||
#define I2S_SFORO_LSB18 0x0002
|
||||
#define I2S_SFORO_LSB20 0x0003
|
||||
#define I2S_SFORO_LSB24 0x0004
|
||||
#define I2S_SFORO_MSB 0x0005
|
||||
#define I2S_SFORO_MASK 0x0007
|
||||
#define I2S_SEL_SOURCE 0x0040
|
||||
#define I2S_SIM 0x0010
|
||||
|
||||
// UDA1380_REG_PWRCTRL bit defines
|
||||
#define PWR_PON_PLL_EN 0x8000 // WSPLL enable
|
||||
#define PWR_PON_HP_EN 0x2000 // Headphone driver enable
|
||||
#define PWR_PON_DAC_EN 0x0400 // DAC power enable
|
||||
#define PWR_PON_BIAS_EN 0x0100 // Power on bias enable (for ADC, AVC, and FSDAC)
|
||||
#define PWR_EN_AVC_EN 0x0080 // Analog mixer enable
|
||||
#define PWR_PON_AVC_EN 0x0040 // Analog mixer power enable
|
||||
#define PWR_EN_LNA_EN 0x0010 // LNA and SDC power enable
|
||||
#define PWR_EN_PGAL_EN 0x0008 // PGA left power enable
|
||||
#define PWR_EN_ADCL_EN 0x0004 // ADC left power enable
|
||||
#define PWR_EN_PGAR_EN 0x0002 // PGA right power enable
|
||||
#define PWR_EN_ADCR_EN 0x0001 // ADC right power enable
|
||||
|
||||
// UDA1380_REG_MSTRMUTE bit defines
|
||||
#define MSTRMUTE_MTM_MUTE_EN 0x4000 // Master mute enable
|
||||
#define MSRTMUTE_CHANNEL2_MUTE_EN 0x0800
|
||||
#define MSRTMUTE_CHANNEL1_MUTE_EN 0x0008
|
||||
|
||||
|
||||
// UDA1380_REG_MODEBBT bit defines
|
||||
#define MODEBBT_BOOST_FLAT 0x0000 // Bits for selecting flat boost
|
||||
#define MODEBBT_BOOST_FULL 0xC000 // Bits for selecting maximum boost
|
||||
#define MODEBBT_BOOST_MASK 0xC000 // Bits for selecting boost mask
|
||||
|
||||
#define UDA1380_FUNC_OK 0
|
||||
#define UDA1380_FUNC_ERR -1
|
||||
|
||||
int32_t Uda1380_Init(uint32_t i2cClockFreq, uint32_t i2sClockFreq);
|
||||
int32_t Uda1380_WriteData(uint8_t reg, uint16_t data);
|
||||
int32_t Uda1380_ReadData(uint8_t reg, uint16_t *data);
|
||||
|
||||
|
||||
#endif /* _UDA1380_H_ */
|
||||
@@ -24,13 +24,10 @@
|
||||
/******************************************************************************
|
||||
* Includes
|
||||
*****************************************************************************/
|
||||
#include "bsp/board.h"
|
||||
|
||||
#ifdef BOARD_EA4357
|
||||
//#include "board.h"
|
||||
#include "chip.h"
|
||||
|
||||
#include "lpc43xx_i2c.h"
|
||||
#include "lpc43xx_cgu.h"
|
||||
#include "lpc_types.h"
|
||||
#include "pca9532.h"
|
||||
|
||||
/******************************************************************************
|
||||
@@ -60,32 +57,40 @@ static uint16_t ledStateShadow = 0;
|
||||
* Local Functions
|
||||
*****************************************************************************/
|
||||
|
||||
static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len)
|
||||
static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len)
|
||||
{
|
||||
I2C_M_SETUP_Type i2cData;
|
||||
I2CM_XFER_T i2cData;
|
||||
|
||||
i2cData.sl_addr7bit = addr;
|
||||
i2cData.tx_data = buf;
|
||||
i2cData.tx_length = len;
|
||||
i2cData.rx_data = NULL;
|
||||
i2cData.rx_length = 0;
|
||||
i2cData.retransmissions_max = 3;
|
||||
i2cData.slaveAddr = addr;
|
||||
i2cData.options = 0;
|
||||
i2cData.status = 0;
|
||||
i2cData.txBuff = buf;
|
||||
i2cData.txSz = len;
|
||||
i2cData.rxBuff = NULL;
|
||||
i2cData.rxSz = 0;
|
||||
|
||||
return I2C_MasterTransferData(I2C_PORT, &i2cData, I2C_TRANSFER_POLLING);
|
||||
if (Chip_I2CM_XferBlocking(LPC_I2C0, &i2cData) == 0) {
|
||||
return ERROR;
|
||||
}
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len)
|
||||
static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len)
|
||||
{
|
||||
I2C_M_SETUP_Type i2cData;
|
||||
I2CM_XFER_T i2cData;
|
||||
|
||||
i2cData.sl_addr7bit = addr;
|
||||
i2cData.tx_data = NULL;
|
||||
i2cData.tx_length = 0;
|
||||
i2cData.rx_data = buf;
|
||||
i2cData.rx_length = len;
|
||||
i2cData.retransmissions_max = 3;
|
||||
i2cData.slaveAddr = addr;
|
||||
i2cData.options = 0;
|
||||
i2cData.status = 0;
|
||||
i2cData.txBuff = NULL;
|
||||
i2cData.txSz = 0;
|
||||
i2cData.rxBuff = buf;
|
||||
i2cData.rxSz = len;
|
||||
|
||||
return I2C_MasterTransferData(I2C_PORT, &i2cData, I2C_TRANSFER_POLLING);
|
||||
if (Chip_I2CM_XferBlocking(LPC_I2C0, &i2cData) == 0) {
|
||||
return ERROR;
|
||||
}
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
static void setLsStates(uint16_t states, uint8_t* ls, uint8_t mode)
|
||||
@@ -176,7 +181,7 @@ uint16_t pca9532_getLedState (uint32_t shadow)
|
||||
* A blinking LED may be reported as on or off depending on
|
||||
* its state when reading the Input register.
|
||||
*/
|
||||
|
||||
|
||||
buf[0] = PCA9532_INPUT0;
|
||||
I2CWrite(PCA9532_I2C_ADDR, buf, 1);
|
||||
|
||||
@@ -345,5 +350,3 @@ void pca9532_setBlink1Leds(uint16_t ledMask)
|
||||
blink1Shadow |= ledMask;
|
||||
setLeds();
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -19,7 +19,7 @@
|
||||
#define __PCA9532C_H
|
||||
|
||||
|
||||
#define PCA9532_I2C_ADDR (0x60)
|
||||
#define PCA9532_I2C_ADDR (0xC0>>1)
|
||||
|
||||
#define PCA9532_INPUT0 0x00
|
||||
#define PCA9532_INPUT1 0x01
|
||||
@@ -48,7 +48,7 @@
|
||||
#define KEY_MASK 0x000F
|
||||
|
||||
/*
|
||||
* MMC Card Detect and MMC Write Protect are mapped to LED4
|
||||
* MMC Card Detect and MMC Write Protect are mapped to LED4
|
||||
* and LED5 on the PCA9532. Please note that WP is active low.
|
||||
*/
|
||||
|
||||
@@ -1,272 +0,0 @@
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright(C) 2011, Embedded Artists AB
|
||||
* All rights reserved.
|
||||
*
|
||||
******************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* Embedded Artists AB assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. Embedded Artists AB
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. Embedded Artists AB also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Includes
|
||||
*****************************************************************************/
|
||||
#include "../board.h"
|
||||
|
||||
#if BOARD == BOARD_EA4357
|
||||
|
||||
#include "LPC43xx.h"
|
||||
#include "lpc_types.h"
|
||||
#include "lpc43xx_scu.h"
|
||||
#include "lpc43xx_timer.h"
|
||||
#include "lpc43xx_cgu.h"
|
||||
#include "sdram.h"
|
||||
#include <string.h>
|
||||
|
||||
/******************************************************************************
|
||||
* Defines and typedefs
|
||||
*****************************************************************************/
|
||||
|
||||
/* SDRAM refresh time to 16 clock num */
|
||||
#define EMC_SDRAM_REFRESH(freq,time) \
|
||||
(((uint64_t)((uint64_t)time * freq)/16000000000ull)+1)
|
||||
|
||||
/******************************************************************************
|
||||
* External global variables
|
||||
*****************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
* Local variables
|
||||
*****************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
* Local Functions
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
/*-------------------------PRIVATE FUNCTIONS------------------------------*/
|
||||
/*********************************************************************
|
||||
* @brief Calculate EMC Clock from nano second
|
||||
* @param[in] freq - frequency of EMC Clk
|
||||
* @param[in] time - nano second
|
||||
* @return None
|
||||
**********************************************************************/
|
||||
uint32_t NS2CLK(uint32_t freq, uint32_t time){
|
||||
return (((uint64_t)time*freq/1000000000));
|
||||
}
|
||||
|
||||
static void pinConfig(void)
|
||||
{
|
||||
/* Set up EMC pin */
|
||||
scu_pinmux( 2 , 9 , MD_PLN_FAST , 3 );//A0
|
||||
scu_pinmux( 2 , 10 , MD_PLN_FAST , 3 );//A1
|
||||
scu_pinmux( 2 , 11 , MD_PLN_FAST , 3 );//A2
|
||||
scu_pinmux( 2 , 12 , MD_PLN_FAST , 3 );//A3
|
||||
scu_pinmux( 2 , 13 , MD_PLN_FAST , 3 );//A4
|
||||
scu_pinmux( 1 , 0 , MD_PLN_FAST , 2 );//A5
|
||||
scu_pinmux( 1 , 1 , MD_PLN_FAST , 2 );//A6
|
||||
scu_pinmux( 1 , 2 , MD_PLN_FAST , 2 );//A7
|
||||
scu_pinmux( 2 , 8 , MD_PLN_FAST , 3 );//A8
|
||||
scu_pinmux( 2 , 7 , MD_PLN_FAST , 3 );//A9
|
||||
scu_pinmux( 2 , 6 , MD_PLN_FAST , 2 );//A10
|
||||
scu_pinmux( 2 , 2 , MD_PLN_FAST , 2 );//A11
|
||||
scu_pinmux( 2 , 1 , MD_PLN_FAST , 2 );//A12
|
||||
scu_pinmux( 2 , 0 , MD_PLN_FAST , 2 );//A13
|
||||
scu_pinmux( 6 , 8 , MD_PLN_FAST , 1 );//A14
|
||||
scu_pinmux( 6 , 7 , MD_PLN_FAST , 1 );//A15
|
||||
scu_pinmux( 13 , 16 , MD_PLN_FAST , 2 );//A16
|
||||
scu_pinmux( 13 , 15 , MD_PLN_FAST , 2 );//A17
|
||||
scu_pinmux( 14 , 0 , MD_PLN_FAST , 3 );//A18
|
||||
scu_pinmux( 14 , 1 , MD_PLN_FAST , 3 );//A19
|
||||
scu_pinmux( 14 , 2 , MD_PLN_FAST , 3 );//A20
|
||||
scu_pinmux( 14 , 3 , MD_PLN_FAST , 3 );//A21
|
||||
scu_pinmux( 14 , 4 , MD_PLN_FAST , 3 );//A22
|
||||
scu_pinmux( 10 , 4 , MD_PLN_FAST , 3 );//A23
|
||||
|
||||
scu_pinmux( 1 , 7 , MD_PLN_FAST , 3 );//D0
|
||||
scu_pinmux( 1 , 8 , MD_PLN_FAST , 3 );//D1
|
||||
scu_pinmux( 1 , 9 , MD_PLN_FAST , 3 );//D2
|
||||
scu_pinmux( 1 , 10 , MD_PLN_FAST , 3 );//D3
|
||||
scu_pinmux( 1 , 11 , MD_PLN_FAST , 3 );//D4
|
||||
scu_pinmux( 1 , 12 , MD_PLN_FAST , 3 );//D5
|
||||
scu_pinmux( 1 , 13 , MD_PLN_FAST , 3 );//D6
|
||||
scu_pinmux( 1 , 14 , MD_PLN_FAST , 3 );//D7
|
||||
scu_pinmux( 5 , 4 , MD_PLN_FAST , 2 );//D8
|
||||
scu_pinmux( 5 , 5 , MD_PLN_FAST , 2 );//D9
|
||||
scu_pinmux( 5 , 6 , MD_PLN_FAST , 2 );//D10
|
||||
scu_pinmux( 5 , 7 , MD_PLN_FAST , 2 );//D11
|
||||
scu_pinmux( 5 , 0 , MD_PLN_FAST , 2 );//D12
|
||||
scu_pinmux( 5 , 1 , MD_PLN_FAST , 2 );//D13
|
||||
scu_pinmux( 5 , 2 , MD_PLN_FAST , 2 );//D14
|
||||
scu_pinmux( 5 , 3 , MD_PLN_FAST , 2 );//D15
|
||||
scu_pinmux( 13 , 2 , MD_PLN_FAST , 2 );//D16
|
||||
scu_pinmux( 13 , 3 , MD_PLN_FAST , 2 );//D17
|
||||
scu_pinmux( 13 , 4 , MD_PLN_FAST , 2 );//D18
|
||||
scu_pinmux( 13 , 5 , MD_PLN_FAST , 2 );//D19
|
||||
scu_pinmux( 13 , 6 , MD_PLN_FAST , 2 );//D20
|
||||
scu_pinmux( 13 , 7 , MD_PLN_FAST , 2 );//D21
|
||||
scu_pinmux( 13 , 8 , MD_PLN_FAST , 2 );//D22
|
||||
scu_pinmux( 13 , 9 , MD_PLN_FAST , 2 );//D23
|
||||
scu_pinmux( 14 , 5 , MD_PLN_FAST , 3 );//D24
|
||||
scu_pinmux( 14 , 6 , MD_PLN_FAST , 3 );//D25
|
||||
scu_pinmux( 14 , 7 , MD_PLN_FAST , 3 );//D26
|
||||
scu_pinmux( 14 , 8 , MD_PLN_FAST , 3 );//D27
|
||||
scu_pinmux( 14 , 9 , MD_PLN_FAST , 3 );//D28
|
||||
scu_pinmux( 14 , 10 , MD_PLN_FAST , 3 );//D29
|
||||
scu_pinmux( 14 , 11 , MD_PLN_FAST , 3 );//D30
|
||||
scu_pinmux( 14 , 12 , MD_PLN_FAST , 3 );//D31
|
||||
|
||||
scu_pinmux( 1 , 3 , MD_PLN_FAST , 3 );//OE
|
||||
scu_pinmux( 1 , 6 , MD_PLN_FAST , 3 );//WE
|
||||
|
||||
scu_pinmux( 1 , 4 , MD_PLN_FAST , 3 );//BLS0
|
||||
scu_pinmux( 6 , 6 , MD_PLN_FAST , 1 );//BLS1
|
||||
scu_pinmux( 13 , 13 , MD_PLN_FAST , 2 );//BLS2
|
||||
scu_pinmux( 13 , 10 , MD_PLN_FAST , 2 );//BLS3
|
||||
|
||||
scu_pinmux( 1 , 5 , MD_PLN_FAST , 3 );//CS0
|
||||
scu_pinmux( 6 , 3 , MD_PLN_FAST , 3 );//CS1
|
||||
scu_pinmux( 13 , 12 , MD_PLN_FAST , 2 );//CS2
|
||||
scu_pinmux( 13 , 11 , MD_PLN_FAST , 2 );//CS3
|
||||
|
||||
scu_pinmux( 6 , 4 , MD_PLN_FAST , 3 );//CAS
|
||||
scu_pinmux( 6 , 5 , MD_PLN_FAST , 3 );//RAS
|
||||
|
||||
scu_pinmux( 6 , 9 , MD_PLN_FAST , 3 );//DYCS0
|
||||
scu_pinmux( 6 , 1 , MD_PLN_FAST , 1 );//DYCS1
|
||||
scu_pinmux( 13 , 14 , MD_PLN_FAST , 2 );//DYCS2
|
||||
scu_pinmux( 15 , 14 , MD_PLN_FAST , 3 );//DYCS3
|
||||
|
||||
scu_pinmux( 6 , 11 , MD_PLN_FAST , 3 );//CKEOUT0
|
||||
scu_pinmux( 6 , 2 , MD_PLN_FAST , 1 );//CKEOUT1
|
||||
scu_pinmux( 13 , 1 , MD_PLN_FAST , 2 );//CKEOUT2
|
||||
scu_pinmux( 14 , 15 , MD_PLN_FAST , 3 );//CKEOUT3
|
||||
|
||||
scu_pinmux( 6 , 12 , MD_PLN_FAST , 3 );//DQMOUT0
|
||||
scu_pinmux( 6 , 10 , MD_PLN_FAST , 3 );//DQMOUT1
|
||||
scu_pinmux( 13 , 0 , MD_PLN_FAST , 2 );//DQMOUT2
|
||||
scu_pinmux( 14 , 13 , MD_PLN_FAST , 3 );//DQMOUT3
|
||||
}
|
||||
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Public Functions
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Initialize the SDRAM
|
||||
*
|
||||
*****************************************************************************/
|
||||
uint32_t sdram_init (void)
|
||||
{
|
||||
uint32_t pclk, temp;
|
||||
uint64_t tmpclk;
|
||||
|
||||
pinConfig(); //Full 32-bit Data bus, 24-bit Address
|
||||
|
||||
/* Select EMC clock-out */
|
||||
LPC_SCU->SFSCLK_0 = MD_PLN_FAST;
|
||||
LPC_SCU->SFSCLK_1 = MD_PLN_FAST;
|
||||
LPC_SCU->SFSCLK_2 = MD_PLN_FAST;
|
||||
LPC_SCU->SFSCLK_3 = MD_PLN_FAST;
|
||||
|
||||
LPC_EMC->CONTROL = 0x00000001;
|
||||
LPC_EMC->CONFIG = 0x00000000;
|
||||
LPC_EMC->DYNAMICCONFIG0 = 1<<14 | 0<<12 | 2<<9 | 1<<7; /* 256Mb, 8Mx32, 4 banks, row=12, column=9 */
|
||||
|
||||
pclk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M4CORE);
|
||||
|
||||
LPC_EMC->DYNAMICRASCAS0 = 0x00000202; /* 2 RAS, 2 CAS latency */
|
||||
LPC_EMC->DYNAMICREADCONFIG = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */
|
||||
|
||||
LPC_EMC->DYNAMICRP = NS2CLK(pclk, 20);
|
||||
LPC_EMC->DYNAMICRAS = NS2CLK(pclk, 42);
|
||||
LPC_EMC->DYNAMICSREX = NS2CLK(pclk, 63);
|
||||
LPC_EMC->DYNAMICAPR = 0x00000005;
|
||||
LPC_EMC->DYNAMICDAL = 0x00000005;
|
||||
LPC_EMC->DYNAMICWR = 2;
|
||||
LPC_EMC->DYNAMICRC = NS2CLK(pclk, 63);
|
||||
LPC_EMC->DYNAMICRFC = NS2CLK(pclk, 63);
|
||||
LPC_EMC->DYNAMICXSR = NS2CLK(pclk, 63);
|
||||
LPC_EMC->DYNAMICRRD = NS2CLK(pclk, 14);
|
||||
LPC_EMC->DYNAMICMRD = 0x00000002;
|
||||
|
||||
TIM_Waitus(100); /* wait 100ms */
|
||||
LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
|
||||
|
||||
TIM_Waitus(200); /* wait 200ms */
|
||||
LPC_EMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */
|
||||
|
||||
LPC_EMC->DYNAMICREFRESH = EMC_SDRAM_REFRESH(pclk,70); /* ( n * 16 ) -> 32 clock cycles */
|
||||
|
||||
//for(i = 0; i < 0x80; i++); /* wait 128 AHB clock cycles */
|
||||
TIM_Waitus(200); /* wait 200ms */
|
||||
|
||||
tmpclk = (uint64_t)15625*(uint64_t)pclk/1000000000/16;
|
||||
LPC_EMC->DYNAMICREFRESH = tmpclk; /* ( n * 16 ) -> 736 clock cycles -> 15.330uS at 48MHz <= 15.625uS ( 64ms / 4096 row ) */
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */
|
||||
|
||||
//Timing for 48/60/72MHZ Bus
|
||||
temp = *((volatile uint32_t *)(SDRAM_BASE | (2<<4| 2)<<(9+2+2))); /* 4 burst, 2 CAS latency */
|
||||
temp = temp;
|
||||
LPC_EMC->DYNAMICCONTROL = 0x00000000; /* Issue NORMAL command */
|
||||
|
||||
//[re]enable buffers
|
||||
LPC_EMC->DYNAMICCONFIG0 |= 1<<19;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
uint32_t sdram_test( void )
|
||||
{
|
||||
volatile uint32_t *wr_ptr;
|
||||
volatile uint16_t *short_wr_ptr;
|
||||
uint32_t data;
|
||||
uint32_t i, j;
|
||||
|
||||
wr_ptr = (uint32_t *)SDRAM_BASE;
|
||||
short_wr_ptr = (uint16_t *)wr_ptr;
|
||||
|
||||
/* 16 bit write */
|
||||
for (i = 0; i < SDRAM_SIZE/0x40000; i++)
|
||||
{
|
||||
for (j = 0; j < 0x100; j++)
|
||||
{
|
||||
*short_wr_ptr++ = (i + j) & 0xFFFF;
|
||||
*short_wr_ptr++ = ((i + j) + 1) & 0xFFFF;
|
||||
}
|
||||
}
|
||||
|
||||
/* Verifying */
|
||||
wr_ptr = (uint32_t *)SDRAM_BASE;
|
||||
for (i = 0; i < SDRAM_SIZE/0x40000; i++)
|
||||
{
|
||||
for (j = 0; j < 0x100; j++)
|
||||
{
|
||||
data = *wr_ptr;
|
||||
if (data != (((((i + j) + 1) & 0xFFFF) << 16) | ((i + j) & 0xFFFF)))
|
||||
{
|
||||
return 0x0;
|
||||
}
|
||||
wr_ptr++;
|
||||
}
|
||||
}
|
||||
return 0x1;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,31 +0,0 @@
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright(C) 2011, Embedded Artists AB
|
||||
* All rights reserved.
|
||||
*
|
||||
******************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* Embedded Artists AB assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. Embedded Artists AB
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. Embedded Artists AB also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
*****************************************************************************/
|
||||
#ifndef __SDRAM_H
|
||||
#define __SDRAM_H
|
||||
|
||||
#define SDRAM_SIZE 0x2000000 /* 256Mbit = 32MB */
|
||||
|
||||
#define SDRAM_BASE 0x28000000 /*CS0*/
|
||||
|
||||
extern uint32_t sdram_init(void);
|
||||
extern uint32_t sdram_test(void);
|
||||
|
||||
#endif /* end __SDRAM_H */
|
||||
/****************************************************************************
|
||||
** End Of File
|
||||
*****************************************************************************/
|
||||
@@ -1,509 +0,0 @@
|
||||
//*****************************************************************************
|
||||
// LPC43xx (Cortex-M4) Microcontroller Startup code for use with LPCXpresso IDE
|
||||
//
|
||||
// Version : 150706
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Copyright(C) NXP Semiconductors, 2013-2015
|
||||
// All rights reserved.
|
||||
//
|
||||
// Software that is described herein is for illustrative purposes only
|
||||
// which provides customers with programming information regarding the
|
||||
// LPC products. This software is supplied "AS IS" without any warranties of
|
||||
// any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
// all warranties, express or implied, including all implied warranties of
|
||||
// merchantability, fitness for a particular purpose and non-infringement of
|
||||
// intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
// or liability for the use of the software, conveys no license or rights under any
|
||||
// patent, copyright, mask work right, or any other intellectual property rights in
|
||||
// or to any products. NXP Semiconductors reserves the right to make changes
|
||||
// in the software without notification. NXP Semiconductors also makes no
|
||||
// representation or warranty that such application will be suitable for the
|
||||
// specified use without further testing or modification.
|
||||
//
|
||||
// Permission to use, copy, modify, and distribute this software and its
|
||||
// documentation is hereby granted, under NXP Semiconductors' and its
|
||||
// licensor's relevant copyrights in the software, without fee, provided that it
|
||||
// is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
// copyright, permission, and disclaimer notice must appear in all copies of
|
||||
// this code.
|
||||
//*****************************************************************************
|
||||
|
||||
#if defined (__cplusplus)
|
||||
#ifdef __REDLIB__
|
||||
#error Redlib does not support C++
|
||||
#else
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The entry point for the C++ library startup
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern "C" {
|
||||
extern void __libc_init_array(void);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define WEAK __attribute__ ((weak))
|
||||
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
|
||||
|
||||
//*****************************************************************************
|
||||
#if defined (__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
|
||||
// Declaration of external SystemInit function
|
||||
extern void SystemInit(void);
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Forward declaration of the default handlers. These are aliased.
|
||||
// When the application defines a handler (with the same name), this will
|
||||
// automatically take precedence over these weak definitions
|
||||
//
|
||||
//*****************************************************************************
|
||||
void ResetISR(void);
|
||||
WEAK void NMI_Handler(void);
|
||||
WEAK void HardFault_Handler(void);
|
||||
WEAK void MemManage_Handler(void);
|
||||
WEAK void BusFault_Handler(void);
|
||||
WEAK void UsageFault_Handler(void);
|
||||
WEAK void SVC_Handler(void);
|
||||
WEAK void DebugMon_Handler(void);
|
||||
WEAK void PendSV_Handler(void);
|
||||
WEAK void SysTick_Handler(void);
|
||||
WEAK void IntDefaultHandler(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Forward declaration of the specific IRQ handlers. These are aliased
|
||||
// to the IntDefaultHandler, which is a 'forever' loop. When the application
|
||||
// defines a handler (with the same name), this will automatically take
|
||||
// precedence over these weak definitions
|
||||
//
|
||||
//*****************************************************************************
|
||||
void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
#if defined (__USE_LPCOPEN)
|
||||
void M0APP_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
#else
|
||||
void M0CORE_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
#endif
|
||||
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void FLASH_EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void USB0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void USB1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void I2S0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void I2S1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SPIFI_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SGPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void GPIO0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void GPIO1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void GPIO2_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void GPIO3_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void GPIO4_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void GPIO5_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void GPIO6_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void GPIO7_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
#if defined (__USE_LPCOPEN)
|
||||
void ADCHS_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
#else
|
||||
void VADC_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
#endif
|
||||
void ATIMER_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void M0SUB_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The entry point for the application.
|
||||
// __main() is the entry point for Redlib based applications
|
||||
// main() is the entry point for Newlib based applications
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined (__REDLIB__)
|
||||
extern void __main(void);
|
||||
#endif
|
||||
extern int main(void);
|
||||
//*****************************************************************************
|
||||
//
|
||||
// External declaration for the pointer to the stack top from the Linker Script
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void _vStackTop(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// External declaration for LPC MCU vector table checksum from Linker Script
|
||||
//
|
||||
//*****************************************************************************
|
||||
WEAK extern void __valid_user_code_checksum();
|
||||
|
||||
//*****************************************************************************
|
||||
#if defined (__cplusplus)
|
||||
} // extern "C"
|
||||
#endif
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The vector table.
|
||||
// This relies on the linker script to place at correct location in memory.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void (* const g_pfnVectors[])(void);
|
||||
__attribute__ ((used,section(".isr_vector")))
|
||||
void (* const g_pfnVectors[])(void) = {
|
||||
// Core Level - CM4
|
||||
&_vStackTop, // The initial stack pointer
|
||||
ResetISR, // The reset handler
|
||||
NMI_Handler, // The NMI handler
|
||||
HardFault_Handler, // The hard fault handler
|
||||
MemManage_Handler, // The MPU fault handler
|
||||
BusFault_Handler, // The bus fault handler
|
||||
UsageFault_Handler, // The usage fault handler
|
||||
__valid_user_code_checksum, // LPC MCU Checksum
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
SVC_Handler, // SVCall handler
|
||||
DebugMon_Handler, // Debug monitor handler
|
||||
0, // Reserved
|
||||
PendSV_Handler, // The PendSV handler
|
||||
SysTick_Handler, // The SysTick handler
|
||||
|
||||
// Chip Level - LPC43 (M4)
|
||||
DAC_IRQHandler, // 16
|
||||
#if defined (__USE_LPCOPEN)
|
||||
M0APP_IRQHandler, // 17 CortexM4/M0 (LPC43XX ONLY)
|
||||
#else
|
||||
M0CORE_IRQHandler, // 17
|
||||
#endif
|
||||
DMA_IRQHandler, // 18
|
||||
0, // 19
|
||||
FLASH_EEPROM_IRQHandler, // 20 ORed flash Bank A, flash Bank B, EEPROM interrupts
|
||||
ETH_IRQHandler, // 21
|
||||
SDIO_IRQHandler, // 22
|
||||
LCD_IRQHandler, // 23
|
||||
USB0_IRQHandler, // 24
|
||||
USB1_IRQHandler, // 25
|
||||
SCT_IRQHandler, // 26
|
||||
RIT_IRQHandler, // 27
|
||||
TIMER0_IRQHandler, // 28
|
||||
TIMER1_IRQHandler, // 29
|
||||
TIMER2_IRQHandler, // 30
|
||||
TIMER3_IRQHandler, // 31
|
||||
MCPWM_IRQHandler, // 32
|
||||
ADC0_IRQHandler, // 33
|
||||
I2C0_IRQHandler, // 34
|
||||
I2C1_IRQHandler, // 35
|
||||
SPI_IRQHandler, // 36
|
||||
ADC1_IRQHandler, // 37
|
||||
SSP0_IRQHandler, // 38
|
||||
SSP1_IRQHandler, // 39
|
||||
UART0_IRQHandler, // 40
|
||||
UART1_IRQHandler, // 41
|
||||
UART2_IRQHandler, // 42
|
||||
UART3_IRQHandler, // 43
|
||||
I2S0_IRQHandler, // 44
|
||||
I2S1_IRQHandler, // 45
|
||||
SPIFI_IRQHandler, // 46
|
||||
SGPIO_IRQHandler, // 47
|
||||
GPIO0_IRQHandler, // 48
|
||||
GPIO1_IRQHandler, // 49
|
||||
GPIO2_IRQHandler, // 50
|
||||
GPIO3_IRQHandler, // 51
|
||||
GPIO4_IRQHandler, // 52
|
||||
GPIO5_IRQHandler, // 53
|
||||
GPIO6_IRQHandler, // 54
|
||||
GPIO7_IRQHandler, // 55
|
||||
GINT0_IRQHandler, // 56
|
||||
GINT1_IRQHandler, // 57
|
||||
EVRT_IRQHandler, // 58
|
||||
CAN1_IRQHandler, // 59
|
||||
0, // 60
|
||||
#if defined (__USE_LPCOPEN)
|
||||
ADCHS_IRQHandler, // 61 ADCHS combined interrupt
|
||||
#else
|
||||
VADC_IRQHandler, // 61
|
||||
#endif
|
||||
ATIMER_IRQHandler, // 62
|
||||
RTC_IRQHandler, // 63
|
||||
0, // 64
|
||||
WDT_IRQHandler, // 65
|
||||
M0SUB_IRQHandler, // 66
|
||||
CAN0_IRQHandler, // 67
|
||||
QEI_IRQHandler, // 68
|
||||
};
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
// Functions to carry out the initialization of RW and BSS data sections. These
|
||||
// are written as separate functions rather than being inlined within the
|
||||
// ResetISR() function in order to cope with MCUs with multiple banks of
|
||||
// memory.
|
||||
//*****************************************************************************
|
||||
__attribute__((section(".after_vectors"
|
||||
)))
|
||||
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
|
||||
unsigned int *pulDest = (unsigned int*) start;
|
||||
unsigned int *pulSrc = (unsigned int*) romstart;
|
||||
unsigned int loop;
|
||||
for (loop = 0; loop < len; loop = loop + 4)
|
||||
*pulDest++ = *pulSrc++;
|
||||
}
|
||||
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void bss_init(unsigned int start, unsigned int len) {
|
||||
unsigned int *pulDest = (unsigned int*) start;
|
||||
unsigned int loop;
|
||||
for (loop = 0; loop < len; loop = loop + 4)
|
||||
*pulDest++ = 0;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
// The following symbols are constructs generated by the linker, indicating
|
||||
// the location of various points in the "Global Section Table". This table is
|
||||
// created by the linker via the Code Red managed linker script mechanism. It
|
||||
// contains the load address, execution address and length of each RW data
|
||||
// section and the execution and length of each BSS (zero initialized) section.
|
||||
//*****************************************************************************
|
||||
extern unsigned int __data_section_table;
|
||||
extern unsigned int __data_section_table_end;
|
||||
extern unsigned int __bss_section_table;
|
||||
extern unsigned int __bss_section_table_end;
|
||||
|
||||
//*****************************************************************************
|
||||
// Reset entry point for your code.
|
||||
// Sets up a simple runtime environment and initializes the C/C++
|
||||
// library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void ResetISR(void) {
|
||||
|
||||
// *************************************************************
|
||||
// The following conditional block of code manually resets as
|
||||
// much of the peripheral set of the LPC43 as possible. This is
|
||||
// done because the LPC43 does not provide a means of triggering
|
||||
// a full system reset under debugger control, which can cause
|
||||
// problems in certain circumstances when debugging.
|
||||
//
|
||||
// You can prevent this code block being included if you require
|
||||
// (for example when creating a final executable which you will
|
||||
// not debug) by setting the define 'DONT_RESET_ON_RESTART'.
|
||||
//
|
||||
#ifndef DONT_RESET_ON_RESTART
|
||||
|
||||
// Disable interrupts
|
||||
__asm volatile ("cpsid i");
|
||||
// equivalent to CMSIS '__disable_irq()' function
|
||||
|
||||
unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100;
|
||||
// LPC_RGU->RESET_CTRL0 @ 0x40053100
|
||||
// LPC_RGU->RESET_CTRL1 @ 0x40053104
|
||||
// Note that we do not use the CMSIS register access mechanism,
|
||||
// as there is no guarantee that the project has been configured
|
||||
// to use CMSIS.
|
||||
|
||||
// Write to LPC_RGU->RESET_CTRL0
|
||||
*(RESET_CONTROL + 0) = 0x10DF1000;
|
||||
// GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST|
|
||||
// USB1_RST|USB0_RST|LCD_RST|M0_SUB_RST
|
||||
|
||||
// Write to LPC_RGU->RESET_CTRL1
|
||||
*(RESET_CONTROL + 1) = 0x01DFF7FF;
|
||||
// M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST|
|
||||
// I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST|
|
||||
// DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST|
|
||||
// RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST
|
||||
|
||||
// Clear all pending interrupts in the NVIC
|
||||
volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
|
||||
unsigned int irqpendloop;
|
||||
for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) {
|
||||
*(NVIC_ICPR + irqpendloop) = 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
// Reenable interrupts
|
||||
__asm volatile ("cpsie i");
|
||||
// equivalent to CMSIS '__enable_irq()' function
|
||||
|
||||
#endif // ifndef DONT_RESET_ON_RESTART
|
||||
// *************************************************************
|
||||
|
||||
#if defined (__USE_LPCOPEN)
|
||||
SystemInit();
|
||||
#endif
|
||||
|
||||
//
|
||||
// Copy the data sections from flash to SRAM.
|
||||
//
|
||||
unsigned int LoadAddr, ExeAddr, SectionLen;
|
||||
unsigned int *SectionTableAddr;
|
||||
|
||||
// Load base address of Global Section Table
|
||||
SectionTableAddr = &__data_section_table;
|
||||
|
||||
// Copy the data sections from flash to SRAM.
|
||||
while (SectionTableAddr < &__data_section_table_end) {
|
||||
LoadAddr = *SectionTableAddr++;
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
data_init(LoadAddr, ExeAddr, SectionLen);
|
||||
}
|
||||
// At this point, SectionTableAddr = &__bss_section_table;
|
||||
// Zero fill the bss segment
|
||||
while (SectionTableAddr < &__bss_section_table_end) {
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
bss_init(ExeAddr, SectionLen);
|
||||
}
|
||||
|
||||
#if !defined (__USE_LPCOPEN)
|
||||
// LPCOpen init code deals with FP and VTOR initialisation
|
||||
#if defined (__VFP_FP__) && !defined (__SOFTFP__)
|
||||
/*
|
||||
* Code to enable the Cortex-M4 FPU only included
|
||||
* if appropriate build options have been selected.
|
||||
* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
|
||||
*/
|
||||
// CPACR is located at address 0xE000ED88
|
||||
asm("LDR.W R0, =0xE000ED88");
|
||||
// Read CPACR
|
||||
asm("LDR R1, [R0]");
|
||||
// Set bits 20-23 to enable CP10 and CP11 coprocessors
|
||||
asm(" ORR R1, R1, #(0xF << 20)");
|
||||
// Write back the modified value to the CPACR
|
||||
asm("STR R1, [R0]");
|
||||
#endif // (__VFP_FP__) && !(__SOFTFP__)
|
||||
// ******************************
|
||||
// Check to see if we are running the code from a non-zero
|
||||
// address (eg RAM, external flash), in which case we need
|
||||
// to modify the VTOR register to tell the CPU that the
|
||||
// vector table is located at a non-0x0 address.
|
||||
|
||||
// Note that we do not use the CMSIS register access mechanism,
|
||||
// as there is no guarantee that the project has been configured
|
||||
// to use CMSIS.
|
||||
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
|
||||
if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) {
|
||||
// CMSIS : SCB->VTOR = <address of vector table>
|
||||
*pSCB_VTOR = (unsigned int) g_pfnVectors;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (__USE_CMSIS)
|
||||
SystemInit();
|
||||
#endif
|
||||
|
||||
#if defined (__cplusplus)
|
||||
//
|
||||
// Call C++ library initialisation
|
||||
//
|
||||
__libc_init_array();
|
||||
#endif
|
||||
|
||||
#if defined (__REDLIB__)
|
||||
// Call the Redlib library, which in turn calls main()
|
||||
__main();
|
||||
#else
|
||||
main();
|
||||
#endif
|
||||
|
||||
//
|
||||
// main() shouldn't return, but if it does, we'll just enter an infinite loop
|
||||
//
|
||||
while (1) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
// Default exception handlers. Override the ones here by defining your own
|
||||
// handler routines in your application code.
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void NMI_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void HardFault_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void MemManage_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void BusFault_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void UsageFault_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void SVC_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void DebugMon_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void PendSV_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void SysTick_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Processor ends up here if an unexpected interrupt occurs or a specific
|
||||
// handler is not present in the application code.
|
||||
//
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void IntDefaultHandler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
@@ -1,154 +0,0 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file board_mcb4300.c
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#include "../board.h"
|
||||
|
||||
#ifdef BOARD_MCB4300
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// INCLUDE
|
||||
//--------------------------------------------------------------------+
|
||||
#define BOARD_MAX_LEDS 8
|
||||
|
||||
#define BOARD_UART_PORT LPC_USART0
|
||||
#define BOARD_UART_PIN_PORT 2
|
||||
#define BOARD_UART_PIN_TX 0
|
||||
#define BOARD_UART_PIN_RX 1
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO CONSTANT TYPEDEF
|
||||
//--------------------------------------------------------------------+
|
||||
static const uint8_t ledports[] = {6, 6, 6, 6, 6, 4, 4, 4};
|
||||
static const uint8_t ledbits[] = {24, 25, 26, 27, 28, 12, 13, 14};
|
||||
|
||||
const static struct {
|
||||
uint8_t port;
|
||||
uint8_t pin;
|
||||
}leds[BOARD_MAX_LEDS] = {
|
||||
{6, 24}, {6, 25}, {6, 26}, {6, 27},
|
||||
{4, 28}, {4, 12}, {4, 13}, {4, 14}};
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// INTERNAL OBJECT & FUNCTION DECLARATION
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// IMPLEMENTATION
|
||||
//--------------------------------------------------------------------+
|
||||
void board_init(void)
|
||||
{
|
||||
CGU_Init();
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE // TODO may move to main.c
|
||||
SysTick_Config(CGU_GetPCLKFrequency(CGU_PERIPHERAL_M4CORE) / BOARD_TICKS_HZ); // 1 msec tick timer
|
||||
#endif
|
||||
|
||||
//------------- USB Bus power HOST ONLY-------------//
|
||||
// Keil VBUS0 is P6_3
|
||||
scu_pinmux(0x6, 3, MD_PUP | MD_EZI, FUNC1); // P6_3 USB0_PWR_EN, USB0 VBus function
|
||||
|
||||
// Keil VBUS1 is P9_5
|
||||
scu_pinmux(0x9, 5, MD_PUP | MD_EZI, FUNC2); // P9_5 USB1_PWR_EN, USB1 VBus function
|
||||
|
||||
//------------- LEDs init, J21 must be installed -------------//
|
||||
LPC_SCU->SFSPD_10 = 4; // GPIO6[24]
|
||||
LPC_SCU->SFSPD_11 = 4; // GPIO6[25]
|
||||
LPC_SCU->SFSPD_12 = 4; // GPIO6[26]
|
||||
LPC_SCU->SFSPD_13 = 4; // GPIO6[27]
|
||||
LPC_SCU->SFSPD_14 = 4; // GPIO6[28]
|
||||
LPC_SCU->SFSP9_0 = 0; // GPIO4[12]
|
||||
LPC_SCU->SFSP9_1 = 0; // GPIO4[13]
|
||||
LPC_SCU->SFSP9_2 = 0; // GPIO4[14]
|
||||
|
||||
for(uint32_t i=0; i<BOARD_MAX_LEDS; i++)
|
||||
{
|
||||
GPIO_SetDir(leds[i].port, BIT_(leds[i].pin), 1); // output
|
||||
}
|
||||
|
||||
//------------- UART -------------//
|
||||
scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_TX, MD_PDN , FUNC1);
|
||||
scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_RX, MD_PLN|MD_EZI|MD_ZI, FUNC1);
|
||||
|
||||
UART_CFG_Type UARTConfigStruct;
|
||||
UART_ConfigStructInit(&UARTConfigStruct);
|
||||
UARTConfigStruct.Baud_rate = CFG_UART_BAUDRATE;
|
||||
UARTConfigStruct.Clock_Speed = 0;
|
||||
|
||||
UART_Init(BOARD_UART_PORT, &UARTConfigStruct);
|
||||
UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// LEDS
|
||||
//--------------------------------------------------------------------+
|
||||
void board_leds(uint32_t on_mask, uint32_t off_mask)
|
||||
{
|
||||
for (uint32_t i=0; i<BOARD_MAX_LEDS; i++)
|
||||
{
|
||||
if ( on_mask & BIT_(i))
|
||||
{
|
||||
GPIO_SetValue(leds[i].port, BIT_(leds[i].pin));
|
||||
}else if ( off_mask & BIT_(i)) // on_mask take precedence over off_mask
|
||||
{
|
||||
GPIO_ClearValue(leds[i].port, BIT_(leds[i].pin));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// BUTTONS
|
||||
//--------------------------------------------------------------------+
|
||||
uint32_t board_buttons(void)
|
||||
{
|
||||
return 0; // TODO buttons for mcb4300
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// UART
|
||||
//--------------------------------------------------------------------+
|
||||
uint8_t board_uart_getchar(void)
|
||||
{
|
||||
return UART_ReceiveByte(BOARD_UART_PORT);
|
||||
}
|
||||
|
||||
void board_uart_putchar(uint8_t c)
|
||||
{
|
||||
UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,59 +0,0 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file board_mcb4300.h
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef _TUSB_BOARD_MCB4300_H_
|
||||
#define _TUSB_BOARD_MCB4300_H_
|
||||
|
||||
#include "LPC43xx.h"
|
||||
#include "lpc43xx_scu.h"
|
||||
#include "lpc43xx_cgu.h"
|
||||
#include "lpc43xx_gpio.h"
|
||||
#include "lpc43xx_uart.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CFG_PRINTF_TARGET PRINTF_TARGET_UART
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_BOARD_MCB4300_H_ */
|
||||
@@ -1,126 +0,0 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file board_lpclink2.c
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#include "../board.h"
|
||||
|
||||
#if BOARD == BOARD_LPCLINK2
|
||||
|
||||
#define BOARD_UART_PORT LPC_USART0
|
||||
#define BOARD_UART_PIN_PORT 0x0f
|
||||
#define BOARD_UART_PIN_TX 10 // PF.10 : UART0_TXD
|
||||
#define BOARD_UART_PIN_RX 11 // PF.11 : UART0_RXD
|
||||
|
||||
#define BOARD_MAX_LEDS 1
|
||||
|
||||
const static struct {
|
||||
uint8_t port;
|
||||
uint8_t pin;
|
||||
}leds[BOARD_MAX_LEDS] = { {0, 8} };
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
CGU_Init();
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE // TODO may move to main.c
|
||||
SysTick_Config(CGU_GetPCLKFrequency(CGU_PERIPHERAL_M4CORE) / BOARD_TICKS_HZ); // 1 msec tick timer
|
||||
#endif
|
||||
|
||||
//------------- USB -------------//
|
||||
|
||||
|
||||
//------------- LED -------------//
|
||||
for (uint8_t i=0; i<BOARD_MAX_LEDS; i++)
|
||||
{
|
||||
scu_pinmux(leds[i].port, leds[i].pin, MD_PUP|MD_EZI|MD_ZI, FUNC0);
|
||||
GPIO_SetDir(leds[i].port, BIT_(leds[i].pin), 1); // output
|
||||
}
|
||||
|
||||
|
||||
#if CFG_UART_ENABLE
|
||||
//------------- UART -------------//
|
||||
scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_TX, MD_PDN, FUNC1);
|
||||
scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_RX, MD_PLN | MD_EZI | MD_ZI, FUNC1);
|
||||
|
||||
UART_CFG_Type UARTConfigStruct;
|
||||
UART_ConfigStructInit(&UARTConfigStruct);
|
||||
UARTConfigStruct.Baud_rate = CFG_UART_BAUDRATE;
|
||||
UARTConfigStruct.Clock_Speed = 0;
|
||||
|
||||
UART_Init(BOARD_UART_PORT, &UARTConfigStruct);
|
||||
UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
|
||||
#endif
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// LEDS
|
||||
//--------------------------------------------------------------------+
|
||||
void board_leds(uint32_t on_mask, uint32_t off_mask)
|
||||
{
|
||||
for (uint32_t i=0; i<BOARD_MAX_LEDS; i++)
|
||||
{
|
||||
if ( on_mask & BIT_(i))
|
||||
{
|
||||
GPIO_SetValue(leds[i].port, BIT_(leds[i].pin));
|
||||
}else if ( off_mask & BIT_(i)) // on_mask take precedence over off_mask
|
||||
{
|
||||
GPIO_ClearValue(leds[i].port, BIT_(leds[i].pin));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// UART
|
||||
//--------------------------------------------------------------------+
|
||||
#if CFG_UART_ENABLE
|
||||
uint32_t board_uart_send(uint8_t *buffer, uint32_t length)
|
||||
{
|
||||
return UART_Send(BOARD_UART_PORT, buffer, length, BLOCKING);
|
||||
}
|
||||
|
||||
uint32_t board_uart_recv(uint8_t *buffer, uint32_t length)
|
||||
{
|
||||
return UART_Receive(BOARD_UART_PORT, buffer, length, BLOCKING);
|
||||
}
|
||||
|
||||
uint8_t board_uart_getchar(void)
|
||||
{
|
||||
return UART_ReceiveByte(BOARD_UART_PORT);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,59 +0,0 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file board_lpclink2.h
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef _TUSB_BOARD_LPCLINK2_H_
|
||||
#define _TUSB_BOARD_LPCLINK2_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "LPC43xx.h"
|
||||
#include "lpc43xx_scu.h"
|
||||
#include "lpc43xx_cgu.h"a
|
||||
#include "lpc43xx_gpio.h"
|
||||
#include "lpc43xx_uart.h"
|
||||
#include "lpc43xx_i2c.h"
|
||||
|
||||
#define CFG_PRINTF_TARGET PRINTF_TARGET_UART
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_BOARD_LPCLINK2_H_ */
|
||||
@@ -1,131 +0,0 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file board_lpcxpresso11u14.c
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#include "../board.h"
|
||||
|
||||
#ifdef BOARD_LPCXPRESSO11U14
|
||||
|
||||
#define LED_PORT (0)
|
||||
#define LED_PIN (7)
|
||||
#define LED_ON (1)
|
||||
|
||||
const static struct {
|
||||
uint8_t port;
|
||||
uint8_t pin;
|
||||
} buttons[] =
|
||||
{
|
||||
{1, 22 }, // Joystick up
|
||||
{1, 20 }, // Joystick down
|
||||
{1, 23 }, // Joystick left
|
||||
{1, 21 }, // Joystick right
|
||||
{1, 19 }, // Joystick press
|
||||
{0, 1 }, // SW3
|
||||
// {1, 4 }, // SW4 (require to remove J28)
|
||||
};
|
||||
|
||||
|
||||
enum {
|
||||
BOARD_BUTTON_COUNT = sizeof(buttons) / sizeof(buttons[0])
|
||||
};
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
SystemInit();
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE // TODO may move to main.c
|
||||
SysTick_Config(SystemCoreClock / BOARD_TICKS_HZ); // 1 msec tick timer
|
||||
#endif
|
||||
|
||||
GPIOInit();
|
||||
|
||||
//------------- LED -------------//
|
||||
GPIOSetDir(LED_PORT, LED_PIN, 1);
|
||||
|
||||
//------------- BUTTON -------------//
|
||||
for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) GPIOSetDir(buttons[i].port, buttons[i].pin, 0);
|
||||
|
||||
//------------- UART -------------//
|
||||
UARTInit(CFG_UART_BAUDRATE);
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// LEDS
|
||||
//--------------------------------------------------------------------+
|
||||
void board_leds(uint32_t on_mask, uint32_t off_mask)
|
||||
{
|
||||
if (on_mask & BIT_(0))
|
||||
{
|
||||
GPIOSetBitValue(LED_PORT, LED_PIN, LED_ON);
|
||||
}else if (off_mask & BIT_(0))
|
||||
{
|
||||
GPIOSetBitValue(LED_PORT, LED_PIN, 1 - LED_ON);
|
||||
}
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Buttons
|
||||
//--------------------------------------------------------------------+
|
||||
static bool button_read(uint8_t id)
|
||||
{
|
||||
return !GPIOGetPinValue(buttons[id].port, buttons[id].pin); // button is active low
|
||||
}
|
||||
|
||||
uint32_t board_buttons(void)
|
||||
{
|
||||
uint32_t result = 0;
|
||||
|
||||
for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? BIT_(i) : 0);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// UART
|
||||
//--------------------------------------------------------------------+
|
||||
void board_uart_putchar(uint8_t c)
|
||||
{
|
||||
UARTSend(&c, 1);
|
||||
}
|
||||
|
||||
uint8_t board_uart_getchar(void)
|
||||
{
|
||||
// *buffer = get_key(); TODO cannot find available code for uart getchar
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,57 +0,0 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file board_lpcxpresso11u14.h
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef _TUSB_BOARD_LPCXPRESSO11U14_H_
|
||||
#define _TUSB_BOARD_LPCXPRESSO11U14_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "LPC11Uxx.h"
|
||||
#include "lpc11uxx_gpio.h"
|
||||
#include "lpc11uxx_uart.h"
|
||||
|
||||
//#define CFG_PRINTF_TARGET PRINTF_TARGET_SEMIHOST
|
||||
#define CFG_PRINTF_TARGET PRINTF_TARGET_UART
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_BOARD_LPCXPRESSO11U14_H_ */
|
||||
@@ -36,16 +36,15 @@
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#include "../board.h"
|
||||
|
||||
#ifdef BOARD_LPCXPRESSO11U68
|
||||
|
||||
#define LED_PORT (1)
|
||||
#define LED_PIN (31)
|
||||
#define LED_ON (0)
|
||||
#define LED_OFF (1)
|
||||
#include "../board.h"
|
||||
|
||||
const static struct {
|
||||
#define LED_PORT 2
|
||||
#define LED_PIN 17
|
||||
#define LED_STATE_ON 0
|
||||
|
||||
static const struct {
|
||||
uint8_t port;
|
||||
uint8_t pin;
|
||||
} buttons[] = { { 0, 1 } };
|
||||
@@ -54,38 +53,78 @@ enum {
|
||||
BOARD_BUTTON_COUNT = sizeof(buttons) / sizeof(buttons[0])
|
||||
};
|
||||
|
||||
/* System oscillator rate and RTC oscillator rate */
|
||||
const uint32_t OscRateIn = 12000000;
|
||||
const uint32_t RTCOscRateIn = 32768;
|
||||
|
||||
/* Pin muxing table, only items that need changing from their default pin
|
||||
state are in this table. Not every pin is mapped. */
|
||||
static const PINMUX_GRP_T pinmuxing[] =
|
||||
{
|
||||
{0, 3, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // USB VBUS
|
||||
{0, 18, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 RX
|
||||
{0, 19, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 TX
|
||||
{2, 0, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // XTALIN
|
||||
{2, 1, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // XTALOUT
|
||||
};
|
||||
|
||||
// Invoked by startup code
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Enable IOCON clock */
|
||||
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
|
||||
Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
|
||||
Chip_SetupXtalClocking();
|
||||
}
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
SystemInit();
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE // TODO may move to main.c
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
SysTick_Config(SystemCoreClock / BOARD_TICKS_HZ); // 1 msec tick timer
|
||||
#endif
|
||||
|
||||
GPIOInit();
|
||||
Chip_GPIO_Init(LPC_GPIO);
|
||||
|
||||
//------------- LED -------------//
|
||||
GPIOSetDir(LED_PORT, LED_PIN, 1);
|
||||
Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
|
||||
|
||||
//------------- BUTTON -------------//
|
||||
for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) GPIOSetDir(buttons[i].port, buttons[i].pin, 0);
|
||||
//for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) GPIOSetDir(buttons[i].port, buttons[i].pin, 0);
|
||||
|
||||
//------------- UART -------------//
|
||||
UARTInit(CFG_UART_BAUDRATE);
|
||||
//UARTInit(CFG_UART_BAUDRATE);
|
||||
|
||||
// USB
|
||||
Chip_USB_Init(); // Setup PLL clock, and power
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
/* TUSB HAL MILLISECOND
|
||||
*------------------------------------------------------------------*/
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
|
||||
volatile uint32_t system_ticks = 0;
|
||||
|
||||
void SysTick_Handler (void)
|
||||
{
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t tusb_hal_millis(void)
|
||||
{
|
||||
return board_tick2ms(system_ticks);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// LEDS
|
||||
//--------------------------------------------------------------------+
|
||||
void board_leds(uint32_t on_mask, uint32_t off_mask)
|
||||
void board_led_control(bool state)
|
||||
{
|
||||
if (on_mask & BIT_(0))
|
||||
{
|
||||
GPIOSetBitValue(LED_PORT, LED_PIN, LED_ON);
|
||||
}else if (off_mask & BIT_(0))
|
||||
{
|
||||
GPIOSetBitValue(LED_PORT, LED_PIN, LED_OFF);
|
||||
}
|
||||
Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
@@ -94,7 +133,8 @@ void board_leds(uint32_t on_mask, uint32_t off_mask)
|
||||
uint32_t board_buttons(void)
|
||||
{
|
||||
// for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) GPIOGetPinValue(buttons[i].port, buttons[i].pin);
|
||||
return GPIOGetPinValue(buttons[0].port, buttons[0].pin) ? 0 : 1; // button is active low
|
||||
// return GPIOGetPinValue(buttons[0].port, buttons[0].pin) ? 0 : 1; // button is active low
|
||||
return 0;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
@@ -102,7 +142,8 @@ uint32_t board_buttons(void)
|
||||
//--------------------------------------------------------------------+
|
||||
void board_uart_putchar(uint8_t c)
|
||||
{
|
||||
UARTSend(&c, 1);
|
||||
(void) c;
|
||||
//UARTSend(&c, 1);
|
||||
}
|
||||
|
||||
uint8_t board_uart_getchar(void)
|
||||
|
||||
@@ -43,12 +43,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "LPC11Uxx.h"
|
||||
#include "lpc11uxx_gpio.h"
|
||||
#include "lpc11uxx_uart.h"
|
||||
|
||||
//#define CFG_PRINTF_TARGET PRINTF_TARGET_SEMIHOST
|
||||
#define CFG_PRINTF_TARGET PRINTF_TARGET_UART
|
||||
#include "chip.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -1,382 +0,0 @@
|
||||
//*****************************************************************************
|
||||
// +--+
|
||||
// | ++----+
|
||||
// +-++ |
|
||||
// | |
|
||||
// +-+--+ |
|
||||
// | +--+--+
|
||||
// +----+ Copyright (c) 2011 Code Red Technologies Ltd.
|
||||
//
|
||||
// Microcontroller Startup code for use with Red Suite
|
||||
//
|
||||
// Version : 110323
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// The software is owned by Code Red Technologies and/or its suppliers, and is
|
||||
// protected under applicable copyright laws. All rights are reserved. Any
|
||||
// use in violation of the foregoing restrictions may subject the user to criminal
|
||||
// sanctions under applicable laws, as well as to civil liability for the breach
|
||||
// of the terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
|
||||
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
|
||||
// CODE RED TECHNOLOGIES LTD.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined (__cplusplus)
|
||||
#ifdef __REDLIB__
|
||||
#error Redlib does not support C++
|
||||
#else
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The entry point for the C++ library startup
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern "C" {
|
||||
extern void __libc_init_array(void);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define WEAK __attribute__ ((weak))
|
||||
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
|
||||
#define SVCall_Handler SVC_Handler
|
||||
|
||||
// Code Red - if CMSIS is being used, then SystemInit() routine
|
||||
// will be called by startup code rather than in application's main()
|
||||
#if defined (__USE_CMSIS)
|
||||
#include "LPC11Uxx.h"
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
#if defined (__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Forward declaration of the default handlers. These are aliased.
|
||||
// When the application defines a handler (with the same name), this will
|
||||
// automatically take precedence over these weak definitions
|
||||
//
|
||||
//*****************************************************************************
|
||||
void ResetISR(void);
|
||||
WEAK void NMI_Handler(void);
|
||||
WEAK void HardFault_Handler(void);
|
||||
WEAK void SVCall_Handler(void);
|
||||
WEAK void PendSV_Handler(void);
|
||||
WEAK void SysTick_Handler(void);
|
||||
WEAK void IntDefaultHandler(void);
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Forward declaration of the specific IRQ handlers. These are aliased
|
||||
// to the IntDefaultHandler, which is a 'forever' loop. When the application
|
||||
// defines a handler (with the same name), this will automatically take
|
||||
// precedence over these weak definitions
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
void FLEX_INT0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void FLEX_INT1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void FLEX_INT2_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void FLEX_INT3_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void FLEX_INT4_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void FLEX_INT5_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void FLEX_INT6_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void FLEX_INT7_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void GINT0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void GINT1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void I2C_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void TIMER16_0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void TIMER16_1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void TIMER32_0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void TIMER32_1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void UART_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void USB_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void USB_FIQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void ADC_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void WDT_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void BOD_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void FMC_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void USBWakeup_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The entry point for the application.
|
||||
// __main() is the entry point for redlib based applications
|
||||
// main() is the entry point for newlib based applications
|
||||
//
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The entry point for the application.
|
||||
// __main() is the entry point for Redlib based applications
|
||||
// main() is the entry point for Newlib based applications
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined (__REDLIB__)
|
||||
extern void __main(void);
|
||||
#endif
|
||||
extern int main(void);
|
||||
//*****************************************************************************
|
||||
//
|
||||
// External declaration for the pointer to the stack top from the Linker Script
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void _vStackTop(void);
|
||||
|
||||
//*****************************************************************************
|
||||
#if defined (__cplusplus)
|
||||
} // extern "C"
|
||||
#endif
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The vector table. Note that the proper constructs must be placed on this to
|
||||
// ensure that it ends up at physical address 0x0000.0000.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void (* const g_pfnVectors[])(void);
|
||||
__attribute__ ((section(".isr_vector")))
|
||||
void (* const g_pfnVectors[])(void) = {
|
||||
&_vStackTop, // The initial stack pointer
|
||||
ResetISR, // The reset handler
|
||||
NMI_Handler, // The NMI handler
|
||||
HardFault_Handler, // The hard fault handler
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
SVCall_Handler, // SVCall handler
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
PendSV_Handler, // The PendSV handler
|
||||
SysTick_Handler, // The SysTick handler
|
||||
|
||||
// LPC11U specific handlers
|
||||
FLEX_INT0_IRQHandler, // 0 - GPIO pin interrupt 0
|
||||
FLEX_INT1_IRQHandler, // 1 - GPIO pin interrupt 1
|
||||
FLEX_INT2_IRQHandler, // 2 - GPIO pin interrupt 2
|
||||
FLEX_INT3_IRQHandler, // 3 - GPIO pin interrupt 3
|
||||
FLEX_INT4_IRQHandler, // 4 - GPIO pin interrupt 4
|
||||
FLEX_INT5_IRQHandler, // 5 - GPIO pin interrupt 5
|
||||
FLEX_INT6_IRQHandler, // 6 - GPIO pin interrupt 6
|
||||
FLEX_INT7_IRQHandler, // 7 - GPIO pin interrupt 7
|
||||
GINT0_IRQHandler, // 8 - GPIO GROUP0 interrupt
|
||||
GINT1_IRQHandler, // 9 - GPIO GROUP1 interrupt
|
||||
0, // 10 - Reserved
|
||||
0, // 11 - Reserved
|
||||
0, // 12 - Reserved
|
||||
0, // 13 - Reserved
|
||||
SSP1_IRQHandler, // 14 - SPI/SSP1 Interrupt
|
||||
I2C_IRQHandler, // 15 - I2C0
|
||||
TIMER16_0_IRQHandler, // 16 - CT16B0 (16-bit Timer 0)
|
||||
TIMER16_1_IRQHandler, // 17 - CT16B1 (16-bit Timer 1)
|
||||
TIMER32_0_IRQHandler, // 18 - CT32B0 (32-bit Timer 0)
|
||||
TIMER32_1_IRQHandler, // 19 - CT32B1 (32-bit Timer 1)
|
||||
SSP0_IRQHandler, // 20 - SPI/SSP0 Interrupt
|
||||
UART_IRQHandler, // 21 - UART0
|
||||
USB_IRQHandler, // 22 - USB IRQ
|
||||
USB_FIQHandler, // 23 - USB FIQ
|
||||
ADC_IRQHandler, // 24 - ADC (A/D Converter)
|
||||
WDT_IRQHandler, // 25 - WDT (Watchdog Timer)
|
||||
BOD_IRQHandler, // 26 - BOD (Brownout Detect)
|
||||
FMC_IRQHandler, // 27 - IP2111 Flash Memory Controller
|
||||
0, // 28 - Reserved
|
||||
0, // 29 - Reserved
|
||||
USBWakeup_IRQHandler, // 30 - USB wake-up interrupt
|
||||
0, // 31 - Reserved
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
// Functions to carry out the initialization of RW and BSS data sections. These
|
||||
// are written as separate functions rather than being inlined within the
|
||||
// ResetISR() function in order to cope with MCUs with multiple banks of
|
||||
// memory.
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
|
||||
unsigned int *pulDest = (unsigned int*) start;
|
||||
unsigned int *pulSrc = (unsigned int*) romstart;
|
||||
unsigned int loop;
|
||||
for (loop = 0; loop < len; loop = loop + 4)
|
||||
*pulDest++ = *pulSrc++;
|
||||
}
|
||||
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void bss_init(unsigned int start, unsigned int len) {
|
||||
unsigned int *pulDest = (unsigned int*) start;
|
||||
unsigned int loop;
|
||||
for (loop = 0; loop < len; loop = loop + 4)
|
||||
*pulDest++ = 0;
|
||||
}
|
||||
|
||||
#ifndef USE_OLD_STYLE_DATA_BSS_INIT
|
||||
//*****************************************************************************
|
||||
// The following symbols are constructs generated by the linker, indicating
|
||||
// the location of various points in the "Global Section Table". This table is
|
||||
// created by the linker via the Code Red managed linker script mechanism. It
|
||||
// contains the load address, execution address and length of each RW data
|
||||
// section and the execution and length of each BSS (zero initialized) section.
|
||||
//*****************************************************************************
|
||||
extern unsigned int __data_section_table;
|
||||
extern unsigned int __data_section_table_end;
|
||||
extern unsigned int __bss_section_table;
|
||||
extern unsigned int __bss_section_table_end;
|
||||
#else
|
||||
//*****************************************************************************
|
||||
// The following symbols are constructs generated by the linker, indicating
|
||||
// the load address, execution address and length of the RW data section and
|
||||
// the execution and length of the BSS (zero initialized) section.
|
||||
// Note that these symbols are not normally used by the managed linker script
|
||||
// mechanism in Red Suite/LPCXpresso 3.6 (Windows) and LPCXpresso 3.8 (Linux).
|
||||
// They are provide here simply so this startup code can be used with earlier
|
||||
// versions of Red Suite which do not support the more advanced managed linker
|
||||
// script mechanism introduced in the above version. To enable their use,
|
||||
// define "USE_OLD_STYLE_DATA_BSS_INIT".
|
||||
//*****************************************************************************
|
||||
extern unsigned int _etext;
|
||||
extern unsigned int _data;
|
||||
extern unsigned int _edata;
|
||||
extern unsigned int _bss;
|
||||
extern unsigned int _ebss;
|
||||
#endif
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
// Reset entry point for your code.
|
||||
// Sets up a simple runtime environment and initializes the C/C++
|
||||
// library.
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void
|
||||
ResetISR(void) {
|
||||
|
||||
#ifndef USE_OLD_STYLE_DATA_BSS_INIT
|
||||
//
|
||||
// Copy the data sections from flash to SRAM.
|
||||
//
|
||||
unsigned int LoadAddr, ExeAddr, SectionLen;
|
||||
unsigned int *SectionTableAddr;
|
||||
|
||||
// Load base address of Global Section Table
|
||||
SectionTableAddr = &__data_section_table;
|
||||
|
||||
// Copy the data sections from flash to SRAM.
|
||||
while (SectionTableAddr < &__data_section_table_end) {
|
||||
LoadAddr = *SectionTableAddr++;
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
data_init(LoadAddr, ExeAddr, SectionLen);
|
||||
}
|
||||
// At this point, SectionTableAddr = &__bss_section_table;
|
||||
// Zero fill the bss segment
|
||||
while (SectionTableAddr < &__bss_section_table_end) {
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
bss_init(ExeAddr, SectionLen);
|
||||
}
|
||||
#else
|
||||
// Use Old Style Data and BSS section initialization.
|
||||
// This will only initialize a single RAM bank.
|
||||
unsigned int * LoadAddr, *ExeAddr, *EndAddr, SectionLen;
|
||||
|
||||
// Copy the data segment from flash to SRAM.
|
||||
LoadAddr = &_etext;
|
||||
ExeAddr = &_data;
|
||||
EndAddr = &_edata;
|
||||
SectionLen = (void*)EndAddr - (void*)ExeAddr;
|
||||
data_init((unsigned int)LoadAddr, (unsigned int)ExeAddr, SectionLen);
|
||||
// Zero fill the bss segment
|
||||
ExeAddr = &_bss;
|
||||
EndAddr = &_ebss;
|
||||
SectionLen = (void*)EndAddr - (void*)ExeAddr;
|
||||
bss_init ((unsigned int)ExeAddr, SectionLen);
|
||||
#endif
|
||||
|
||||
#ifdef __USE_CMSIS
|
||||
SystemInit();
|
||||
#endif
|
||||
|
||||
#if defined (__cplusplus)
|
||||
//
|
||||
// Call C++ library initialisation
|
||||
//
|
||||
__libc_init_array();
|
||||
#endif
|
||||
|
||||
#if defined (__REDLIB__)
|
||||
// Call the Redlib library, which in turn calls main()
|
||||
__main() ;
|
||||
#else
|
||||
main();
|
||||
#endif
|
||||
//
|
||||
// main() shouldn't return, but if it does, we'll just enter an infinite loop
|
||||
//
|
||||
while (1) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
// Default exception handlers. Override the ones here by defining your own
|
||||
// handler routines in your application code.
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void SVCall_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void PendSV_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Processor ends up here if an unexpected interrupt occurs or a specific
|
||||
// handler is not present in the application code.
|
||||
//
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void IntDefaultHandler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
@@ -36,16 +36,14 @@
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#include "../board.h"
|
||||
|
||||
#ifdef BOARD_LPCXPRESSO1347
|
||||
|
||||
#define LED_PORT (0)
|
||||
#define LED_PIN (7)
|
||||
#define LED_ON (1)
|
||||
#define LED_OFF (0)
|
||||
#include "../board.h"
|
||||
|
||||
const static struct {
|
||||
#define LED_PORT 0
|
||||
#define LED_PIN 7
|
||||
|
||||
static const struct {
|
||||
uint8_t port;
|
||||
uint8_t pin;
|
||||
} buttons[] =
|
||||
@@ -63,55 +61,103 @@ enum {
|
||||
BOARD_BUTTON_COUNT = sizeof(buttons) / sizeof(buttons[0])
|
||||
};
|
||||
|
||||
/* System oscillator rate and RTC oscillator rate */
|
||||
const uint32_t OscRateIn = 12000000;
|
||||
const uint32_t ExtRateIn = 0;
|
||||
|
||||
/* Pin muxing table, only items that need changing from their default pin
|
||||
state are in this table. */
|
||||
static const PINMUX_GRP_T pinmuxing[] =
|
||||
{
|
||||
{0, 1, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO0_1 used for CLKOUT */
|
||||
{0, 2, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_PULLUP)}, /* PIO0_2 used for SSEL */
|
||||
{0, 3, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO0_3 used for USB_VBUS */
|
||||
{0, 6, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO0_6 used for USB_CONNECT */
|
||||
{0, 8, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO0_8 used for MISO0 */
|
||||
{0, 9, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO0_9 used for MOSI0 */
|
||||
{0, 11, (IOCON_FUNC2 | IOCON_ADMODE_EN | IOCON_FILT_DIS)}, /* PIO0_11 used for AD0 */
|
||||
{0, 18, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO0_18 used for RXD */
|
||||
{0, 19, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO0_19 used for TXD */
|
||||
{1, 29, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO1_29 used for SCK0 */
|
||||
};
|
||||
|
||||
// Invoked by startup code
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Enable IOCON clock */
|
||||
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
|
||||
Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
|
||||
Chip_SetupXtalClocking();
|
||||
}
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
SystemInit();
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE // TODO may move to main.c
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
SysTick_Config(SystemCoreClock / BOARD_TICKS_HZ); // 1 msec tick timer
|
||||
#endif
|
||||
|
||||
GPIOInit();
|
||||
Chip_GPIO_Init(LPC_GPIO_PORT);
|
||||
|
||||
//------------- LED -------------//
|
||||
GPIOSetDir(LED_PORT, LED_PIN, 1);
|
||||
Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, LED_PORT, LED_PIN);
|
||||
|
||||
//------------- BUTTON -------------//
|
||||
for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) GPIOSetDir(buttons[i].port, BIT_(buttons[i].pin), 0);
|
||||
// for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) GPIOSetDir(buttons[i].port, TU_BIT(buttons[i].pin), 0);
|
||||
|
||||
//------------- UART -------------//
|
||||
UARTInit(CFG_UART_BAUDRATE);
|
||||
//UARTInit(CFG_UART_BAUDRATE);
|
||||
|
||||
// USB
|
||||
Chip_USB_Init(); // Setup PLL clock, and power
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
/* TUSB HAL MILLISECOND
|
||||
*------------------------------------------------------------------*/
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
|
||||
volatile uint32_t system_ticks = 0;
|
||||
|
||||
void SysTick_Handler (void)
|
||||
{
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t tusb_hal_millis(void)
|
||||
{
|
||||
return board_tick2ms(system_ticks);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// LEDS
|
||||
//--------------------------------------------------------------------+
|
||||
void board_leds(uint32_t on_mask, uint32_t off_mask)
|
||||
void board_led_control(bool state)
|
||||
{
|
||||
if (on_mask & BIT_(0))
|
||||
{
|
||||
GPIOSetBitValue(LED_PORT, LED_PIN, LED_ON);
|
||||
}else if (off_mask & BIT_(0))
|
||||
{
|
||||
GPIOSetBitValue(LED_PORT, LED_PIN, LED_OFF);
|
||||
}
|
||||
Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state);
|
||||
}
|
||||
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// BUTTONS
|
||||
//--------------------------------------------------------------------+
|
||||
#if 0
|
||||
static bool button_read(uint8_t id)
|
||||
{
|
||||
return !GPIOGetPinValue(buttons[id].port, buttons[id].pin); // button is active low
|
||||
(void) id;
|
||||
// return !GPIOGetPinValue(buttons[id].port, buttons[id].pin); // button is active low
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
uint32_t board_buttons(void)
|
||||
{
|
||||
uint32_t result = 0;
|
||||
|
||||
for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? BIT_(i) : 0);
|
||||
// for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? TU_BIT(i) : 0);
|
||||
|
||||
return result;
|
||||
}
|
||||
@@ -121,7 +167,8 @@ uint32_t board_buttons(void)
|
||||
//--------------------------------------------------------------------+
|
||||
void board_uart_putchar(uint8_t c)
|
||||
{
|
||||
UARTSend(&c, 1);
|
||||
(void) c;
|
||||
// UARTSend(&c, 1);
|
||||
}
|
||||
|
||||
uint8_t board_uart_getchar(void)
|
||||
|
||||
@@ -43,11 +43,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "LPC13Uxx.h"
|
||||
#include "gpio.h"
|
||||
#include "uart.h"
|
||||
|
||||
#define CFG_PRINTF_TARGET PRINTF_TARGET_UART
|
||||
#include "chip.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -1,354 +0,0 @@
|
||||
//*****************************************************************************
|
||||
// +--+
|
||||
// | ++----+
|
||||
// +-++ |
|
||||
// | |
|
||||
// +-+--+ |
|
||||
// | +--+--+
|
||||
// +----+ Copyright (c) 2012 Code Red Technologies Ltd.
|
||||
//
|
||||
// NXP LPC13U Microcontroller Startup code for use with Red Suite
|
||||
//
|
||||
// Version : 120202
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// The software is owned by Code Red Technologies and/or its suppliers, and is
|
||||
// protected under applicable copyright laws. All rights are reserved. Any
|
||||
// use in violation of the foregoing restrictions may subject the user to criminal
|
||||
// sanctions under applicable laws, as well as to civil liability for the breach
|
||||
// of the terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
|
||||
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
|
||||
// CODE RED TECHNOLOGIES LTD.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined (__cplusplus)
|
||||
#ifdef __REDLIB__
|
||||
#error Redlib does not support C++
|
||||
#else
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The entry point for the C++ library startup
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern "C" {
|
||||
extern void __libc_init_array(void);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define WEAK __attribute__ ((weak))
|
||||
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
|
||||
|
||||
// Code Red - if CMSIS is being used, then SystemInit() routine
|
||||
// will be called by startup code rather than in application's main()
|
||||
#if defined (__USE_CMSIS)
|
||||
#include "LPC13Uxx.h"
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
#if defined (__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Forward declaration of the default handlers. These are aliased.
|
||||
// When the application defines a handler (with the same name), this will
|
||||
// automatically take precedence over these weak definitions
|
||||
//
|
||||
//*****************************************************************************
|
||||
void ResetISR(void);
|
||||
WEAK void NMI_Handler(void);
|
||||
WEAK void HardFault_Handler(void);
|
||||
WEAK void MemManage_Handler(void);
|
||||
WEAK void BusFault_Handler(void);
|
||||
WEAK void UsageFault_Handler(void);
|
||||
WEAK void SVC_Handler(void);
|
||||
WEAK void DebugMon_Handler(void);
|
||||
WEAK void PendSV_Handler(void);
|
||||
WEAK void SysTick_Handler(void);
|
||||
WEAK void IntDefaultHandler(void);
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Forward declaration of the specific IRQ handlers. These are aliased
|
||||
// to the IntDefaultHandler, which is a 'forever' loop. When the application
|
||||
// defines a handler (with the same name), this will automatically take
|
||||
// precedence over these weak definitions
|
||||
//
|
||||
//*****************************************************************************
|
||||
void PIN_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void OSTIMER_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void I2C_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void CT16B0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void CT16B1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void CT32B0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void CT32B1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void USART_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void USB_FIQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void FMC_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void OSCFAIL_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PVTCIRCUIT_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void USBWakeup_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The entry point for the application.
|
||||
// __main() is the entry point for Redlib based applications
|
||||
// main() is the entry point for Newlib based applications
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined (__REDLIB__)
|
||||
extern void __main(void);
|
||||
#endif
|
||||
extern int main(void);
|
||||
//*****************************************************************************
|
||||
//
|
||||
// External declaration for the pointer to the stack top from the Linker Script
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void _vStackTop(void);
|
||||
|
||||
//*****************************************************************************
|
||||
#if defined (__cplusplus)
|
||||
} // extern "C"
|
||||
#endif
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The vector table. Note that the proper constructs must be placed on this to
|
||||
// ensure that it ends up at physical address 0x0000.0000.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void (* const g_pfnVectors[])(void);
|
||||
__attribute__ ((section(".isr_vector")))
|
||||
void (* const g_pfnVectors[])(void) = {
|
||||
// Core Level - CM3
|
||||
&_vStackTop, // The initial stack pointer
|
||||
ResetISR, // The reset handler
|
||||
NMI_Handler, // The NMI handler
|
||||
HardFault_Handler, // The hard fault handler
|
||||
MemManage_Handler, // The MPU fault handler
|
||||
BusFault_Handler, // The bus fault handler
|
||||
UsageFault_Handler, // The usage fault handler
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
SVC_Handler, // SVCall handler
|
||||
DebugMon_Handler, // Debug monitor handler
|
||||
0, // Reserved
|
||||
PendSV_Handler, // The PendSV handler
|
||||
SysTick_Handler, // The SysTick handler
|
||||
|
||||
// LPC13U External Interrupts
|
||||
PIN_INT0_IRQHandler, // All GPIO pin can be routed to PIN_INTx
|
||||
PIN_INT1_IRQHandler,
|
||||
PIN_INT2_IRQHandler,
|
||||
PIN_INT3_IRQHandler,
|
||||
PIN_INT4_IRQHandler,
|
||||
PIN_INT5_IRQHandler,
|
||||
PIN_INT6_IRQHandler,
|
||||
PIN_INT7_IRQHandler,
|
||||
GINT0_IRQHandler,
|
||||
GINT1_IRQHandler, // PIO0 (0:7)
|
||||
0,
|
||||
0,
|
||||
OSTIMER_IRQHandler,
|
||||
0,
|
||||
SSP1_IRQHandler, // SSP1
|
||||
I2C_IRQHandler, // I2C
|
||||
CT16B0_IRQHandler, // 16-bit Timer0
|
||||
CT16B1_IRQHandler, // 16-bit Timer1
|
||||
CT32B0_IRQHandler, // 32-bit Timer0
|
||||
CT32B1_IRQHandler, // 32-bit Timer1
|
||||
SSP0_IRQHandler, // SSP0
|
||||
USART_IRQHandler, // USART
|
||||
USB_IRQHandler, // USB IRQ
|
||||
USB_FIQHandler, // USB FIQ
|
||||
ADC_IRQHandler, // A/D Converter
|
||||
WDT_IRQHandler, // Watchdog timer
|
||||
BOD_IRQHandler, // Brown Out Detect
|
||||
FMC_IRQHandler, // IP2111 Flash Memory Controller
|
||||
OSCFAIL_IRQHandler, // OSC FAIL
|
||||
PVTCIRCUIT_IRQHandler, // PVT CIRCUIT
|
||||
USBWakeup_IRQHandler, // USB wake up
|
||||
0,
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
// Functions to carry out the initialization of RW and BSS data sections. These
|
||||
// are written as separate functions rather than being inlined within the
|
||||
// ResetISR() function in order to cope with MCUs with multiple banks of
|
||||
// memory.
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
|
||||
unsigned int *pulDest = (unsigned int*) start;
|
||||
unsigned int *pulSrc = (unsigned int*) romstart;
|
||||
unsigned int loop;
|
||||
for (loop = 0; loop < len; loop = loop + 4)
|
||||
*pulDest++ = *pulSrc++;
|
||||
}
|
||||
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void bss_init(unsigned int start, unsigned int len) {
|
||||
unsigned int *pulDest = (unsigned int*) start;
|
||||
unsigned int loop;
|
||||
for (loop = 0; loop < len; loop = loop + 4)
|
||||
*pulDest++ = 0;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
// The following symbols are constructs generated by the linker, indicating
|
||||
// the location of various points in the "Global Section Table". This table is
|
||||
// created by the linker via the Code Red managed linker script mechanism. It
|
||||
// contains the load address, execution address and length of each RW data
|
||||
// section and the execution and length of each BSS (zero initialized) section.
|
||||
//*****************************************************************************
|
||||
extern unsigned int __data_section_table;
|
||||
extern unsigned int __data_section_table_end;
|
||||
extern unsigned int __bss_section_table;
|
||||
extern unsigned int __bss_section_table_end;
|
||||
|
||||
//*****************************************************************************
|
||||
// Reset entry point for your code.
|
||||
// Sets up a simple runtime environment and initializes the C/C++
|
||||
// library.
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void
|
||||
ResetISR(void) {
|
||||
|
||||
//
|
||||
// Copy the data sections from flash to SRAM.
|
||||
//
|
||||
unsigned int LoadAddr, ExeAddr, SectionLen;
|
||||
unsigned int *SectionTableAddr;
|
||||
|
||||
// Load base address of Global Section Table
|
||||
SectionTableAddr = &__data_section_table;
|
||||
|
||||
// Copy the data sections from flash to SRAM.
|
||||
while (SectionTableAddr < &__data_section_table_end) {
|
||||
LoadAddr = *SectionTableAddr++;
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
data_init(LoadAddr, ExeAddr, SectionLen);
|
||||
}
|
||||
// At this point, SectionTableAddr = &__bss_section_table;
|
||||
// Zero fill the bss segment
|
||||
while (SectionTableAddr < &__bss_section_table_end) {
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
bss_init(ExeAddr, SectionLen);
|
||||
}
|
||||
|
||||
#ifdef __USE_CMSIS
|
||||
SystemInit();
|
||||
#endif
|
||||
|
||||
#if defined (__cplusplus)
|
||||
//
|
||||
// Call C++ library initialisation
|
||||
//
|
||||
__libc_init_array();
|
||||
#endif
|
||||
|
||||
#if defined (__REDLIB__)
|
||||
// Call the Redlib library, which in turn calls main()
|
||||
__main() ;
|
||||
#else
|
||||
main();
|
||||
#endif
|
||||
//
|
||||
// main() shouldn't return, but if it does, we'll just enter an infinite loop
|
||||
//
|
||||
while (1) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
// Default exception handlers. Override the ones here by defining your own
|
||||
// handler routines in your application code.
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void NMI_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void HardFault_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void MemManage_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void BusFault_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void UsageFault_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void SVC_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void DebugMon_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void PendSV_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void SysTick_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Processor ends up here if an unexpected interrupt occurs or a handler
|
||||
// is not present in the application code.
|
||||
//
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void IntDefaultHandler(void) {
|
||||
//
|
||||
// Go into an infinite loop.
|
||||
//
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
@@ -36,59 +36,81 @@
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#include "../board.h"
|
||||
|
||||
#ifdef BOARD_LPCXPRESSO1769
|
||||
|
||||
#define BOARD_LED_PORT (0)
|
||||
#define BOARD_LED_PIN (22)
|
||||
#include "../board.h"
|
||||
#include "tusb.h"
|
||||
|
||||
const static struct {
|
||||
uint8_t port;
|
||||
uint8_t pin;
|
||||
} buttons[] =
|
||||
{
|
||||
{2, 3 }, // Joystick up
|
||||
{0, 15 }, // Joystick down
|
||||
{2, 4 }, // Joystick left
|
||||
{0, 16 }, // Joystick right
|
||||
{0, 17 }, // Joystick press
|
||||
{0, 4 }, // SW3
|
||||
// {1, 31 }, // SW4 (require to remove J28)
|
||||
};
|
||||
|
||||
enum {
|
||||
BOARD_BUTTON_COUNT = sizeof(buttons) / sizeof(buttons[0])
|
||||
};
|
||||
#define LED_PORT 0
|
||||
#define LED_PIN 22
|
||||
|
||||
#define BOARD_UART_PORT LPC_UART3
|
||||
|
||||
/* System oscillator rate and RTC oscillator rate */
|
||||
const uint32_t OscRateIn = 12000000;
|
||||
const uint32_t RTCOscRateIn = 32768;
|
||||
|
||||
/* Pin muxing configuration */
|
||||
static const PINMUX_GRP_T pinmuxing[] =
|
||||
{
|
||||
{0, 0, IOCON_MODE_INACT | IOCON_FUNC2}, /* TXD3 */
|
||||
{0, 1, IOCON_MODE_INACT | IOCON_FUNC2}, /* RXD3 */
|
||||
{0, 22, IOCON_MODE_INACT | IOCON_FUNC0}, /* Led 0 */
|
||||
|
||||
/* Joystick buttons. */
|
||||
{2, 3, IOCON_MODE_INACT | IOCON_FUNC0}, /* JOYSTICK_UP */
|
||||
{0, 15, IOCON_MODE_INACT | IOCON_FUNC0}, /* JOYSTICK_DOWN */
|
||||
{2, 4, IOCON_MODE_INACT | IOCON_FUNC0}, /* JOYSTICK_LEFT */
|
||||
{0, 16, IOCON_MODE_INACT | IOCON_FUNC0}, /* JOYSTICK_RIGHT */
|
||||
{0, 17, IOCON_MODE_INACT | IOCON_FUNC0}, /* JOYSTICK_PRESS */
|
||||
};
|
||||
|
||||
static const PINMUX_GRP_T pin_usb_mux[] =
|
||||
{
|
||||
{0, 29, IOCON_MODE_INACT | IOCON_FUNC1}, // D+
|
||||
{0, 30, IOCON_MODE_INACT | IOCON_FUNC1}, // D-
|
||||
{2, 9, IOCON_MODE_INACT | IOCON_FUNC1}, // Connect
|
||||
|
||||
{1, 19, IOCON_MODE_INACT | IOCON_FUNC2}, // USB_PPWR
|
||||
{1, 22, IOCON_MODE_INACT | IOCON_FUNC2}, // USB_PWRD
|
||||
|
||||
/* VBUS is not connected on this board, so leave the pin at default setting. */
|
||||
/*Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);*/ /* USB VBUS */
|
||||
};
|
||||
|
||||
enum {
|
||||
BOARD_BUTTON_COUNT = 5
|
||||
};
|
||||
|
||||
// Invoked by startup code
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Enable IOCON clock */
|
||||
Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
|
||||
Chip_SetupXtalClocking();
|
||||
}
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
SystemInit();
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE // TODO may move to main.c
|
||||
SysTick_Config(SystemCoreClock / BOARD_TICKS_HZ); // 1 msec tick timer
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
SysTick_Config(SystemCoreClock / BOARD_TICKS_HZ);
|
||||
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||
NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
|
||||
#endif
|
||||
|
||||
Chip_GPIO_Init(LPC_GPIO);
|
||||
|
||||
//------------- LED -------------//
|
||||
GPIO_SetDir(BOARD_LED_PORT, BIT_(BOARD_LED_PIN), 1);
|
||||
Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
|
||||
|
||||
//------------- BUTTON -------------//
|
||||
for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) GPIO_SetDir(buttons[i].port, BIT_(buttons[i].pin), 0);
|
||||
|
||||
#if TUSB_OPT_DEVICE_ENABLED
|
||||
//------------- USB Device -------------//
|
||||
// VBUS sense is wrongly connected to P0_5 (instead of P1_30). So we need to always pull P1_30 to high
|
||||
// so that USB device block can work. However, Device Controller (thus tinyusb) cannot able to determine
|
||||
// if device is disconnected or not
|
||||
PINSEL_ConfigPin( &(PINSEL_CFG_Type) {
|
||||
.Portnum = 1, .Pinnum = 30,
|
||||
.Funcnum = 2, .Pinmode = PINSEL_PINMODE_PULLUP} );
|
||||
|
||||
//P0_21 instead of P2_9 as USB connect
|
||||
#endif
|
||||
// for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) GPIO_SetDir(buttons[i].port, TU_BIT(buttons[i].pin), 0);
|
||||
|
||||
#if 0
|
||||
//------------- UART -------------//
|
||||
PINSEL_CFG_Type PinCfg =
|
||||
{
|
||||
@@ -110,35 +132,73 @@ void board_init(void)
|
||||
|
||||
UART_Init(BOARD_UART_PORT, &UARTConfigStruct);
|
||||
UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
|
||||
#endif
|
||||
|
||||
//------------- USB -------------//
|
||||
Chip_USB_Init();
|
||||
|
||||
enum {
|
||||
USBCLK_DEVCIE = 0x12, // AHB + Device
|
||||
USBCLK_HOST = 0x19, // AHB + Host + OTG
|
||||
// 0x1B // Host + Device + OTG + AHB
|
||||
};
|
||||
|
||||
uint32_t const clk_en = TUSB_OPT_DEVICE_ENABLED ? USBCLK_DEVCIE : USBCLK_HOST;
|
||||
|
||||
LPC_USB->OTGClkCtrl = clk_en;
|
||||
while ( (LPC_USB->OTGClkSt & clk_en) != clk_en );
|
||||
|
||||
#if TUSB_OPT_HOST_ENABLED
|
||||
// set portfunc to host !!!
|
||||
LPC_USB->StCtrl = 0x3; // should be 1
|
||||
#endif
|
||||
|
||||
Chip_IOCON_SetPinMuxing(LPC_IOCON, pin_usb_mux, sizeof(pin_usb_mux) / sizeof(PINMUX_GRP_T));
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
/* TUSB HAL MILLISECOND
|
||||
*------------------------------------------------------------------*/
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
|
||||
volatile uint32_t system_ticks = 0;
|
||||
|
||||
void SysTick_Handler (void)
|
||||
{
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t tusb_hal_millis(void)
|
||||
{
|
||||
return board_tick2ms(system_ticks);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// LEDS
|
||||
//--------------------------------------------------------------------+
|
||||
void board_leds(uint32_t on_mask, uint32_t off_mask)
|
||||
void board_led_control(bool state)
|
||||
{
|
||||
if (on_mask & BIT_(0))
|
||||
{
|
||||
GPIO_SetValue(BOARD_LED_PORT, BIT_(BOARD_LED_PIN));
|
||||
}else if (off_mask & BIT_(0))
|
||||
{
|
||||
GPIO_ClearValue(BOARD_LED_PORT, BIT_(BOARD_LED_PIN));
|
||||
}
|
||||
Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state);
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// BUTTONS
|
||||
//--------------------------------------------------------------------+
|
||||
#if 0
|
||||
static bool button_read(uint8_t id)
|
||||
{
|
||||
return !BIT_TEST_( GPIO_ReadValue(buttons[id].port), buttons[id].pin ); // button is active low
|
||||
// return !TU_BIT_TEST( GPIO_ReadValue(buttons[id].port), buttons[id].pin ); // button is active low
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
uint32_t board_buttons(void)
|
||||
{
|
||||
uint32_t result = 0;
|
||||
|
||||
for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? BIT_(i) : 0);
|
||||
// for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? TU_BIT(i) : 0);
|
||||
|
||||
return result;
|
||||
}
|
||||
@@ -148,12 +208,14 @@ uint32_t board_buttons(void)
|
||||
//--------------------------------------------------------------------+
|
||||
void board_uart_putchar(uint8_t c)
|
||||
{
|
||||
UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
|
||||
(void) c;
|
||||
// UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
|
||||
}
|
||||
|
||||
uint8_t board_uart_getchar(void)
|
||||
{
|
||||
return UART_ReceiveByte(BOARD_UART_PORT);
|
||||
// return UART_ReceiveByte(BOARD_UART_PORT);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -39,20 +39,11 @@
|
||||
#ifndef _TUSB_BOARD_LPCXPRESSO1769_H_
|
||||
#define _TUSB_BOARD_LPCXPRESSO1769_H_
|
||||
|
||||
#include "LPC17xx.h"
|
||||
|
||||
#include "lpc17xx_clkpwr.h"
|
||||
#include "lpc17xx_pinsel.h"
|
||||
#include "lpc17xx_gpio.h"
|
||||
#include "lpc17xx_uart.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CFG_PRINTF_TARGET PRINTF_TARGET_UART
|
||||
//#define CFG_PRINTF_TARGET PRINTF_TARGET_SWO
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -1,423 +0,0 @@
|
||||
//*****************************************************************************
|
||||
// +--+
|
||||
// | ++----+
|
||||
// +-++ |
|
||||
// | |
|
||||
// +-+--+ |
|
||||
// | +--+--+
|
||||
// +----+ Copyright (c) 2009-10 Code Red Technologies Ltd.
|
||||
//
|
||||
// Microcontroller Startup code for use with Red Suite
|
||||
//
|
||||
// Version : 101130
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// The software is owned by Code Red Technologies and/or its suppliers, and is
|
||||
// protected under applicable copyright laws. All rights are reserved. Any
|
||||
// use in violation of the foregoing restrictions may subject the user to criminal
|
||||
// sanctions under applicable laws, as well as to civil liability for the breach
|
||||
// of the terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
|
||||
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
|
||||
// CODE RED TECHNOLOGIES LTD.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined (__cplusplus)
|
||||
#ifdef __REDLIB__
|
||||
#error Redlib does not support C++
|
||||
#else
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The entry point for the C++ library startup
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern "C" {
|
||||
extern void __libc_init_array(void);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define WEAK __attribute__ ((weak))
|
||||
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
|
||||
|
||||
#define SVCall_Handler SVC_Handler
|
||||
|
||||
// Code Red - if CMSIS is being used, then SystemInit() routine
|
||||
// will be called by startup code rather than in application's main()
|
||||
#if defined (__USE_CMSIS)
|
||||
#include "system_LPC17xx.h"
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
#if defined (__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Forward declaration of the default handlers. These are aliased.
|
||||
// When the application defines a handler (with the same name), this will
|
||||
// automatically take precedence over these weak definitions
|
||||
//
|
||||
//*****************************************************************************
|
||||
void ResetISR(void);
|
||||
WEAK void NMI_Handler(void);
|
||||
WEAK void HardFault_Handler(void);
|
||||
WEAK void MemManage_Handler(void);
|
||||
WEAK void BusFault_Handler(void);
|
||||
WEAK void UsageFault_Handler(void);
|
||||
WEAK void SVCall_Handler(void);
|
||||
WEAK void DebugMon_Handler(void);
|
||||
WEAK void PendSV_Handler(void);
|
||||
WEAK void SysTick_Handler(void);
|
||||
WEAK void IntDefaultHandler(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Forward declaration of the specific IRQ handlers. These are aliased
|
||||
// to the IntDefaultHandler, which is a 'forever' loop. When the application
|
||||
// defines a handler (with the same name), this will automatically take
|
||||
// precedence over these weak definitions
|
||||
//
|
||||
//*****************************************************************************
|
||||
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void EINT3_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The entry point for the application.
|
||||
// __main() is the entry point for Redlib based applications
|
||||
// main() is the entry point for Newlib based applications
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined (__REDLIB__)
|
||||
extern void __main(void);
|
||||
#endif
|
||||
extern int main(void);
|
||||
//*****************************************************************************
|
||||
//
|
||||
// External declaration for the pointer to the stack top from the Linker Script
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void _vStackTop(void);
|
||||
|
||||
//*****************************************************************************
|
||||
#if defined (__cplusplus)
|
||||
} // extern "C"
|
||||
#endif
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The vector table.
|
||||
// This relies on the linker script to place at correct location in memory.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void (* const g_pfnVectors[])(void);
|
||||
__attribute__ ((section(".isr_vector")))
|
||||
void (* const g_pfnVectors[])(void) = {
|
||||
// Core Level - CM3
|
||||
&_vStackTop, // The initial stack pointer
|
||||
ResetISR, // The reset handler
|
||||
NMI_Handler, // The NMI handler
|
||||
HardFault_Handler, // The hard fault handler
|
||||
MemManage_Handler, // The MPU fault handler
|
||||
BusFault_Handler, // The bus fault handler
|
||||
UsageFault_Handler, // The usage fault handler
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
SVCall_Handler, // SVCall handler
|
||||
DebugMon_Handler, // Debug monitor handler
|
||||
0, // Reserved
|
||||
PendSV_Handler, // The PendSV handler
|
||||
SysTick_Handler, // The SysTick handler
|
||||
|
||||
// Chip Level - LPC17
|
||||
WDT_IRQHandler, // 16, 0x40 - WDT
|
||||
TIMER0_IRQHandler, // 17, 0x44 - TIMER0
|
||||
TIMER1_IRQHandler, // 18, 0x48 - TIMER1
|
||||
TIMER2_IRQHandler, // 19, 0x4c - TIMER2
|
||||
TIMER3_IRQHandler, // 20, 0x50 - TIMER3
|
||||
UART0_IRQHandler, // 21, 0x54 - UART0
|
||||
UART1_IRQHandler, // 22, 0x58 - UART1
|
||||
UART2_IRQHandler, // 23, 0x5c - UART2
|
||||
UART3_IRQHandler, // 24, 0x60 - UART3
|
||||
PWM1_IRQHandler, // 25, 0x64 - PWM1
|
||||
I2C0_IRQHandler, // 26, 0x68 - I2C0
|
||||
I2C1_IRQHandler, // 27, 0x6c - I2C1
|
||||
I2C2_IRQHandler, // 28, 0x70 - I2C2
|
||||
SPI_IRQHandler, // 29, 0x74 - SPI
|
||||
SSP0_IRQHandler, // 30, 0x78 - SSP0
|
||||
SSP1_IRQHandler, // 31, 0x7c - SSP1
|
||||
PLL0_IRQHandler, // 32, 0x80 - PLL0 (Main PLL)
|
||||
RTC_IRQHandler, // 33, 0x84 - RTC
|
||||
EINT0_IRQHandler, // 34, 0x88 - EINT0
|
||||
EINT1_IRQHandler, // 35, 0x8c - EINT1
|
||||
EINT2_IRQHandler, // 36, 0x90 - EINT2
|
||||
EINT3_IRQHandler, // 37, 0x94 - EINT3
|
||||
ADC_IRQHandler, // 38, 0x98 - ADC
|
||||
BOD_IRQHandler, // 39, 0x9c - BOD
|
||||
USB_IRQHandler, // 40, 0xA0 - USB
|
||||
CAN_IRQHandler, // 41, 0xa4 - CAN
|
||||
DMA_IRQHandler, // 42, 0xa8 - GP DMA
|
||||
I2S_IRQHandler, // 43, 0xac - I2S
|
||||
ENET_IRQHandler, // 44, 0xb0 - Ethernet
|
||||
RIT_IRQHandler, // 45, 0xb4 - RITINT
|
||||
MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM
|
||||
QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder
|
||||
PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)
|
||||
USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup
|
||||
CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
// Functions to carry out the initialization of RW and BSS data sections. These
|
||||
// are written as separate functions rather than being inlined within the
|
||||
// ResetISR() function in order to cope with MCUs with multiple banks of
|
||||
// memory.
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
|
||||
unsigned int *pulDest = (unsigned int*) start;
|
||||
unsigned int *pulSrc = (unsigned int*) romstart;
|
||||
unsigned int loop;
|
||||
for (loop = 0; loop < len; loop = loop + 4)
|
||||
*pulDest++ = *pulSrc++;
|
||||
}
|
||||
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void bss_init(unsigned int start, unsigned int len) {
|
||||
unsigned int *pulDest = (unsigned int*) start;
|
||||
unsigned int loop;
|
||||
for (loop = 0; loop < len; loop = loop + 4)
|
||||
*pulDest++ = 0;
|
||||
}
|
||||
|
||||
#ifndef USE_OLD_STYLE_DATA_BSS_INIT
|
||||
//*****************************************************************************
|
||||
// The following symbols are constructs generated by the linker, indicating
|
||||
// the location of various points in the "Global Section Table". This table is
|
||||
// created by the linker via the Code Red managed linker script mechanism. It
|
||||
// contains the load address, execution address and length of each RW data
|
||||
// section and the execution and length of each BSS (zero initialized) section.
|
||||
//*****************************************************************************
|
||||
extern unsigned int __data_section_table;
|
||||
extern unsigned int __data_section_table_end;
|
||||
extern unsigned int __bss_section_table;
|
||||
extern unsigned int __bss_section_table_end;
|
||||
#else
|
||||
//*****************************************************************************
|
||||
// The following symbols are constructs generated by the linker, indicating
|
||||
// the load address, execution address and length of the RW data section and
|
||||
// the execution and length of the BSS (zero initialized) section.
|
||||
// Note that these symbols are not normally used by the managed linker script
|
||||
// mechanism in Red Suite/LPCXpresso 3.6 (Windows) and LPCXpresso 3.8 (Linux).
|
||||
// They are provide here simply so this startup code can be used with earlier
|
||||
// versions of Red Suite which do not support the more advanced managed linker
|
||||
// script mechanism introduced in the above version. To enable their use,
|
||||
// define "USE_OLD_STYLE_DATA_BSS_INIT".
|
||||
//*****************************************************************************
|
||||
extern unsigned int _etext;
|
||||
extern unsigned int _data;
|
||||
extern unsigned int _edata;
|
||||
extern unsigned int _bss;
|
||||
extern unsigned int _ebss;
|
||||
#endif
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
// Reset entry point for your code.
|
||||
// Sets up a simple runtime environment and initializes the C/C++
|
||||
// library.
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void
|
||||
ResetISR(void) {
|
||||
|
||||
#ifndef USE_OLD_STYLE_DATA_BSS_INIT
|
||||
//
|
||||
// Copy the data sections from flash to SRAM.
|
||||
//
|
||||
unsigned int LoadAddr, ExeAddr, SectionLen;
|
||||
unsigned int *SectionTableAddr;
|
||||
|
||||
// Load base address of Global Section Table
|
||||
SectionTableAddr = &__data_section_table;
|
||||
|
||||
// Copy the data sections from flash to SRAM.
|
||||
while (SectionTableAddr < &__data_section_table_end) {
|
||||
LoadAddr = *SectionTableAddr++;
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
data_init(LoadAddr, ExeAddr, SectionLen);
|
||||
}
|
||||
// At this point, SectionTableAddr = &__bss_section_table;
|
||||
// Zero fill the bss segment
|
||||
while (SectionTableAddr < &__bss_section_table_end) {
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
bss_init(ExeAddr, SectionLen);
|
||||
}
|
||||
#else
|
||||
// Use Old Style Data and BSS section initialization.
|
||||
// This will only initialize a single RAM bank.
|
||||
unsigned int * LoadAddr, *ExeAddr, *EndAddr, SectionLen;
|
||||
|
||||
// Copy the data segment from flash to SRAM.
|
||||
LoadAddr = &_etext;
|
||||
ExeAddr = &_data;
|
||||
EndAddr = &_edata;
|
||||
SectionLen = (void*)EndAddr - (void*)ExeAddr;
|
||||
data_init((unsigned int)LoadAddr, (unsigned int)ExeAddr, SectionLen);
|
||||
// Zero fill the bss segment
|
||||
ExeAddr = &_bss;
|
||||
EndAddr = &_ebss;
|
||||
SectionLen = (void*)EndAddr - (void*)ExeAddr;
|
||||
bss_init ((unsigned int)ExeAddr, SectionLen);
|
||||
#endif
|
||||
|
||||
#ifdef __USE_CMSIS
|
||||
SystemInit();
|
||||
#endif
|
||||
|
||||
#if defined (__cplusplus)
|
||||
//
|
||||
// Call C++ library initialisation
|
||||
//
|
||||
__libc_init_array();
|
||||
#endif
|
||||
|
||||
#if defined (__REDLIB__)
|
||||
// Call the Redlib library, which in turn calls main()
|
||||
__main() ;
|
||||
#else
|
||||
main();
|
||||
#endif
|
||||
|
||||
//
|
||||
// main() shouldn't return, but if it does, we'll just enter an infinite loop
|
||||
//
|
||||
while (1) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
// Default exception handlers. Override the ones here by defining your own
|
||||
// handler routines in your application code.
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void MemManage_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void BusFault_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void UsageFault_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void SVCall_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void DebugMon_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void PendSV_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Processor ends up here if an unexpected interrupt occurs or a specific
|
||||
// handler is not present in the application code.
|
||||
//
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void IntDefaultHandler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,245 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file board_mcb1800.c
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2018, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#ifdef BOARD_MCB1800
|
||||
|
||||
#include "../board.h"
|
||||
#include "tusb.h"
|
||||
|
||||
#define LED_PORT 6
|
||||
#define LED_PIN 24
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
|
||||
//--------------------------------------------------------------------+
|
||||
/* System configuration variables used by chip driver */
|
||||
const uint32_t ExtRateIn = 0;
|
||||
const uint32_t OscRateIn = 12000000;
|
||||
|
||||
static const PINMUX_GRP_T pinmuxing[] =
|
||||
{
|
||||
/* Board LEDs */
|
||||
{0xD, 10, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)},
|
||||
{0xD, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)},
|
||||
{0xD, 12, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)},
|
||||
{0xD, 13, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)},
|
||||
{0xD, 14, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)},
|
||||
{0x9, 0, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)},
|
||||
{0x9, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)},
|
||||
{0x9, 2, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)},
|
||||
|
||||
/* I2S */
|
||||
{0x3, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
|
||||
{0x6, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC4)},
|
||||
{0x7, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
|
||||
{0x6, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
|
||||
{0x7, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
|
||||
{0x6, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
|
||||
};
|
||||
|
||||
/* Pin clock mux values, re-used structure, value in first index is meaningless */
|
||||
static const PINMUX_GRP_T pinclockmuxing[] =
|
||||
{
|
||||
{0, 0, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
|
||||
{0, 1, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
|
||||
{0, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
|
||||
{0, 3, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
|
||||
};
|
||||
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
/* BOARD API
|
||||
*------------------------------------------------------------------*/
|
||||
// Invoked by startup code
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Setup system level pin muxing */
|
||||
Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
|
||||
|
||||
/* Clock pins only, group field not used */
|
||||
for (int i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++)
|
||||
{
|
||||
Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
|
||||
}
|
||||
|
||||
Chip_SetupXtalClocking();
|
||||
}
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
SysTick_Config( SystemCoreClock / BOARD_TICKS_HZ );
|
||||
#endif
|
||||
|
||||
Chip_GPIO_Init(LPC_GPIO_PORT);
|
||||
|
||||
//------------- LED -------------//
|
||||
/* Port and bit mapping for LEDs on GPIOs */
|
||||
const uint8_t ledports[] = {6, 6, 6, 6, 6, 4, 4, 4};
|
||||
const uint8_t ledbits[] = {24, 25, 26, 27, 28, 12, 13, 14};
|
||||
|
||||
for (int i = 0; i < (sizeof(ledports) / sizeof(ledports[0])); i++)
|
||||
{
|
||||
Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, ledports[i], ledbits[i]);
|
||||
Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, false);
|
||||
}
|
||||
|
||||
#if 0
|
||||
//------------- BUTTON -------------//
|
||||
for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++)
|
||||
{
|
||||
scu_pinmux(buttons[i].mux_port, buttons[i].mux_pin, GPIO_NOPULL, FUNC0);
|
||||
GPIO_SetDir(buttons[i].gpio_port, TU_BIT(buttons[i].gpio_pin), 0);
|
||||
}
|
||||
|
||||
//------------- UART -------------//
|
||||
scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_TX, MD_PDN, FUNC1);
|
||||
scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_RX, MD_PLN | MD_EZI | MD_ZI, FUNC1);
|
||||
|
||||
UART_CFG_Type UARTConfigStruct;
|
||||
UART_ConfigStructInit(&UARTConfigStruct);
|
||||
UARTConfigStruct.Baud_rate = CFG_UART_BAUDRATE;
|
||||
UARTConfigStruct.Clock_Speed = 0;
|
||||
|
||||
UART_Init(BOARD_UART_PORT, &UARTConfigStruct);
|
||||
UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
|
||||
#endif
|
||||
|
||||
//------------- USB -------------//
|
||||
enum {
|
||||
USBMODE_DEVICE = 2,
|
||||
USBMODE_HOST = 3
|
||||
};
|
||||
|
||||
enum {
|
||||
USBMODE_VBUS_LOW = 0,
|
||||
USBMODE_VBUS_HIGH = 1
|
||||
};
|
||||
|
||||
// USB0
|
||||
#if CFG_TUSB_RHPORT0_MODE
|
||||
Chip_USB0_Init();
|
||||
|
||||
// Reset controller
|
||||
LPC_USB0->USBCMD_D |= 0x02;
|
||||
while( LPC_USB0->USBCMD_D & 0x02 ) {}
|
||||
|
||||
// Set mode
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
|
||||
LPC_USB0->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
|
||||
#else // TODO OTG
|
||||
LPC_USB0->USBMODE_D = USBMODE_DEVICE;
|
||||
LPC_USB0->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// USB1
|
||||
#if CFG_TUSB_RHPORT1_MODE
|
||||
Chip_USB1_Init();
|
||||
|
||||
// Reset controller
|
||||
LPC_USB1->USBCMD_D |= 0x02;
|
||||
while( LPC_USB1->USBCMD_D & 0x02 ) {}
|
||||
|
||||
// Set mode
|
||||
#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
|
||||
LPC_USB1->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
|
||||
#else // TODO OTG
|
||||
LPC_USB1->USBMODE_D = USBMODE_DEVICE;
|
||||
#endif
|
||||
|
||||
// USB1 as fullspeed
|
||||
LPC_USB1->PORTSC1_D |= (1<<24);
|
||||
#endif
|
||||
}
|
||||
|
||||
//------------- LED -------------//
|
||||
void board_led_control(bool state)
|
||||
{
|
||||
Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state);
|
||||
}
|
||||
|
||||
//------------- Buttons -------------//
|
||||
static bool button_read(uint8_t id)
|
||||
{
|
||||
// return !TU_BIT_TEST( GPIO_ReadValue(buttons[id].gpio_port), buttons[id].gpio_pin ); // button is active low
|
||||
}
|
||||
|
||||
uint32_t board_buttons(void)
|
||||
{
|
||||
uint32_t result = 0;
|
||||
|
||||
// for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? TU_BIT(i) : 0);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
//------------- UART -------------//
|
||||
uint8_t board_uart_getchar(void)
|
||||
{
|
||||
//return UART_ReceiveByte(BOARD_UART_PORT);
|
||||
}
|
||||
void board_uart_putchar(uint8_t c)
|
||||
{
|
||||
//UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
/* TUSB HAL MILLISECOND
|
||||
*------------------------------------------------------------------*/
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
|
||||
volatile uint32_t system_ticks = 0;
|
||||
|
||||
void SysTick_Handler (void)
|
||||
{
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t tusb_hal_millis(void)
|
||||
{
|
||||
return board_tick2ms(system_ticks);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,51 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file board_mcb1800.h
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2018, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
#ifndef BOARD_MCB1800_H_
|
||||
#define BOARD_MCB1800_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* BOARD_MCB1800_H_ */
|
||||
@@ -52,7 +52,7 @@
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
|
||||
//--------------------------------------------------------------------+
|
||||
#define LED_STATE_ON 1
|
||||
#define LED_PIN 17
|
||||
|
||||
/* Referenced GCLKs, should be initialized firstly */
|
||||
#define _GCLK_INIT_1ST (1 << 0 | 1 << 1)
|
||||
@@ -74,8 +74,8 @@ void board_init(void)
|
||||
_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
|
||||
|
||||
// Led init
|
||||
gpio_set_pin_direction(BOARD_LED0, GPIO_DIRECTION_OUT);
|
||||
gpio_set_pin_level(BOARD_LED0, 1-LED_STATE_ON);
|
||||
gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
|
||||
gpio_set_pin_level(LED_PIN, 0);
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
// Tick init, samd SystemCoreClock may not correct
|
||||
@@ -110,9 +110,9 @@ void board_init(void)
|
||||
_gclk_enable_channel(TCC0_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK0_Val);
|
||||
}
|
||||
|
||||
void board_led_control(uint32_t led_id, bool state)
|
||||
void board_led_control(bool state)
|
||||
{
|
||||
gpio_set_pin_level(led_id, state ? LED_STATE_ON : (1-LED_STATE_ON));
|
||||
gpio_set_pin_level(LED_PIN, state);
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -42,8 +42,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define BOARD_LED_NUM 1
|
||||
#define BOARD_LED0 17
|
||||
#include "sam.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -49,7 +49,7 @@
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
|
||||
//--------------------------------------------------------------------+
|
||||
#define LED_STATE_ON 1
|
||||
#define LED_PIN 16
|
||||
|
||||
/* Referenced GCLKs, should be initialized firstly */
|
||||
#define _GCLK_INIT_1ST 0xFFFFFFFF
|
||||
@@ -72,8 +72,8 @@ void board_init(void)
|
||||
_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
|
||||
|
||||
// Led init
|
||||
gpio_set_pin_direction(BOARD_LED0, GPIO_DIRECTION_OUT);
|
||||
gpio_set_pin_level(BOARD_LED0, 1 - LED_STATE_ON);
|
||||
gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
|
||||
gpio_set_pin_level(LED_PIN, 0);
|
||||
|
||||
// Systick init
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
@@ -100,9 +100,9 @@ void board_init(void)
|
||||
gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP);
|
||||
}
|
||||
|
||||
void board_led_control(uint32_t led_id, bool state)
|
||||
void board_led_control(bool state)
|
||||
{
|
||||
gpio_set_pin_level(led_id, state ? LED_STATE_ON : (1-LED_STATE_ON));
|
||||
gpio_set_pin_level(LED_PIN, state);
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -42,8 +42,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define BOARD_LED_NUM 1
|
||||
#define BOARD_LED0 16
|
||||
#include "sam.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -1,158 +0,0 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file board_ngx4330.c
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#include "../board.h"
|
||||
|
||||
#ifdef BOARD_NGX4330
|
||||
|
||||
#define BOARD_UART_PORT LPC_USART0
|
||||
|
||||
const static struct {
|
||||
uint8_t mux_port;
|
||||
uint8_t mux_pin;
|
||||
|
||||
uint8_t gpio_port;
|
||||
uint8_t gpio_pin;
|
||||
}leds[] = { {2, 11, 1, 11}, {2, 12, 1,12} };
|
||||
|
||||
enum {
|
||||
BOARD_MAX_LEDS = sizeof(leds) / sizeof(leds[0])
|
||||
};
|
||||
|
||||
const static struct {
|
||||
uint8_t mux_port;
|
||||
uint8_t mux_pin;
|
||||
|
||||
uint8_t gpio_port;
|
||||
uint8_t gpio_pin;
|
||||
}buttons[] = { {0x02, 7, 0, 7 } };
|
||||
|
||||
enum {
|
||||
BOARD_BUTTON_COUNT = sizeof(buttons) / sizeof(buttons[0])
|
||||
};
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
CGU_Init();
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE // TODO may move to main.c
|
||||
SysTick_Config( CGU_GetPCLKFrequency(CGU_PERIPHERAL_M4CORE)/BOARD_TICKS_HZ ); /* 1 ms Timer */
|
||||
#endif
|
||||
|
||||
//------------- USB Bus power HOST ONLY-------------//
|
||||
scu_pinmux(0x1, 7, MD_PUP | MD_EZI, FUNC4); // P1_7 USB0_PWR_EN, USB0 VBus function Xplorer
|
||||
|
||||
scu_pinmux(0x2, 6, MD_PUP | MD_EZI, FUNC4); // P2_6 is configured as GPIO5[6] for USB1_PWR_EN
|
||||
GPIO_SetDir (5, BIT_(6), 1); // GPIO5[6] is output
|
||||
GPIO_SetValue (5, BIT_(6)); // GPIO5[6] output high
|
||||
|
||||
//------------- LED -------------//
|
||||
for (uint8_t i=0; i<BOARD_MAX_LEDS; i++)
|
||||
{
|
||||
scu_pinmux(leds[i].mux_port, leds[i].mux_pin, MD_PUP|MD_EZI|MD_ZI, FUNC0);
|
||||
GPIO_SetDir(leds[i].gpio_port, BIT_(leds[i].gpio_pin), 1); // output
|
||||
}
|
||||
|
||||
//------------- BUTTONS -------------//
|
||||
for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++)
|
||||
{
|
||||
scu_pinmux(buttons[i].mux_port, buttons[i].mux_pin, GPIO_NOPULL, FUNC0);
|
||||
GPIO_SetDir(buttons[i].gpio_port, BIT_(buttons[i].gpio_pin), 0);
|
||||
}
|
||||
|
||||
//------------- UART init -------------//
|
||||
scu_pinmux(0x6 ,4, MD_PDN | MD_EZI, FUNC2); // UART0_TXD
|
||||
scu_pinmux(0x6 ,5, MD_PDN | MD_EZI, FUNC2); // UART0_RXD
|
||||
|
||||
UART_CFG_Type UARTConfigStruct;
|
||||
UART_ConfigStructInit(&UARTConfigStruct); // default: baud = 9600, 8 bit data, 1 stop bit, no parity
|
||||
UARTConfigStruct.Baud_rate = CFG_UART_BAUDRATE; // Re-configure baudrate
|
||||
UARTConfigStruct.Clock_Speed = 0;
|
||||
|
||||
UART_Init(BOARD_UART_PORT, &UARTConfigStruct);
|
||||
UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// LEDS
|
||||
//--------------------------------------------------------------------+
|
||||
void board_leds(uint32_t on_mask, uint32_t off_mask)
|
||||
{
|
||||
for (uint32_t i=0; i<BOARD_MAX_LEDS; i++)
|
||||
{
|
||||
if ( on_mask & BIT_(i))
|
||||
{
|
||||
GPIO_SetValue(leds[i].gpio_port, BIT_(leds[i].gpio_pin));
|
||||
}else if ( off_mask & BIT_(i)) // on_mask take precedence over off_mask
|
||||
{
|
||||
GPIO_ClearValue(leds[i].gpio_port, BIT_(leds[i].gpio_pin));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// BUTTONS
|
||||
//--------------------------------------------------------------------+
|
||||
static bool button_read(uint8_t id)
|
||||
{
|
||||
return !BIT_TEST_( GPIO_ReadValue(buttons[id].gpio_port), buttons[id].gpio_pin ); // button is active low
|
||||
}
|
||||
|
||||
uint32_t board_buttons(void)
|
||||
{
|
||||
uint32_t result = 0;
|
||||
|
||||
for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? BIT_(i) : 0);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// UART
|
||||
//--------------------------------------------------------------------+
|
||||
uint8_t board_uart_getchar(void)
|
||||
{
|
||||
return UART_ReceiveByte(BOARD_UART_PORT);
|
||||
}
|
||||
|
||||
void board_uart_putchar(uint8_t c)
|
||||
{
|
||||
UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,59 +0,0 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file board_ngx4330.h
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef _TUSB_BOARD_NGX4330_H_
|
||||
#define _TUSB_BOARD_NGX4330_H_
|
||||
|
||||
#include "LPC43xx.h"
|
||||
#include "lpc43xx_scu.h"
|
||||
#include "lpc43xx_cgu.h"
|
||||
#include "lpc43xx_gpio.h"
|
||||
#include "lpc43xx_uart.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CFG_PRINTF_TARGET PRINTF_TARGET_UART
|
||||
//#define CFG_PRINTF_TARGET PRINTF_TARGET_SWO
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_BOARD_NGX4330_H_ */
|
||||
@@ -46,6 +46,7 @@
|
||||
/*------------------------------------------------------------------*/
|
||||
/* MACRO TYPEDEF CONSTANT ENUM
|
||||
*------------------------------------------------------------------*/
|
||||
#define LED_PIN 13
|
||||
#define LED_STATE_ON 0
|
||||
|
||||
uint8_t _button_pins[] = { 11, 12, 24, 25 };
|
||||
@@ -92,15 +93,8 @@ void board_init(void)
|
||||
NRF_CLOCK->TASKS_LFCLKSTART = 1UL;
|
||||
|
||||
// LEDs
|
||||
nrf_gpio_cfg_output(BOARD_LED0);
|
||||
nrf_gpio_cfg_output(BOARD_LED1);
|
||||
nrf_gpio_cfg_output(BOARD_LED2);
|
||||
nrf_gpio_cfg_output(BOARD_LED3);
|
||||
|
||||
board_led_control(BOARD_LED0, false);
|
||||
board_led_control(BOARD_LED1, false);
|
||||
board_led_control(BOARD_LED2, false);
|
||||
board_led_control(BOARD_LED3, false);
|
||||
nrf_gpio_cfg_output(LED_PIN);
|
||||
board_led_control(false);
|
||||
|
||||
// Button
|
||||
for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) nrf_gpio_cfg_input(_button_pins[i], NRF_GPIO_PIN_PULLUP);
|
||||
@@ -223,9 +217,9 @@ void board_init(void)
|
||||
}
|
||||
}
|
||||
|
||||
void board_led_control(uint32_t led_id, bool state)
|
||||
void board_led_control(bool state)
|
||||
{
|
||||
nrf_gpio_pin_write(led_id, state ? LED_STATE_ON : (1-LED_STATE_ON));
|
||||
nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
|
||||
}
|
||||
|
||||
uint32_t board_buttons(void)
|
||||
@@ -248,7 +242,7 @@ uint8_t board_uart_getchar(void)
|
||||
|
||||
void board_uart_putchar(uint8_t c)
|
||||
{
|
||||
|
||||
(void) c;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -45,12 +45,6 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define BOARD_LED_NUM 4
|
||||
#define BOARD_LED0 13
|
||||
#define BOARD_LED1 14
|
||||
#define BOARD_LED2 15
|
||||
#define BOARD_LED3 16
|
||||
|
||||
// Flash type used for MSC example
|
||||
#define BOARD_MSC_FLASH_QSPI
|
||||
#define BOARD_MSC_FLASH_SIZE (8*1024*1024)
|
||||
|
||||
+17
-8
@@ -2,19 +2,28 @@
|
||||
|
||||
## Supported Boards ##
|
||||
|
||||
This code base already had supported for a handful of boards. However due to my limited collection, **only bold ones are (probably) guaranteed to run out of the box**. Other are merely implemented based on their schematics and needed help from you to make it work.
|
||||
This code base already had supported for a handful of following boards
|
||||
|
||||
### NXP MCU ###
|
||||
|
||||
- [LPCXpresso 11u14](http://www.embeddedartists.com/products/lpcxpresso/lpc11U14_xpr.php) with base board (for some peripherals to work)
|
||||
- [<b>LPCXpresso 1347</b>](http://www.embeddedartists.com/products/lpcxpresso/lpc1347_xpr.php) with base board (for some peripherals to work)
|
||||
- [<b>LPCXpresso 1769</b>](http://www.embeddedartists.com/products/lpcxpresso/lpc1347_xpr.php) with base board (for some peripherals to work)
|
||||
- [<b>Embedded Artists LPC4357 OEM & Base board</b>](http://www.embeddedartists.com/products/kits/lpc4357_kit.php)
|
||||
- [<b>NGX LPC4330 Explorer</b>](http://shop.ngxtechnologies.com/product_info.php?products_id=104)
|
||||
- [Keil MCB4357 Evaluation Board](http://www.keil.com/mcb4300)
|
||||
- [LPCXpresso 11U68](https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc11u68:OM13058)
|
||||
- [LPCXpresso 1347](https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc1347:OM13045)
|
||||
- [LPCXpresso 1769](https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc1769:OM13000)
|
||||
- [Keil MCB1800 Evaluation Board](http://www.keil.com/mcb1800)
|
||||
- [Embedded Artists LPC4088 Quick Start board](https://www.embeddedartists.com/products/lpc4088-quickstart-board)
|
||||
- [Embedded Artists LPC4357 Developer Kit](http://www.embeddedartists.com/products/kits/lpc4357_kit.php)
|
||||
|
||||
### MicroChip SAMD ###
|
||||
|
||||
- [Adafruit Metro M0 Express](https://www.adafruit.com/product/3505)
|
||||
- [Adafruit Metro M4 Express](https://www.adafruit.com/product/3382)
|
||||
|
||||
### Nordic nRF52840 ###
|
||||
|
||||
- [nRF52840-DK (aka pca10056)](https://www.nordicsemi.com/eng/Products/nRF52840-DK)
|
||||
|
||||
## Add your own board ##
|
||||
|
||||
If you don't possess any of supported board above. Don't worry you can easily implemented your own one by following this guide as long as the mcu is supported.
|
||||
|
||||
**Guide to implement a new board is coming soon** ...
|
||||
**Guide to implement a new board is coming soon** ...
|
||||
|
||||
@@ -1,35 +0,0 @@
|
||||
History of updates to CMSIS_CORE_LPC11Uxx
|
||||
===========================================
|
||||
|
||||
18 July 2013
|
||||
------------
|
||||
CMSIS library project using ARM Cortex-M0 CMSIS files as
|
||||
supplied in ARM's CMSIS 3.20 March 2013 release, together
|
||||
with NXP's device specific files taken from old
|
||||
CMSISv2p00_LPC11Uxx project.
|
||||
|
||||
Note files are built -Os for both Debug and Release
|
||||
|
||||
|
||||
History of updates to CMSISv2p00_LPC11Uxx
|
||||
=========================================
|
||||
|
||||
2 June 2011
|
||||
-----------
|
||||
Updated version of core_cm0.h from ARM (V2.03, dated
|
||||
23. May 2011) - with main change being removal of
|
||||
core debug registers (which are not accessible from
|
||||
application code on Cortex-M0).
|
||||
|
||||
8 April 2011
|
||||
------------
|
||||
Minor fix to LPC11Uxx.h to change LPC_CT32B1_BASE from
|
||||
0x40014000 to 0x40018000
|
||||
|
||||
23 March 2011
|
||||
-------------
|
||||
LPC11Uxx CMSIS 2.0 library project using ARM
|
||||
Cortex-M0 CMSIS files as supplied in ARM's CMSIS 2.0
|
||||
December 2010 release, together with device/board
|
||||
specific files from NXP.
|
||||
|
||||
@@ -1,670 +0,0 @@
|
||||
|
||||
/****************************************************************************************************//**
|
||||
* @file LPC11Uxx.h
|
||||
*
|
||||
*
|
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
|
||||
* default LPC11Uxx Device Series
|
||||
*
|
||||
* @version V0.1
|
||||
* @date 21. March 2011
|
||||
*
|
||||
* @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
|
||||
*
|
||||
* from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,
|
||||
* created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
|
||||
*
|
||||
*******************************************************************************************************/
|
||||
|
||||
// ################################################################################
|
||||
// Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000
|
||||
// ################################################################################
|
||||
|
||||
/** @addtogroup NXP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LPC11Uxx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC11UXX_H__
|
||||
#define __LPC11UXX_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/* Interrupt Number Definition */
|
||||
|
||||
typedef enum {
|
||||
// ------------------------- Cortex-M0 Processor Exceptions Numbers -----------------------------
|
||||
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
|
||||
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
|
||||
SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
|
||||
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
|
||||
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
|
||||
// --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------
|
||||
FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */
|
||||
FLEX_INT1_IRQn = 1,
|
||||
FLEX_INT2_IRQn = 2,
|
||||
FLEX_INT3_IRQn = 3,
|
||||
FLEX_INT4_IRQn = 4,
|
||||
FLEX_INT5_IRQn = 5,
|
||||
FLEX_INT6_IRQn = 6,
|
||||
FLEX_INT7_IRQn = 7,
|
||||
GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */
|
||||
GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */
|
||||
Reserved0_IRQn = 10, /*!< Reserved Interrupt */
|
||||
Reserved1_IRQn = 11,
|
||||
Reserved2_IRQn = 12,
|
||||
Reserved3_IRQn = 13,
|
||||
SSP1_IRQn = 14, /*!< SSP1 Interrupt */
|
||||
I2C_IRQn = 15, /*!< I2C Interrupt */
|
||||
TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
|
||||
TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
|
||||
TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
|
||||
TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
|
||||
SSP0_IRQn = 20, /*!< SSP0 Interrupt */
|
||||
UART_IRQn = 21, /*!< UART Interrupt */
|
||||
USB_IRQn = 22, /*!< USB IRQ Interrupt */
|
||||
USB_FIQn = 23, /*!< USB FIQ Interrupt */
|
||||
ADC_IRQn = 24, /*!< A/D Converter Interrupt */
|
||||
WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
|
||||
BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
|
||||
FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
|
||||
Reserved4_IRQn = 28, /*!< Reserved Interrupt */
|
||||
Reserved5_IRQn = 29, /*!< Reserved Interrupt */
|
||||
USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */
|
||||
Reserved6_IRQn = 31, /*!< Reserved Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/** @addtogroup Configuration_of_CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */
|
||||
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
/** @} */ /* End of group Configuration_of_CMSIS */
|
||||
|
||||
#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
|
||||
#include "system_LPC11Uxx.h" /*!< LPC11Uxx System */
|
||||
|
||||
/** @addtogroup Device_Peripheral_Registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- I2C -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
/**
|
||||
* @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C)
|
||||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x40000000) I2C Structure */
|
||||
__IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */
|
||||
__I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */
|
||||
__IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */
|
||||
__IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */
|
||||
__IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */
|
||||
__IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */
|
||||
__IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/
|
||||
__IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/
|
||||
__IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/
|
||||
__IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/
|
||||
__IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/
|
||||
__I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */
|
||||
union{
|
||||
__IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */
|
||||
struct{
|
||||
__IO uint32_t MASK0;
|
||||
__IO uint32_t MASK1;
|
||||
__IO uint32_t MASK2;
|
||||
__IO uint32_t MASK3;
|
||||
};
|
||||
};
|
||||
} LPC_I2C_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- WWDT -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
/**
|
||||
* @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT)
|
||||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x40004000) WWDT Structure */
|
||||
__IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/
|
||||
__IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */
|
||||
__IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */
|
||||
__I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */
|
||||
__IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
|
||||
__IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
|
||||
__IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
|
||||
} LPC_WWDT_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- USART -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
/**
|
||||
* @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART)
|
||||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x40008000) USART Structure */
|
||||
|
||||
union {
|
||||
__IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
|
||||
__O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
|
||||
__I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
|
||||
};
|
||||
|
||||
union {
|
||||
__IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
|
||||
__IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
|
||||
};
|
||||
|
||||
union {
|
||||
__O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
|
||||
__I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
|
||||
};
|
||||
__IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
|
||||
__IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
|
||||
__I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
|
||||
__I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
|
||||
__IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
|
||||
__IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
|
||||
__IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
|
||||
__IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
|
||||
__IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
|
||||
__IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
|
||||
__I uint32_t RESERVED0[3];
|
||||
__IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
|
||||
__I uint32_t RESERVED1;
|
||||
__IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
|
||||
__IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
|
||||
__IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
|
||||
__IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
|
||||
__IO uint32_t SYNCCTRL;
|
||||
} LPC_USART_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- Timer -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
/**
|
||||
* @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3
|
||||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
|
||||
__IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */
|
||||
__IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */
|
||||
__IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */
|
||||
__IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */
|
||||
__IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */
|
||||
__IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */
|
||||
union {
|
||||
__IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */
|
||||
struct{
|
||||
__IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
|
||||
__IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
|
||||
__IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
|
||||
__IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
|
||||
};
|
||||
};
|
||||
__IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */
|
||||
union{
|
||||
__I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */
|
||||
struct{
|
||||
__I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
|
||||
__I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
|
||||
__I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
|
||||
__I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
|
||||
};
|
||||
};
|
||||
__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */
|
||||
__I uint32_t RESERVED0[12];
|
||||
__IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */
|
||||
__IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */
|
||||
} LPC_CTxxBx_Type;
|
||||
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- ADC -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
/**
|
||||
* @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC)
|
||||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x4001C000) ADC Structure */
|
||||
__IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */
|
||||
__IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */
|
||||
__I uint32_t RESERVED0[1];
|
||||
__IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */
|
||||
union{
|
||||
__I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
|
||||
struct{
|
||||
__IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/
|
||||
__IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/
|
||||
__IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/
|
||||
__IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/
|
||||
__IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/
|
||||
__IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/
|
||||
__IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/
|
||||
__IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/
|
||||
};
|
||||
};
|
||||
__I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */
|
||||
} LPC_ADC_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- PMU -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
/**
|
||||
* @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU)
|
||||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x40038000) PMU Structure */
|
||||
__IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
|
||||
union{
|
||||
__IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
|
||||
struct{
|
||||
__IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
|
||||
__IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
|
||||
__IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
|
||||
__IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
|
||||
};
|
||||
};
|
||||
} LPC_PMU_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- FLASHCTRL -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
/**
|
||||
* @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL)
|
||||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
|
||||
__I uint32_t RESERVED0[4];
|
||||
__IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
|
||||
__I uint32_t RESERVED1[3];
|
||||
__IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
|
||||
__IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
|
||||
__I uint32_t RESERVED2[1];
|
||||
__I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
|
||||
__I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
|
||||
__I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
|
||||
__I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
|
||||
__I uint32_t RESERVED3[1001];
|
||||
__I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
|
||||
__I uint32_t RESERVED4[1];
|
||||
__IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
|
||||
} LPC_FLASHCTRL_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- SSP0/1 -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
/**
|
||||
* @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0)
|
||||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
|
||||
__IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
|
||||
__IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
|
||||
__IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
|
||||
__I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
|
||||
__IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
|
||||
__IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
|
||||
__I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
|
||||
__I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
|
||||
__IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
|
||||
} LPC_SSPx_Type;
|
||||
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- IOCONFIG -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
/**
|
||||
* @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
|
||||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
|
||||
__IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
|
||||
__IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
|
||||
__IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
|
||||
__IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
|
||||
__IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
|
||||
__IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
|
||||
__IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
|
||||
__IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
|
||||
__IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
|
||||
__IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
|
||||
__IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
|
||||
__IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
|
||||
__IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
|
||||
__IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
|
||||
__IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
|
||||
__IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
|
||||
__IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
|
||||
__IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
|
||||
__IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
|
||||
__IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
|
||||
__IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
|
||||
__IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
|
||||
__IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
|
||||
__IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
|
||||
__IO uint32_t PIO1_0; /*!< Offset: 0x060 */
|
||||
__IO uint32_t PIO1_1;
|
||||
__IO uint32_t PIO1_2;
|
||||
__IO uint32_t PIO1_3;
|
||||
__IO uint32_t PIO1_4; /*!< Offset: 0x070 */
|
||||
__IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
|
||||
__IO uint32_t PIO1_6;
|
||||
__IO uint32_t PIO1_7;
|
||||
__IO uint32_t PIO1_8; /*!< Offset: 0x080 */
|
||||
__IO uint32_t PIO1_9;
|
||||
__IO uint32_t PIO1_10;
|
||||
__IO uint32_t PIO1_11;
|
||||
__IO uint32_t PIO1_12; /*!< Offset: 0x090 */
|
||||
__IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */
|
||||
__IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */
|
||||
__IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
|
||||
__IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
|
||||
__IO uint32_t PIO1_17;
|
||||
__IO uint32_t PIO1_18;
|
||||
__IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
|
||||
__IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
|
||||
__IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
|
||||
__IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
|
||||
__IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
|
||||
__IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
|
||||
__IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
|
||||
__IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
|
||||
__IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
|
||||
__IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
|
||||
__IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
|
||||
__IO uint32_t PIO1_30;
|
||||
__IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
|
||||
} LPC_IOCON_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- SYSCON -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
/**
|
||||
* @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON)
|
||||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
|
||||
__IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
|
||||
__IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
|
||||
__IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
|
||||
__I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
|
||||
__IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
|
||||
__I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
|
||||
__I uint32_t RESERVED0[2];
|
||||
__IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
|
||||
__IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
|
||||
__I uint32_t RESERVED1[2];
|
||||
__IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
|
||||
__I uint32_t RESERVED2[3];
|
||||
__IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
|
||||
__IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
|
||||
__IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
|
||||
__IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */
|
||||
__I uint32_t RESERVED3[8];
|
||||
__IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
|
||||
__IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
|
||||
__IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
|
||||
__I uint32_t RESERVED4[1];
|
||||
__IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
|
||||
__I uint32_t RESERVED5[4];
|
||||
__IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
|
||||
__IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
|
||||
__IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
|
||||
__I uint32_t RESERVED6[8];
|
||||
__IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
|
||||
__IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */
|
||||
__IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
|
||||
__I uint32_t RESERVED7[5];
|
||||
__IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
|
||||
__IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
|
||||
__IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
|
||||
__I uint32_t RESERVED8[5];
|
||||
__I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
|
||||
__I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
|
||||
__I uint32_t RESERVED9[18];
|
||||
__IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
|
||||
__IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
|
||||
__I uint32_t RESERVED10[6];
|
||||
__IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */
|
||||
__IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
|
||||
__IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
|
||||
__IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
|
||||
__I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
|
||||
__I uint32_t RESERVED11[25];
|
||||
__IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
|
||||
__I uint32_t RESERVED12[3];
|
||||
__IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
|
||||
__I uint32_t RESERVED13[6];
|
||||
__IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
|
||||
__IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
|
||||
__IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
|
||||
__I uint32_t RESERVED14[110];
|
||||
__I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */
|
||||
} LPC_SYSCON_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- GPIO_PIN_INT -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
/**
|
||||
* @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT)
|
||||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
|
||||
__IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
|
||||
__IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
|
||||
__IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
|
||||
__IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
|
||||
__IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
|
||||
__IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
|
||||
__IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
|
||||
__IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
|
||||
__IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
|
||||
__IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
|
||||
} LPC_GPIO_PIN_INT_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- GPIO_GROUP_INT0/1 -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
/**
|
||||
* @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0)
|
||||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
|
||||
__IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
|
||||
__I uint32_t RESERVED0[7];
|
||||
__IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
|
||||
__I uint32_t RESERVED1[6];
|
||||
__IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
|
||||
} LPC_GPIO_GROUP_INTx_Type;
|
||||
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- USB -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
/**
|
||||
* @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB)
|
||||
*/
|
||||
|
||||
typedef struct { /*!< (@ 0x40080000) USB Structure */
|
||||
__IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */
|
||||
__IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */
|
||||
__IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */
|
||||
__IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */
|
||||
__IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */
|
||||
__IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */
|
||||
__IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */
|
||||
__IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
|
||||
__IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */
|
||||
__IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */
|
||||
__IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */
|
||||
__IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */
|
||||
__I uint32_t RESERVED0[1];
|
||||
__I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */
|
||||
} LPC_USB_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- GPIO_PORT -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
/**
|
||||
* @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
__IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
|
||||
__IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
|
||||
};
|
||||
__IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
|
||||
};
|
||||
__I uint32_t RESERVED0[1008];
|
||||
union {
|
||||
struct {
|
||||
__IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
|
||||
__IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
|
||||
};
|
||||
__IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
|
||||
};
|
||||
uint32_t RESERVED1[960];
|
||||
__IO uint32_t DIR[2]; /* 0x2000 */
|
||||
uint32_t RESERVED2[30];
|
||||
__IO uint32_t MASK[2]; /* 0x2080 */
|
||||
uint32_t RESERVED3[30];
|
||||
__IO uint32_t PIN[2]; /* 0x2100 */
|
||||
uint32_t RESERVED4[30];
|
||||
__IO uint32_t MPIN[2]; /* 0x2180 */
|
||||
uint32_t RESERVED5[30];
|
||||
__IO uint32_t SET[2]; /* 0x2200 */
|
||||
uint32_t RESERVED6[30];
|
||||
__O uint32_t CLR[2]; /* 0x2280 */
|
||||
uint32_t RESERVED7[30];
|
||||
__O uint32_t NOT[2]; /* 0x2300 */
|
||||
} LPC_GPIO_Type;
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- Peripheral memory map -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
#define LPC_I2C_BASE (0x40000000)
|
||||
#define LPC_WWDT_BASE (0x40004000)
|
||||
#define LPC_USART_BASE (0x40008000)
|
||||
#define LPC_CT16B0_BASE (0x4000C000)
|
||||
#define LPC_CT16B1_BASE (0x40010000)
|
||||
#define LPC_CT32B0_BASE (0x40014000)
|
||||
#define LPC_CT32B1_BASE (0x40018000)
|
||||
#define LPC_ADC_BASE (0x4001C000)
|
||||
#define LPC_PMU_BASE (0x40038000)
|
||||
#define LPC_FLASHCTRL_BASE (0x4003C000)
|
||||
#define LPC_SSP0_BASE (0x40040000)
|
||||
#define LPC_SSP1_BASE (0x40058000)
|
||||
#define LPC_IOCON_BASE (0x40044000)
|
||||
#define LPC_SYSCON_BASE (0x40048000)
|
||||
#define LPC_GPIO_PIN_INT_BASE (0x4004C000)
|
||||
#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
|
||||
#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
|
||||
#define LPC_USB_BASE (0x40080000)
|
||||
#define LPC_GPIO_BASE (0x50000000)
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- Peripheral declaration -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
|
||||
#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
|
||||
#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
|
||||
#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
|
||||
#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
|
||||
#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
|
||||
#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
|
||||
#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
|
||||
#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
|
||||
#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
|
||||
#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
|
||||
#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
|
||||
#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
|
||||
#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
|
||||
#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
|
||||
#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)
|
||||
#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)
|
||||
#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
|
||||
#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
|
||||
|
||||
|
||||
/** @} */ /* End of group Device_Peripheral_Registers */
|
||||
/** @} */ /* End of group (null) */
|
||||
/** @} */ /* End of group LPC11Uxx */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif // __LPC11UXX_H__
|
||||
@@ -1,82 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267 $
|
||||
* Project: NXP LPC11Uxx software example
|
||||
*
|
||||
* Description:
|
||||
* Power API Header File for NXP LPC11Uxx Device Series
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef __LPC11UXX_POWER_API_H__
|
||||
#define __LPC11UXX_POWER_API_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PWRROMD_PRESENT
|
||||
|
||||
typedef struct _PWRD {
|
||||
void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
|
||||
void (*set_power)(unsigned int cmd[], unsigned int resp[]);
|
||||
} PWRD;
|
||||
|
||||
typedef struct _ROM {
|
||||
#ifdef USBROMD_PRESENT
|
||||
const USB * pUSBD;
|
||||
#else
|
||||
const unsigned p_usbd;
|
||||
#endif /* USBROMD_PRESENT */
|
||||
const unsigned p_clib;
|
||||
const unsigned p_cand;
|
||||
#ifdef PWRROMD_PRESENT
|
||||
const PWRD * pPWRD;
|
||||
#else
|
||||
const unsigned p_pwrd;
|
||||
#endif /* PWRROMD_PRESENT */
|
||||
const unsigned p_dev1;
|
||||
const unsigned p_dev2;
|
||||
const unsigned p_dev3;
|
||||
const unsigned p_dev4;
|
||||
} ROM;
|
||||
|
||||
//PLL setup related definitions
|
||||
#define CPU_FREQ_EQU 0 //main PLL freq must be equal to the specified
|
||||
#define CPU_FREQ_LTE 1 //main PLL freq must be less than or equal the specified
|
||||
#define CPU_FREQ_GTE 2 //main PLL freq must be greater than or equal the specified
|
||||
#define CPU_FREQ_APPROX 3 //main PLL freq must be as close as possible the specified
|
||||
|
||||
#define PLL_CMD_SUCCESS 0 //PLL setup successfully found
|
||||
#define PLL_INVALID_FREQ 1 //specified freq out of range (either input or output)
|
||||
#define PLL_INVALID_MODE 2 //invalid mode (see above for valid) specified
|
||||
#define PLL_FREQ_NOT_FOUND 3 //specified freq not found under specified conditions
|
||||
#define PLL_NOT_LOCKED 4 //PLL not locked => no changes to the PLL setup
|
||||
|
||||
//power setup elated definitions
|
||||
#define PARAM_DEFAULT 0 //default power settings (voltage regulator, flash interface)
|
||||
#define PARAM_CPU_PERFORMANCE 1 //setup for maximum CPU performance (higher current, more computation)
|
||||
#define PARAM_EFFICIENCY 2 //balanced setting (power vs CPU performance)
|
||||
#define PARAM_LOW_CURRENT 3 //lowest active current, lowest CPU performance
|
||||
|
||||
#define PARAM_CMD_SUCCESS 0 //power setting successfully found
|
||||
#define PARAM_INVALID_FREQ 1 //specified freq out of range (=0 or > 50 MHz)
|
||||
#define PARAM_INVALID_MODE 2 //specified mode not valid (see above for valid)
|
||||
|
||||
#define MAX_CLOCK_KHZ_PARAM 50000
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LPC11UXX_POWER_API_H__ */
|
||||
|
||||
@@ -1,64 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_LPC11Uxx.h
|
||||
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File
|
||||
* for the NXP LPC11Uxx Device Series
|
||||
* @version V1.10
|
||||
* @date 24. November 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_LPC11Uxx_H
|
||||
#define __SYSTEM_LPC11Uxx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_LPC11Uxx_H */
|
||||
@@ -1,32 +0,0 @@
|
||||
<!-- liblinks.xml
|
||||
|
||||
LPCXpresso "Smart update wizard" script file
|
||||
When executed on a particular application project, will
|
||||
add appropriate links to the specified library project.
|
||||
|
||||
Note that this script assumes that the application project
|
||||
contains the standard 'Debug' and 'Release' build
|
||||
configurations.
|
||||
-->
|
||||
|
||||
<project name="" update="true">
|
||||
<setting id="all.compiler.inc">
|
||||
<value>${workspace_loc:/CMSIS_CORE_LPC11Uxx/inc}</value>
|
||||
</setting>
|
||||
<setting id="all.compiler.def">
|
||||
<value>__USE_CMSIS=CMSIS_CORE_LPC11Uxx</value>
|
||||
</setting>
|
||||
<setting id="linker.libs">
|
||||
<value>CMSIS_CORE_LPC11Uxx</value>
|
||||
</setting>
|
||||
<setting id="linker.paths" buildType="Debug">
|
||||
<value>${workspace_loc:/CMSIS_CORE_LPC11Uxx/Debug}</value>
|
||||
</setting>
|
||||
<setting id="linker.paths" buildType="Release">
|
||||
<value>${workspace_loc:/CMSIS_CORE_LPC11Uxx/Release}</value>
|
||||
</setting>
|
||||
<requires msg="Library project `CMSIS_CORE_LPC11Uxx` not found">
|
||||
<value>CMSIS_CORE_LPC11Uxx</value>
|
||||
</requires>
|
||||
</project>
|
||||
|
||||
@@ -1,451 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file system_LPC11Uxx.c
|
||||
* @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File
|
||||
* for the NXP LPC13xx Device Series
|
||||
* @version V1.10
|
||||
* @date 24. November 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include "LPC11Uxx.h"
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
/*--------------------- Clock Configuration ----------------------------------
|
||||
//
|
||||
// <e> Clock Configuration
|
||||
// <h> System Oscillator Control Register (SYSOSCCTRL)
|
||||
// <o1.0> BYPASS: System Oscillator Bypass Enable
|
||||
// <i> If enabled then PLL input (sys_osc_clk) is fed
|
||||
// <i> directly from XTALIN and XTALOUT pins.
|
||||
// <o1.9> FREQRANGE: System Oscillator Frequency Range
|
||||
// <i> Determines frequency range for Low-power oscillator.
|
||||
// <0=> 1 - 20 MHz
|
||||
// <1=> 15 - 25 MHz
|
||||
// </h>
|
||||
//
|
||||
// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
|
||||
// <o2.0..4> DIVSEL: Select Divider for Fclkana
|
||||
// <i> wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
|
||||
// <0-31>
|
||||
// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
|
||||
// <0=> Undefined
|
||||
// <1=> 0.5 MHz
|
||||
// <2=> 0.8 MHz
|
||||
// <3=> 1.1 MHz
|
||||
// <4=> 1.4 MHz
|
||||
// <5=> 1.6 MHz
|
||||
// <6=> 1.8 MHz
|
||||
// <7=> 2.0 MHz
|
||||
// <8=> 2.2 MHz
|
||||
// <9=> 2.4 MHz
|
||||
// <10=> 2.6 MHz
|
||||
// <11=> 2.7 MHz
|
||||
// <12=> 2.9 MHz
|
||||
// <13=> 3.1 MHz
|
||||
// <14=> 3.2 MHz
|
||||
// <15=> 3.4 MHz
|
||||
// </h>
|
||||
//
|
||||
// <h> System PLL Control Register (SYSPLLCTRL)
|
||||
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
|
||||
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
|
||||
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
|
||||
// <o3.0..4> MSEL: Feedback Divider Selection
|
||||
// <i> M = MSEL + 1
|
||||
// <0-31>
|
||||
// <o3.5..6> PSEL: Post Divider Selection
|
||||
// <0=> P = 1
|
||||
// <1=> P = 2
|
||||
// <2=> P = 4
|
||||
// <3=> P = 8
|
||||
// </h>
|
||||
//
|
||||
// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
|
||||
// <o4.0..1> SEL: System PLL Clock Source
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> Main Clock Source Select Register (MAINCLKSEL)
|
||||
// <o5.0..1> SEL: Clock Source for Main Clock
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> Input Clock to System PLL
|
||||
// <2=> WDT Oscillator
|
||||
// <3=> System PLL Clock Out
|
||||
// </h>
|
||||
//
|
||||
// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
|
||||
// <o6.0..7> DIV: System AHB Clock Divider
|
||||
// <i> Divides main clock to provide system clock to core, memories, and peripherals.
|
||||
// <i> 0 = is disabled
|
||||
// <0-255>
|
||||
// </h>
|
||||
//
|
||||
// <h> USB PLL Control Register (USBPLLCTRL)
|
||||
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
|
||||
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
|
||||
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
|
||||
// <o7.0..4> MSEL: Feedback Divider Selection
|
||||
// <i> M = MSEL + 1
|
||||
// <0-31>
|
||||
// <o7.5..6> PSEL: Post Divider Selection
|
||||
// <0=> P = 1
|
||||
// <1=> P = 2
|
||||
// <2=> P = 4
|
||||
// <3=> P = 8
|
||||
// </h>
|
||||
//
|
||||
// <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
|
||||
// <o8.0..1> SEL: USB PLL Clock Source
|
||||
// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> USB Clock Source Select Register (USBCLKSEL)
|
||||
// <o9.0..1> SEL: System PLL Clock Source
|
||||
// <0=> USB PLL out
|
||||
// <1=> Main clock
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> USB Clock Divider Register (USBCLKDIV)
|
||||
// <o10.0..7> DIV: USB Clock Divider
|
||||
// <i> Divides USB clock to 48 MHz.
|
||||
// <i> 0 = is disabled
|
||||
// <0-255>
|
||||
// </h>
|
||||
// </e>
|
||||
*/
|
||||
#define CLOCK_SETUP 1
|
||||
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000
|
||||
#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
|
||||
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
|
||||
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
|
||||
#define USBPLLCTRL_Val 0x00000023 // Reset: 0x000
|
||||
#define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000
|
||||
#define USBCLKSEL_Val 0x00000000 // Reset: 0x000
|
||||
#define USBCLKDIV_Val 0x00000001 // Reset: 0x001
|
||||
|
||||
/*
|
||||
//-------- <<< end of configuration section >>> ------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Check the register settings
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
||||
#define CHECK_RSVD(val, mask) (val & mask)
|
||||
|
||||
/* Clock Configuration -------------------------------------------------------*/
|
||||
#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
|
||||
#error "SYSOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
|
||||
#error "WDTOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
|
||||
#error "SYSPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
|
||||
#error "SYSPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
|
||||
#error "MAINCLKSEL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
|
||||
#error "SYSAHBCLKDIV: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
|
||||
#error "USBPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
|
||||
#error "USBPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
|
||||
#error "USBCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
|
||||
#error "USBCLKDIV: Value out of range!"
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __XTAL (12000000UL) /* Oscillator frequency */
|
||||
#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
|
||||
#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
|
||||
|
||||
|
||||
#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
|
||||
#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
#if (__FREQSEL == 0)
|
||||
#define __WDT_OSC_CLK ( 0) /* undefined */
|
||||
#elif (__FREQSEL == 1)
|
||||
#define __WDT_OSC_CLK ( 500000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 2)
|
||||
#define __WDT_OSC_CLK ( 800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 3)
|
||||
#define __WDT_OSC_CLK (1100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 4)
|
||||
#define __WDT_OSC_CLK (1400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 5)
|
||||
#define __WDT_OSC_CLK (1600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 6)
|
||||
#define __WDT_OSC_CLK (1800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 7)
|
||||
#define __WDT_OSC_CLK (2000000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 8)
|
||||
#define __WDT_OSC_CLK (2200000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 9)
|
||||
#define __WDT_OSC_CLK (2400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 10)
|
||||
#define __WDT_OSC_CLK (2600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 11)
|
||||
#define __WDT_OSC_CLK (2700000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 12)
|
||||
#define __WDT_OSC_CLK (2900000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 13)
|
||||
#define __WDT_OSC_CLK (3100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 14)
|
||||
#define __WDT_OSC_CLK (3200000 / __DIVSEL)
|
||||
#else
|
||||
#define __WDT_OSC_CLK (3400000 / __DIVSEL)
|
||||
#endif
|
||||
|
||||
/* sys_pllclkin calculation */
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
|
||||
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
|
||||
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
|
||||
#else
|
||||
#define __SYS_PLLCLKIN (0)
|
||||
#endif
|
||||
|
||||
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
|
||||
|
||||
/* main clock calculation */
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 0)
|
||||
#define __MAIN_CLOCK (__IRC_OSC_CLK)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 1)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKIN)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 2)
|
||||
#if (__FREQSEL == 0)
|
||||
#error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
|
||||
#else
|
||||
#define __MAIN_CLOCK (__WDT_OSC_CLK)
|
||||
#endif
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 3)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
|
||||
#else
|
||||
#define __MAIN_CLOCK (0)
|
||||
#endif
|
||||
|
||||
#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
|
||||
|
||||
#else
|
||||
#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
|
||||
#endif // CLOCK_SETUP
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
uint32_t wdt_osc = 0;
|
||||
|
||||
/* Determine clock frequency according to clock register values */
|
||||
switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
|
||||
case 0: wdt_osc = 0; break;
|
||||
case 1: wdt_osc = 500000; break;
|
||||
case 2: wdt_osc = 800000; break;
|
||||
case 3: wdt_osc = 1100000; break;
|
||||
case 4: wdt_osc = 1400000; break;
|
||||
case 5: wdt_osc = 1600000; break;
|
||||
case 6: wdt_osc = 1800000; break;
|
||||
case 7: wdt_osc = 2000000; break;
|
||||
case 8: wdt_osc = 2200000; break;
|
||||
case 9: wdt_osc = 2400000; break;
|
||||
case 10: wdt_osc = 2600000; break;
|
||||
case 11: wdt_osc = 2700000; break;
|
||||
case 12: wdt_osc = 2900000; break;
|
||||
case 13: wdt_osc = 3100000; break;
|
||||
case 14: wdt_osc = 3200000; break;
|
||||
case 15: wdt_osc = 3400000; break;
|
||||
}
|
||||
wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
|
||||
|
||||
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* Input Clock to System PLL */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 2: /* WDT Oscillator */
|
||||
SystemCoreClock = wdt_osc;
|
||||
break;
|
||||
case 3: /* System PLL Clock Out */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
} else {
|
||||
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
} else {
|
||||
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void) {
|
||||
volatile uint32_t i;
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
|
||||
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
|
||||
for (i = 0; i < 200; i++) __NOP();
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
|
||||
LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
|
||||
LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
|
||||
LPC_SYSCON->SYSPLLCLKUEN = 0x01;
|
||||
while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
|
||||
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
|
||||
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
#endif
|
||||
|
||||
#if (((MAINCLKSEL_Val & 0x03) == 2) )
|
||||
LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
|
||||
for (i = 0; i < 200; i++) __NOP();
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
|
||||
LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
|
||||
LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
|
||||
LPC_SYSCON->MAINCLKUEN = 0x01;
|
||||
while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
|
||||
|
||||
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
|
||||
|
||||
#if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
|
||||
|
||||
#if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
|
||||
LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
|
||||
LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */
|
||||
LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */
|
||||
LPC_SYSCON->USBPLLCLKUEN = 0x01;
|
||||
while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */
|
||||
LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
|
||||
while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
|
||||
LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
|
||||
|
||||
#else /* USB clock is not used */
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* System clock to the IOCON needs to be enabled or
|
||||
most of the I/O related peripherals won't work. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
|
||||
|
||||
}
|
||||
@@ -1,819 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: gpio.c 6172 2011-01-13 18:22:51Z usb00423 $
|
||||
* Project: NXP LPC11Uxx GPIO example
|
||||
*
|
||||
* Description:
|
||||
* This file contains GPIO code example which include GPIO
|
||||
* initialization, GPIO interrupt handler, and related APIs for
|
||||
* GPIO access.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#include "LPC11Uxx.h" /* LPC11Uxx Peripheral Registers */
|
||||
#include "lpc11uxx_gpio.h"
|
||||
|
||||
volatile uint32_t flex_int0_counter = 0;
|
||||
volatile uint32_t flex_int1_counter = 0;
|
||||
volatile uint32_t flex_int2_counter = 0;
|
||||
volatile uint32_t flex_int3_counter = 0;
|
||||
volatile uint32_t flex_int4_counter = 0;
|
||||
volatile uint32_t flex_int5_counter = 0;
|
||||
volatile uint32_t flex_int6_counter = 0;
|
||||
volatile uint32_t flex_int7_counter = 0;
|
||||
volatile uint32_t gint0_counter = 0;
|
||||
volatile uint32_t gint1_counter = 0;
|
||||
volatile uint32_t flex_int0_level_counter = 0;
|
||||
volatile uint32_t flex_int0_rising_edge_counter = 0;
|
||||
volatile uint32_t flex_int0_falling_edge_counter = 0;
|
||||
volatile uint32_t flex_int1_level_counter = 0;
|
||||
volatile uint32_t flex_int1_rising_edge_counter = 0;
|
||||
volatile uint32_t flex_int1_falling_edge_counter = 0;
|
||||
volatile uint32_t flex_int2_level_counter = 0;
|
||||
volatile uint32_t flex_int2_rising_edge_counter = 0;
|
||||
volatile uint32_t flex_int2_falling_edge_counter = 0;
|
||||
volatile uint32_t flex_int3_level_counter = 0;
|
||||
volatile uint32_t flex_int3_rising_edge_counter = 0;
|
||||
volatile uint32_t flex_int3_falling_edge_counter = 0;
|
||||
volatile uint32_t flex_int4_level_counter = 0;
|
||||
volatile uint32_t flex_int4_rising_edge_counter = 0;
|
||||
volatile uint32_t flex_int4_falling_edge_counter = 0;
|
||||
volatile uint32_t flex_int5_level_counter = 0;
|
||||
volatile uint32_t flex_int5_rising_edge_counter = 0;
|
||||
volatile uint32_t flex_int5_falling_edge_counter = 0;
|
||||
volatile uint32_t flex_int6_level_counter = 0;
|
||||
volatile uint32_t flex_int6_rising_edge_counter = 0;
|
||||
volatile uint32_t flex_int6_falling_edge_counter = 0;
|
||||
volatile uint32_t flex_int7_level_counter = 0;
|
||||
volatile uint32_t flex_int7_rising_edge_counter = 0;
|
||||
volatile uint32_t flex_int7_falling_edge_counter = 0;
|
||||
volatile uint32_t gint0_level_counter = 0;
|
||||
volatile uint32_t gint0_edge_counter = 0;
|
||||
volatile uint32_t gint1_level_counter = 0;
|
||||
volatile uint32_t gint1_edge_counter = 0;
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: FLEX_INT0_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void FLEX_INT0_IRQHandler(void)
|
||||
{
|
||||
flex_int0_counter++;
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<0) )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<0) )
|
||||
{
|
||||
flex_int0_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->RISE & (0x1<<0) )
|
||||
{
|
||||
flex_int0_rising_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->RISE = 0x1<<0;
|
||||
}
|
||||
else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<0) )
|
||||
{
|
||||
flex_int0_falling_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->FALL = 0x1<<0;
|
||||
}
|
||||
LPC_GPIO_PIN_INT->IST = 0x1<<0;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: FLEX_INT1_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void FLEX_INT1_IRQHandler(void)
|
||||
{
|
||||
flex_int1_counter++;
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<1) )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<1) )
|
||||
{
|
||||
flex_int1_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->RISE & (0x1<<1) )
|
||||
{
|
||||
flex_int1_rising_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->RISE = 0x1<<1;
|
||||
}
|
||||
else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<1) )
|
||||
{
|
||||
flex_int1_falling_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->FALL = 0x1<<1;
|
||||
}
|
||||
LPC_GPIO_PIN_INT->IST = 0x1<<1;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: FLEX_INT2_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void FLEX_INT2_IRQHandler(void)
|
||||
{
|
||||
flex_int2_counter++;
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<2) )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<2) )
|
||||
{
|
||||
flex_int2_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->RISE & (0x1<<2) )
|
||||
{
|
||||
flex_int2_rising_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->RISE = 0x1<<2;
|
||||
}
|
||||
else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<2) )
|
||||
{
|
||||
flex_int2_falling_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->FALL = 0x1<<2;
|
||||
}
|
||||
LPC_GPIO_PIN_INT->IST = 0x1<<2;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: FLEX_INT3_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void FLEX_INT3_IRQHandler(void)
|
||||
{
|
||||
flex_int3_counter++;
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<3) )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<3) )
|
||||
{
|
||||
flex_int3_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->RISE & (0x1<<3) )
|
||||
{
|
||||
flex_int3_rising_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->RISE = 0x1<<3;
|
||||
}
|
||||
else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<3) )
|
||||
{
|
||||
flex_int3_falling_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->FALL = 0x1<<3;
|
||||
}
|
||||
LPC_GPIO_PIN_INT->IST = 0x1<<3;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: FLEX_INT4_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void FLEX_INT4_IRQHandler(void)
|
||||
{
|
||||
flex_int4_counter++;
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<4) )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<4) )
|
||||
{
|
||||
flex_int4_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->RISE & (0x1<<4) )
|
||||
{
|
||||
flex_int4_rising_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->RISE = 0x1<<4;
|
||||
}
|
||||
else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<4) )
|
||||
{
|
||||
flex_int4_falling_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->FALL = 0x1<<4;
|
||||
}
|
||||
LPC_GPIO_PIN_INT->IST = 0x1<<4;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: FLEX_INT5_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void FLEX_INT5_IRQHandler(void)
|
||||
{
|
||||
flex_int5_counter++;
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<5) )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<5) )
|
||||
{
|
||||
flex_int5_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->RISE & (0x1<<5) )
|
||||
{
|
||||
flex_int5_rising_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->RISE = 0x1<<5;
|
||||
}
|
||||
else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<5) )
|
||||
{
|
||||
flex_int5_falling_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->FALL = 0x1<<5;
|
||||
}
|
||||
LPC_GPIO_PIN_INT->IST = 0x1<<5;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: FLEX_INT6_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void FLEX_INT6_IRQHandler(void)
|
||||
{
|
||||
flex_int6_counter++;
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<6) )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<6) )
|
||||
{
|
||||
flex_int6_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->RISE & (0x1<<6) )
|
||||
{
|
||||
flex_int6_rising_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->RISE = 0x1<<6;
|
||||
}
|
||||
else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<6) )
|
||||
{
|
||||
flex_int6_falling_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->FALL = 0x1<<6;
|
||||
}
|
||||
LPC_GPIO_PIN_INT->IST = 0x1<<6;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: FLEX_INT7_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void FLEX_INT7_IRQHandler(void)
|
||||
{
|
||||
flex_int7_counter++;
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<7) )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<7) )
|
||||
{
|
||||
flex_int7_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->RISE & (0x1<<7) )
|
||||
{
|
||||
flex_int7_rising_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->RISE = 0x1<<7;
|
||||
}
|
||||
else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<7) )
|
||||
{
|
||||
flex_int7_falling_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->FALL = 0x1<<7;
|
||||
}
|
||||
LPC_GPIO_PIN_INT->IST = 0x1<<7;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GINT0_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GINT0_IRQHandler(void)
|
||||
{
|
||||
gint0_counter++;
|
||||
if ( LPC_GPIO_GROUP_INT0->CTRL & 0x1 )
|
||||
{
|
||||
if ( LPC_GPIO_GROUP_INT0->CTRL & (0x1<<4) )
|
||||
{
|
||||
gint0_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
gint0_edge_counter++;
|
||||
}
|
||||
LPC_GPIO_GROUP_INT0->CTRL |= 0x1;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GINT1_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GINT1_IRQHandler(void)
|
||||
{
|
||||
gint1_counter++;
|
||||
if ( LPC_GPIO_GROUP_INT1->CTRL & 0x1 )
|
||||
{
|
||||
if ( LPC_GPIO_GROUP_INT1->CTRL & (0x1<<4) )
|
||||
{
|
||||
gint1_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
gint1_edge_counter++;
|
||||
}
|
||||
LPC_GPIO_GROUP_INT1->CTRL |= 0x1;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOInit
|
||||
**
|
||||
** Descriptions: Initialize GPIO, install the
|
||||
** GPIO interrupt handler
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: true or false, return false if the VIC table
|
||||
** is full and GPIO interrupt handler can be
|
||||
** installed.
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GPIOInit( void )
|
||||
{
|
||||
/* Enable AHB clock to the GPIO domain. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
|
||||
|
||||
/* Enable AHB clock to the FlexInt, GroupedInt domain. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOSetFlexInterrupt
|
||||
**
|
||||
** Descriptions: Set interrupt sense, event, etc.
|
||||
** sense: edge or level, 0 is edge, 1 is level
|
||||
** event/polarity: 0 is active low/falling, 1 is high/rising.
|
||||
**
|
||||
** parameters: channel #, port #, bit position, sense, event(polarity)
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GPIOSetFlexInterrupt( uint32_t channelNum, uint32_t portNum, uint32_t bitPosi,
|
||||
uint32_t sense, uint32_t event )
|
||||
{
|
||||
switch ( channelNum )
|
||||
{
|
||||
case CHANNEL0:
|
||||
if ( portNum )
|
||||
{
|
||||
LPC_SYSCON->PINTSEL[0] = bitPosi + 24;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_SYSCON->PINTSEL[0] = bitPosi;
|
||||
}
|
||||
NVIC_EnableIRQ(FLEX_INT0_IRQn);
|
||||
break;
|
||||
case CHANNEL1:
|
||||
if ( portNum )
|
||||
{
|
||||
LPC_SYSCON->PINTSEL[1] = bitPosi + 24;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_SYSCON->PINTSEL[1] = bitPosi;
|
||||
}
|
||||
NVIC_EnableIRQ(FLEX_INT1_IRQn);
|
||||
break;
|
||||
case CHANNEL2:
|
||||
if ( portNum )
|
||||
{
|
||||
LPC_SYSCON->PINTSEL[2] = bitPosi + 24;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_SYSCON->PINTSEL[2] = bitPosi;
|
||||
}
|
||||
NVIC_EnableIRQ(FLEX_INT2_IRQn);
|
||||
break;
|
||||
case CHANNEL3:
|
||||
if ( portNum )
|
||||
{
|
||||
LPC_SYSCON->PINTSEL[3] = bitPosi + 24;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_SYSCON->PINTSEL[3] = bitPosi;
|
||||
}
|
||||
NVIC_EnableIRQ(FLEX_INT3_IRQn);
|
||||
break;
|
||||
case CHANNEL4:
|
||||
if ( portNum )
|
||||
{
|
||||
LPC_SYSCON->PINTSEL[4] = bitPosi + 24;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_SYSCON->PINTSEL[4] = bitPosi;
|
||||
}
|
||||
NVIC_EnableIRQ(FLEX_INT4_IRQn);
|
||||
break;
|
||||
case CHANNEL5:
|
||||
if ( portNum )
|
||||
{
|
||||
LPC_SYSCON->PINTSEL[5] = bitPosi + 24;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_SYSCON->PINTSEL[5] = bitPosi;
|
||||
}
|
||||
NVIC_EnableIRQ(FLEX_INT5_IRQn);
|
||||
break;
|
||||
case CHANNEL6:
|
||||
if ( portNum )
|
||||
{
|
||||
LPC_SYSCON->PINTSEL[6] = bitPosi + 24;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_SYSCON->PINTSEL[6] = bitPosi;
|
||||
}
|
||||
NVIC_EnableIRQ(FLEX_INT6_IRQn);
|
||||
break;
|
||||
case CHANNEL7:
|
||||
if ( portNum )
|
||||
{
|
||||
LPC_SYSCON->PINTSEL[7] = bitPosi + 24;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_SYSCON->PINTSEL[7] = bitPosi;
|
||||
}
|
||||
NVIC_EnableIRQ(FLEX_INT7_IRQn);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
if ( sense == 0 )
|
||||
{
|
||||
LPC_GPIO_PIN_INT->ISEL &= ~(0x1<<channelNum); /* Edge trigger */
|
||||
if ( event == 0 )
|
||||
{
|
||||
LPC_GPIO_PIN_INT->IENF |= (0x1<<channelNum); /* faling edge */
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_PIN_INT->IENR |= (0x1<<channelNum); /* Rising edge */
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_PIN_INT->ISEL |= (0x1<<channelNum); /* Level trigger. */
|
||||
LPC_GPIO_PIN_INT->IENR |= (0x1<<channelNum); /* Level enable */
|
||||
if ( event == 0 )
|
||||
{
|
||||
LPC_GPIO_PIN_INT->IENF &= ~(0x1<<channelNum); /* active-low */
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_PIN_INT->IENF |= (0x1<<channelNum); /* active-high */
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOFlexIntEnable
|
||||
**
|
||||
** Descriptions: Enable Interrupt
|
||||
**
|
||||
** parameters: channel num, event(0 is falling edge, 1 is rising edge)
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GPIOFlexIntEnable( uint32_t channelNum, uint32_t event )
|
||||
{
|
||||
if ( !( LPC_GPIO_PIN_INT->ISEL & (0x1<<channelNum) ) )
|
||||
{
|
||||
if ( event == 0 )
|
||||
{
|
||||
LPC_GPIO_PIN_INT->SIENF |= (0x1<<channelNum); /* faling edge */
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_PIN_INT->SIENR |= (0x1<<channelNum); /* Rising edge */
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_PIN_INT->SIENR |= (0x1<<channelNum); /* Level */
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOFlexIntDisable
|
||||
**
|
||||
** Descriptions: Disable Interrupt
|
||||
**
|
||||
** parameters: channel num, event(0 is falling edge, 1 is rising edge)
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GPIOFlexIntDisable( uint32_t channelNum, uint32_t event )
|
||||
{
|
||||
if ( !( LPC_GPIO_PIN_INT->ISEL & (0x1<<channelNum) ) )
|
||||
{
|
||||
if ( event == 0 )
|
||||
{
|
||||
LPC_GPIO_PIN_INT->CIENF |= (0x1<<channelNum); /* faling edge */
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_PIN_INT->CIENR |= (0x1<<channelNum); /* Rising edge */
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_PIN_INT->CIENR |= (0x1<<channelNum); /* Level */
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOFlexIntStatus
|
||||
**
|
||||
** Descriptions: Get Interrupt status
|
||||
**
|
||||
** parameters: channel num
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
uint32_t GPIOFlexIntStatus( uint32_t channelNum )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<channelNum) )
|
||||
{
|
||||
return( 1 );
|
||||
}
|
||||
else
|
||||
{
|
||||
return( 0 );
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOFlexIntClear
|
||||
**
|
||||
** Descriptions: Clear Interrupt
|
||||
**
|
||||
** parameters: channel num
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GPIOFlexIntClear( uint32_t channelNum )
|
||||
{
|
||||
if ( !( LPC_GPIO_PIN_INT->ISEL & (0x1<<channelNum) ) )
|
||||
{
|
||||
LPC_GPIO_PIN_INT->IST = (1<<channelNum);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOSetGroupedInterrupt
|
||||
**
|
||||
** Descriptions: Set interrupt logic, sense, eventPattern, etc.
|
||||
** logic: AND or OR, 0 is OR, 1 is AND
|
||||
** sensePattern: edge or level, 0 is edge, 1 is level
|
||||
** event/polarity: 0 is active low/falling, 1 is high/rising.
|
||||
**
|
||||
** parameters: group #, bit pattern, logic, sense, event(polarity) pattern
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GPIOSetGroupedInterrupt( uint32_t groupNum, uint32_t *bitPattern, uint32_t logic,
|
||||
uint32_t sense, uint32_t *eventPattern )
|
||||
{
|
||||
switch ( groupNum )
|
||||
{
|
||||
case GROUP0:
|
||||
if ( sense == 0 )
|
||||
{
|
||||
LPC_GPIO_GROUP_INT0->CTRL &= ~(0x1<<2); /* Edge trigger */
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_GROUP_INT0->CTRL |= (0x1<<2); /* Level trigger. */
|
||||
}
|
||||
LPC_GPIO_GROUP_INT0->CTRL |= (logic<<1);
|
||||
LPC_GPIO_GROUP_INT0->PORT_POL[0] = *((uint32_t *)(eventPattern + 0));
|
||||
LPC_GPIO_GROUP_INT0->PORT_POL[1] = *((uint32_t *)(eventPattern + 1));
|
||||
LPC_GPIO_GROUP_INT0->PORT_ENA[0] = *((uint32_t *)(bitPattern + 0));
|
||||
LPC_GPIO_GROUP_INT0->PORT_ENA[1] = *((uint32_t *)(bitPattern + 1));
|
||||
/* as soon as enabled, an edge may be generated */
|
||||
/* clear interrupt flag and NVIC pending interrupt to */
|
||||
/* workaround the potential edge generated as enabled */
|
||||
LPC_GPIO_GROUP_INT0->CTRL |= (1<<0);
|
||||
NVIC_ClearPendingIRQ(GINT0_IRQn);
|
||||
NVIC_EnableIRQ(GINT0_IRQn);
|
||||
break;
|
||||
case GROUP1:
|
||||
if ( sense == 0 )
|
||||
{
|
||||
LPC_GPIO_GROUP_INT1->CTRL &= ~(0x1<<2); /* Edge trigger */
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_GROUP_INT1->CTRL |= (0x1<<2); /* Level trigger. */
|
||||
}
|
||||
LPC_GPIO_GROUP_INT1->CTRL |= (logic<<1);
|
||||
LPC_GPIO_GROUP_INT1->PORT_POL[0] = *((uint32_t *)(eventPattern + 0));
|
||||
LPC_GPIO_GROUP_INT1->PORT_POL[1] = *((uint32_t *)(eventPattern + 1));
|
||||
LPC_GPIO_GROUP_INT1->PORT_ENA[0] = *((uint32_t *)(bitPattern + 0));
|
||||
LPC_GPIO_GROUP_INT1->PORT_ENA[1] = *((uint32_t *)(bitPattern + 1));
|
||||
/* as soon as enabled, an edge may be generated */
|
||||
/* clear interrupt flag and NVIC pending interrupt to */
|
||||
/* workaround the potential edge generated as enabled */
|
||||
LPC_GPIO_GROUP_INT1->CTRL |= (1<<0);
|
||||
NVIC_ClearPendingIRQ(GINT1_IRQn);
|
||||
NVIC_EnableIRQ(GINT1_IRQn);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOGetPinValue
|
||||
**
|
||||
** Descriptions: Read Current state of port pin, PIN register value
|
||||
**
|
||||
** parameters: port num, bit position
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi )
|
||||
{
|
||||
uint32_t regVal = 0;
|
||||
|
||||
if( bitPosi < 0x20 )
|
||||
{
|
||||
if ( LPC_GPIO->PIN[portNum] & (0x1<<bitPosi) )
|
||||
{
|
||||
regVal = 1;
|
||||
}
|
||||
}
|
||||
else if( bitPosi == 0xFF )
|
||||
{
|
||||
regVal = LPC_GPIO->PIN[portNum];
|
||||
}
|
||||
return ( regVal );
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOSetBitValue
|
||||
**
|
||||
** Descriptions: Set/clear a bit in a specific position
|
||||
**
|
||||
** parameters: port num, bit position, bit value
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal )
|
||||
{
|
||||
if ( bitVal )
|
||||
{
|
||||
LPC_GPIO->SET[portNum] = 1<<bitPosi;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO->CLR[portNum] = 1<<bitPosi;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOSetDir
|
||||
**
|
||||
** Descriptions: Set the direction in GPIO port
|
||||
**
|
||||
** parameters: portNum, bit position, direction (1 out, 0 input)
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GPIOSetDir( uint32_t portNum, uint32_t bitPosi, uint32_t dir )
|
||||
{
|
||||
if( dir )
|
||||
{
|
||||
LPC_GPIO->DIR[portNum] |= (1<<bitPosi);
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO->DIR[portNum] &= ~(1<<bitPosi);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@@ -1,64 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: gpio.h 6172 2011-01-13 18:22:51Z usb00423 $
|
||||
* Project: NXP LPC11Uxx software example
|
||||
*
|
||||
* Description:
|
||||
* This file contains definition and prototype for GPIO.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef __GPIO_H
|
||||
#define __GPIO_H
|
||||
|
||||
#define CHANNEL0 0
|
||||
#define CHANNEL1 1
|
||||
#define CHANNEL2 2
|
||||
#define CHANNEL3 3
|
||||
#define CHANNEL4 4
|
||||
#define CHANNEL5 5
|
||||
#define CHANNEL6 6
|
||||
#define CHANNEL7 7
|
||||
|
||||
#define PORT0 0
|
||||
#define PORT1 1
|
||||
|
||||
#define GROUP0 0
|
||||
#define GROUP1 1
|
||||
|
||||
void FLEX_INT0_IRQHandler(void);
|
||||
void FLEX_INT1_IRQHandler(void);
|
||||
void FLEX_INT2_IRQHandler(void);
|
||||
void FLEX_INT3_IRQHandler(void);
|
||||
void FLEX_INT4_IRQHandler(void);
|
||||
void FLEX_INT5_IRQHandler(void);
|
||||
void FLEX_INT6_IRQHandler(void);
|
||||
void FLEX_INT7_IRQHandler(void);
|
||||
void GINT0_IRQHandler(void);
|
||||
void GINT1_IRQHandler(void);
|
||||
void GPIOInit( void );
|
||||
void GPIOSetFlexInterrupt( uint32_t channelNum, uint32_t portNum, uint32_t bitPosi,
|
||||
uint32_t sense, uint32_t event );
|
||||
void GPIOFlexIntEnable( uint32_t channelNum, uint32_t event );
|
||||
void GPIOFlexIntDisable( uint32_t channelNum, uint32_t event );
|
||||
uint32_t GPIOFlexIntStatus( uint32_t channelNum );
|
||||
void GPIOFlexIntClear( uint32_t channelNum );
|
||||
void GPIOSetGroupedInterrupt( uint32_t groupNum, uint32_t *bitPattern, uint32_t logic,
|
||||
uint32_t sense, uint32_t *eventPattern );
|
||||
uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi );
|
||||
void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal );
|
||||
void GPIOSetDir( uint32_t portNum, uint32_t bitPosi, uint32_t dir );
|
||||
|
||||
#endif /* end __GPIO_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@@ -1,238 +0,0 @@
|
||||
/*****************************************************************************
|
||||
* uart.c: UART API file for NXP LPC11xx Family Microprocessors
|
||||
*
|
||||
* Copyright(C) 2008, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
* History
|
||||
* 2009.12.07 ver 1.00 Preliminary version, first Release
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "LPC11Uxx.h"
|
||||
#include "lpc11uxx_uart.h"
|
||||
|
||||
volatile uint32_t UARTStatus;
|
||||
volatile uint8_t UARTTxEmpty = 1;
|
||||
volatile uint8_t UARTBuffer[BUFSIZE];
|
||||
volatile uint32_t UARTCount = 0;
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: UART_IRQHandler
|
||||
**
|
||||
** Descriptions: UART interrupt handler
|
||||
**
|
||||
** parameters: None
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void UART_IRQHandler(void)
|
||||
{
|
||||
uint8_t IIRValue, LSRValue;
|
||||
uint8_t Dummy = Dummy;
|
||||
|
||||
IIRValue = LPC_USART->IIR;
|
||||
|
||||
IIRValue >>= 1; /* skip pending bit in IIR */
|
||||
IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
|
||||
if (IIRValue == IIR_RLS) /* Receive Line Status */
|
||||
{
|
||||
LSRValue = LPC_USART->LSR;
|
||||
/* Receive Line Status */
|
||||
if (LSRValue & (LSR_OE | LSR_PE | LSR_FE | LSR_RXFE | LSR_BI))
|
||||
{
|
||||
/* There are errors or break interrupt */
|
||||
/* Read LSR will clear the interrupt */
|
||||
UARTStatus = LSRValue;
|
||||
Dummy = LPC_USART->RBR; /* Dummy read on RX to clear
|
||||
interrupt, then bail out */
|
||||
return;
|
||||
}
|
||||
if (LSRValue & LSR_RDR) /* Receive Data Ready */
|
||||
{
|
||||
/* If no error on RLS, normal ready, save into the data buffer. */
|
||||
/* Note: read RBR will clear the interrupt */
|
||||
UARTBuffer[UARTCount++] = LPC_USART->RBR;
|
||||
if (UARTCount == BUFSIZE)
|
||||
{
|
||||
UARTCount = 0; /* buffer overflow */
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (IIRValue == IIR_RDA) /* Receive Data Available */
|
||||
{
|
||||
/* Receive Data Available */
|
||||
UARTBuffer[UARTCount++] = LPC_USART->RBR;
|
||||
if (UARTCount == BUFSIZE)
|
||||
{
|
||||
UARTCount = 0; /* buffer overflow */
|
||||
}
|
||||
}
|
||||
else if (IIRValue == IIR_CTI) /* Character timeout indicator */
|
||||
{
|
||||
/* Character Time-out indicator */
|
||||
UARTStatus |= 0x100; /* Bit 9 as the CTI error */
|
||||
}
|
||||
else if (IIRValue == IIR_THRE) /* THRE, transmit holding register empty */
|
||||
{
|
||||
/* THRE interrupt */
|
||||
LSRValue = LPC_USART->LSR; /* Check status in the LSR to see if
|
||||
valid data in U0THR or not */
|
||||
if (LSRValue & LSR_THRE)
|
||||
{
|
||||
UARTTxEmpty = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
UARTTxEmpty = 0;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
#if MODEM_TEST
|
||||
/*****************************************************************************
|
||||
** Function name: ModemInit
|
||||
**
|
||||
** Descriptions: Initialize UART0 port as modem, setup pin select.
|
||||
**
|
||||
** parameters: None
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void ModemInit( void )
|
||||
{
|
||||
LPC_IOCON->PIO2_0 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO2_0 |= 0x01; /* UART DTR */
|
||||
LPC_IOCON->PIO0_7 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO0_7 |= 0x01; /* UART CTS */
|
||||
LPC_IOCON->PIO1_5 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_5 |= 0x01; /* UART RTS */
|
||||
#if 1
|
||||
LPC_IOCON->DSR_LOC = 0;
|
||||
LPC_IOCON->PIO2_1 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO2_1 |= 0x01; /* UART DSR */
|
||||
|
||||
LPC_IOCON->DCD_LOC = 0;
|
||||
LPC_IOCON->PIO2_2 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO2_2 |= 0x01; /* UART DCD */
|
||||
|
||||
LPC_IOCON->RI_LOC = 0;
|
||||
LPC_IOCON->PIO2_3 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO2_3 |= 0x01; /* UART RI */
|
||||
|
||||
#else
|
||||
LPC_IOCON->DSR_LOC = 1;
|
||||
LPC_IOCON->PIO3_1 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO3_1 |= 0x01; /* UART DSR */
|
||||
|
||||
LPC_IOCON->DCD_LOC = 1;
|
||||
LPC_IOCON->PIO3_2 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO3_2 |= 0x01; /* UART DCD */
|
||||
|
||||
LPC_IOCON->RI_LOC = 1;
|
||||
LPC_IOCON->PIO3_3 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO3_3 |= 0x01; /* UART RI */
|
||||
#endif
|
||||
LPC_USART->MCR = 0xC0; /* Enable Auto RTS and Auto CTS. */
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: UARTInit
|
||||
**
|
||||
** Descriptions: Initialize UART0 port, setup pin select,
|
||||
** clock, parity, stop bits, FIFO, etc.
|
||||
**
|
||||
** parameters: UART baudrate
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void UARTInit(uint32_t baudrate)
|
||||
{
|
||||
uint32_t Fdiv;
|
||||
uint32_t regVal;
|
||||
|
||||
UARTTxEmpty = 1;
|
||||
UARTCount = 0;
|
||||
|
||||
NVIC_DisableIRQ(UART_IRQn);
|
||||
|
||||
LPC_IOCON->PIO0_18 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO0_18 |= 0x01; /* UART RXD */
|
||||
LPC_IOCON->PIO0_19 &= ~0x07;
|
||||
LPC_IOCON->PIO0_19 |= 0x01; /* UART TXD */
|
||||
/* Enable UART clock */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
|
||||
LPC_SYSCON->UARTCLKDIV = 0x1; /* divided by 1 */
|
||||
|
||||
LPC_USART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
|
||||
regVal = LPC_SYSCON->UARTCLKDIV;
|
||||
|
||||
Fdiv = (((SystemCoreClock*LPC_SYSCON->SYSAHBCLKDIV)/regVal)/16)/baudrate ; /*baud rate */
|
||||
|
||||
LPC_USART->DLM = Fdiv / 256;
|
||||
LPC_USART->DLL = Fdiv % 256;
|
||||
LPC_USART->LCR = 0x03; /* DLAB = 0 */
|
||||
LPC_USART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
|
||||
|
||||
/* Read to clear the line status. */
|
||||
regVal = LPC_USART->LSR;
|
||||
|
||||
/* Ensure a clean start, no data in either TX or RX FIFO. */
|
||||
// CodeRed - added parentheses around comparison in operand of &
|
||||
while (( LPC_USART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
|
||||
while ( LPC_USART->LSR & LSR_RDR )
|
||||
{
|
||||
regVal = LPC_USART->RBR; /* Dump data from RX FIFO */
|
||||
}
|
||||
|
||||
/* Enable the UART Interrupt */
|
||||
NVIC_EnableIRQ(UART_IRQn);
|
||||
|
||||
#if CONFIG_UART_ENABLE_INTERRUPT==1
|
||||
#if CONFIG_UART_ENABLE_TX_INTERRUPT==1
|
||||
LPC_USART->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */
|
||||
#else
|
||||
LPC_USART->IER = IER_RBR | IER_RLS; /* Enable UART interrupt */
|
||||
#endif
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: UARTSend
|
||||
**
|
||||
** Descriptions: Send a block of data to the UART 0 port based
|
||||
** on the data length
|
||||
**
|
||||
** parameters: buffer pointer, and data length
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void UARTSend(uint8_t *BufferPtr, uint32_t Length)
|
||||
{
|
||||
|
||||
while ( Length != 0 )
|
||||
{
|
||||
/* THRE status, contain valid data */
|
||||
#if CONFIG_UART_ENABLE_TX_INTERRUPT==1
|
||||
/* Below flag is set inside the interrupt handler when THRE occurs. */
|
||||
while ( !(UARTTxEmpty & 0x01) );
|
||||
LPC_USART->THR = *BufferPtr;
|
||||
UARTTxEmpty = 0; /* not empty in the THR until it shifts out */
|
||||
#else
|
||||
while ( !(LPC_USART->LSR & LSR_THRE) );
|
||||
LPC_USART->THR = *BufferPtr;
|
||||
#endif
|
||||
BufferPtr++;
|
||||
Length--;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@@ -1,55 +0,0 @@
|
||||
/*****************************************************************************
|
||||
* uart.h: Header file for NXP LPC1xxx Family Microprocessors
|
||||
*
|
||||
* Copyright(C) 2008, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
* History
|
||||
* 2009.12.07 ver 1.00 Preliminary version, first Release
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __UART_H
|
||||
#define __UART_H
|
||||
|
||||
#define RS485_ENABLED 0
|
||||
#define TX_INTERRUPT 0 /* 0 if TX uses polling, 1 interrupt driven. */
|
||||
#define MODEM_TEST 0
|
||||
|
||||
#define IER_RBR 0x01
|
||||
#define IER_THRE 0x02
|
||||
#define IER_RLS 0x04
|
||||
|
||||
#define IIR_PEND 0x01
|
||||
#define IIR_RLS 0x03
|
||||
#define IIR_RDA 0x02
|
||||
#define IIR_CTI 0x06
|
||||
#define IIR_THRE 0x01
|
||||
|
||||
#define LSR_RDR 0x01
|
||||
#define LSR_OE 0x02
|
||||
#define LSR_PE 0x04
|
||||
#define LSR_FE 0x08
|
||||
#define LSR_BI 0x10
|
||||
#define LSR_THRE 0x20
|
||||
#define LSR_TEMT 0x40
|
||||
#define LSR_RXFE 0x80
|
||||
|
||||
#define BUFSIZE 0x40
|
||||
|
||||
/* RS485 mode definition. */
|
||||
#define RS485_NMMEN (0x1<<0)
|
||||
#define RS485_RXDIS (0x1<<1)
|
||||
#define RS485_AADEN (0x1<<2)
|
||||
#define RS485_SEL (0x1<<3)
|
||||
#define RS485_DCTRL (0x1<<4)
|
||||
#define RS485_OINV (0x1<<5)
|
||||
|
||||
void ModemInit( void );
|
||||
void UARTInit(uint32_t Baudrate);
|
||||
void UART_IRQHandler(void);
|
||||
void UARTSend(uint8_t *BufferPtr, uint32_t Length);
|
||||
|
||||
#endif /* end __UART_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@@ -1,81 +0,0 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file hal_lpc11uxx.c
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#include "common/tusb_common.h"
|
||||
#include "hal.h"
|
||||
|
||||
#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX
|
||||
|
||||
void tusb_hal_int_enable(uint8_t rhport)
|
||||
{
|
||||
(void) rhport; // discard compiler's warning
|
||||
NVIC_EnableIRQ(USB_IRQn);
|
||||
}
|
||||
|
||||
void tusb_hal_int_disable(uint8_t rhport)
|
||||
{
|
||||
(void) rhport; // discard compiler's warning
|
||||
NVIC_DisableIRQ(USB_IRQn);
|
||||
}
|
||||
|
||||
bool tusb_hal_init(void)
|
||||
{
|
||||
// TODO remove magic number
|
||||
/* Enable AHB clock to the USB block and USB RAM. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= ((0x1<<14) | (0x1<<27));
|
||||
LPC_SYSCON->PDRUNCFG &= ~( BIT_(8) | BIT_(10) ); // enable USB PLL & USB transceiver
|
||||
|
||||
/* Pull-down is needed, or internally, VBUS will be floating. This is to
|
||||
address the wrong status in VBUSDebouncing bit in CmdStatus register. */
|
||||
// set PIO0_3 as USB_VBUS
|
||||
LPC_IOCON->PIO0_3 &= ~0x1F;
|
||||
LPC_IOCON->PIO0_3 |= (0x01<<0) | (1 << 3); /* Secondary function VBUS */
|
||||
|
||||
// set PIO0_6 as usb connect
|
||||
LPC_IOCON->PIO0_6 &= ~0x07;
|
||||
LPC_IOCON->PIO0_6 |= (0x01<<0); /* Secondary function SoftConn */
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void USB_IRQHandler(void)
|
||||
{
|
||||
hal_dcd_isr(0);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,53 +0,0 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file hal_lpc11uxx.h
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef _TUSB_HAL_MCU_H_
|
||||
#define _TUSB_HAL_MCU_H_
|
||||
|
||||
#include "LPC11Uxx.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_HAL_MCU_H_ */
|
||||
@@ -1,25 +0,0 @@
|
||||
History of updates to CMSIS_CORE_LPC13Uxx
|
||||
===========================================
|
||||
|
||||
18 July 2013
|
||||
------------
|
||||
CMSIS library project using ARM Cortex-M0 CMSIS files as
|
||||
supplied in ARM's CMSIS 3.20 March 2013 release, together
|
||||
with NXP's device specific files taken from old
|
||||
CMSISv2p10_LPC13Uxx project.
|
||||
|
||||
Note files are built -Os for both Debug and Release
|
||||
|
||||
|
||||
History of updates to CMSISv2p10_LPC13Uxx
|
||||
=========================================
|
||||
|
||||
17 February 2012
|
||||
----------------
|
||||
|
||||
CMSIS 2.1 library project using ARM Cortex-M3 CMSIS
|
||||
files as supplied in ARM's CMSIS 2.1 July 2011 release,
|
||||
together with device/board specific files from NXP for
|
||||
LPC1300 (12bit ADC) parts (ie LPC1315/16/17/45/46/47).
|
||||
|
||||
|
||||
@@ -1,760 +0,0 @@
|
||||
|
||||
/****************************************************************************************************//**
|
||||
* @file LPC13Uxx.h
|
||||
*
|
||||
*
|
||||
*
|
||||
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
|
||||
* default LPC13Uxx Device Series
|
||||
*
|
||||
* @version V0.1
|
||||
* @date 18. Jan 2012
|
||||
*
|
||||
* @note Generated with SFDGen V2.6 Build 4f on Tuesday, 17.01.2012 13:39:52
|
||||
*
|
||||
* from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
|
||||
* created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
|
||||
*
|
||||
*******************************************************************************************************/
|
||||
|
||||
/** @addtogroup NXP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LPC13Uxx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC13UXX_H__
|
||||
#define __LPC13UXX_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/* Interrupt Number Definition */
|
||||
|
||||
typedef enum {
|
||||
// ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
|
||||
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
|
||||
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
|
||||
BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
|
||||
UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
|
||||
SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
|
||||
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
|
||||
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
|
||||
// ---------------------------- LPC13Uxx Specific Interrupt Numbers --------------------------------
|
||||
PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
|
||||
PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
|
||||
PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
|
||||
PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
|
||||
PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
|
||||
PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
|
||||
PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
|
||||
PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
|
||||
GINT0_IRQn = 8, /*!< 8 GINT0 */
|
||||
GINT1_IRQn = 9, /*!< 9 GINT1 */
|
||||
Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
|
||||
Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
|
||||
RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
|
||||
Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
|
||||
SSP1_IRQn = 14, /*!< 14 SSP1 */
|
||||
I2C_IRQn = 15, /*!< 15 I2C */
|
||||
CT16B0_IRQn = 16, /*!< 16 CT16B0 */
|
||||
CT16B1_IRQn = 17, /*!< 17 CT16B1 */
|
||||
CT32B0_IRQn = 18, /*!< 18 CT32B0 */
|
||||
CT32B1_IRQn = 19, /*!< 19 CT32B1 */
|
||||
SSP0_IRQn = 20, /*!< 20 SSP0 */
|
||||
USART_IRQn = 21, /*!< 21 USART */
|
||||
USB_IRQ_IRQn = 22, /*!< 22 USB_IRQ */
|
||||
USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
|
||||
ADC_IRQn = 24, /*!< 24 ADC */
|
||||
WDT_IRQn = 25, /*!< 25 WDT */
|
||||
BOD_IRQn = 26, /*!< 26 BOD */
|
||||
FMC_IRQn = 27, /*!< 27 FMC */
|
||||
Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
|
||||
Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
|
||||
USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
|
||||
Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/** @addtogroup Configuration_of_CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
|
||||
|
||||
#define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
/** @} */ /* End of group Configuration_of_CMSIS */
|
||||
|
||||
#include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
|
||||
#include "system_LPC13Uxx.h" /*!< LPC13Uxx System */
|
||||
|
||||
/** @addtogroup Device_Peripheral_Registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- I2C -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
typedef struct { /*!< (@ 0x40000000) I2C Structure */
|
||||
__IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
|
||||
__I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
|
||||
__IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
|
||||
__IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
|
||||
__IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
|
||||
__IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
|
||||
__O uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
|
||||
__IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register. */
|
||||
union{
|
||||
__IO uint32_t ADR[3]; /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
|
||||
struct{
|
||||
__IO uint32_t ADR1;
|
||||
__IO uint32_t ADR2;
|
||||
__IO uint32_t ADR3;
|
||||
};
|
||||
};
|
||||
__I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
|
||||
union{
|
||||
__IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
|
||||
struct{
|
||||
__IO uint32_t MASK0;
|
||||
__IO uint32_t MASK1;
|
||||
__IO uint32_t MASK2;
|
||||
__IO uint32_t MASK3;
|
||||
};
|
||||
};
|
||||
} LPC_I2C_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- WWDT -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
typedef struct { /*!< (@ 0x40004000) WWDT Structure */
|
||||
__IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
|
||||
__IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
|
||||
__O uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
|
||||
__I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
|
||||
__IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
|
||||
__IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
|
||||
__IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
|
||||
} LPC_WWDT_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- USART -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
typedef struct { /*!< (@ 0x40008000) USART Structure */
|
||||
|
||||
union {
|
||||
__IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
|
||||
__O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
|
||||
__I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
|
||||
};
|
||||
|
||||
union {
|
||||
__IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
|
||||
__IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
|
||||
};
|
||||
|
||||
union {
|
||||
__O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
|
||||
__I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
|
||||
};
|
||||
__IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
|
||||
__IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
|
||||
__I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
|
||||
__I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
|
||||
__IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
|
||||
__IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
|
||||
__IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
|
||||
__IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
|
||||
__IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
|
||||
__IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
|
||||
__I uint32_t RESERVED0[3];
|
||||
__IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
|
||||
__I uint32_t RESERVED1;
|
||||
__IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
|
||||
__IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
|
||||
__IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
|
||||
__IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
|
||||
__IO uint32_t SYNCCTRL; /*!< (@ 0x40008058) Synchronous mode control register. */
|
||||
} LPC_USART_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- CT16B0 -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
typedef struct { /*!< (@ 0x4000C000) CT16B0 Structure */
|
||||
__IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
|
||||
__IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
|
||||
__IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
|
||||
__IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
|
||||
__IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
|
||||
__IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
|
||||
union {
|
||||
__IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
|
||||
struct{
|
||||
__IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
|
||||
__IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
|
||||
__IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
|
||||
__IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
|
||||
};
|
||||
};
|
||||
__IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
|
||||
union{
|
||||
__I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
|
||||
struct{
|
||||
__I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
|
||||
__I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
|
||||
__I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
|
||||
__I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
|
||||
};
|
||||
};
|
||||
__IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
|
||||
__I uint32_t RESERVED0[12];
|
||||
__IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
|
||||
__IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
|
||||
} LPC_CT16B0_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- CT16B1 -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
typedef struct { /*!< (@ 0x40010000) CT16B1 Structure */
|
||||
__IO uint32_t IR; /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
|
||||
__IO uint32_t TCR; /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
|
||||
__IO uint32_t TC; /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
|
||||
__IO uint32_t PR; /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
|
||||
__IO uint32_t PC; /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
|
||||
__IO uint32_t MCR; /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
|
||||
union {
|
||||
__IO uint32_t MR[4]; /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
|
||||
struct{
|
||||
__IO uint32_t MR0; /*!< (@ 0x40010018) Match Register. MR0 */
|
||||
__IO uint32_t MR1; /*!< (@ 0x4001001C) Match Register. MR1 */
|
||||
__IO uint32_t MR2; /*!< (@ 0x40010020) Match Register. MR2 */
|
||||
__IO uint32_t MR3; /*!< (@ 0x40010024) Match Register. MR3 */
|
||||
};
|
||||
};
|
||||
__IO uint32_t CCR; /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
|
||||
union{
|
||||
__I uint32_t CR[4]; /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
|
||||
struct{
|
||||
__I uint32_t CR0; /*!< (@ 0x4001002C) Capture Register. CR 0 */
|
||||
__I uint32_t CR1; /*!< (@ 0x40010030) Capture Register. CR 1 */
|
||||
__I uint32_t CR2; /*!< (@ 0x40010034) Capture Register. CR 2 */
|
||||
__I uint32_t CR3; /*!< (@ 0x40010038) Capture Register. CR 3 */
|
||||
};
|
||||
};
|
||||
__IO uint32_t EMR; /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins */
|
||||
__I uint32_t RESERVED0[12];
|
||||
__IO uint32_t CTCR; /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
|
||||
__IO uint32_t PWMC; /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
|
||||
} LPC_CT16B1_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- CT32B0 -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
|
||||
__IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
|
||||
__IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
|
||||
__IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
|
||||
__IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
|
||||
__IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
|
||||
__IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
|
||||
union {
|
||||
__IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
|
||||
struct{
|
||||
__IO uint32_t MR0; /*!< (@ 0x40014018) Match Register. MR0 */
|
||||
__IO uint32_t MR1; /*!< (@ 0x4001401C) Match Register. MR1 */
|
||||
__IO uint32_t MR2; /*!< (@ 0x40014020) Match Register. MR2 */
|
||||
__IO uint32_t MR3; /*!< (@ 0x40014024) Match Register. MR3 */
|
||||
};
|
||||
};
|
||||
__IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
|
||||
union{
|
||||
__I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
|
||||
struct{
|
||||
__I uint32_t CR0; /*!< (@ 0x4001402C) Capture Register. CR 0 */
|
||||
__I uint32_t CR1; /*!< (@ 0x40014030) Capture Register. CR 1 */
|
||||
__I uint32_t CR2; /*!< (@ 0x40014034) Capture Register. CR 2 */
|
||||
__I uint32_t CR3; /*!< (@ 0x40014038) Capture Register. CR 3 */
|
||||
};
|
||||
};
|
||||
__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
|
||||
__I uint32_t RESERVED0[12];
|
||||
__IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
|
||||
__IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
|
||||
} LPC_CT32B0_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- CT32B1 -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
typedef struct { /*!< (@ 0x40018000) CT32B1 Structure */
|
||||
__IO uint32_t IR; /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
|
||||
__IO uint32_t TCR; /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
|
||||
__IO uint32_t TC; /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
|
||||
__IO uint32_t PR; /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
|
||||
__IO uint32_t PC; /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
|
||||
__IO uint32_t MCR; /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
|
||||
union {
|
||||
__IO uint32_t MR[4]; /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
|
||||
struct{
|
||||
__IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
|
||||
__IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
|
||||
__IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
|
||||
__IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
|
||||
};
|
||||
};
|
||||
__IO uint32_t CCR; /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
|
||||
union{
|
||||
__I uint32_t CR[4]; /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
|
||||
struct{
|
||||
__I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
|
||||
__I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
|
||||
__I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
|
||||
__I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
|
||||
};
|
||||
};
|
||||
__IO uint32_t EMR; /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
|
||||
__I uint32_t RESERVED0[12];
|
||||
__IO uint32_t CTCR; /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
|
||||
__IO uint32_t PWMC; /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
|
||||
} LPC_CT32B1_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- ADC -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
typedef struct { /*!< (@ 0x4001C000) ADC Structure */
|
||||
__IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
|
||||
__IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
|
||||
__I uint32_t RESERVED0[1];
|
||||
__IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
|
||||
union{
|
||||
__I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
|
||||
struct{
|
||||
__I uint32_t DR0; /*!< (@ 0x4001C010) A/D Channel Data Register 0*/
|
||||
__I uint32_t DR1; /*!< (@ 0x4001C014) A/D Channel Data Register 1*/
|
||||
__I uint32_t DR2; /*!< (@ 0x4001C018) A/D Channel Data Register 2*/
|
||||
__I uint32_t DR3; /*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
|
||||
__I uint32_t DR4; /*!< (@ 0x4001C020) A/D Channel Data Register 4*/
|
||||
__I uint32_t DR5; /*!< (@ 0x4001C024) A/D Channel Data Register 5*/
|
||||
__I uint32_t DR6; /*!< (@ 0x4001C028) A/D Channel Data Register 6*/
|
||||
__I uint32_t DR7; /*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
|
||||
};
|
||||
};
|
||||
__I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
|
||||
} LPC_ADC_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- PMU -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
typedef struct { /*!< (@ 0x40038000) PMU Structure */
|
||||
__IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
|
||||
union{
|
||||
__IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
|
||||
struct{
|
||||
__IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
|
||||
__IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
|
||||
__IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
|
||||
__IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
|
||||
};
|
||||
};
|
||||
__IO uint32_t GPREG4; /*!< (@ 0x40038014) General purpose register 4 */
|
||||
} LPC_PMU_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- FLASHCTRL -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
|
||||
__I uint32_t RESERVED0[4];
|
||||
__IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
|
||||
__I uint32_t RESERVED1[3];
|
||||
__IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
|
||||
__IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
|
||||
__I uint32_t RESERVED2[1];
|
||||
__I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
|
||||
__I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
|
||||
__I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
|
||||
__I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
|
||||
__I uint32_t RESERVED3[1001];
|
||||
__I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
|
||||
__I uint32_t RESERVED4[1];
|
||||
__O uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
|
||||
} LPC_FLASHCTRL_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- SSP0 -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
|
||||
__IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
|
||||
__IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
|
||||
__IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
|
||||
__I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
|
||||
__IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
|
||||
__IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
|
||||
__I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
|
||||
__I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
|
||||
__O uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
|
||||
} LPC_SSP0_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- IOCON -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
typedef struct { /*!< (@ 0x40044000) IOCON Structure */
|
||||
__IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
|
||||
__IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
|
||||
__IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
|
||||
__IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
|
||||
__IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
|
||||
__IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
|
||||
__IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
|
||||
__IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
|
||||
__IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/SWO */
|
||||
__IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/TRACECLK */
|
||||
__IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
|
||||
__IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
|
||||
__IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
|
||||
__IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
|
||||
__IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
|
||||
__IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
|
||||
__IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
|
||||
__IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
|
||||
__IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
|
||||
__IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
|
||||
__IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
|
||||
__IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
|
||||
__IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
|
||||
__IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
|
||||
__IO uint32_t PIO1_0; /*!< (@ 0x40044060) I/O configuration for pin PIO1_0/CT32B1_MAT0 */
|
||||
__IO uint32_t PIO1_1; /*!< (@ 0x40044064) I/O configuration for pin PIO1_1/CT32B1_MAT1 */
|
||||
__IO uint32_t PIO1_2; /*!< (@ 0x40044068) I/O configuration for pin PIO1_2/CT32B1_MAT2 */
|
||||
__IO uint32_t PIO1_3; /*!< (@ 0x4004406C) I/O configuration for pin PIO1_3/CT32B1_MAT3 */
|
||||
__IO uint32_t PIO1_4; /*!< (@ 0x40044070) I/O configuration for pin PIO1_4/CT32B1_CAP0 */
|
||||
__IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
|
||||
__IO uint32_t PIO1_6; /*!< (@ 0x40044078) I/O configuration for pin PIO1_6 */
|
||||
__IO uint32_t PIO1_7; /*!< (@ 0x4004407C) I/O configuration for pin PIO1_7 */
|
||||
__IO uint32_t PIO1_8; /*!< (@ 0x40044080) I/O configuration for pin PIO1_8 */
|
||||
__IO uint32_t PIO1_9; /*!< (@ 0x40044084) I/O configuration for pin PIO1_9 */
|
||||
__IO uint32_t PIO1_10; /*!< (@ 0x40044088) I/O configuration for pin PIO1_10 */
|
||||
__IO uint32_t PIO1_11; /*!< (@ 0x4004408C) I/O configuration for pin PIO1_11 */
|
||||
__IO uint32_t PIO1_12; /*!< (@ 0x40044090) I/O configuration for pin PIO1_12 */
|
||||
__IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD */
|
||||
__IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD */
|
||||
__IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
|
||||
__IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
|
||||
__IO uint32_t PIO1_17; /*!< (@ 0x400440A4) I/O configuration for PIO1_17/CT16B0_CAP1/RXD */
|
||||
__IO uint32_t PIO1_18; /*!< (@ 0x400440A8) I/O configuration for PIO1_18/CT16B1_CAP1/TXD */
|
||||
__IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
|
||||
__IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
|
||||
__IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
|
||||
__IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
|
||||
__IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
|
||||
__IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
|
||||
__IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
|
||||
__IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
|
||||
__IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
|
||||
__IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
|
||||
__IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
|
||||
__IO uint32_t PIO1_30; /*!< (@ 0x400440D8) I/O configuration for pin PIO1_30 */
|
||||
__IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
|
||||
} LPC_IOCON_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- SYSCON -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
|
||||
__IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
|
||||
__IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
|
||||
__IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
|
||||
__I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
|
||||
__IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
|
||||
__I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
|
||||
__I uint32_t RESERVED0[2];
|
||||
__IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
|
||||
__IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
|
||||
__I uint32_t RESERVED1[2];
|
||||
__IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
|
||||
__I uint32_t RESERVED2[3];
|
||||
__IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
|
||||
__I uint32_t RESERVED3;
|
||||
__IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
|
||||
__I uint32_t RESERVED4[9];
|
||||
__IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
|
||||
__I uint32_t RESERVED5;
|
||||
__IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
|
||||
__I uint32_t RESERVED6;
|
||||
__IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
|
||||
__I uint32_t RESERVED7[4];
|
||||
__IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
|
||||
__IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
|
||||
__IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
|
||||
__I uint32_t RESERVED8[3];
|
||||
__IO uint32_t TRACECLKDIV; /*!< (@ 0x400480AC) ARM trace clock divider */
|
||||
__IO uint32_t SYSTICKCLKDIV; /*!< (@ 0x400480B0) SYSTICK clock divder */
|
||||
__I uint32_t RESERVED9[3];
|
||||
__IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
|
||||
__I uint32_t RESERVED10;
|
||||
__IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
|
||||
__I uint32_t RESERVED11[5];
|
||||
__IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
|
||||
__I uint32_t RESERVED12;
|
||||
__IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
|
||||
__I uint32_t RESERVED13[5];
|
||||
__I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
|
||||
__I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
|
||||
__I uint32_t RESERVED14[18];
|
||||
__IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
|
||||
__IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
|
||||
__I uint32_t RESERVED15[6];
|
||||
__IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
|
||||
__IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
|
||||
__IO uint32_t PINSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register */
|
||||
__IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
|
||||
__I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
|
||||
__I uint32_t RESERVED16[25];
|
||||
__IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
|
||||
__I uint32_t RESERVED17[3];
|
||||
__IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
|
||||
__I uint32_t RESERVED18[6];
|
||||
__IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
|
||||
__IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
|
||||
__IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
|
||||
__I uint32_t RESERVED19[111];
|
||||
__I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
|
||||
} LPC_SYSCON_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- GPIO_PIN_INT -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
|
||||
__IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
|
||||
__IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
|
||||
__O uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
|
||||
__O uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
|
||||
__IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
|
||||
__O uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
|
||||
__O uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
|
||||
__IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
|
||||
__IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
|
||||
__IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
|
||||
} LPC_GPIO_PIN_INT_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- SSP1 -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
typedef struct { /*!< (@ 0x40058000) SSP1 Structure */
|
||||
__IO uint32_t CR0; /*!< (@ 0x40058000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
|
||||
__IO uint32_t CR1; /*!< (@ 0x40058004) Control Register 1. Selects master/slave and other modes. */
|
||||
__IO uint32_t DR; /*!< (@ 0x40058008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
|
||||
__I uint32_t SR; /*!< (@ 0x4005800C) Status Register */
|
||||
__IO uint32_t CPSR; /*!< (@ 0x40058010) Clock Prescale Register */
|
||||
__IO uint32_t IMSC; /*!< (@ 0x40058014) Interrupt Mask Set and Clear Register */
|
||||
__I uint32_t RIS; /*!< (@ 0x40058018) Raw Interrupt Status Register */
|
||||
__I uint32_t MIS; /*!< (@ 0x4005801C) Masked Interrupt Status Register */
|
||||
__O uint32_t ICR; /*!< (@ 0x40058020) SSPICR Interrupt Clear Register */
|
||||
} LPC_SSP1_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- GPIO_GROUP_INT0 -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
|
||||
__IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
|
||||
__I uint32_t RESERVED0[7];
|
||||
__IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
|
||||
__I uint32_t RESERVED1[6];
|
||||
__IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
|
||||
} LPC_GPIO_GROUP_INT0_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- GPIO_GROUP_INT1 -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
typedef struct { /*!< (@ 0x40060000) GPIO_GROUP_INT1 Structure */
|
||||
__IO uint32_t CTRL; /*!< (@ 0x40060000) GPIO grouped interrupt control register */
|
||||
__I uint32_t RESERVED0[7];
|
||||
__IO uint32_t PORT_POL[2]; /*!< (@ 0x40060020) GPIO grouped interrupt port 0 polarity register */
|
||||
__I uint32_t RESERVED1[6];
|
||||
__IO uint32_t PORT_ENA[2]; /*!< (@ 0x40060040) GPIO grouped interrupt port 0/1 enable register */
|
||||
} LPC_GPIO_GROUP_INT1_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- Repetitive Interrupt Timer (RIT) -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
typedef struct { /*!< (@ 0x40064000) RITIMER Structure */
|
||||
__IO uint32_t COMPVAL; /*!< (@ 0x40064000) RITIMER compare register */
|
||||
__IO uint32_t MASK; /*!< (@ 0x40064004) RITIMER mask register */
|
||||
__IO uint32_t CTRL; /*!< (@ 0x40064008) RITIMER control register */
|
||||
__IO uint32_t COUNTER; /*!< (@ 0x4006400C) RITIMER counter register */
|
||||
__IO uint32_t COMPVAL_H; /*!< (@ 0x40064010) RITIMER compare upper register */
|
||||
__IO uint32_t MASK_H; /*!< (@ 0x40064014) RITIMER mask upper register */
|
||||
__I uint32_t RESERVED0[1];
|
||||
__IO uint32_t COUNTER_H; /*!< (@ 0x4006401C) RITIMER counter upper register */
|
||||
} LPC_RITIMER_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- USB -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
typedef struct { /*!< (@ 0x40020000) USB Structure */
|
||||
__IO uint32_t DEVCMDSTAT; /*!< (@ 0x40020000) USB Device Command/Status register */
|
||||
__IO uint32_t INFO; /*!< (@ 0x40020004) USB Info register */
|
||||
__IO uint32_t EPLISTSTART; /*!< (@ 0x40020008) USB EP Command/Status List start address */
|
||||
__IO uint32_t DATABUFSTART; /*!< (@ 0x4002000C) USB Data buffer start address */
|
||||
__IO uint32_t LPM; /*!< (@ 0x40020010) Link Power Management register */
|
||||
__IO uint32_t EPSKIP; /*!< (@ 0x40020014) USB Endpoint skip */
|
||||
__IO uint32_t EPINUSE; /*!< (@ 0x40020018) USB Endpoint Buffer in use */
|
||||
__IO uint32_t EPBUFCFG; /*!< (@ 0x4002001C) USB Endpoint Buffer Configuration register */
|
||||
__IO uint32_t INTSTAT; /*!< (@ 0x40020020) USB interrupt status register */
|
||||
__IO uint32_t INTEN; /*!< (@ 0x40020024) USB interrupt enable register */
|
||||
__IO uint32_t INTSETSTAT; /*!< (@ 0x40020028) USB set interrupt status register */
|
||||
__IO uint32_t INTROUTING; /*!< (@ 0x4002002C) USB interrupt routing register */
|
||||
__I uint32_t RESERVED0[1];
|
||||
__I uint32_t EPTOGGLE; /*!< (@ 0x40020034) USB Endpoint toggle register */
|
||||
} LPC_USB_Type;
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- GPIO_PORT -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
typedef struct { /*!< (@ 0x50000000) GPIO_PORT Structure */
|
||||
union {
|
||||
struct {
|
||||
__IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
|
||||
__IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
|
||||
};
|
||||
__IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
|
||||
};
|
||||
__I uint32_t RESERVED0[1008];
|
||||
union {
|
||||
struct {
|
||||
__IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
|
||||
__IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
|
||||
};
|
||||
__IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
|
||||
};
|
||||
__I uint32_t RESERVED1[960];
|
||||
__IO uint32_t DIR[2]; /*!< (@ 0x50002000) Direction registers port 0/1 */
|
||||
__I uint32_t RESERVED2[30];
|
||||
__IO uint32_t MASK[2]; /*!< (@ 0x50002080) Mask register port 0/1 */
|
||||
__I uint32_t RESERVED3[30];
|
||||
__IO uint32_t PIN[2]; /*!< (@ 0x50002100) Portpin register port 0 */
|
||||
__I uint32_t RESERVED4[30];
|
||||
__IO uint32_t MPIN[2]; /*!< (@ 0x50002180) Masked port register port 0/1 */
|
||||
__I uint32_t RESERVED5[30];
|
||||
__IO uint32_t SET[2]; /*!< (@ 0x50002200) Write: Set register for port 0/1 Read: output bits for port 0/1 */
|
||||
__I uint32_t RESERVED6[30];
|
||||
__O uint32_t CLR[2]; /*!< (@ 0x50002280) Clear port 0/1 */
|
||||
__I uint32_t RESERVED7[30];
|
||||
__O uint32_t NOT[2]; /*!< (@ 0x50002300) Toggle port 0/1 */
|
||||
} LPC_GPIO_Type;
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- Peripheral memory map -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
#define LPC_I2C_BASE (0x40000000)
|
||||
#define LPC_WWDT_BASE (0x40004000)
|
||||
#define LPC_USART_BASE (0x40008000)
|
||||
#define LPC_CT16B0_BASE (0x4000C000)
|
||||
#define LPC_CT16B1_BASE (0x40010000)
|
||||
#define LPC_CT32B0_BASE (0x40014000)
|
||||
#define LPC_CT32B1_BASE (0x40018000)
|
||||
#define LPC_ADC_BASE (0x4001C000)
|
||||
#define LPC_PMU_BASE (0x40038000)
|
||||
#define LPC_FLASHCTRL_BASE (0x4003C000)
|
||||
#define LPC_SSP0_BASE (0x40040000)
|
||||
#define LPC_IOCON_BASE (0x40044000)
|
||||
#define LPC_SYSCON_BASE (0x40048000)
|
||||
#define LPC_GPIO_PIN_INT_BASE (0x4004C000)
|
||||
#define LPC_SSP1_BASE (0x40058000)
|
||||
#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
|
||||
#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
|
||||
#define LPC_RITIMER_BASE (0x40064000)
|
||||
#define LPC_USB_BASE (0x40080000)
|
||||
#define LPC_GPIO_BASE (0x50000000)
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// ----- Peripheral declaration -----
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
|
||||
#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
|
||||
#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
|
||||
#define LPC_CT16B0 ((LPC_CT16B0_Type *) LPC_CT16B0_BASE)
|
||||
#define LPC_CT16B1 ((LPC_CT16B1_Type *) LPC_CT16B1_BASE)
|
||||
#define LPC_CT32B0 ((LPC_CT32B0_Type *) LPC_CT32B0_BASE)
|
||||
#define LPC_CT32B1 ((LPC_CT32B1_Type *) LPC_CT32B1_BASE)
|
||||
#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
|
||||
#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
|
||||
#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
|
||||
#define LPC_SSP0 ((LPC_SSP0_Type *) LPC_SSP0_BASE)
|
||||
#define LPC_SSP1 ((LPC_SSP1_Type *) LPC_SSP1_BASE)
|
||||
#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
|
||||
#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
|
||||
#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
|
||||
#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)
|
||||
#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)
|
||||
#define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)
|
||||
#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
|
||||
#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
|
||||
|
||||
|
||||
/** @} */ /* End of group Device_Peripheral_Registers */
|
||||
/** @} */ /* End of group (null) */
|
||||
/** @} */ /* End of group h1usf */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif // __LPC13UXX_H__
|
||||
@@ -1,88 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267 $
|
||||
* Project: NXP LPC13Uxx software example
|
||||
*
|
||||
* Description:
|
||||
* Power API Header File for NXP LPC13Uxx Device Series
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef __LPC13UXX_POWER_API_H__
|
||||
#define __LPC13UXX_POWER_API_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PWRROMD_PRESENT
|
||||
|
||||
#define USBROMD_PRESENT
|
||||
|
||||
#ifdef USBROMD_PRESENT
|
||||
#include "mw_usbd_rom_api.h"
|
||||
#endif
|
||||
|
||||
typedef struct _PWRD {
|
||||
void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
|
||||
void (*set_power)(unsigned int cmd[], unsigned int resp[]);
|
||||
} PWRD;
|
||||
|
||||
typedef struct _ROM {
|
||||
#ifdef USBROMD_PRESENT
|
||||
const USBD_API_T * pUSBD;
|
||||
#else
|
||||
const unsigned p_usbd;
|
||||
#endif /* USBROMD_PRESENT */
|
||||
const unsigned p_clib;
|
||||
const unsigned p_cand;
|
||||
#ifdef PWRROMD_PRESENT
|
||||
const PWRD * pPWRD;
|
||||
#else
|
||||
const unsigned p_pwrd;
|
||||
#endif /* PWRROMD_PRESENT */
|
||||
const unsigned p_dev1;
|
||||
const unsigned p_dev2;
|
||||
const unsigned p_dev3;
|
||||
const unsigned p_dev4;
|
||||
} ROM;
|
||||
|
||||
//PLL setup related definitions
|
||||
#define CPU_FREQ_EQU 0 //main PLL freq must be equal to the specified
|
||||
#define CPU_FREQ_LTE 1 //main PLL freq must be less than or equal the specified
|
||||
#define CPU_FREQ_GTE 2 //main PLL freq must be greater than or equal the specified
|
||||
#define CPU_FREQ_APPROX 3 //main PLL freq must be as close as possible the specified
|
||||
|
||||
#define PLL_CMD_SUCCESS 0 //PLL setup successfully found
|
||||
#define PLL_INVALID_FREQ 1 //specified freq out of range (either input or output)
|
||||
#define PLL_INVALID_MODE 2 //invalid mode (see above for valid) specified
|
||||
#define PLL_FREQ_NOT_FOUND 3 //specified freq not found under specified conditions
|
||||
#define PLL_NOT_LOCKED 4 //PLL not locked => no changes to the PLL setup
|
||||
|
||||
//power setup elated definitions
|
||||
#define PARAM_DEFAULT 0 //default power settings (voltage regulator, flash interface)
|
||||
#define PARAM_CPU_PERFORMANCE 1 //setup for maximum CPU performance (higher current, more computation)
|
||||
#define PARAM_EFFICIENCY 2 //balanced setting (power vs CPU performance)
|
||||
#define PARAM_LOW_CURRENT 3 //lowest active current, lowest CPU performance
|
||||
|
||||
#define PARAM_CMD_SUCCESS 0 //power setting successfully found
|
||||
#define PARAM_INVALID_FREQ 1 //specified freq out of range (=0 or > 50 MHz)
|
||||
#define PARAM_INVALID_MODE 2 //specified mode not valid (see above for valid)
|
||||
|
||||
#define MAX_CLOCK_KHZ_PARAM 50000
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LPC13UXX_POWER_API_H__ */
|
||||
|
||||
@@ -1,64 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_LPC13Uxx.h
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
|
||||
* for the NXP LPC13Uxx Device Series
|
||||
* @version V1.10
|
||||
* @date 24. November 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_LPC13Uxx_H
|
||||
#define __SYSTEM_LPC13Uxx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_LPC13Uxx_H */
|
||||
@@ -1,32 +0,0 @@
|
||||
<!-- liblinks.xml
|
||||
|
||||
LPCXpresso "Smart update wizard" script file
|
||||
When executed on a particular application project, will
|
||||
add appropriate links to the specified library project.
|
||||
|
||||
Note that this script assumes that the application project
|
||||
contains the standard 'Debug' and 'Release' build
|
||||
configurations.
|
||||
-->
|
||||
|
||||
<project name="" update="true">
|
||||
<setting id="all.compiler.inc">
|
||||
<value>${workspace_loc:/CMSIS_CORE_LPC13Uxx/inc}</value>
|
||||
</setting>
|
||||
<setting id="all.compiler.def">
|
||||
<value>__USE_CMSIS=CMSIS_CORE_LPC13Uxx</value>
|
||||
</setting>
|
||||
<setting id="linker.libs">
|
||||
<value>CMSIS_CORE_LPC13Uxx</value>
|
||||
</setting>
|
||||
<setting id="linker.paths" buildType="Debug">
|
||||
<value>${workspace_loc:/CMSIS_CORE_LPC13Uxx/Debug}</value>
|
||||
</setting>
|
||||
<setting id="linker.paths" buildType="Release">
|
||||
<value>${workspace_loc:/CMSIS_CORE_LPC13Uxx/Release}</value>
|
||||
</setting>
|
||||
<requires msg="Library project `CMSIS_CORE_LPC13Uxx` not found">
|
||||
<value>CMSIS_CORE_LPC13Uxx</value>
|
||||
</requires>
|
||||
</project>
|
||||
|
||||
@@ -1,437 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file system_LPC13Uxx.c
|
||||
* @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File
|
||||
* for the NXP LPC13xx Device Series
|
||||
* @version V1.10
|
||||
* @date 24. November 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include "LPC13Uxx.h"
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
/*--------------------- Clock Configuration ----------------------------------
|
||||
//
|
||||
// <e> Clock Configuration
|
||||
// <h> System Oscillator Control Register (SYSOSCCTRL)
|
||||
// <o1.0> BYPASS: System Oscillator Bypass Enable
|
||||
// <i> If enabled then PLL input (sys_osc_clk) is fed
|
||||
// <i> directly from XTALIN and XTALOUT pins.
|
||||
// <o1.9> FREQRANGE: System Oscillator Frequency Range
|
||||
// <i> Determines frequency range for Low-power oscillator.
|
||||
// <0=> 1 - 20 MHz
|
||||
// <1=> 15 - 25 MHz
|
||||
// </h>
|
||||
//
|
||||
// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
|
||||
// <o2.0..4> DIVSEL: Select Divider for Fclkana
|
||||
// <i> wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
|
||||
// <0-31>
|
||||
// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
|
||||
// <0=> Undefined
|
||||
// <1=> 0.5 MHz
|
||||
// <2=> 0.8 MHz
|
||||
// <3=> 1.1 MHz
|
||||
// <4=> 1.4 MHz
|
||||
// <5=> 1.6 MHz
|
||||
// <6=> 1.8 MHz
|
||||
// <7=> 2.0 MHz
|
||||
// <8=> 2.2 MHz
|
||||
// <9=> 2.4 MHz
|
||||
// <10=> 2.6 MHz
|
||||
// <11=> 2.7 MHz
|
||||
// <12=> 2.9 MHz
|
||||
// <13=> 3.1 MHz
|
||||
// <14=> 3.2 MHz
|
||||
// <15=> 3.4 MHz
|
||||
// </h>
|
||||
//
|
||||
// <h> System PLL Control Register (SYSPLLCTRL)
|
||||
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
|
||||
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
|
||||
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
|
||||
// <o3.0..4> MSEL: Feedback Divider Selection
|
||||
// <i> M = MSEL + 1
|
||||
// <0-31>
|
||||
// <o3.5..6> PSEL: Post Divider Selection
|
||||
// <0=> P = 1
|
||||
// <1=> P = 2
|
||||
// <2=> P = 4
|
||||
// <3=> P = 8
|
||||
// </h>
|
||||
//
|
||||
// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
|
||||
// <o4.0..1> SEL: System PLL Clock Source
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> Main Clock Source Select Register (MAINCLKSEL)
|
||||
// <o5.0..1> SEL: Clock Source for Main Clock
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> Input Clock to System PLL
|
||||
// <2=> WDT Oscillator
|
||||
// <3=> System PLL Clock Out
|
||||
// </h>
|
||||
//
|
||||
// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
|
||||
// <o6.0..7> DIV: System AHB Clock Divider
|
||||
// <i> Divides main clock to provide system clock to core, memories, and peripherals.
|
||||
// <i> 0 = is disabled
|
||||
// <0-255>
|
||||
// </h>
|
||||
//
|
||||
// <h> USB PLL Control Register (USBPLLCTRL)
|
||||
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
|
||||
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
|
||||
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
|
||||
// <o7.0..4> MSEL: Feedback Divider Selection
|
||||
// <i> M = MSEL + 1
|
||||
// <0-31>
|
||||
// <o7.5..6> PSEL: Post Divider Selection
|
||||
// <0=> P = 1
|
||||
// <1=> P = 2
|
||||
// <2=> P = 4
|
||||
// <3=> P = 8
|
||||
// </h>
|
||||
//
|
||||
// <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
|
||||
// <o8.0..1> SEL: USB PLL Clock Source
|
||||
// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> USB Clock Source Select Register (USBCLKSEL)
|
||||
// <o9.0..1> SEL: System PLL Clock Source
|
||||
// <0=> USB PLL out
|
||||
// <1=> Main clock
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> USB Clock Divider Register (USBCLKDIV)
|
||||
// <o10.0..7> DIV: USB Clock Divider
|
||||
// <i> Divides USB clock to 48 MHz.
|
||||
// <i> 0 = is disabled
|
||||
// <0-255>
|
||||
// </h>
|
||||
// </e>
|
||||
*/
|
||||
#define CLOCK_SETUP 1
|
||||
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define SYSPLLCTRL_Val 0x00000025 // Reset: 0x000
|
||||
#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
|
||||
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
|
||||
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
|
||||
#define USBPLLCTRL_Val 0x00000023 // Reset: 0x000
|
||||
#define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000
|
||||
#define USBCLKSEL_Val 0x00000000 // Reset: 0x000
|
||||
#define USBCLKDIV_Val 0x00000001 // Reset: 0x001
|
||||
|
||||
/*
|
||||
//-------- <<< end of configuration section >>> ------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Check the register settings
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
||||
#define CHECK_RSVD(val, mask) (val & mask)
|
||||
|
||||
/* Clock Configuration -------------------------------------------------------*/
|
||||
#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
|
||||
#error "SYSOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
|
||||
#error "WDTOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
|
||||
#error "SYSPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
|
||||
#error "SYSPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
|
||||
#error "MAINCLKSEL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
|
||||
#error "SYSAHBCLKDIV: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
|
||||
#error "USBPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
|
||||
#error "USBPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
|
||||
#error "USBCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
|
||||
#error "USBCLKDIV: Value out of range!"
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __XTAL (12000000UL) /* Oscillator frequency */
|
||||
#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
|
||||
#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
|
||||
|
||||
|
||||
#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
|
||||
#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
#if (__FREQSEL == 0)
|
||||
#define __WDT_OSC_CLK ( 0) /* undefined */
|
||||
#elif (__FREQSEL == 1)
|
||||
#define __WDT_OSC_CLK ( 500000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 2)
|
||||
#define __WDT_OSC_CLK ( 800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 3)
|
||||
#define __WDT_OSC_CLK (1100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 4)
|
||||
#define __WDT_OSC_CLK (1400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 5)
|
||||
#define __WDT_OSC_CLK (1600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 6)
|
||||
#define __WDT_OSC_CLK (1800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 7)
|
||||
#define __WDT_OSC_CLK (2000000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 8)
|
||||
#define __WDT_OSC_CLK (2200000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 9)
|
||||
#define __WDT_OSC_CLK (2400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 10)
|
||||
#define __WDT_OSC_CLK (2600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 11)
|
||||
#define __WDT_OSC_CLK (2700000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 12)
|
||||
#define __WDT_OSC_CLK (2900000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 13)
|
||||
#define __WDT_OSC_CLK (3100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 14)
|
||||
#define __WDT_OSC_CLK (3200000 / __DIVSEL)
|
||||
#else
|
||||
#define __WDT_OSC_CLK (3400000 / __DIVSEL)
|
||||
#endif
|
||||
|
||||
/* sys_pllclkin calculation */
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
|
||||
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
|
||||
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
|
||||
#else
|
||||
#define __SYS_PLLCLKIN (0)
|
||||
#endif
|
||||
|
||||
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
|
||||
|
||||
/* main clock calculation */
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 0)
|
||||
#define __MAIN_CLOCK (__IRC_OSC_CLK)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 1)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKIN)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 2)
|
||||
#if (__FREQSEL == 0)
|
||||
#error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
|
||||
#else
|
||||
#define __MAIN_CLOCK (__WDT_OSC_CLK)
|
||||
#endif
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 3)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
|
||||
#else
|
||||
#define __MAIN_CLOCK (0)
|
||||
#endif
|
||||
|
||||
#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
|
||||
|
||||
#else
|
||||
#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
|
||||
#endif // CLOCK_SETUP
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
uint32_t wdt_osc = 0;
|
||||
|
||||
/* Determine clock frequency according to clock register values */
|
||||
switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
|
||||
case 0: wdt_osc = 0; break;
|
||||
case 1: wdt_osc = 500000; break;
|
||||
case 2: wdt_osc = 800000; break;
|
||||
case 3: wdt_osc = 1100000; break;
|
||||
case 4: wdt_osc = 1400000; break;
|
||||
case 5: wdt_osc = 1600000; break;
|
||||
case 6: wdt_osc = 1800000; break;
|
||||
case 7: wdt_osc = 2000000; break;
|
||||
case 8: wdt_osc = 2200000; break;
|
||||
case 9: wdt_osc = 2400000; break;
|
||||
case 10: wdt_osc = 2600000; break;
|
||||
case 11: wdt_osc = 2700000; break;
|
||||
case 12: wdt_osc = 2900000; break;
|
||||
case 13: wdt_osc = 3100000; break;
|
||||
case 14: wdt_osc = 3200000; break;
|
||||
case 15: wdt_osc = 3400000; break;
|
||||
}
|
||||
wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
|
||||
|
||||
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* Input Clock to System PLL */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 2: /* WDT Oscillator */
|
||||
SystemCoreClock = wdt_osc;
|
||||
break;
|
||||
case 3: /* System PLL Clock Out */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
} else {
|
||||
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
} else {
|
||||
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void) {
|
||||
volatile uint32_t i;
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
|
||||
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
|
||||
for (i = 0; i < 200; i++) __NOP();
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
|
||||
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
|
||||
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
#endif
|
||||
|
||||
#if (((MAINCLKSEL_Val & 0x03) == 2) )
|
||||
LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
|
||||
for (i = 0; i < 200; i++) __NOP();
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
|
||||
|
||||
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
|
||||
|
||||
#if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
|
||||
|
||||
/* Regardless USB PLL is used as USB clock or not, USB PLL needs to be configured. */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
|
||||
LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
|
||||
LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
|
||||
while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
|
||||
LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
|
||||
LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
|
||||
|
||||
#else /* USB clock is not used */
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* System clock to the IOCON needs to be enabled or
|
||||
most of the I/O related peripherals won't work. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
|
||||
|
||||
}
|
||||
@@ -1,44 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: clkconfig.h 6172 2011-01-13 18:22:51Z usb00423 $
|
||||
* Project: NXP LPC13Uxx software example
|
||||
*
|
||||
* Description:
|
||||
* This file contains definition and prototype for clock configuration.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef __CLKCONFIG_H
|
||||
#define __CLKCONFIG_H
|
||||
|
||||
#define SYSPLL_SRC_IRC_OSC 0
|
||||
#define SYSPLL_SRC_SYS_OSC 1
|
||||
|
||||
#define MAINCLK_SRC_IRC_OSC 0
|
||||
#define MAINCLK_SRC_SYSPLL_IN 1
|
||||
#define MAINCLK_SRC_WDT_OSC 2
|
||||
#define MAINCLK_SRC_SYS_PLL 3
|
||||
|
||||
#define WDTCLK_SRC_IRC_OSC 0
|
||||
#define WDTCLK_SRC_WDT_OSC 1
|
||||
|
||||
#define CLKOUTCLK_SRC_IRC_OSC 0
|
||||
#define CLKOUTCLK_SRC_SYS_OSC 1
|
||||
#define CLKOUTCLK_SRC_WDT_OSC 2
|
||||
#define CLKOUTCLK_SRC_MAIN_CLK 3
|
||||
|
||||
void WDT_CLK_Setup(uint32_t timer_num);
|
||||
void CLKOUT_Setup(uint32_t timer_num);
|
||||
#endif /* end __CLKCONFIG_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@@ -1,64 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: gpio.h 6172 2011-01-13 18:22:51Z usb00423 $
|
||||
* Project: NXP LPC13Uxx software example
|
||||
*
|
||||
* Description:
|
||||
* This file contains definition and prototype for GPIO.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef __GPIO_H
|
||||
#define __GPIO_H
|
||||
|
||||
#define CHANNEL0 0
|
||||
#define CHANNEL1 1
|
||||
#define CHANNEL2 2
|
||||
#define CHANNEL3 3
|
||||
#define CHANNEL4 4
|
||||
#define CHANNEL5 5
|
||||
#define CHANNEL6 6
|
||||
#define CHANNEL7 7
|
||||
|
||||
#define PORT0 0
|
||||
#define PORT1 1
|
||||
|
||||
#define GROUP0 0
|
||||
#define GROUP1 1
|
||||
|
||||
void PIN_INT0_IRQHandler(void);
|
||||
void PIN_INT1_IRQHandler(void);
|
||||
void PIN_INT2_IRQHandler(void);
|
||||
void PIN_INT3_IRQHandler(void);
|
||||
void PIN_INT4_IRQHandler(void);
|
||||
void PIN_INT5_IRQHandler(void);
|
||||
void PIN_INT6_IRQHandler(void);
|
||||
void PIN_INT7_IRQHandler(void);
|
||||
void GINT0_IRQHandler(void);
|
||||
void GINT1_IRQHandler(void);
|
||||
void GPIOInit( void );
|
||||
void GPIOSetPinInterrupt( uint32_t channelNum, uint32_t portNum, uint32_t bitPosi,
|
||||
uint32_t sense, uint32_t event );
|
||||
void GPIOPinIntEnable( uint32_t channelNum, uint32_t event );
|
||||
void GPIOPinIntDisable( uint32_t channelNum, uint32_t event );
|
||||
uint32_t GPIOPinIntStatus( uint32_t channelNum );
|
||||
void GPIOPinIntClear( uint32_t channelNum );
|
||||
void GPIOSetGroupedInterrupt( uint32_t groupNum, uint32_t *bitPattern, uint32_t logic,
|
||||
uint32_t sense, uint32_t *eventPattern );
|
||||
uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi );
|
||||
void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal );
|
||||
void GPIOSetDir( uint32_t portNum, uint32_t bitPosi, uint32_t dir );
|
||||
|
||||
#endif /* end __GPIO_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@@ -1,32 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: nmi.h 6172 2011-01-13 18:22:51Z usb00423 $
|
||||
* Project: NXP LPC13Uxx NMI software example
|
||||
*
|
||||
* Description:
|
||||
* This file contains definition and prototype for NMI interrupt.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef __NMI_H
|
||||
#define __NMI_H
|
||||
|
||||
#define NMI_ENABLED 1
|
||||
|
||||
#define MAX_NMI_NUM 32
|
||||
|
||||
void NMI_Init( uint32_t NMI_num );
|
||||
void NMI_Handler(void);
|
||||
#endif /* end __NMI_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@@ -1,88 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267 $
|
||||
* Project: NXP LPC13Uxx software example
|
||||
*
|
||||
* Description:
|
||||
* Power API Header File for NXP LPC13Uxx Device Series
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef __LPC13UXX_POWER_API_H__
|
||||
#define __LPC13UXX_POWER_API_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PWRROMD_PRESENT
|
||||
|
||||
#define USBROMD_PRESENT
|
||||
|
||||
#ifdef USBROMD_PRESENT
|
||||
#include "mw_usbd_rom_api.h"
|
||||
#endif
|
||||
|
||||
typedef struct _PWRD {
|
||||
void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
|
||||
void (*set_power)(unsigned int cmd[], unsigned int resp[]);
|
||||
} PWRD;
|
||||
|
||||
typedef struct _ROM {
|
||||
#ifdef USBROMD_PRESENT
|
||||
const USBD_API_T * pUSBD;
|
||||
#else
|
||||
const unsigned p_usbd;
|
||||
#endif /* USBROMD_PRESENT */
|
||||
const unsigned p_clib;
|
||||
const unsigned p_cand;
|
||||
#ifdef PWRROMD_PRESENT
|
||||
const PWRD * pPWRD;
|
||||
#else
|
||||
const unsigned p_pwrd;
|
||||
#endif /* PWRROMD_PRESENT */
|
||||
const unsigned p_dev1;
|
||||
const unsigned p_dev2;
|
||||
const unsigned p_dev3;
|
||||
const unsigned p_dev4;
|
||||
} ROM;
|
||||
|
||||
//PLL setup related definitions
|
||||
#define CPU_FREQ_EQU 0 //main PLL freq must be equal to the specified
|
||||
#define CPU_FREQ_LTE 1 //main PLL freq must be less than or equal the specified
|
||||
#define CPU_FREQ_GTE 2 //main PLL freq must be greater than or equal the specified
|
||||
#define CPU_FREQ_APPROX 3 //main PLL freq must be as close as possible the specified
|
||||
|
||||
#define PLL_CMD_SUCCESS 0 //PLL setup successfully found
|
||||
#define PLL_INVALID_FREQ 1 //specified freq out of range (either input or output)
|
||||
#define PLL_INVALID_MODE 2 //invalid mode (see above for valid) specified
|
||||
#define PLL_FREQ_NOT_FOUND 3 //specified freq not found under specified conditions
|
||||
#define PLL_NOT_LOCKED 4 //PLL not locked => no changes to the PLL setup
|
||||
|
||||
//power setup elated definitions
|
||||
#define PARAM_DEFAULT 0 //default power settings (voltage regulator, flash interface)
|
||||
#define PARAM_CPU_PERFORMANCE 1 //setup for maximum CPU performance (higher current, more computation)
|
||||
#define PARAM_EFFICIENCY 2 //balanced setting (power vs CPU performance)
|
||||
#define PARAM_LOW_CURRENT 3 //lowest active current, lowest CPU performance
|
||||
|
||||
#define PARAM_CMD_SUCCESS 0 //power setting successfully found
|
||||
#define PARAM_INVALID_FREQ 1 //specified freq out of range (=0 or > 50 MHz)
|
||||
#define PARAM_INVALID_MODE 2 //specified mode not valid (see above for valid)
|
||||
|
||||
#define MAX_CLOCK_KHZ_PARAM 50000
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LPC13UXX_POWER_API_H__ */
|
||||
|
||||
@@ -1,59 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: timer16.h 6956 2011-03-23 23:03:25Z usb00423 $
|
||||
* Project: NXP LPC13Uxx software example
|
||||
*
|
||||
* Description:
|
||||
* This file contains definition and prototype for 16-bit timer
|
||||
* configuration.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef __TIMER16_H
|
||||
#define __TIMER16_H
|
||||
|
||||
/* The test is either MAT_OUT or CAP_IN. Default is MAT_OUT. */
|
||||
#define TIMER_MATCH 0
|
||||
|
||||
|
||||
#define EMC0 4
|
||||
#define EMC1 6
|
||||
#define EMC2 8
|
||||
#define EMC3 10
|
||||
|
||||
#define MATCH0 (1<<0)
|
||||
#define MATCH1 (1<<1)
|
||||
#define MATCH2 (1<<2)
|
||||
#define MATCH3 (1<<3)
|
||||
|
||||
///* For 16-bit timer, make sure that TIME_INTERVAL should be no
|
||||
//greater than 0xFFFF. */
|
||||
#ifndef TIME_INTERVAL
|
||||
#define TIME_INTERVAL (SystemCoreClock/1000 - 1)
|
||||
#endif
|
||||
|
||||
void delayMs(uint8_t timer_num, uint32_t delayInMs);
|
||||
void CT16B0_IRQHandler(void);
|
||||
void CT16B1_IRQHandler(void);
|
||||
void enable_timer16(uint8_t timer_num);
|
||||
void disable_timer16(uint8_t timer_num);
|
||||
void reset_timer16(uint8_t timer_num);
|
||||
void set_timer16_capture(uint8_t timer_num, uint8_t location );
|
||||
void set_timer16_match(uint8_t timer_num, uint8_t match_enable, uint8_t location);
|
||||
void init_timer16(uint8_t timer_num, uint32_t timerInterval);
|
||||
void init_timer16PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable, uint8_t cap_enabled);
|
||||
void setMatch_timer16PWM (uint8_t timer_num, uint8_t match_nr, uint32_t value);
|
||||
|
||||
#endif /* end __TIMER16_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@@ -1,58 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: timer32.h 7146 2011-04-19 19:48:01Z nxp28548 $
|
||||
* Project: NXP LPC13Uxx software example
|
||||
*
|
||||
* Description:
|
||||
* This file contains definition and prototype for 32-bit timer
|
||||
* configuration.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef __TIMER32_H
|
||||
#define __TIMER32_H
|
||||
|
||||
/* The test is either MAT_OUT or CAP_IN. Default is CAP_IN. */
|
||||
#ifndef TIMER_MATCH
|
||||
#define TIMER_MATCH 0
|
||||
#endif//TIMER_MATCH
|
||||
|
||||
#define EMC0 4
|
||||
#define EMC1 6
|
||||
#define EMC2 8
|
||||
#define EMC3 10
|
||||
|
||||
#define MATCH0 (1<<0)
|
||||
#define MATCH1 (1<<1)
|
||||
#define MATCH2 (1<<2)
|
||||
#define MATCH3 (1<<3)
|
||||
|
||||
#ifndef TIME_INTERVAL
|
||||
#define TIME_INTERVAL (SystemCoreClock/100 - 1)
|
||||
#endif
|
||||
|
||||
void delay32Ms(uint8_t timer_num, uint32_t delayInMs);
|
||||
void CT32B0_IRQHandler(void);
|
||||
void CT32B1_IRQHandler(void);
|
||||
void enable_timer32(uint8_t timer_num);
|
||||
void disable_timer32(uint8_t timer_num);
|
||||
void reset_timer32(uint8_t timer_num);
|
||||
void set_timer32_capture(uint8_t timer_num, uint8_t location );
|
||||
void set_timer32_match(uint8_t timer_num, uint8_t match_enable, uint8_t location);
|
||||
void init_timer32(uint8_t timer_num, uint32_t timerInterval);
|
||||
void init_timer32PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable);
|
||||
void setMatch_timer32PWM (uint8_t timer_num, uint8_t match_nr, uint32_t value);
|
||||
|
||||
#endif /* end __TIMER32_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@@ -1,52 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: type.h 6172 2011-01-13 18:22:51Z usb00423 $
|
||||
* Project: NXP LPC13Uxx software example
|
||||
*
|
||||
* Description:
|
||||
* This file contains different type definition.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef __TYPE_H__
|
||||
#define __TYPE_H__
|
||||
|
||||
#if defined (__GNUC__)
|
||||
#include <stdint.h>
|
||||
|
||||
#else
|
||||
/* exact-width signed integer types */
|
||||
typedef signed char int8_t;
|
||||
typedef signed short int int16_t;
|
||||
typedef signed int int32_t;
|
||||
//typedef signed __int64 int64_t;
|
||||
|
||||
/* exact-width unsigned integer types */
|
||||
typedef unsigned char uint8_t;
|
||||
typedef unsigned short int uint16_t;
|
||||
typedef unsigned int uint32_t;
|
||||
//typedef unsigned __int64 uint64_t;
|
||||
#endif
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL ((void *)0)
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE (0)
|
||||
#endif
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE (1)
|
||||
#endif
|
||||
|
||||
#endif /* __TYPE_H__ */
|
||||
@@ -1,72 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: uart.h 6172 2011-01-13 18:22:51Z usb00423 $
|
||||
* Project: NXP LPC13Uxx software example
|
||||
*
|
||||
* Description:
|
||||
* This file contains definition and prototype for UART configuration.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef __UART_H
|
||||
#define __UART_H
|
||||
|
||||
#define AUTOBAUD_ENABLE 0
|
||||
#define FDR_CALIBRATION 0
|
||||
#define RS485_ENABLED 0
|
||||
#define TX_INTERRUPT 0 /* 0 if TX uses polling, 1 interrupt driven. */
|
||||
#define MODEM_TEST 0
|
||||
|
||||
#define IER_RBR (0x01<<0)
|
||||
#define IER_THRE (0x01<<1)
|
||||
#define IER_RLS (0x01<<2)
|
||||
#define IER_ABEO (0x01<<8)
|
||||
#define IER_ABTO (0x01<<9)
|
||||
|
||||
#define IIR_PEND 0x01
|
||||
#define IIR_RLS 0x03
|
||||
#define IIR_RDA 0x02
|
||||
#define IIR_CTI 0x06
|
||||
#define IIR_THRE 0x01
|
||||
#define IIR_ABEO (0x01<<8)
|
||||
#define IIR_ABTO (0x01<<9)
|
||||
|
||||
#define LSR_RDR (0x01<<0)
|
||||
#define LSR_OE (0x01<<1)
|
||||
#define LSR_PE (0x01<<2)
|
||||
#define LSR_FE (0x01<<3)
|
||||
#define LSR_BI (0x01<<4)
|
||||
#define LSR_THRE (0x01<<5)
|
||||
#define LSR_TEMT (0x01<<6)
|
||||
#define LSR_RXFE (0x01<<7)
|
||||
|
||||
#define BUFSIZE 0x40
|
||||
|
||||
/* RS485 mode definition. */
|
||||
#define RS485_NMMEN (0x1<<0)
|
||||
#define RS485_RXDIS (0x1<<1)
|
||||
#define RS485_AADEN (0x1<<2)
|
||||
#define RS485_SEL (0x1<<3)
|
||||
#define RS485_DCTRL (0x1<<4)
|
||||
#define RS485_OINV (0x1<<5)
|
||||
|
||||
void ModemInit( void );
|
||||
void UARTInit(uint32_t Baudrate);
|
||||
void USART_IRQHandler(void);
|
||||
void UARTSend(uint8_t *BufferPtr, uint32_t Length);
|
||||
void print_string( uint8_t *str_ptr );
|
||||
uint8_t get_key( void );
|
||||
|
||||
#endif /* end __UART_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@@ -1,44 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: usart.h 6172 2011-01-13 18:22:51Z usb00423 $
|
||||
* Project: NXP LPC13Uxx software example
|
||||
*
|
||||
* Description:
|
||||
* This file contains definition and prototype for UART configuration.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef __USART_H
|
||||
#define __USART_H
|
||||
|
||||
/* Synchronous mode control register definition. */
|
||||
#define SYNC_ON (0x1<<0)
|
||||
#define SYNC_OFF (0x0<<0)
|
||||
|
||||
#define SYNC_MASTER (0x1<<1)
|
||||
#define SYNC_SLAVE (0x0<<1)
|
||||
|
||||
#define SYNC_RE (0x0<<2)
|
||||
#define SYNC_FE (0x1<<2)
|
||||
|
||||
#define SYNC_CONT_CLK_EN (0x1<<4)
|
||||
#define SYNC_CONT_CLK_DIS (0x0<<4)
|
||||
|
||||
#define SYNC_STARTSTOPOFF (0x1<<5)
|
||||
#define SYNC_STARTSTOPON (0x0<<5)
|
||||
|
||||
#define SYNC_CON_CLK_CLR (0x1<<6)
|
||||
|
||||
#endif /* end __USART_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@@ -1,33 +0,0 @@
|
||||
/******************************************************************************/
|
||||
/* SERIAL.C: Low Level Serial Routines */
|
||||
/******************************************************************************/
|
||||
/* This file is part of the uVision/ARM development tools. */
|
||||
/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
|
||||
/* This software may only be used under the terms of a valid, current, */
|
||||
/* end user licence from KEIL for a compatible version of KEIL software */
|
||||
/* development tools. Nothing else gives you the right to use this software. */
|
||||
/******************************************************************************/
|
||||
|
||||
#include "LPC13Uxx.h" /* LPC13Uxx definitions */
|
||||
#include "uart.h"
|
||||
|
||||
#define CR 0x0D
|
||||
|
||||
/* implementation of putchar (also used by printf function to output data) */
|
||||
int sendchar (int ch) { /* Write character to Serial Port */
|
||||
|
||||
|
||||
if (ch == '\n') {
|
||||
while (!(LPC_USART->LSR & 0x20));
|
||||
LPC_USART->THR = CR; /* output CR */
|
||||
}
|
||||
while (!(LPC_USART->LSR & 0x20));
|
||||
return (LPC_USART->THR = ch);
|
||||
}
|
||||
|
||||
|
||||
int getkey (void) { /* Read character from Serial Port */
|
||||
|
||||
while (!(LPC_USART->LSR & 0x01));
|
||||
return (LPC_USART->RBR);
|
||||
}
|
||||
@@ -1,69 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: clkconfig.c 6874 2011-03-22 01:58:31Z usb00423 $
|
||||
* Project: NXP LPC13Uxx Clock Configuration example
|
||||
*
|
||||
* Description:
|
||||
* This file contains clock configuration code example which include
|
||||
* watchdog setup and debug clock out setup.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
****************************************************************************/
|
||||
#include "LPC13Uxx.h"
|
||||
#include "clkconfig.h"
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: WDT_CLK_Setup
|
||||
**
|
||||
** Descriptions: Configure WDT clock.
|
||||
** parameters: clock source: irc_osc(0), main_clk(1), wdt_osc(2).
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void WDT_CLK_Setup ( uint32_t clksrc )
|
||||
{
|
||||
/* Freq = 0.5Mhz, div_sel is 0x1F, divided by 64. WDT_OSC should be 7.8125khz */
|
||||
LPC_SYSCON->WDTOSCCTRL = (0x1<<5)|0x1F;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(0x1<<6); /* Let WDT clock run */
|
||||
|
||||
/* Enables clock for WDT */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<15);
|
||||
LPC_WWDT->CLKSEL = clksrc; /* Select clock source */
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: CLKOUT_Setup
|
||||
**
|
||||
** Descriptions: Configure CLKOUT for reference clock check.
|
||||
** parameters: clock source: irc_osc(0), sys_osc(1), wdt_osc(2),
|
||||
** main_clk(3).
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void CLKOUT_Setup ( uint32_t clksrc )
|
||||
{
|
||||
/* debug PLL after configuration. */
|
||||
LPC_SYSCON->CLKOUTSEL = clksrc; /* Select Main clock */
|
||||
LPC_SYSCON->CLKOUTDIV = 1; /* Divided by 1 */
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -1,838 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: gpio.c 6874 2011-03-22 01:58:31Z usb00423 $
|
||||
* Project: NXP LPC13Uxx GPIO example
|
||||
*
|
||||
* Description:
|
||||
* This file contains GPIO code example which include GPIO
|
||||
* initialization, GPIO interrupt handler, and related APIs for
|
||||
* GPIO access.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
****************************************************************************/
|
||||
#include "LPC13Uxx.h" /* LPC13Uxx Peripheral Registers */
|
||||
#include "gpio.h"
|
||||
|
||||
volatile uint32_t pin_int0_counter = 0;
|
||||
volatile uint32_t pin_int1_counter = 0;
|
||||
volatile uint32_t pin_int2_counter = 0;
|
||||
volatile uint32_t pin_int3_counter = 0;
|
||||
volatile uint32_t pin_int4_counter = 0;
|
||||
volatile uint32_t pin_int5_counter = 0;
|
||||
volatile uint32_t pin_int6_counter = 0;
|
||||
volatile uint32_t pin_int7_counter = 0;
|
||||
volatile uint32_t gint0_counter = 0;
|
||||
volatile uint32_t gint1_counter = 0;
|
||||
volatile uint32_t pin_int0_level_counter = 0;
|
||||
volatile uint32_t pin_int0_rising_edge_counter = 0;
|
||||
volatile uint32_t pin_int0_falling_edge_counter = 0;
|
||||
volatile uint32_t pin_int1_level_counter = 0;
|
||||
volatile uint32_t pin_int1_rising_edge_counter = 0;
|
||||
volatile uint32_t pin_int1_falling_edge_counter = 0;
|
||||
volatile uint32_t pin_int2_level_counter = 0;
|
||||
volatile uint32_t pin_int2_rising_edge_counter = 0;
|
||||
volatile uint32_t pin_int2_falling_edge_counter = 0;
|
||||
volatile uint32_t pin_int3_level_counter = 0;
|
||||
volatile uint32_t pin_int3_rising_edge_counter = 0;
|
||||
volatile uint32_t pin_int3_falling_edge_counter = 0;
|
||||
volatile uint32_t pin_int4_level_counter = 0;
|
||||
volatile uint32_t pin_int4_rising_edge_counter = 0;
|
||||
volatile uint32_t pin_int4_falling_edge_counter = 0;
|
||||
volatile uint32_t pin_int5_level_counter = 0;
|
||||
volatile uint32_t pin_int5_rising_edge_counter = 0;
|
||||
volatile uint32_t pin_int5_falling_edge_counter = 0;
|
||||
volatile uint32_t pin_int6_level_counter = 0;
|
||||
volatile uint32_t pin_int6_rising_edge_counter = 0;
|
||||
volatile uint32_t pin_int6_falling_edge_counter = 0;
|
||||
volatile uint32_t pin_int7_level_counter = 0;
|
||||
volatile uint32_t pin_int7_rising_edge_counter = 0;
|
||||
volatile uint32_t pin_int7_falling_edge_counter = 0;
|
||||
volatile uint32_t gint0_level_counter = 0;
|
||||
volatile uint32_t gint0_edge_counter = 0;
|
||||
volatile uint32_t gint1_level_counter = 0;
|
||||
volatile uint32_t gint1_edge_counter = 0;
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: PIN_INT0_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void PIN_INT0_IRQHandler(void)
|
||||
{
|
||||
pin_int0_counter++;
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<0) )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<0) )
|
||||
{
|
||||
pin_int0_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<0) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<0) ) )
|
||||
{
|
||||
pin_int0_rising_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->RISE = 0x1<<0;
|
||||
}
|
||||
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<0) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<0) ) )
|
||||
{
|
||||
pin_int0_falling_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->FALL = 0x1<<0;
|
||||
}
|
||||
LPC_GPIO_PIN_INT->IST = 0x1<<0;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: PIN_INT1_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void PIN_INT1_IRQHandler(void)
|
||||
{
|
||||
pin_int1_counter++;
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<1) )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<1) )
|
||||
{
|
||||
pin_int1_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<1) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<1) ) )
|
||||
{
|
||||
pin_int1_rising_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->RISE = 0x1<<1;
|
||||
}
|
||||
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<1) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<1) ) )
|
||||
{
|
||||
pin_int1_falling_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->FALL = 0x1<<1;
|
||||
}
|
||||
LPC_GPIO_PIN_INT->IST = 0x1<<1;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: PIN_INT2_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void PIN_INT2_IRQHandler(void)
|
||||
{
|
||||
pin_int2_counter++;
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<2) )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<2) )
|
||||
{
|
||||
pin_int2_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<2) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<2) ) )
|
||||
{
|
||||
pin_int2_rising_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->RISE = 0x1<<2;
|
||||
}
|
||||
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<2) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<2) ) )
|
||||
{
|
||||
pin_int2_falling_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->FALL = 0x1<<2;
|
||||
}
|
||||
LPC_GPIO_PIN_INT->IST = 0x1<<2;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: PIN_INT3_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void PIN_INT3_IRQHandler(void)
|
||||
{
|
||||
pin_int3_counter++;
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<3) )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<3) )
|
||||
{
|
||||
pin_int3_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<3) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<3) ) )
|
||||
{
|
||||
pin_int3_rising_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->RISE = 0x1<<3;
|
||||
}
|
||||
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<3) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<3) ) )
|
||||
{
|
||||
pin_int3_falling_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->FALL = 0x1<<3;
|
||||
}
|
||||
LPC_GPIO_PIN_INT->IST = 0x1<<3;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: PIN_INT4_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void PIN_INT4_IRQHandler(void)
|
||||
{
|
||||
pin_int4_counter++;
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<4) )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<4) )
|
||||
{
|
||||
pin_int4_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<4) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<4) ) )
|
||||
{
|
||||
pin_int4_rising_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->RISE = 0x1<<4;
|
||||
}
|
||||
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<4) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<4) ) )
|
||||
{
|
||||
pin_int4_falling_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->FALL = 0x1<<4;
|
||||
}
|
||||
LPC_GPIO_PIN_INT->IST = 0x1<<4;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: PIN_INT5_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void PIN_INT5_IRQHandler(void)
|
||||
{
|
||||
pin_int5_counter++;
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<5) )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<5) )
|
||||
{
|
||||
pin_int5_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<5) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<5) ) )
|
||||
{
|
||||
pin_int5_rising_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->RISE = 0x1<<5;
|
||||
}
|
||||
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<5) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<5) ) )
|
||||
{
|
||||
pin_int5_falling_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->FALL = 0x1<<5;
|
||||
}
|
||||
LPC_GPIO_PIN_INT->IST = 0x1<<5;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: PIN_INT6_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void PIN_INT6_IRQHandler(void)
|
||||
{
|
||||
pin_int6_counter++;
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<6) )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<6) )
|
||||
{
|
||||
pin_int6_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<6) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<6) ) )
|
||||
{
|
||||
pin_int6_rising_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->RISE = 0x1<<6;
|
||||
}
|
||||
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<6) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<6) ) )
|
||||
{
|
||||
pin_int6_falling_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->FALL = 0x1<<6;
|
||||
}
|
||||
LPC_GPIO_PIN_INT->IST = 0x1<<6;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: PIN_INT7_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void PIN_INT7_IRQHandler(void)
|
||||
{
|
||||
pin_int7_counter++;
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<7) )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<7) )
|
||||
{
|
||||
pin_int7_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<7) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<7) ) )
|
||||
{
|
||||
pin_int7_rising_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->RISE = 0x1<<7;
|
||||
}
|
||||
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<7) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<7) ) )
|
||||
{
|
||||
pin_int7_falling_edge_counter++;
|
||||
LPC_GPIO_PIN_INT->FALL = 0x1<<7;
|
||||
}
|
||||
LPC_GPIO_PIN_INT->IST = 0x1<<7;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GINT0_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GINT0_IRQHandler(void)
|
||||
{
|
||||
gint0_counter++;
|
||||
if ( LPC_GPIO_GROUP_INT0->CTRL & (0x1<<0) )
|
||||
{
|
||||
if ( LPC_GPIO_GROUP_INT0->CTRL & (0x1<<2) )
|
||||
{
|
||||
gint0_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
gint0_edge_counter++;
|
||||
}
|
||||
LPC_GPIO_GROUP_INT0->CTRL |= (0x1<<0);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GINT1_IRQHandler
|
||||
**
|
||||
** Descriptions: Use one GPIO pin as interrupt source
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GINT1_IRQHandler(void)
|
||||
{
|
||||
gint1_counter++;
|
||||
if ( LPC_GPIO_GROUP_INT1->CTRL & (0x1<<0) )
|
||||
{
|
||||
if ( LPC_GPIO_GROUP_INT1->CTRL & (0x1<<2) )
|
||||
{
|
||||
gint1_level_counter++;
|
||||
}
|
||||
else
|
||||
{
|
||||
gint1_edge_counter++;
|
||||
}
|
||||
LPC_GPIO_GROUP_INT1->CTRL |= (0x1<<0);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOInit
|
||||
**
|
||||
** Descriptions: Initialize GPIO, install the
|
||||
** GPIO interrupt handler
|
||||
**
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: true or false, return false if the VIC table
|
||||
** is full and GPIO interrupt handler can be
|
||||
** installed.
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GPIOInit( void )
|
||||
{
|
||||
/* Enable AHB clock to the GPIO domain. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
|
||||
|
||||
/* Enable AHB clock to the PinInt, GroupedInt domain. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOSetPinInterrupt
|
||||
**
|
||||
** Descriptions: Set interrupt sense, event, etc.
|
||||
** sense: edge or level, 0 is edge, 1 is level
|
||||
** event/polarity: 0 is active low/falling, 1 is high/rising.
|
||||
**
|
||||
** parameters: channel #, port #, bit position, sense, event(polarity)
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GPIOSetPinInterrupt( uint32_t channelNum, uint32_t portNum, uint32_t bitPosi,
|
||||
uint32_t sense, uint32_t event )
|
||||
{
|
||||
switch ( channelNum )
|
||||
{
|
||||
case CHANNEL0:
|
||||
if ( portNum )
|
||||
{
|
||||
LPC_SYSCON->PINSEL[0] = bitPosi + 24;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_SYSCON->PINSEL[0] = bitPosi;
|
||||
}
|
||||
NVIC_EnableIRQ(PIN_INT0_IRQn);
|
||||
break;
|
||||
case CHANNEL1:
|
||||
if ( portNum )
|
||||
{
|
||||
LPC_SYSCON->PINSEL[1] = bitPosi + 24;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_SYSCON->PINSEL[1] = bitPosi;
|
||||
}
|
||||
NVIC_EnableIRQ(PIN_INT1_IRQn);
|
||||
break;
|
||||
case CHANNEL2:
|
||||
if ( portNum )
|
||||
{
|
||||
LPC_SYSCON->PINSEL[2] = bitPosi + 24;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_SYSCON->PINSEL[2] = bitPosi;
|
||||
}
|
||||
NVIC_EnableIRQ(PIN_INT2_IRQn);
|
||||
break;
|
||||
case CHANNEL3:
|
||||
if ( portNum )
|
||||
{
|
||||
LPC_SYSCON->PINSEL[3] = bitPosi + 24;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_SYSCON->PINSEL[3] = bitPosi;
|
||||
}
|
||||
NVIC_EnableIRQ(PIN_INT3_IRQn);
|
||||
break;
|
||||
case CHANNEL4:
|
||||
if ( portNum )
|
||||
{
|
||||
LPC_SYSCON->PINSEL[4] = bitPosi + 24;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_SYSCON->PINSEL[4] = bitPosi;
|
||||
}
|
||||
NVIC_EnableIRQ(PIN_INT4_IRQn);
|
||||
break;
|
||||
case CHANNEL5:
|
||||
if ( portNum )
|
||||
{
|
||||
LPC_SYSCON->PINSEL[5] = bitPosi + 24;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_SYSCON->PINSEL[5] = bitPosi;
|
||||
}
|
||||
NVIC_EnableIRQ(PIN_INT5_IRQn);
|
||||
break;
|
||||
case CHANNEL6:
|
||||
if ( portNum )
|
||||
{
|
||||
LPC_SYSCON->PINSEL[6] = bitPosi + 24;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_SYSCON->PINSEL[6] = bitPosi;
|
||||
}
|
||||
NVIC_EnableIRQ(PIN_INT6_IRQn);
|
||||
break;
|
||||
case CHANNEL7:
|
||||
if ( portNum )
|
||||
{
|
||||
LPC_SYSCON->PINSEL[7] = bitPosi + 24;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_SYSCON->PINSEL[7] = bitPosi;
|
||||
}
|
||||
NVIC_EnableIRQ(PIN_INT7_IRQn);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
if ( sense == 0 )
|
||||
{
|
||||
LPC_GPIO_PIN_INT->ISEL &= ~(0x1<<channelNum); /* Edge trigger */
|
||||
if ( event == 0 )
|
||||
{
|
||||
LPC_GPIO_PIN_INT->IENF |= (0x1<<channelNum); /* faling edge */
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_PIN_INT->IENR |= (0x1<<channelNum); /* Rising edge */
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_PIN_INT->ISEL |= (0x1<<channelNum); /* Level trigger. */
|
||||
LPC_GPIO_PIN_INT->IENR |= (0x1<<channelNum); /* Level enable */
|
||||
if ( event == 0 )
|
||||
{
|
||||
LPC_GPIO_PIN_INT->IENF &= ~(0x1<<channelNum); /* active-low */
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_PIN_INT->IENF |= (0x1<<channelNum); /* active-high */
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOPinIntEnable
|
||||
**
|
||||
** Descriptions: Enable Interrupt
|
||||
**
|
||||
** parameters: channel num, event(0 is falling edge, 1 is rising edge)
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GPIOPinIntEnable( uint32_t channelNum, uint32_t event )
|
||||
{
|
||||
if ( !( LPC_GPIO_PIN_INT->ISEL & (0x1<<channelNum) ) )
|
||||
{
|
||||
if ( event == 0 )
|
||||
{
|
||||
LPC_GPIO_PIN_INT->SIENF |= (0x1<<channelNum); /* faling edge */
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_PIN_INT->SIENR |= (0x1<<channelNum); /* Rising edge */
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_PIN_INT->SIENR |= (0x1<<channelNum); /* Level */
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOPinIntDisable
|
||||
**
|
||||
** Descriptions: Disable Interrupt
|
||||
**
|
||||
** parameters: channel num, event(0 is falling edge, 1 is rising edge)
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GPIOPinIntDisable( uint32_t channelNum, uint32_t event )
|
||||
{
|
||||
if ( !( LPC_GPIO_PIN_INT->ISEL & (0x1<<channelNum) ) )
|
||||
{
|
||||
if ( event == 0 )
|
||||
{
|
||||
LPC_GPIO_PIN_INT->CIENF |= (0x1<<channelNum); /* faling edge */
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_PIN_INT->CIENR |= (0x1<<channelNum); /* Rising edge */
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_PIN_INT->CIENR |= (0x1<<channelNum); /* Level */
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOPinIntStatus
|
||||
**
|
||||
** Descriptions: Get Interrupt status
|
||||
**
|
||||
** parameters: channel num
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
uint32_t GPIOPinIntStatus( uint32_t channelNum )
|
||||
{
|
||||
if ( LPC_GPIO_PIN_INT->IST & (0x1<<channelNum) )
|
||||
{
|
||||
return( 1 );
|
||||
}
|
||||
else
|
||||
{
|
||||
return( 0 );
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOPinIntClear
|
||||
**
|
||||
** Descriptions: Clear Interrupt
|
||||
**
|
||||
** parameters: channel num
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GPIOPinIntClear( uint32_t channelNum )
|
||||
{
|
||||
if ( !( LPC_GPIO_PIN_INT->ISEL & (0x1<<channelNum) ) )
|
||||
{
|
||||
LPC_GPIO_PIN_INT->IST = (1<<channelNum);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOSetGroupedInterrupt
|
||||
**
|
||||
** Descriptions: Set interrupt logic, sense, eventPattern, etc.
|
||||
** logic: AND or OR, 0 is OR, 1 is AND
|
||||
** sensePattern: edge or level, 0 is edge, 1 is level
|
||||
** event/polarity: 0 is active low/falling, 1 is high/rising.
|
||||
**
|
||||
** parameters: group #, bit pattern, logic, sense, event(polarity) pattern
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GPIOSetGroupedInterrupt( uint32_t groupNum, uint32_t *bitPattern, uint32_t logic,
|
||||
uint32_t sense, uint32_t *eventPattern )
|
||||
{
|
||||
switch ( groupNum )
|
||||
{
|
||||
case GROUP0:
|
||||
if ( sense == 0 )
|
||||
{
|
||||
LPC_GPIO_GROUP_INT0->CTRL &= ~(0x1<<2); /* Edge trigger */
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_GROUP_INT0->CTRL |= (0x1<<2); /* Level trigger. */
|
||||
}
|
||||
if ( logic == 0 )
|
||||
{
|
||||
LPC_GPIO_GROUP_INT0->CTRL &= ~(0x1<<1); /* OR */
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_GROUP_INT0->CTRL |= (0x1<<1); /* AND */
|
||||
}
|
||||
LPC_GPIO_GROUP_INT0->PORT_POL[0] = *((uint32_t *)(eventPattern + 0));
|
||||
LPC_GPIO_GROUP_INT0->PORT_POL[1] = *((uint32_t *)(eventPattern + 1));
|
||||
LPC_GPIO_GROUP_INT0->PORT_ENA[0] = *((uint32_t *)(bitPattern + 0));
|
||||
LPC_GPIO_GROUP_INT0->PORT_ENA[1] = *((uint32_t *)(bitPattern + 1));
|
||||
/* as soon as enabled, an edge may be generated */
|
||||
/* clear interrupt flag and NVIC pending interrupt to */
|
||||
/* workaround the potential edge generated as enabled */
|
||||
LPC_GPIO_GROUP_INT0->CTRL |= (1<<0);
|
||||
NVIC_ClearPendingIRQ(GINT0_IRQn);
|
||||
NVIC_EnableIRQ(GINT0_IRQn);
|
||||
break;
|
||||
case GROUP1:
|
||||
if ( sense == 0 )
|
||||
{
|
||||
LPC_GPIO_GROUP_INT1->CTRL &= ~(0x1<<2); /* Edge trigger */
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_GROUP_INT1->CTRL |= (0x1<<2); /* Level trigger. */
|
||||
}
|
||||
if ( logic == 0 )
|
||||
{
|
||||
LPC_GPIO_GROUP_INT1->CTRL &= ~(0x1<<1); /* OR */
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO_GROUP_INT1->CTRL |= (0x1<<1); /* AND */
|
||||
}
|
||||
LPC_GPIO_GROUP_INT1->PORT_POL[0] = *((uint32_t *)(eventPattern + 0));
|
||||
LPC_GPIO_GROUP_INT1->PORT_POL[1] = *((uint32_t *)(eventPattern + 1));
|
||||
LPC_GPIO_GROUP_INT1->PORT_ENA[0] = *((uint32_t *)(bitPattern + 0));
|
||||
LPC_GPIO_GROUP_INT1->PORT_ENA[1] = *((uint32_t *)(bitPattern + 1));
|
||||
/* as soon as enabled, an edge may be generated */
|
||||
/* clear interrupt flag and NVIC pending interrupt to */
|
||||
/* workaround the potential edge generated as enabled */
|
||||
LPC_GPIO_GROUP_INT1->CTRL |= (1<<0);
|
||||
NVIC_ClearPendingIRQ(GINT1_IRQn);
|
||||
NVIC_EnableIRQ(GINT1_IRQn);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOGetPinValue
|
||||
**
|
||||
** Descriptions: Read Current state of port pin, PIN register value
|
||||
**
|
||||
** parameters: port num, bit position
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi )
|
||||
{
|
||||
uint32_t regVal = 0;
|
||||
|
||||
if( bitPosi < 0x20 )
|
||||
{
|
||||
if ( LPC_GPIO->PIN[portNum] & (0x1<<bitPosi) )
|
||||
{
|
||||
regVal = 1;
|
||||
}
|
||||
}
|
||||
else if( bitPosi == 0xFF )
|
||||
{
|
||||
regVal = LPC_GPIO->PIN[portNum];
|
||||
}
|
||||
return ( regVal );
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOSetBitValue
|
||||
**
|
||||
** Descriptions: Set/clear a bit in a specific position
|
||||
**
|
||||
** parameters: port num, bit position, bit value
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal )
|
||||
{
|
||||
if ( bitVal )
|
||||
{
|
||||
LPC_GPIO->SET[portNum] = 1<<bitPosi;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO->CLR[portNum] = 1<<bitPosi;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: GPIOSetDir
|
||||
**
|
||||
** Descriptions: Set the direction in GPIO port
|
||||
**
|
||||
** parameters: portNum, bit position, direction (1 out, 0 input)
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void GPIOSetDir( uint32_t portNum, uint32_t bitPosi, uint32_t dir )
|
||||
{
|
||||
if( dir )
|
||||
{
|
||||
LPC_GPIO->DIR[portNum] |= (1<<bitPosi);
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_GPIO->DIR[portNum] &= ~(1<<bitPosi);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@@ -1,95 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: nmi.c 7227 2011-04-27 20:20:38Z usb01267 $
|
||||
* Project: NXP LPC13Uxx NMI interrupt example
|
||||
*
|
||||
* Description:
|
||||
* This file contains NMI interrupt handler code example.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
****************************************************************************/
|
||||
#include "LPC13Uxx.h"
|
||||
#include "nmi.h"
|
||||
|
||||
#if NMI_ENABLED
|
||||
volatile uint32_t NMI_Counter[MAX_NMI_NUM];
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: NMI_Handler
|
||||
**
|
||||
** Descriptions: NMI interrupt handler
|
||||
** parameters: None
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void NMI_Handler( void )
|
||||
{
|
||||
uint32_t regVal;
|
||||
|
||||
regVal = LPC_SYSCON->NMISRC;
|
||||
regVal &= ~0x80000000;
|
||||
if ( regVal < MAX_NMI_NUM )
|
||||
{
|
||||
if ( regVal == CT16B0_IRQn )
|
||||
{
|
||||
/* Use TIMER16_0_IRQHandler as example for real application. */
|
||||
LPC_CT16B0->IR = 0xFF; /* Clear timer16_0 interrupt */
|
||||
}
|
||||
else if ( regVal == CT16B1_IRQn )
|
||||
{
|
||||
/* Use TIMER16_1_IRQHandler as example for real application. */
|
||||
LPC_CT16B1->IR = 0xFF; /* Clear timer16_1 interrupt */
|
||||
}
|
||||
else if ( regVal == CT32B0_IRQn )
|
||||
{
|
||||
/* Use TIMER32_0_IRQHandler as example for real application. */
|
||||
LPC_CT32B0->IR = 0xFF; /* Clear timer32_0 interrupt */
|
||||
}
|
||||
else if ( regVal == CT32B1_IRQn )
|
||||
{
|
||||
/* Use TIMER32_0_IRQHandler as example for real application. */
|
||||
LPC_CT32B1->IR = 0xFF; /* Clear timer32_1 interrupt */
|
||||
}
|
||||
NMI_Counter[regVal]++;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: NMI_Init
|
||||
**
|
||||
** Descriptions: NMI initialization
|
||||
** parameters: NMI number
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void NMI_Init( uint32_t NMI_num )
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for ( i = 0; i < MAX_NMI_NUM; i++ )
|
||||
{
|
||||
NMI_Counter[i] = 0x0;
|
||||
}
|
||||
LPC_SYSCON->NMISRC = 0x80000000|NMI_num;
|
||||
return;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,628 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: timer16.c 6950 2011-03-23 22:09:44Z usb00423 $
|
||||
* Project: NXP LPC13Uxx 16-bit timer example
|
||||
*
|
||||
* Description:
|
||||
* This file contains 16-bit timer code example which include timer
|
||||
* initialization, timer interrupt handler, and related APIs for
|
||||
* timer setup.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
****************************************************************************/
|
||||
#include "LPC13Uxx.h"
|
||||
#include "timer16.h"
|
||||
#include "nmi.h"
|
||||
|
||||
volatile uint32_t timer16_0_counter[4] = {0,0,0,0};
|
||||
volatile uint32_t timer16_1_counter[4] = {0,0,0,0};
|
||||
volatile uint32_t timer16_0_capture[4] = {0,0,0,0};
|
||||
volatile uint32_t timer16_1_capture[4] = {0,0,0,0};
|
||||
volatile uint32_t timer16_0_period = 0;
|
||||
volatile uint32_t timer16_1_period = 0;
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: delayMs
|
||||
**
|
||||
** Descriptions: Start the timer delay in milo seconds
|
||||
** until elapsed
|
||||
**
|
||||
** parameters: timer number, Delay value in milo second
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void delayMs(uint8_t timer_num, uint32_t delayInMs)
|
||||
{
|
||||
if (timer_num == 0)
|
||||
{
|
||||
/*
|
||||
* setup timer #0 for delay
|
||||
*/
|
||||
LPC_CT16B0->TCR = 0x02; /* reset timer */
|
||||
LPC_CT16B0->PR = 0x00; /* set prescaler to zero */
|
||||
LPC_CT16B0->MR0 = delayInMs * (SystemCoreClock / 1000);
|
||||
LPC_CT16B0->IR = 0xff; /* reset all interrrupts */
|
||||
LPC_CT16B0->MCR = 0x04; /* stop timer on match */
|
||||
LPC_CT16B0->TCR = 0x01; /* start timer */
|
||||
/* wait until delay time has elapsed */
|
||||
while (LPC_CT16B0->TCR & 0x01);
|
||||
}
|
||||
else if (timer_num == 1)
|
||||
{
|
||||
/*
|
||||
* setup timer #1 for delay
|
||||
*/
|
||||
LPC_CT16B1->TCR = 0x02; /* reset timer */
|
||||
LPC_CT16B1->PR = 0x00; /* set prescaler to zero */
|
||||
LPC_CT16B1->MR0 = delayInMs * (SystemCoreClock / 1000);
|
||||
LPC_CT16B1->IR = 0xff; /* reset all interrrupts */
|
||||
LPC_CT16B1->MCR = 0x04; /* stop timer on match */
|
||||
LPC_CT16B1->TCR = 0x01; /* start timer */
|
||||
/* wait until delay time has elapsed */
|
||||
while (LPC_CT16B1->TCR & 0x01);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: CT16B0_IRQHandler
|
||||
**
|
||||
** Descriptions: Timer/CounterX and CaptureX interrupt handler
|
||||
**
|
||||
** parameters: None
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CT16B0_IRQHandler(void)
|
||||
{
|
||||
if ( LPC_CT16B0->IR & (0x1<<0) )
|
||||
{
|
||||
LPC_CT16B0->IR = 0x1<<0; /* clear interrupt flag */
|
||||
timer16_0_counter[0]++;
|
||||
}
|
||||
if ( LPC_CT16B0->IR & (0x1<<1) )
|
||||
{
|
||||
LPC_CT16B0->IR = 0x1<<1; /* clear interrupt flag */
|
||||
timer16_0_counter[1]++;
|
||||
}
|
||||
if ( LPC_CT16B0->IR & (0x1<<2) )
|
||||
{
|
||||
LPC_CT16B0->IR = 0x1<<2; /* clear interrupt flag */
|
||||
timer16_0_counter[2]++;
|
||||
}
|
||||
if ( LPC_CT16B0->IR & (0x1<<3) )
|
||||
{
|
||||
LPC_CT16B0->IR = 0x1<<3; /* clear interrupt flag */
|
||||
timer16_0_counter[3]++;
|
||||
}
|
||||
if ( LPC_CT16B0->IR & (0x1<<4) )
|
||||
{
|
||||
LPC_CT16B0->IR = 0x1<<4; /* clear interrupt flag */
|
||||
timer16_0_capture[0]++;
|
||||
}
|
||||
if ( LPC_CT16B0->IR & (0x1<<5) )
|
||||
{
|
||||
LPC_CT16B0->IR = 0x1<<5; /* clear interrupt flag */
|
||||
timer16_0_capture[1]++;
|
||||
}
|
||||
if ( LPC_CT16B0->IR & (0x1<<6) )
|
||||
{
|
||||
LPC_CT16B0->IR = 0x1<<6; /* clear interrupt flag */
|
||||
timer16_0_capture[2]++;
|
||||
}
|
||||
if ( LPC_CT16B0->IR & (0x1<<7) )
|
||||
{
|
||||
LPC_CT16B0->IR = 0x1<<7; /* clear interrupt flag */
|
||||
timer16_0_capture[3]++;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: CT16B1_IRQHandler
|
||||
**
|
||||
** Descriptions: Timer/CounterX and CaptureX interrupt handler
|
||||
**
|
||||
** parameters: None
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CT16B1_IRQHandler(void)
|
||||
{
|
||||
if ( LPC_CT16B1->IR & (0x1<<0) )
|
||||
{
|
||||
LPC_CT16B1->IR = 0x1<<0; /* clear interrupt flag */
|
||||
timer16_1_counter[0]++;
|
||||
}
|
||||
if ( LPC_CT16B1->IR & (0x1<<1) )
|
||||
{
|
||||
LPC_CT16B1->IR = 0x1<<1; /* clear interrupt flag */
|
||||
timer16_1_counter[1]++;
|
||||
}
|
||||
if ( LPC_CT16B1->IR & (0x1<<2) )
|
||||
{
|
||||
LPC_CT16B1->IR = 0x1<<2; /* clear interrupt flag */
|
||||
timer16_1_counter[2]++;
|
||||
}
|
||||
if ( LPC_CT16B1->IR & (0x1<<3) )
|
||||
{
|
||||
LPC_CT16B1->IR = 0x1<<3; /* clear interrupt flag */
|
||||
timer16_1_counter[3]++;
|
||||
}
|
||||
if ( LPC_CT16B1->IR & (0x1<<4) )
|
||||
{
|
||||
LPC_CT16B1->IR = 0x1<<4; /* clear interrupt flag */
|
||||
timer16_1_capture[0]++;
|
||||
}
|
||||
if ( LPC_CT16B1->IR & (0x1<<5) )
|
||||
{
|
||||
LPC_CT16B1->IR = 0x1<<5; /* clear interrupt flag */
|
||||
timer16_1_capture[1]++;
|
||||
}
|
||||
if ( LPC_CT16B1->IR & (0x1<<6) )
|
||||
{
|
||||
LPC_CT16B1->IR = 0x1<<6; /* clear interrupt flag */
|
||||
timer16_1_capture[2]++;
|
||||
}
|
||||
if ( LPC_CT16B1->IR & (0x1<<7) )
|
||||
{
|
||||
LPC_CT16B1->IR = 0x1<<7; /* clear interrupt flag */
|
||||
timer16_1_capture[3]++;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: enable_timer
|
||||
**
|
||||
** Descriptions: Enable timer
|
||||
**
|
||||
** parameters: timer number: 0 or 1
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void enable_timer16(uint8_t timer_num)
|
||||
{
|
||||
if ( timer_num == 0 )
|
||||
{
|
||||
LPC_CT16B0->TCR = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_CT16B1->TCR = 1;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: disable_timer
|
||||
**
|
||||
** Descriptions: Disable timer
|
||||
**
|
||||
** parameters: timer number: 0 or 1
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void disable_timer16(uint8_t timer_num)
|
||||
{
|
||||
if ( timer_num == 0 )
|
||||
{
|
||||
LPC_CT16B0->TCR = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_CT16B1->TCR = 0;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: reset_timer
|
||||
**
|
||||
** Descriptions: Reset timer
|
||||
**
|
||||
** parameters: timer number: 0 or 1
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void reset_timer16(uint8_t timer_num)
|
||||
{
|
||||
uint32_t regVal;
|
||||
|
||||
if ( timer_num == 0 )
|
||||
{
|
||||
regVal = LPC_CT16B0->TCR;
|
||||
regVal |= 0x02;
|
||||
LPC_CT16B0->TCR = regVal;
|
||||
}
|
||||
else
|
||||
{
|
||||
regVal = LPC_CT16B1->TCR;
|
||||
regVal |= 0x02;
|
||||
LPC_CT16B1->TCR = regVal;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: Set_timer_capture
|
||||
**
|
||||
** Descriptions: set timer capture based on LOC number.
|
||||
**
|
||||
** parameters: timer number and location number
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void set_timer16_capture(uint8_t timer_num, uint8_t location )
|
||||
{
|
||||
if ( timer_num == 0 )
|
||||
{
|
||||
/* Timer0_16 I/O config */
|
||||
if ( location == 0 )
|
||||
{
|
||||
LPC_IOCON->PIO1_16 &= ~0x07;
|
||||
LPC_IOCON->PIO1_16 |= 0x02; /* Timer0_16 CAP0 */
|
||||
LPC_IOCON->PIO1_17 &= ~0x07;
|
||||
LPC_IOCON->PIO1_17 |= 0x01; /* Timer0_16 CAP2 */
|
||||
}
|
||||
else if ( location == 1 )
|
||||
{
|
||||
LPC_IOCON->PIO0_2 &= ~0x07;
|
||||
LPC_IOCON->PIO0_2 |= 0x02; /* Timer0_16 CAP0 */
|
||||
}
|
||||
else
|
||||
{
|
||||
while ( 1 ); /* Fatal location number error */
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Timer1_16 I/O config */
|
||||
if ( location == 0 )
|
||||
{
|
||||
LPC_IOCON->PIO0_20 &= ~0x07; /* Timer1_16 I/O config */
|
||||
LPC_IOCON->PIO0_20 |= 0x01; /* Timer1_16 CAP0 */
|
||||
LPC_IOCON->PIO1_18 &= ~0x07;
|
||||
LPC_IOCON->PIO1_18 |= 0x01; /* Timer1_16 CAP1 */
|
||||
}
|
||||
else
|
||||
{
|
||||
while ( 1 ); /* Fatal location number error */
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: Set_timer_match
|
||||
**
|
||||
** Descriptions: set timer match based on LOC number.
|
||||
**
|
||||
** parameters: timer number, match enable, and location number
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void set_timer16_match(uint8_t timer_num, uint8_t match_enable, uint8_t location)
|
||||
{
|
||||
if ( timer_num == 0 )
|
||||
{
|
||||
if ( match_enable & 0x01 )
|
||||
{
|
||||
/* Timer0_16 I/O config */
|
||||
if ( location == 0 )
|
||||
{
|
||||
LPC_IOCON->PIO0_8 &= ~0x07;
|
||||
LPC_IOCON->PIO0_8 |= 0x02; /* Timer0_16 MAT0 */
|
||||
}
|
||||
else if ( location == 1 )
|
||||
{
|
||||
LPC_IOCON->PIO1_13 &= ~0x07;
|
||||
LPC_IOCON->PIO1_13 |= 0x02; /* Timer0_16 MAT0 */
|
||||
}
|
||||
}
|
||||
if ( match_enable & 0x02 )
|
||||
{
|
||||
/* Timer0_16 I/O config */
|
||||
if ( location == 0 )
|
||||
{
|
||||
LPC_IOCON->PIO0_9 &= ~0x07;
|
||||
LPC_IOCON->PIO0_9 |= 0x02; /* Timer0_16 MAT1 */
|
||||
}
|
||||
else if ( location == 1 )
|
||||
{
|
||||
LPC_IOCON->PIO1_14 &= ~0x07;
|
||||
LPC_IOCON->PIO1_14 |= 0x02; /* Timer0_16 MAT1 */
|
||||
}
|
||||
}
|
||||
if ( match_enable & 0x04 )
|
||||
{
|
||||
/* Timer0_16 I/O config */
|
||||
if ( location == 0 )
|
||||
{
|
||||
#ifdef __SWD_DISABLED
|
||||
LPC_IOCON->SWCLK_PIO0_10 &= ~0x07;
|
||||
LPC_IOCON->SWCLK_PIO0_10 |= 0x03; /* Timer0_16 MAT2 */
|
||||
#endif
|
||||
}
|
||||
else if ( location == 1 )
|
||||
{
|
||||
LPC_IOCON->PIO1_15 &= ~0x07;
|
||||
LPC_IOCON->PIO1_15 |= 0x02; /* Timer0_16 MAT2 */
|
||||
}
|
||||
}
|
||||
}
|
||||
else if ( timer_num == 1 )
|
||||
{
|
||||
if ( match_enable & 0x01 )
|
||||
{
|
||||
/* Timer1_16 I/O config */
|
||||
if ( location == 0 )
|
||||
{
|
||||
LPC_IOCON->PIO0_21 &= ~0x07;
|
||||
LPC_IOCON->PIO0_21 |= 0x01; /* Timer1_16 MAT0 */
|
||||
}
|
||||
}
|
||||
if ( match_enable & 0x02 )
|
||||
{
|
||||
/* Timer1_16 I/O config */
|
||||
if ( location == 0 )
|
||||
{
|
||||
LPC_IOCON->PIO0_22 &= ~0x07;
|
||||
LPC_IOCON->PIO0_22 |= 0x02; /* Timer1_16 MAT1 */
|
||||
}
|
||||
else if ( location == 1 )
|
||||
{
|
||||
LPC_IOCON->PIO1_23 &= ~0x07;
|
||||
LPC_IOCON->PIO1_23 |= 0x01; /* Timer1_16 MAT1 */
|
||||
}
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: init_timer
|
||||
**
|
||||
** Descriptions: Initialize timer, set timer interval, reset timer,
|
||||
** install timer interrupt handler
|
||||
**
|
||||
** parameters: timer number and timer interval
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void init_timer16(uint8_t timer_num, uint32_t TimerInterval)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
if ( timer_num == 0 )
|
||||
{
|
||||
/* Some of the I/O pins need to be clearfully planned if
|
||||
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<7);
|
||||
|
||||
LPC_CT16B0->MR0 = TimerInterval;
|
||||
LPC_CT16B0->MR1 = TimerInterval;
|
||||
#if TIMER_MATCH
|
||||
for ( i = 0; i < 4; i++ )
|
||||
{
|
||||
timer16_0_counter[i] = 0;
|
||||
}
|
||||
set_timer16_match(timer_num, 0x07, 0);
|
||||
LPC_CT16B0->EMR &= ~(0xFF<<4);
|
||||
LPC_CT16B0->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8));
|
||||
#else
|
||||
for ( i = 0; i < 4; i++ )
|
||||
{
|
||||
timer16_0_capture[i] = 0;
|
||||
}
|
||||
set_timer16_capture(timer_num, 0);
|
||||
/* Capture 0 and 2 on rising edge, interrupt enable. */
|
||||
LPC_CT16B0->CCR = (0x5<<0)|(0x5<<6);
|
||||
#endif
|
||||
LPC_CT16B0->MCR = (0x3<<0)|(0x3<<3); /* Interrupt and Reset on MR0 and MR1 */
|
||||
|
||||
/* Enable the TIMER0 Interrupt */
|
||||
#if NMI_ENABLED
|
||||
NVIC_DisableIRQ(CT16B0_IRQn);
|
||||
NMI_Init( CT16B0_IRQn );
|
||||
#else
|
||||
NVIC_EnableIRQ(CT16B0_IRQn);
|
||||
#endif
|
||||
}
|
||||
else if ( timer_num == 1 )
|
||||
{
|
||||
/* Some of the I/O pins need to be clearfully planned if
|
||||
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<8);
|
||||
LPC_CT16B1->MR0 = TimerInterval;
|
||||
LPC_CT16B1->MR1 = TimerInterval;
|
||||
#if TIMER_MATCH
|
||||
for ( i = 0; i < 4; i++ )
|
||||
{
|
||||
timer16_1_counter[i] = 0;
|
||||
}
|
||||
set_timer16_match(timer_num, 0x07, 0);
|
||||
LPC_CT16B1->EMR &= ~(0xFF<<4);
|
||||
LPC_CT16B1->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8));
|
||||
#else
|
||||
for ( i = 0; i < 4; i++ )
|
||||
{
|
||||
timer16_1_capture[i] = 0;
|
||||
}
|
||||
set_timer16_capture(timer_num, 0);
|
||||
/* Capture 0 and 1 on rising edge, interrupt enable. */
|
||||
LPC_CT16B1->CCR = (0x5<<0)|(0x5<<3);
|
||||
#endif
|
||||
LPC_CT16B1->MCR = (0x3<<0)|(0x3<<3); /* Interrupt and Reset on MR0 and MR1 */
|
||||
|
||||
/* Enable the TIMER1 Interrupt */
|
||||
#if NMI_ENABLED
|
||||
NVIC_DisableIRQ(CT16B1_IRQn);
|
||||
NMI_Init( CT16B1_IRQn );
|
||||
#else
|
||||
NVIC_EnableIRQ(CT16B1_IRQn);
|
||||
#endif
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: init_timer16PWM
|
||||
**
|
||||
** Descriptions: Initialize timer as PWM
|
||||
**
|
||||
** parameters: timer number, period and match enable:
|
||||
** match_enable[0] = PWM for MAT0
|
||||
** match_enable[1] = PWM for MAT1
|
||||
** match_enable[2] = PWM for MAT2
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void init_timer16PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable, uint8_t cap_enabled)
|
||||
{
|
||||
disable_timer16(timer_num);
|
||||
|
||||
if (timer_num == 1)
|
||||
{
|
||||
/* Some of the I/O pins need to be clearfully planned if
|
||||
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<8);
|
||||
|
||||
/* Setup the external match register */
|
||||
LPC_CT16B1->EMR = (1<<EMC3)|(1<<EMC2)|(1<<EMC1)|(2<<EMC0)|(1<<3)|(match_enable);
|
||||
|
||||
/* Setup the outputs */
|
||||
/* If match0 is enabled, set the output */
|
||||
set_timer16_match(timer_num, match_enable, 0 );
|
||||
|
||||
/* Enable the selected PWMs and enable Match3 */
|
||||
LPC_CT16B1->PWMC = (1<<3)|(match_enable);
|
||||
|
||||
/* Setup the match registers */
|
||||
/* set the period value to a global variable */
|
||||
timer16_1_period = period;
|
||||
LPC_CT16B1->MR3 = timer16_1_period;
|
||||
LPC_CT16B1->MR0 = timer16_1_period/2;
|
||||
LPC_CT16B1->MR1 = timer16_1_period/2;
|
||||
LPC_CT16B1->MR2 = timer16_1_period/2;
|
||||
|
||||
/* Set match control register */
|
||||
LPC_CT16B1->MCR = 1<<10;// | 1<<9; /* Reset on MR3 */
|
||||
|
||||
if (cap_enabled)
|
||||
{
|
||||
/* Use location 0 for test. */
|
||||
set_timer16_capture( timer_num, 0 );
|
||||
LPC_CT16B1->IR = 0xF; /* clear interrupt flag */
|
||||
|
||||
/* Set the capture control register */
|
||||
LPC_CT16B1->CCR = 7;
|
||||
|
||||
}
|
||||
/* Enable the TIMER1 Interrupt */
|
||||
NVIC_EnableIRQ(CT16B1_IRQn);
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<7);
|
||||
|
||||
/* Setup the external match register */
|
||||
LPC_CT16B0->EMR = (1<<EMC3)|(1<<EMC2)|(1<<EMC1)|(1<<EMC0)|(1<<3)|(match_enable);
|
||||
|
||||
/* Setup the outputs */
|
||||
/* If match0 is enabled, set the output */
|
||||
set_timer16_match(timer_num, match_enable, 0 );
|
||||
|
||||
/* Enable the selected PWMs and enable Match3 */
|
||||
LPC_CT16B0->PWMC = (1<<3)|(match_enable);
|
||||
|
||||
/* Setup the match registers */
|
||||
/* set the period value to a global variable */
|
||||
timer16_0_period = period;
|
||||
LPC_CT16B0->MR3 = timer16_0_period;
|
||||
LPC_CT16B0->MR0 = timer16_0_period/2;
|
||||
LPC_CT16B0->MR1 = timer16_0_period/2;
|
||||
LPC_CT16B0->MR2 = timer16_0_period/2;
|
||||
|
||||
/* Set the match control register */
|
||||
LPC_CT16B0->MCR = 1<<10; /* Reset on MR3 */
|
||||
|
||||
/* Enable the TIMER1 Interrupt */
|
||||
NVIC_EnableIRQ(CT16B0_IRQn);
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: pwm16_setMatch
|
||||
**
|
||||
** Descriptions: Set the pwm16 match values
|
||||
**
|
||||
** parameters: timer number, match numner and the value
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void setMatch_timer16PWM (uint8_t timer_num, uint8_t match_nr, uint32_t value)
|
||||
{
|
||||
if (timer_num)
|
||||
{
|
||||
switch (match_nr)
|
||||
{
|
||||
case 0:
|
||||
LPC_CT16B1->MR0 = value;
|
||||
break;
|
||||
case 1:
|
||||
LPC_CT16B1->MR1 = value;
|
||||
break;
|
||||
case 2:
|
||||
LPC_CT16B1->MR2 = value;
|
||||
break;
|
||||
case 3:
|
||||
LPC_CT16B1->MR3 = value;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (match_nr)
|
||||
{
|
||||
case 0:
|
||||
LPC_CT16B0->MR0 = value;
|
||||
break;
|
||||
case 1:
|
||||
LPC_CT16B0->MR1 = value;
|
||||
break;
|
||||
case 2:
|
||||
LPC_CT16B0->MR2 = value;
|
||||
break;
|
||||
case 3:
|
||||
LPC_CT16B0->MR3 = value;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@@ -1,646 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: timer32.c 6951 2011-03-23 22:11:07Z usb00423 $
|
||||
* Project: NXP LPC13Uxx 32-bit timer example
|
||||
*
|
||||
* Description:
|
||||
* This file contains 32-bit timer code example which include timer
|
||||
* initialization, timer interrupt handler, and related APIs for
|
||||
* timer setup.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
****************************************************************************/
|
||||
#include "LPC13Uxx.h"
|
||||
#include "timer32.h"
|
||||
#include "nmi.h"
|
||||
|
||||
volatile uint32_t timer32_0_counter[4] = {0,0,0,0};
|
||||
volatile uint32_t timer32_1_counter[4] = {0,0,0,0};
|
||||
volatile uint32_t timer32_0_capture[4] = {0,0,0,0};
|
||||
volatile uint32_t timer32_1_capture[4] = {0,0,0,0};
|
||||
volatile uint32_t timer32_0_period = 0;
|
||||
volatile uint32_t timer32_1_period = 0;
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: delay32Ms
|
||||
**
|
||||
** Descriptions: Start the timer delay in milo seconds
|
||||
** until elapsed
|
||||
**
|
||||
** parameters: timer number, Delay value in milo second
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void delay32Ms(uint8_t timer_num, uint32_t delayInMs)
|
||||
{
|
||||
if (timer_num == 0)
|
||||
{
|
||||
/* setup timer #0 for delay */
|
||||
LPC_CT32B0->TCR = 0x02; /* reset timer */
|
||||
LPC_CT32B0->PR = 0x00; /* set prescaler to zero */
|
||||
LPC_CT32B0->MR0 = delayInMs * (SystemCoreClock / 1000);
|
||||
LPC_CT32B0->IR = 0xff; /* reset all interrrupts */
|
||||
LPC_CT32B0->MCR = 0x04; /* stop timer on match */
|
||||
LPC_CT32B0->TCR = 0x01; /* start timer */
|
||||
|
||||
/* wait until delay time has elapsed */
|
||||
while (LPC_CT32B0->TCR & 0x01);
|
||||
}
|
||||
else if (timer_num == 1)
|
||||
{
|
||||
/* setup timer #1 for delay */
|
||||
LPC_CT32B1->TCR = 0x02; /* reset timer */
|
||||
LPC_CT32B1->PR = 0x00; /* set prescaler to zero */
|
||||
LPC_CT32B1->MR0 = delayInMs * (SystemCoreClock / 1000);
|
||||
LPC_CT32B1->IR = 0xff; /* reset all interrrupts */
|
||||
LPC_CT32B1->MCR = 0x04; /* stop timer on match */
|
||||
LPC_CT32B1->TCR = 0x01; /* start timer */
|
||||
|
||||
/* wait until delay time has elapsed */
|
||||
while (LPC_CT32B1->TCR & 0x01);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: CT32B0_IRQHandler
|
||||
**
|
||||
** Descriptions: Timer/CounterX and captureX interrupt handler
|
||||
**
|
||||
** parameters: None
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CT32B0_IRQHandler(void)
|
||||
{
|
||||
if ( LPC_CT32B0->IR & (0x01<<0) )
|
||||
{
|
||||
LPC_CT32B0->IR = 0x1<<0; /* clear interrupt flag */
|
||||
timer32_0_counter[0]++;
|
||||
}
|
||||
if ( LPC_CT32B0->IR & (0x01<<1) )
|
||||
{
|
||||
LPC_CT32B0->IR = 0x1<<1; /* clear interrupt flag */
|
||||
timer32_0_counter[1]++;
|
||||
}
|
||||
if ( LPC_CT32B0->IR & (0x01<<2) )
|
||||
{
|
||||
LPC_CT32B0->IR = 0x1<<2; /* clear interrupt flag */
|
||||
timer32_0_counter[2]++;
|
||||
}
|
||||
if ( LPC_CT32B0->IR & (0x01<<3) )
|
||||
{
|
||||
LPC_CT32B0->IR = 0x1<<3; /* clear interrupt flag */
|
||||
timer32_0_counter[3]++;
|
||||
}
|
||||
if ( LPC_CT32B0->IR & (0x1<<4) )
|
||||
{
|
||||
LPC_CT32B0->IR = 0x1<<4; /* clear interrupt flag */
|
||||
timer32_0_capture[0]++;
|
||||
}
|
||||
if ( LPC_CT32B0->IR & (0x1<<5) )
|
||||
{
|
||||
LPC_CT32B0->IR = 0x1<<5; /* clear interrupt flag */
|
||||
timer32_0_capture[1]++;
|
||||
}
|
||||
if ( LPC_CT32B0->IR & (0x1<<6) )
|
||||
{
|
||||
LPC_CT32B0->IR = 0x1<<6; /* clear interrupt flag */
|
||||
timer32_0_capture[2]++;
|
||||
}
|
||||
if ( LPC_CT32B0->IR & (0x1<<7) )
|
||||
{
|
||||
LPC_CT32B0->IR = 0x1<<7; /* clear interrupt flag */
|
||||
timer32_0_capture[3]++;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: CT32B1_IRQHandler
|
||||
**
|
||||
** Descriptions: Timer/CounterX and captureX interrupt handler
|
||||
**
|
||||
** parameters: None
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void CT32B1_IRQHandler(void)
|
||||
{
|
||||
if ( LPC_CT32B1->IR & (0x01<<0) )
|
||||
{
|
||||
LPC_CT32B1->IR = 0x1<<0; /* clear interrupt flag */
|
||||
timer32_1_counter[0]++;
|
||||
}
|
||||
if ( LPC_CT32B1->IR & (0x01<<1) )
|
||||
{
|
||||
LPC_CT32B1->IR = 0x1<<1; /* clear interrupt flag */
|
||||
timer32_1_counter[1]++;
|
||||
}
|
||||
if ( LPC_CT32B1->IR & (0x01<<2) )
|
||||
{
|
||||
LPC_CT32B1->IR = 0x1<<2; /* clear interrupt flag */
|
||||
timer32_1_counter[2]++;
|
||||
}
|
||||
if ( LPC_CT32B1->IR & (0x01<<3) )
|
||||
{
|
||||
LPC_CT32B1->IR = 0x1<<3; /* clear interrupt flag */
|
||||
timer32_1_counter[3]++;
|
||||
}
|
||||
if ( LPC_CT32B1->IR & (0x1<<4) )
|
||||
{
|
||||
LPC_CT32B1->IR = 0x1<<4; /* clear interrupt flag */
|
||||
timer32_1_capture[0]++;
|
||||
}
|
||||
if ( LPC_CT32B1->IR & (0x1<<5) )
|
||||
{
|
||||
LPC_CT32B1->IR = 0x1<<5; /* clear interrupt flag */
|
||||
timer32_1_capture[1]++;
|
||||
}
|
||||
if ( LPC_CT32B1->IR & (0x1<<6) )
|
||||
{
|
||||
LPC_CT32B1->IR = 0x1<<6; /* clear interrupt flag */
|
||||
timer32_1_capture[2]++;
|
||||
}
|
||||
if ( LPC_CT32B1->IR & (0x1<<7) )
|
||||
{
|
||||
LPC_CT32B1->IR = 0x1<<7; /* clear interrupt flag */
|
||||
timer32_1_capture[3]++;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: enable_timer
|
||||
**
|
||||
** Descriptions: Enable timer
|
||||
**
|
||||
** parameters: timer number: 0 or 1
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void enable_timer32(uint8_t timer_num)
|
||||
{
|
||||
if ( timer_num == 0 )
|
||||
{
|
||||
LPC_CT32B0->TCR = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_CT32B1->TCR = 1;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: disable_timer
|
||||
**
|
||||
** Descriptions: Disable timer
|
||||
**
|
||||
** parameters: timer number: 0 or 1
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void disable_timer32(uint8_t timer_num)
|
||||
{
|
||||
if ( timer_num == 0 )
|
||||
{
|
||||
LPC_CT32B0->TCR = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
LPC_CT32B1->TCR = 0;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: reset_timer
|
||||
**
|
||||
** Descriptions: Reset timer
|
||||
**
|
||||
** parameters: timer number: 0 or 1
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void reset_timer32(uint8_t timer_num)
|
||||
{
|
||||
uint32_t regVal;
|
||||
|
||||
if ( timer_num == 0 )
|
||||
{
|
||||
regVal = LPC_CT32B0->TCR;
|
||||
regVal |= 0x02;
|
||||
LPC_CT32B0->TCR = regVal;
|
||||
}
|
||||
else
|
||||
{
|
||||
regVal = LPC_CT32B1->TCR;
|
||||
regVal |= 0x02;
|
||||
LPC_CT32B1->TCR = regVal;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: set_timer_capture
|
||||
**
|
||||
** Descriptions: Set timer capture based on location
|
||||
**
|
||||
** parameters: timer number: 0~1, location 0~2
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void set_timer32_capture(uint8_t timer_num, uint8_t location )
|
||||
{
|
||||
if ( timer_num == 0 )
|
||||
{
|
||||
/* Timer0_32 I/O config */
|
||||
if ( location == 0 )
|
||||
{
|
||||
LPC_IOCON->PIO1_28 &= ~0x07;
|
||||
LPC_IOCON->PIO1_28 |= 0x01; /* Timer0_32 CAP0 */
|
||||
LPC_IOCON->PIO1_29 &= ~0x07;
|
||||
LPC_IOCON->PIO1_29 |= 0x02; /* Timer0_32 CAP2 */
|
||||
}
|
||||
else if ( location == 1 )
|
||||
{
|
||||
LPC_IOCON->PIO0_17 &= ~0x07;
|
||||
LPC_IOCON->PIO0_17 |= 0x02; /* Timer0_32 CAP0 */
|
||||
}
|
||||
else
|
||||
{
|
||||
while ( 1 ); /* Fatal location number error */
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Timer1_32 I/O config */
|
||||
if ( location == 0 )
|
||||
{
|
||||
LPC_IOCON->PIO1_4 &= ~0x07; /* Timer1_32 I/O config */
|
||||
LPC_IOCON->PIO1_4 |= 0x01; /* Timer1_32 CAP0 */
|
||||
LPC_IOCON->PIO1_5 &= ~0x07;
|
||||
LPC_IOCON->PIO1_5 |= 0x01; /* Timer1_32 CAP1 */
|
||||
}
|
||||
else if ( location == 1 )
|
||||
{
|
||||
LPC_IOCON->TMS_PIO0_12 &= ~0x07;
|
||||
LPC_IOCON->TMS_PIO0_12 |= 0x03; /* Timer1_32 CAP0 */
|
||||
}
|
||||
else
|
||||
{
|
||||
while ( 1 ); /* Fatal location number error */
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: set_timer_match
|
||||
**
|
||||
** Descriptions: Set timer match based on location
|
||||
**
|
||||
** parameters: timer number: 0~1, location 0~2
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void set_timer32_match(uint8_t timer_num, uint8_t match_enable, uint8_t location)
|
||||
{
|
||||
if ( timer_num == 0 )
|
||||
{
|
||||
if ( match_enable & 0x01 )
|
||||
{
|
||||
if ( location == 0 )
|
||||
{
|
||||
LPC_IOCON->PIO0_18 &= ~0x07;
|
||||
LPC_IOCON->PIO0_18 |= 0x02; /* Timer0_32 MAT0 */
|
||||
}
|
||||
else if ( location == 1 )
|
||||
{
|
||||
LPC_IOCON->PIO1_24 &= ~0x07;
|
||||
LPC_IOCON->PIO1_24 |= 0x01; /* Timer0_32 MAT0 */
|
||||
}
|
||||
}
|
||||
if ( match_enable & 0x02 )
|
||||
{
|
||||
if ( location == 0 )
|
||||
{
|
||||
LPC_IOCON->PIO0_19 &= ~0x07;
|
||||
LPC_IOCON->PIO0_19 |= 0x02; /* Timer0_32 MAT1 */
|
||||
}
|
||||
else if ( location == 1 )
|
||||
{
|
||||
LPC_IOCON->PIO1_25 &= ~0x07;
|
||||
LPC_IOCON->PIO1_25 |= 0x01; /* Timer0_32 MAT1 */
|
||||
}
|
||||
}
|
||||
if ( match_enable & 0x04 )
|
||||
{
|
||||
if ( location == 0 )
|
||||
{
|
||||
LPC_IOCON->PIO0_1 &= ~0x07;
|
||||
LPC_IOCON->PIO0_1 |= 0x02; /* Timer0_32 MAT2 */
|
||||
}
|
||||
else if ( location == 1 )
|
||||
{
|
||||
LPC_IOCON->PIO1_26 &= ~0x07;
|
||||
LPC_IOCON->PIO1_26 |= 0x01; /* Timer0_32 MAT2 */
|
||||
}
|
||||
}
|
||||
if ( match_enable & 0x08 )
|
||||
{
|
||||
if ( location == 0 )
|
||||
{
|
||||
LPC_IOCON->TDI_PIO0_11 &= ~0x07;
|
||||
LPC_IOCON->TDI_PIO0_11 |= 0x03; /* Timer0_32 MAT3 */
|
||||
}
|
||||
else if ( location == 1 )
|
||||
{
|
||||
LPC_IOCON->PIO1_27 &= ~0x07;
|
||||
LPC_IOCON->PIO1_27 |= 0x01; /* Timer0_32 MAT3 */
|
||||
}
|
||||
}
|
||||
}
|
||||
else if ( timer_num == 1 )
|
||||
{
|
||||
if ( match_enable & 0x01 )
|
||||
{
|
||||
if ( location == 0 )
|
||||
{
|
||||
LPC_IOCON->PIO1_0 &= ~0x07;
|
||||
LPC_IOCON->PIO1_0 |= 0x01; /* Timer1_32 MAT0 */
|
||||
}
|
||||
else if ( location == 1 )
|
||||
{
|
||||
LPC_IOCON->TDO_PIO0_13 &= ~0x07;
|
||||
LPC_IOCON->TDO_PIO0_13 |= 0x03; /* Timer1_32 MAT0 */
|
||||
}
|
||||
}
|
||||
if ( match_enable & 0x02 )
|
||||
{
|
||||
if ( location == 0 )
|
||||
{
|
||||
LPC_IOCON->PIO1_1 &= ~0x07;
|
||||
LPC_IOCON->PIO1_1 |= 0x01; /* Timer1_32 MAT1 */
|
||||
}
|
||||
else if ( location == 1 )
|
||||
{
|
||||
LPC_IOCON->TRST_PIO0_14 &= ~0x07;
|
||||
LPC_IOCON->TRST_PIO0_14 |= 0x03; /* Timer1_32 MAT1 */
|
||||
}
|
||||
}
|
||||
if ( match_enable & 0x04 )
|
||||
{
|
||||
if ( location == 0 )
|
||||
{
|
||||
LPC_IOCON->PIO1_2 &= ~0x07;
|
||||
LPC_IOCON->PIO1_2 |= 0x01; /* Timer1_32 MAT2 */
|
||||
}
|
||||
else if ( location == 1 )
|
||||
{
|
||||
#if __SWD_DISABLED
|
||||
LPC_IOCON->SWDIO_PIO0_15 &= ~0x07;
|
||||
LPC_IOCON->SWDIO_PIO0_15 |= 0x03; /* Timer1_32 MAT2 */
|
||||
#endif
|
||||
}
|
||||
}
|
||||
if ( match_enable & 0x08 )
|
||||
{
|
||||
if ( location == 0 )
|
||||
{
|
||||
LPC_IOCON->PIO1_3 &= ~0x07;
|
||||
LPC_IOCON->PIO1_3 |= 0x01; /* Timer1_32 MAT3 */
|
||||
}
|
||||
else if ( location == 1 )
|
||||
{
|
||||
LPC_IOCON->PIO0_16 &= ~0x07;
|
||||
LPC_IOCON->PIO0_16 |= 0x02; /* Timer1_32 MAT3 */
|
||||
}
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: init_timer
|
||||
**
|
||||
** Descriptions: Initialize timer, set timer interval, reset timer,
|
||||
** install timer interrupt handler
|
||||
**
|
||||
** parameters: timer number and timer interval
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void init_timer32(uint8_t timer_num, uint32_t TimerInterval)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
if ( timer_num == 0 )
|
||||
{
|
||||
/* Some of the I/O pins need to be clearfully planned if
|
||||
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<9);
|
||||
|
||||
LPC_CT32B0->MR0 = TimerInterval;
|
||||
#if TIMER_MATCH
|
||||
for ( i = 0; i < 4; i++ )
|
||||
{
|
||||
timer32_0_counter[i] = 0;
|
||||
}
|
||||
set_timer32_match(timer_num, 0x0F, 0);
|
||||
LPC_CT32B0->EMR &= ~(0xFF<<4);
|
||||
LPC_CT32B0->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8)|(0x3<<10)); /* MR0/1/2/3 Toggle */
|
||||
#else
|
||||
for ( i = 0; i < 4; i++ )
|
||||
{
|
||||
timer32_0_capture[i] = 0;
|
||||
}
|
||||
set_timer32_capture(timer_num, 0 );
|
||||
/* Capture 0 on rising edge, interrupt enable. */
|
||||
LPC_CT32B0->CCR = (0x5<<0)|(0x5<<6);
|
||||
#endif
|
||||
LPC_CT32B0->MCR = 3; /* Interrupt and Reset on MR0 */
|
||||
|
||||
/* Enable the TIMER0 Interrupt */
|
||||
#if NMI_ENABLED
|
||||
NVIC_DisableIRQ( CT32B0_IRQn );
|
||||
NMI_Init( CT32B0_IRQn );
|
||||
#else
|
||||
NVIC_EnableIRQ(CT32B0_IRQn);
|
||||
#endif
|
||||
}
|
||||
else if ( timer_num == 1 )
|
||||
{
|
||||
/* Some of the I/O pins need to be clearfully planned if
|
||||
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10);
|
||||
|
||||
LPC_CT32B1->MR0 = TimerInterval;
|
||||
#if TIMER_MATCH
|
||||
for ( i = 0; i < 4; i++ )
|
||||
{
|
||||
timer32_1_counter[i] = 0;
|
||||
}
|
||||
set_timer32_match(timer_num, 0x0F, 0);
|
||||
LPC_CT32B1->EMR &= ~(0xFF<<4);
|
||||
LPC_CT32B1->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8)|(0x3<<10)); /* MR0/1/2 Toggle */
|
||||
#else
|
||||
for ( i = 0; i < 4; i++ )
|
||||
{
|
||||
timer32_1_capture[i] = 0;
|
||||
}
|
||||
set_timer32_capture(timer_num, 0 );
|
||||
/* Capture 0 on rising edge, interrupt enable. */
|
||||
LPC_CT32B1->CCR = (0x5<<0)|(0x5<<3);
|
||||
#endif
|
||||
LPC_CT32B1->MCR = 3; /* Interrupt and Reset on MR0 */
|
||||
|
||||
/* Enable the TIMER1 Interrupt */
|
||||
#if NMI_ENABLED
|
||||
NVIC_DisableIRQ( CT32B1_IRQn );
|
||||
NMI_Init( CT32B1_IRQn );
|
||||
#else
|
||||
NVIC_EnableIRQ(CT32B1_IRQn);
|
||||
#endif
|
||||
}
|
||||
return;
|
||||
}
|
||||
/******************************************************************************
|
||||
** Function name: init_timer32PWM
|
||||
**
|
||||
** Descriptions: Initialize timer as PWM
|
||||
**
|
||||
** parameters: timer number, period and match enable:
|
||||
** match_enable[0] = PWM for MAT0
|
||||
** match_enable[1] = PWM for MAT1
|
||||
** match_enable[2] = PWM for MAT2
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void init_timer32PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable)
|
||||
{
|
||||
disable_timer32(timer_num);
|
||||
if (timer_num == 1)
|
||||
{
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10);
|
||||
|
||||
/* Setup the external match register */
|
||||
LPC_CT32B1->EMR = (1<<EMC3)|(1<<EMC2)|(2<<EMC1)|(1<<EMC0)|MATCH3|(match_enable);
|
||||
|
||||
/* Setup the outputs */
|
||||
/* If match0 is enabled, set the output, use location 0 for test. */
|
||||
set_timer32_match( timer_num, match_enable, 0 );
|
||||
|
||||
/* Enable the selected PWMs and enable Match3 */
|
||||
LPC_CT32B1->PWMC = MATCH3|(match_enable);
|
||||
|
||||
/* Setup the match registers */
|
||||
/* set the period value to a global variable */
|
||||
timer32_1_period = period;
|
||||
LPC_CT32B1->MR3 = timer32_1_period;
|
||||
LPC_CT32B1->MR0 = timer32_1_period/2;
|
||||
LPC_CT32B1->MR1 = timer32_1_period/2;
|
||||
LPC_CT32B1->MR2 = timer32_1_period/2;
|
||||
LPC_CT32B1->MCR = 1<<10; /* Reset on MR3 */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Some of the I/O pins need to be clearfully planned if
|
||||
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<9);
|
||||
|
||||
/* Setup the external match register */
|
||||
LPC_CT32B0->EMR = (1<<EMC3)|(2<<EMC2)|(1<<EMC1)|(1<<EMC0)|MATCH3|(match_enable);
|
||||
|
||||
/* Setup the outputs */
|
||||
/* If match0 is enabled, set the output, use location 0 for test. */
|
||||
set_timer32_match( timer_num, match_enable, 0 );
|
||||
|
||||
/* Enable the selected PWMs and enable Match3 */
|
||||
LPC_CT32B0->PWMC = MATCH3|(match_enable);
|
||||
|
||||
/* Setup the match registers */
|
||||
/* set the period value to a global variable */
|
||||
timer32_0_period = period;
|
||||
LPC_CT32B0->MR3 = timer32_0_period;
|
||||
LPC_CT32B0->MR0 = timer32_0_period/2;
|
||||
LPC_CT32B0->MR1 = timer32_0_period/2;
|
||||
LPC_CT32B0->MR2 = timer32_0_period/2;
|
||||
LPC_CT32B0->MCR = 1<<10; /* Reset on MR3 */
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** Function name: pwm32_setMatch
|
||||
**
|
||||
** Descriptions: Set the pwm32 match values
|
||||
**
|
||||
** parameters: timer number, match numner and the value
|
||||
**
|
||||
** Returned value: None
|
||||
**
|
||||
******************************************************************************/
|
||||
void setMatch_timer32PWM (uint8_t timer_num, uint8_t match_nr, uint32_t value)
|
||||
{
|
||||
if (timer_num)
|
||||
{
|
||||
switch (match_nr)
|
||||
{
|
||||
case 0:
|
||||
LPC_CT32B1->MR0 = value;
|
||||
break;
|
||||
case 1:
|
||||
LPC_CT32B1->MR1 = value;
|
||||
break;
|
||||
case 2:
|
||||
LPC_CT32B1->MR2 = value;
|
||||
break;
|
||||
case 3:
|
||||
LPC_CT32B1->MR3 = value;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (match_nr)
|
||||
{
|
||||
case 0:
|
||||
LPC_CT32B0->MR0 = value;
|
||||
break;
|
||||
case 1:
|
||||
LPC_CT32B0->MR1 = value;
|
||||
break;
|
||||
case 2:
|
||||
LPC_CT32B0->MR2 = value;
|
||||
break;
|
||||
case 3:
|
||||
LPC_CT32B0->MR3 = value;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@@ -1,437 +0,0 @@
|
||||
/****************************************************************************
|
||||
* $Id:: uart.c 7125 2011-04-15 00:22:12Z usb01267 $
|
||||
* Project: NXP LPC13Uxx UART example
|
||||
*
|
||||
* Description:
|
||||
* This file contains UART code example which include UART
|
||||
* initialization, UART interrupt handler, and related APIs for
|
||||
* UART access.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
****************************************************************************/
|
||||
#include "LPC13Uxx.h"
|
||||
#include "type.h"
|
||||
#include "uart.h"
|
||||
|
||||
volatile uint32_t UARTStatus;
|
||||
volatile uint8_t UARTTxEmpty = 1;
|
||||
volatile uint8_t UARTBuffer[BUFSIZE];
|
||||
volatile uint32_t UARTCount = 0;
|
||||
|
||||
#if AUTOBAUD_ENABLE
|
||||
volatile uint32_t UARTAutoBaud = 0, AutoBaudTimeout = 0;
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: USART_IRQHandler
|
||||
**
|
||||
** Descriptions: USART interrupt handler
|
||||
**
|
||||
** parameters: None
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void USART_IRQHandler(void)
|
||||
{
|
||||
uint8_t IIRValue, LSRValue;
|
||||
uint8_t Dummy = Dummy;
|
||||
|
||||
IIRValue = LPC_USART->IIR;
|
||||
|
||||
IIRValue >>= 1; /* skip pending bit in IIR */
|
||||
IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
|
||||
if (IIRValue == IIR_RLS) /* Receive Line Status */
|
||||
{
|
||||
LSRValue = LPC_USART->LSR;
|
||||
/* Receive Line Status */
|
||||
if (LSRValue & (LSR_OE | LSR_PE | LSR_FE | LSR_RXFE | LSR_BI))
|
||||
{
|
||||
/* There are errors or break interrupt */
|
||||
/* Read LSR will clear the interrupt */
|
||||
UARTStatus = LSRValue;
|
||||
Dummy = LPC_USART->RBR; /* Dummy read on RX to clear
|
||||
interrupt, then bail out */
|
||||
return;
|
||||
}
|
||||
if (LSRValue & LSR_RDR) /* Receive Data Ready */
|
||||
{
|
||||
/* If no error on RLS, normal ready, save into the data buffer. */
|
||||
/* Note: read RBR will clear the interrupt */
|
||||
UARTBuffer[UARTCount++] = LPC_USART->RBR;
|
||||
if (UARTCount == BUFSIZE)
|
||||
{
|
||||
UARTCount = 0; /* buffer overflow */
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (IIRValue == IIR_RDA) /* Receive Data Available */
|
||||
{
|
||||
/* Receive Data Available */
|
||||
UARTBuffer[UARTCount++] = LPC_USART->RBR;
|
||||
if (UARTCount == BUFSIZE)
|
||||
{
|
||||
UARTCount = 0; /* buffer overflow */
|
||||
}
|
||||
}
|
||||
else if (IIRValue == IIR_CTI) /* Character timeout indicator */
|
||||
{
|
||||
/* Character Time-out indicator */
|
||||
UARTStatus |= 0x100; /* Bit 9 as the CTI error */
|
||||
}
|
||||
else if (IIRValue == IIR_THRE) /* THRE, transmit holding register empty */
|
||||
{
|
||||
/* THRE interrupt */
|
||||
LSRValue = LPC_USART->LSR; /* Check status in the LSR to see if
|
||||
valid data in U0THR or not */
|
||||
if (LSRValue & LSR_THRE)
|
||||
{
|
||||
UARTTxEmpty = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
UARTTxEmpty = 0;
|
||||
}
|
||||
}
|
||||
#if AUTOBAUD_ENABLE
|
||||
if (LPC_USART->IIR & IIR_ABEO) /* End of Auto baud */
|
||||
{
|
||||
LPC_USART->IER &= ~IIR_ABEO;
|
||||
/* clear bit ABEOInt in the IIR by set ABEOIntClr in the ACR register */
|
||||
LPC_USART->ACR |= IIR_ABEO;
|
||||
UARTAutoBaud = 1;
|
||||
}
|
||||
else if (LPC_USART->IIR & IIR_ABTO)/* Auto baud time out */
|
||||
{
|
||||
LPC_USART->IER &= ~IIR_ABTO;
|
||||
AutoBaudTimeout = 1;
|
||||
/* clear bit ABTOInt in the IIR by set ABTOIntClr in the ACR register */
|
||||
LPC_USART->ACR |= IIR_ABTO;
|
||||
}
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
#if MODEM_TEST
|
||||
/*****************************************************************************
|
||||
** Function name: ModemInit
|
||||
**
|
||||
** Descriptions: Initialize UART0 port as modem, setup pin select.
|
||||
**
|
||||
** parameters: None
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void ModemInit( void )
|
||||
{
|
||||
|
||||
LPC_IOCON->PIO0_7 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO0_7 |= 0x01; /* UART CTS */
|
||||
LPC_IOCON->PIO0_17 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO0_17 |= 0x01; /* UART RTS */
|
||||
#if 1
|
||||
LPC_IOCON->PIO1_13 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_13 |= 0x01; /* UART DTR */
|
||||
LPC_IOCON->PIO1_14 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_14 |= 0x01; /* UART DSR */
|
||||
LPC_IOCON->PIO1_15 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_15 |= 0x01; /* UART DCD */
|
||||
LPC_IOCON->PIO1_16 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_16 |= 0x01; /* UART RI */
|
||||
|
||||
#else
|
||||
LPC_IOCON->PIO1_19 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_19 |= 0x01; /* UART DTR */
|
||||
LPC_IOCON->PIO1_20 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_20 |= 0x01; /* UART DSR */
|
||||
LPC_IOCON->PIO1_21 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_21 |= 0x01; /* UART DCD */
|
||||
LPC_IOCON->PIO1_22 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_22 |= 0x01; /* UART RI */
|
||||
#endif
|
||||
LPC_USART->MCR = 0xC0; /* Enable Auto RTS and Auto CTS. */
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
/***********************************************************************
|
||||
*
|
||||
* Function: uart_set_divisors
|
||||
*
|
||||
* Purpose: Determines best dividers to get a target clock rate
|
||||
*
|
||||
* Processing:
|
||||
* See function.
|
||||
*
|
||||
* Parameters:
|
||||
* UARTClk : UART clock
|
||||
* baudrate : Desired UART baud rate
|
||||
*
|
||||
* Outputs:
|
||||
* baudrate : Sets the estimated buadrate value in DLL, DLM, and FDR.
|
||||
*
|
||||
* Returns: Error status.
|
||||
*
|
||||
* Notes: None
|
||||
*
|
||||
**********************************************************************/
|
||||
uint32_t uart_set_divisors(uint32_t UARTClk, uint32_t baudrate)
|
||||
{
|
||||
uint32_t uClk;
|
||||
uint32_t calcBaudrate = 0;
|
||||
uint32_t temp = 0;
|
||||
|
||||
uint32_t mulFracDiv, dividerAddFracDiv;
|
||||
uint32_t diviser = 0 ;
|
||||
uint32_t mulFracDivOptimal = 1;
|
||||
uint32_t dividerAddOptimal = 0;
|
||||
uint32_t diviserOptimal = 0;
|
||||
|
||||
uint32_t relativeError = 0;
|
||||
uint32_t relativeOptimalError = 100000;
|
||||
|
||||
/* get UART block clock */
|
||||
uClk = UARTClk >> 4; /* div by 16 */
|
||||
/* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
|
||||
* The formula is :
|
||||
* BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
|
||||
* It involves floating point calculations. That's the reason the formulae are adjusted with
|
||||
* Multiply and divide method.*/
|
||||
/* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
|
||||
* 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
|
||||
for (mulFracDiv = 1; mulFracDiv <= 15; mulFracDiv++)
|
||||
{
|
||||
for (dividerAddFracDiv = 0; dividerAddFracDiv <= 15; dividerAddFracDiv++)
|
||||
{
|
||||
temp = (mulFracDiv * uClk) / ((mulFracDiv + dividerAddFracDiv));
|
||||
diviser = temp / baudrate;
|
||||
if ((temp % baudrate) > (baudrate / 2))
|
||||
diviser++;
|
||||
|
||||
if (diviser > 2 && diviser < 65536)
|
||||
{
|
||||
calcBaudrate = temp / diviser;
|
||||
|
||||
if (calcBaudrate <= baudrate)
|
||||
relativeError = baudrate - calcBaudrate;
|
||||
else
|
||||
relativeError = calcBaudrate - baudrate;
|
||||
|
||||
if ((relativeError < relativeOptimalError))
|
||||
{
|
||||
mulFracDivOptimal = mulFracDiv ;
|
||||
dividerAddOptimal = dividerAddFracDiv;
|
||||
diviserOptimal = diviser;
|
||||
relativeOptimalError = relativeError;
|
||||
if (relativeError == 0)
|
||||
break;
|
||||
}
|
||||
} /* End of if */
|
||||
} /* end of inner for loop */
|
||||
if (relativeError == 0)
|
||||
break;
|
||||
} /* end of outer for loop */
|
||||
|
||||
if (relativeOptimalError < (baudrate / 30))
|
||||
{
|
||||
/* Set the `Divisor Latch Access Bit` and enable so the DLL/DLM access*/
|
||||
/* Initialise the `Divisor latch LSB` and `Divisor latch MSB` registers */
|
||||
LPC_USART->DLM = (diviserOptimal >> 8) & 0xFF;
|
||||
LPC_USART->DLL = diviserOptimal & 0xFF;
|
||||
|
||||
/* Initialise the Fractional Divider Register */
|
||||
LPC_USART->FDR = ((mulFracDivOptimal & 0xF) << 4) | (dividerAddOptimal & 0xF);
|
||||
return( TRUE );
|
||||
}
|
||||
return ( FALSE );
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: UARTInit
|
||||
**
|
||||
** Descriptions: Initialize UART0 port, setup pin select,
|
||||
** clock, parity, stop bits, FIFO, etc.
|
||||
**
|
||||
** parameters: UART baudrate
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void UARTInit(uint32_t baudrate)
|
||||
{
|
||||
#if !AUTOBAUD_ENABLE
|
||||
uint32_t Fdiv;
|
||||
#endif
|
||||
volatile uint32_t regVal;
|
||||
|
||||
UARTTxEmpty = 1;
|
||||
UARTCount = 0;
|
||||
|
||||
NVIC_DisableIRQ(USART_IRQn);
|
||||
/* Select only one location from below. */
|
||||
#if 1
|
||||
LPC_IOCON->PIO0_18 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO0_18 |= 0x01; /* UART RXD */
|
||||
LPC_IOCON->PIO0_19 &= ~0x07;
|
||||
LPC_IOCON->PIO0_19 |= 0x01; /* UART TXD */
|
||||
#endif
|
||||
#if 0
|
||||
LPC_IOCON->PIO1_14 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_14 |= 0x03; /* UART RXD */
|
||||
LPC_IOCON->PIO1_13 &= ~0x07;
|
||||
LPC_IOCON->PIO1_13 |= 0x03; /* UART TXD */
|
||||
#endif
|
||||
#if 0
|
||||
LPC_IOCON->PIO1_17 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_17 |= 0x02; /* UART RXD */
|
||||
LPC_IOCON->PIO1_18 &= ~0x07;
|
||||
LPC_IOCON->PIO1_18 |= 0x02; /* UART TXD */
|
||||
#endif
|
||||
#if 0
|
||||
LPC_IOCON->PIO1_26 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_26 |= 0x02; /* UART RXD */
|
||||
LPC_IOCON->PIO1_27 &= ~0x07;
|
||||
LPC_IOCON->PIO1_27 |= 0x02; /* UART TXD */
|
||||
#endif
|
||||
|
||||
/* Enable UART clock */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
|
||||
LPC_SYSCON->UARTCLKDIV = 0x1; /* divided by 1 */
|
||||
|
||||
LPC_USART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
|
||||
#if !AUTOBAUD_ENABLE
|
||||
#if FDR_CALIBRATION
|
||||
if ( uart_set_divisors(SystemCoreClock/LPC_SYSCON->UARTCLKDIV, baudrate) != TRUE )
|
||||
{
|
||||
Fdiv = ((SystemCoreClock/LPC_SYSCON->UARTCLKDIV)/16)/baudrate ; /*baud rate */
|
||||
LPC_USART->DLM = Fdiv / 256;
|
||||
LPC_USART->DLL = Fdiv % 256;
|
||||
LPC_USART->FDR = 0x10; /* Default */
|
||||
}
|
||||
#else
|
||||
Fdiv = ((SystemCoreClock/LPC_SYSCON->UARTCLKDIV)/16)/baudrate ; /*baud rate */
|
||||
LPC_USART->DLM = Fdiv / 256;
|
||||
LPC_USART->DLL = Fdiv % 256;
|
||||
LPC_USART->FDR = 0x10; /* Default */
|
||||
#endif
|
||||
#endif
|
||||
LPC_USART->LCR = 0x03; /* DLAB = 0 */
|
||||
LPC_USART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
|
||||
|
||||
/* Read to clear the line status. */
|
||||
regVal = LPC_USART->LSR;
|
||||
|
||||
/* Ensure a clean start, no data in either TX or RX FIFO. */
|
||||
while (( LPC_USART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
|
||||
while ( LPC_USART->LSR & LSR_RDR )
|
||||
{
|
||||
regVal = LPC_USART->RBR; /* Dump data from RX FIFO */
|
||||
}
|
||||
|
||||
/* Enable the UART Interrupt */
|
||||
NVIC_EnableIRQ(USART_IRQn);
|
||||
|
||||
#if TX_INTERRUPT
|
||||
LPC_USART->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */
|
||||
#else
|
||||
LPC_USART->IER = IER_RBR | IER_RLS; /* Enable UART interrupt */
|
||||
#endif
|
||||
#if AUTOBAUD_ENABLE
|
||||
LPC_USART->IER |= IER_ABEO | IER_ABTO;
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: UARTSend
|
||||
**
|
||||
** Descriptions: Send a block of data to the UART 0 port based
|
||||
** on the data length
|
||||
**
|
||||
** parameters: buffer pointer, and data length
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void UARTSend(uint8_t *BufferPtr, uint32_t Length)
|
||||
{
|
||||
|
||||
while ( Length != 0 )
|
||||
{
|
||||
/* THRE status, contain valid data */
|
||||
#if !TX_INTERRUPT
|
||||
while ( !(LPC_USART->LSR & LSR_THRE) );
|
||||
LPC_USART->THR = *BufferPtr;
|
||||
#else
|
||||
/* Below flag is set inside the interrupt handler when THRE occurs. */
|
||||
while ( !(UARTTxEmpty & 0x01) );
|
||||
LPC_USART->THR = *BufferPtr;
|
||||
UARTTxEmpty = 0; /* not empty in the THR until it shifts out */
|
||||
#endif
|
||||
BufferPtr++;
|
||||
Length--;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: print_string
|
||||
**
|
||||
** Descriptions: print out string on the terminal
|
||||
**
|
||||
** parameters: pointer to the string end with NULL char.
|
||||
** Returned value: none.
|
||||
**
|
||||
*****************************************************************************/
|
||||
void print_string( uint8_t *str_ptr )
|
||||
{
|
||||
while(*str_ptr != 0x00)
|
||||
{
|
||||
while((LPC_USART->LSR & 0x60) != 0x60);
|
||||
LPC_USART->THR = *str_ptr;
|
||||
str_ptr++;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: get_key
|
||||
**
|
||||
** Descriptions: Get a character from the terminal
|
||||
**
|
||||
** parameters: None
|
||||
** Returned value: character, zero is none.
|
||||
**
|
||||
*****************************************************************************/
|
||||
uint8_t get_key( void )
|
||||
{
|
||||
uint8_t dummy;
|
||||
|
||||
while ( !(LPC_USART->LSR & 0x01) );
|
||||
dummy = LPC_USART->RBR;
|
||||
if ((dummy>=65) && (dummy<=90))
|
||||
{
|
||||
/* convert capital to non-capital character, A2a, B2b, C2c. */
|
||||
dummy +=32;
|
||||
}
|
||||
/* echo */
|
||||
LPC_USART->THR = dummy;
|
||||
return(dummy);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
@@ -1,83 +0,0 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file hal_lpc13uxx.c
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#include "common/tusb_common.h"
|
||||
#include "hal.h"
|
||||
|
||||
#if CFG_TUSB_MCU == OPT_MCU_LPC13UXX
|
||||
|
||||
void tusb_hal_int_enable(uint8_t rhport)
|
||||
{
|
||||
(void) rhport; // discard compiler's warning
|
||||
NVIC_EnableIRQ(USB_IRQ_IRQn);
|
||||
}
|
||||
|
||||
void tusb_hal_int_disable(uint8_t rhport)
|
||||
{
|
||||
(void) rhport; // discard compiler's warning
|
||||
NVIC_DisableIRQ(USB_IRQ_IRQn);
|
||||
}
|
||||
|
||||
bool tusb_hal_init(void)
|
||||
{
|
||||
// TODO remove magic number
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= ((0x1<<14) | (0x1<<27)); /* Enable AHB clock to the USB block and USB RAM. */
|
||||
LPC_SYSCON->PDRUNCFG &= ~( BIT_(8) | BIT_(10) ); // enable USB PLL & USB transceiver
|
||||
|
||||
/* Pull-down is needed, or internally, VBUS will be floating. This is to
|
||||
address the wrong status in VBUSDebouncing bit in CmdStatus register. */
|
||||
// set PIO0_3 as USB_VBUS
|
||||
LPC_IOCON->PIO0_3 &= ~0x1F;
|
||||
LPC_IOCON->PIO0_3 |= (0x01<<0) | (1 << 3); /* Secondary function VBUS */
|
||||
|
||||
// set PIO0_6 as usb connect
|
||||
LPC_IOCON->PIO0_6 &= ~0x07;
|
||||
LPC_IOCON->PIO0_6 |= (0x01<<0); /* Secondary function SoftConn */
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void USB_IRQHandler(void)
|
||||
{
|
||||
hal_dcd_isr(0);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@@ -1,54 +0,0 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file hal_lpc13uxx.h
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef _TUSB_HAL_MCU_H_
|
||||
#define _TUSB_HAL_MCU_H_
|
||||
|
||||
#include "LPC13Uxx.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_HAL_MCU_H_ */
|
||||
|
||||
@@ -1,24 +0,0 @@
|
||||
History of updates to CMSIS_CORE_LPC17xx
|
||||
===========================================
|
||||
|
||||
18 July 2013
|
||||
------------
|
||||
CMSIS library project using ARM Cortex-M0 CMSIS files as
|
||||
supplied in ARM's CMSIS 3.20 March 2013 release, together
|
||||
with NXP's device specific files taken from old
|
||||
CMSISv2p00_LPC17xx project.
|
||||
|
||||
Note files are built -Os for both Debug and Release
|
||||
|
||||
|
||||
History of updates to CMSISv2p00_LPC17xx
|
||||
========================================
|
||||
|
||||
7 March 2011
|
||||
------------
|
||||
LPC17xx CMSIS 2.0 library project using ARM
|
||||
Cortex-M3 CMSIS files as supplied in ARM's CMSIS 2.0
|
||||
December 2010 release, together with device/board
|
||||
specific files from NXP (as previously supplied in
|
||||
CMSISv1p30_LPC17xx library project, dated 24 Aug 2010).
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,64 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_LPC17xx.h
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
|
||||
* for the NXP LPC17xx Device Series
|
||||
* @version V1.02
|
||||
* @date 08. September 2009
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_LPC17xx_H
|
||||
#define __SYSTEM_LPC17xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_LPC17xx_H */
|
||||
@@ -1,32 +0,0 @@
|
||||
<!-- liblinks.xml
|
||||
|
||||
LPCXpresso "Smart update wizard" script file
|
||||
When executed on a particular application project, will
|
||||
add appropriate links to the specified library project.
|
||||
|
||||
Note that this script assumes that the application project
|
||||
contains the standard 'Debug' and 'Release' build
|
||||
configurations.
|
||||
-->
|
||||
|
||||
<project name="" update="true">
|
||||
<setting id="all.compiler.inc">
|
||||
<value>${workspace_loc:/CMSIS_CORE_LPC17xx/inc}</value>
|
||||
</setting>
|
||||
<setting id="all.compiler.def">
|
||||
<value>__USE_CMSIS=CMSIS_CORE_LPC17xx</value>
|
||||
</setting>
|
||||
<setting id="linker.libs">
|
||||
<value>CMSIS_CORE_LPC17xx</value>
|
||||
</setting>
|
||||
<setting id="linker.paths" buildType="Debug">
|
||||
<value>${workspace_loc:/CMSIS_CORE_LPC17xx/Debug}</value>
|
||||
</setting>
|
||||
<setting id="linker.paths" buildType="Release">
|
||||
<value>${workspace_loc:/CMSIS_CORE_LPC17xx/Release}</value>
|
||||
</setting>
|
||||
<requires msg="Library project `CMSIS_CORE_LPC17xx` not found">
|
||||
<value>CMSIS_CORE_LPC17xx</value>
|
||||
</requires>
|
||||
</project>
|
||||
|
||||
@@ -1,532 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_LPC17xx.c
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
|
||||
* for the NXP LPC17xx Device Series
|
||||
* @version V1.08
|
||||
* @date 12. May 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include "LPC17xx.h"
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
/*--------------------- Clock Configuration ----------------------------------
|
||||
//
|
||||
// <e> Clock Configuration
|
||||
// <h> System Controls and Status Register (SCS)
|
||||
// <o1.4> OSCRANGE: Main Oscillator Range Select
|
||||
// <0=> 1 MHz to 20 MHz
|
||||
// <1=> 15 MHz to 24 MHz
|
||||
// <e1.5> OSCEN: Main Oscillator Enable
|
||||
// </e>
|
||||
// </h>
|
||||
//
|
||||
// <h> Clock Source Select Register (CLKSRCSEL)
|
||||
// <o2.0..1> CLKSRC: PLL Clock Source Selection
|
||||
// <0=> Internal RC oscillator
|
||||
// <1=> Main oscillator
|
||||
// <2=> RTC oscillator
|
||||
// </h>
|
||||
//
|
||||
// <e3> PLL0 Configuration (Main PLL)
|
||||
// <h> PLL0 Configuration Register (PLL0CFG)
|
||||
// <i> F_cco0 = (2 * M * F_in) / N
|
||||
// <i> F_in must be in the range of 32 kHz to 50 MHz
|
||||
// <i> F_cco0 must be in the range of 275 MHz to 550 MHz
|
||||
// <o4.0..14> MSEL: PLL Multiplier Selection
|
||||
// <6-32768><#-1>
|
||||
// <i> M Value
|
||||
// <o4.16..23> NSEL: PLL Divider Selection
|
||||
// <1-256><#-1>
|
||||
// <i> N Value
|
||||
// </h>
|
||||
// </e>
|
||||
//
|
||||
// <e5> PLL1 Configuration (USB PLL)
|
||||
// <h> PLL1 Configuration Register (PLL1CFG)
|
||||
// <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
|
||||
// <i> F_cco1 = F_osc * M * 2 * P
|
||||
// <i> F_cco1 must be in the range of 156 MHz to 320 MHz
|
||||
// <o6.0..4> MSEL: PLL Multiplier Selection
|
||||
// <1-32><#-1>
|
||||
// <i> M Value (for USB maximum value is 4)
|
||||
// <o6.5..6> PSEL: PLL Divider Selection
|
||||
// <0=> 1
|
||||
// <1=> 2
|
||||
// <2=> 4
|
||||
// <3=> 8
|
||||
// <i> P Value
|
||||
// </h>
|
||||
// </e>
|
||||
//
|
||||
// <h> CPU Clock Configuration Register (CCLKCFG)
|
||||
// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
|
||||
// <1-256><#-1>
|
||||
// </h>
|
||||
//
|
||||
// <h> USB Clock Configuration Register (USBCLKCFG)
|
||||
// <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
|
||||
// <0-15>
|
||||
// <i> Divide is USBSEL + 1
|
||||
// </h>
|
||||
//
|
||||
// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
|
||||
// <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 6
|
||||
// <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 6
|
||||
// <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 6
|
||||
// </h>
|
||||
//
|
||||
// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
|
||||
// <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// </h>
|
||||
//
|
||||
// <h> Power Control for Peripherals Register (PCONP)
|
||||
// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
|
||||
// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
|
||||
// <o11.3> PCUART0: UART 0 power/clock enable
|
||||
// <o11.4> PCUART1: UART 1 power/clock enable
|
||||
// <o11.6> PCPWM1: PWM 1 power/clock enable
|
||||
// <o11.7> PCI2C0: I2C interface 0 power/clock enable
|
||||
// <o11.8> PCSPI: SPI interface power/clock enable
|
||||
// <o11.9> PCRTC: RTC power/clock enable
|
||||
// <o11.10> PCSSP1: SSP interface 1 power/clock enable
|
||||
// <o11.12> PCAD: A/D converter power/clock enable
|
||||
// <o11.13> PCCAN1: CAN controller 1 power/clock enable
|
||||
// <o11.14> PCCAN2: CAN controller 2 power/clock enable
|
||||
// <o11.15> PCGPIO: GPIOs power/clock enable
|
||||
// <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
|
||||
// <o11.17> PCMC: Motor control PWM power/clock enable
|
||||
// <o11.18> PCQEI: Quadrature encoder interface power/clock enable
|
||||
// <o11.19> PCI2C1: I2C interface 1 power/clock enable
|
||||
// <o11.21> PCSSP0: SSP interface 0 power/clock enable
|
||||
// <o11.22> PCTIM2: Timer 2 power/clock enable
|
||||
// <o11.23> PCTIM3: Timer 3 power/clock enable
|
||||
// <o11.24> PCUART2: UART 2 power/clock enable
|
||||
// <o11.25> PCUART3: UART 3 power/clock enable
|
||||
// <o11.26> PCI2C2: I2C interface 2 power/clock enable
|
||||
// <o11.27> PCI2S: I2S interface power/clock enable
|
||||
// <o11.29> PCGPDMA: GP DMA function power/clock enable
|
||||
// <o11.30> PCENET: Ethernet block power/clock enable
|
||||
// <o11.31> PCUSB: USB interface power/clock enable
|
||||
// </h>
|
||||
//
|
||||
// <h> Clock Output Configuration Register (CLKOUTCFG)
|
||||
// <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
|
||||
// <0=> CPU clock
|
||||
// <1=> Main oscillator
|
||||
// <2=> Internal RC oscillator
|
||||
// <3=> USB clock
|
||||
// <4=> RTC oscillator
|
||||
// <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
|
||||
// <1-16><#-1>
|
||||
// <o12.8> CLKOUT_EN: CLKOUT enable control
|
||||
// </h>
|
||||
//
|
||||
// </e>
|
||||
*/
|
||||
#define CLOCK_SETUP 1
|
||||
#define SCS_Val 0x00000020
|
||||
#define CLKSRCSEL_Val 0x00000001
|
||||
#define PLL0_SETUP 1
|
||||
#define PLL0CFG_Val 0x00050063
|
||||
#define PLL1_SETUP 1
|
||||
#define PLL1CFG_Val 0x00000023
|
||||
#define CCLKCFG_Val 0x00000003
|
||||
#define USBCLKCFG_Val 0x00000000
|
||||
#define PCLKSEL0_Val 0x00000000
|
||||
#define PCLKSEL1_Val 0x00000000
|
||||
#define PCONP_Val 0x042887DE
|
||||
#define CLKOUTCFG_Val 0x00000000
|
||||
|
||||
|
||||
/*--------------------- Flash Accelerator Configuration ----------------------
|
||||
//
|
||||
// <e> Flash Accelerator Configuration
|
||||
// <o1.12..15> FLASHTIM: Flash Access Time
|
||||
// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
|
||||
// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
|
||||
// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
|
||||
// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
|
||||
// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
|
||||
// <5=> 6 CPU clocks (for any CPU clock)
|
||||
// </e>
|
||||
*/
|
||||
#define FLASH_SETUP 1
|
||||
#define FLASHCFG_Val 0x00004000
|
||||
|
||||
/*
|
||||
//-------- <<< end of configuration section >>> ------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Check the register settings
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
||||
#define CHECK_RSVD(val, mask) (val & mask)
|
||||
|
||||
/* Clock Configuration -------------------------------------------------------*/
|
||||
#if (CHECK_RSVD((SCS_Val), ~0x00000030))
|
||||
#error "SCS: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
|
||||
#error "CLKSRCSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
|
||||
#error "PLL0CFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
|
||||
#error "PLL1CFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (PLL0_SETUP) /* if PLL0 is used */
|
||||
#if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */
|
||||
#error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((CCLKCFG_Val), 2, 255))
|
||||
#error "CCLKCFG: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
|
||||
#error "USBCLKCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
|
||||
#error "PCLKSEL0: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
|
||||
#error "PCLKSEL1: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCONP_Val), 0x10100821))
|
||||
#error "PCONP: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
|
||||
#error "CLKOUTCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
/* Flash Accelerator Configuration -------------------------------------------*/
|
||||
#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
|
||||
#error "FLASHCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define XTAL (12000000UL) /* Oscillator frequency */
|
||||
#define OSC_CLK ( XTAL) /* Main oscillator frequency */
|
||||
#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
|
||||
#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
|
||||
|
||||
|
||||
/* F_cco0 = (2 * M * F_in) / N */
|
||||
#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
|
||||
#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
|
||||
#define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N)
|
||||
#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
|
||||
|
||||
/* Determine core clock frequency according to settings */
|
||||
#if (PLL0_SETUP)
|
||||
#if ((CLKSRCSEL_Val & 0x03) == 1)
|
||||
#define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
|
||||
#elif ((CLKSRCSEL_Val & 0x03) == 2)
|
||||
#define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
|
||||
#else
|
||||
#define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
|
||||
#endif
|
||||
#else
|
||||
#if ((CLKSRCSEL_Val & 0x03) == 1)
|
||||
#define __CORE_CLK (OSC_CLK / __CCLK_DIV)
|
||||
#elif ((CLKSRCSEL_Val & 0x03) == 2)
|
||||
#define __CORE_CLK (RTC_CLK / __CCLK_DIV)
|
||||
#else
|
||||
#define __CORE_CLK (IRC_OSC / __CCLK_DIV)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
/* Determine clock frequency according to clock register values */
|
||||
if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
|
||||
switch (LPC_SC->CLKSRCSEL & 0x03) {
|
||||
case 0: /* Int. RC oscillator => PLL0 */
|
||||
case 3: /* Reserved, default to Int. RC */
|
||||
SystemCoreClock = (IRC_OSC *
|
||||
((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
|
||||
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
|
||||
((LPC_SC->CCLKCFG & 0xFF)+ 1));
|
||||
break;
|
||||
case 1: /* Main oscillator => PLL0 */
|
||||
SystemCoreClock = (OSC_CLK *
|
||||
((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
|
||||
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
|
||||
((LPC_SC->CCLKCFG & 0xFF)+ 1));
|
||||
break;
|
||||
case 2: /* RTC oscillator => PLL0 */
|
||||
SystemCoreClock = (RTC_CLK *
|
||||
((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
|
||||
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
|
||||
((LPC_SC->CCLKCFG & 0xFF)+ 1));
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (LPC_SC->CLKSRCSEL & 0x03) {
|
||||
case 0: /* Int. RC oscillator => PLL0 */
|
||||
case 3: /* Reserved, default to Int. RC */
|
||||
SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
|
||||
break;
|
||||
case 1: /* Main oscillator => PLL0 */
|
||||
SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
|
||||
break;
|
||||
case 2: /* RTC oscillator => PLL0 */
|
||||
SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
LPC_SC->SCS = SCS_Val;
|
||||
if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
|
||||
while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
|
||||
}
|
||||
|
||||
LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
|
||||
|
||||
LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
|
||||
LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
|
||||
|
||||
LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
|
||||
|
||||
#if (PLL0_SETUP)
|
||||
LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */
|
||||
LPC_SC->PLL0FEED = 0xAA;
|
||||
LPC_SC->PLL0FEED = 0x55;
|
||||
|
||||
LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
|
||||
LPC_SC->PLL0FEED = 0xAA;
|
||||
LPC_SC->PLL0FEED = 0x55;
|
||||
while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
|
||||
|
||||
LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
|
||||
LPC_SC->PLL0FEED = 0xAA;
|
||||
LPC_SC->PLL0FEED = 0x55;
|
||||
while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
|
||||
#endif
|
||||
|
||||
#if (PLL1_SETUP)
|
||||
LPC_SC->PLL1CFG = PLL1CFG_Val;
|
||||
LPC_SC->PLL1FEED = 0xAA;
|
||||
LPC_SC->PLL1FEED = 0x55;
|
||||
|
||||
LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
|
||||
LPC_SC->PLL1FEED = 0xAA;
|
||||
LPC_SC->PLL1FEED = 0x55;
|
||||
while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
|
||||
|
||||
LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
|
||||
LPC_SC->PLL1FEED = 0xAA;
|
||||
LPC_SC->PLL1FEED = 0x55;
|
||||
while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
|
||||
#else
|
||||
LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
|
||||
#endif
|
||||
|
||||
LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
|
||||
|
||||
LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
|
||||
#endif
|
||||
|
||||
#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
|
||||
LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val;
|
||||
#endif
|
||||
}
|
||||
@@ -1,80 +0,0 @@
|
||||
/**********************************************************************
|
||||
* $Id$ debug_frmwrk.h 2010-05-21
|
||||
*//**
|
||||
* @file debug_frmwrk.h
|
||||
* @brief Contains some utilities that used for debugging through UART
|
||||
* @version 2.0
|
||||
* @date 21. May. 2010
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2010, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
#ifndef DEBUG_FRMWRK_H_
|
||||
#define DEBUG_FRMWRK_H_
|
||||
|
||||
//#include <stdarg.h>
|
||||
#include "lpc17xx_uart.h"
|
||||
|
||||
#define USED_UART_DEBUG_PORT 0
|
||||
|
||||
#if (USED_UART_DEBUG_PORT==0)
|
||||
#define DEBUG_UART_PORT LPC_UART0
|
||||
#elif (USED_UART_DEBUG_PORT==1)
|
||||
#define DEBUG_UART_PORT LPC_UART1
|
||||
#endif
|
||||
|
||||
#define _DBG(x) _db_msg(DEBUG_UART_PORT, x)
|
||||
#define _DBG_(x) _db_msg_(DEBUG_UART_PORT, x)
|
||||
#define _DBC(x) _db_char(DEBUG_UART_PORT, x)
|
||||
#define _DBD(x) _db_dec(DEBUG_UART_PORT, x)
|
||||
#define _DBD16(x) _db_dec_16(DEBUG_UART_PORT, x)
|
||||
#define _DBD32(x) _db_dec_32(DEBUG_UART_PORT, x)
|
||||
#define _DBH(x) _db_hex(DEBUG_UART_PORT, x)
|
||||
#define _DBH16(x) _db_hex_16(DEBUG_UART_PORT, x)
|
||||
#define _DBH32(x) _db_hex_32(DEBUG_UART_PORT, x)
|
||||
#define _DG _db_get_char(DEBUG_UART_PORT)
|
||||
//void _printf (const char *format, ...);
|
||||
|
||||
extern void (*_db_msg)(LPC_UART_TypeDef *UARTx, const void *s);
|
||||
extern void (*_db_msg_)(LPC_UART_TypeDef *UARTx, const void *s);
|
||||
extern void (*_db_char)(LPC_UART_TypeDef *UARTx, uint8_t ch);
|
||||
extern void (*_db_dec)(LPC_UART_TypeDef *UARTx, uint8_t decn);
|
||||
extern void (*_db_dec_16)(LPC_UART_TypeDef *UARTx, uint16_t decn);
|
||||
extern void (*_db_dec_32)(LPC_UART_TypeDef *UARTx, uint32_t decn);
|
||||
extern void (*_db_hex)(LPC_UART_TypeDef *UARTx, uint8_t hexn);
|
||||
extern void (*_db_hex_16)(LPC_UART_TypeDef *UARTx, uint16_t hexn);
|
||||
extern void (*_db_hex_32)(LPC_UART_TypeDef *UARTx, uint32_t hexn);
|
||||
extern uint8_t (*_db_get_char)(LPC_UART_TypeDef *UARTx);
|
||||
|
||||
void UARTPutChar (LPC_UART_TypeDef *UARTx, uint8_t ch);
|
||||
void UARTPuts(LPC_UART_TypeDef *UARTx, const void *str);
|
||||
void UARTPuts_(LPC_UART_TypeDef *UARTx, const void *str);
|
||||
void UARTPutDec(LPC_UART_TypeDef *UARTx, uint8_t decnum);
|
||||
void UARTPutDec16(LPC_UART_TypeDef *UARTx, uint16_t decnum);
|
||||
void UARTPutDec32(LPC_UART_TypeDef *UARTx, uint32_t decnum);
|
||||
void UARTPutHex (LPC_UART_TypeDef *UARTx, uint8_t hexnum);
|
||||
void UARTPutHex16 (LPC_UART_TypeDef *UARTx, uint16_t hexnum);
|
||||
void UARTPutHex32 (LPC_UART_TypeDef *UARTx, uint32_t hexnum);
|
||||
uint8_t UARTGetChar (LPC_UART_TypeDef *UARTx);
|
||||
void debug_frmwrk_init(void);
|
||||
|
||||
#endif /* DEBUG_FRMWRK_H_ */
|
||||
@@ -1,302 +0,0 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc17xx_adc.h 2008-07-27
|
||||
*//**
|
||||
* @file lpc17xx_adc.h
|
||||
* @brief Contains the NXP ABL typedefs for C standard types.
|
||||
* It is intended to be used in ISO C conforming development
|
||||
* environments and checks for this insofar as it is possible
|
||||
* to do so.
|
||||
* @version 2.0
|
||||
* @date 27 Jul. 2008
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2008, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup ADC ADC (Analog-to-Digital Converter)
|
||||
* @ingroup LPC1700CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef LPC17XX_ADC_H_
|
||||
#define LPC17XX_ADC_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC17xx.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Private macros ------------------------------------------------------------- */
|
||||
/** @defgroup ADC_Private_Macros ADC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* -------------------------- BIT DEFINITIONS ----------------------------------- */
|
||||
/*********************************************************************//**
|
||||
* Macro defines for ADC control register
|
||||
**********************************************************************/
|
||||
/** Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
|
||||
#define ADC_CR_CH_SEL(n) ((1UL << n))
|
||||
/** The APB clock (PCLK) is divided by (this value plus one)
|
||||
* to produce the clock for the A/D */
|
||||
#define ADC_CR_CLKDIV(n) ((n<<8))
|
||||
/** Repeated conversions A/D enable bit */
|
||||
#define ADC_CR_BURST ((1UL<<16))
|
||||
/** ADC convert in power down mode */
|
||||
#define ADC_CR_PDN ((1UL<<21))
|
||||
/** Start mask bits */
|
||||
#define ADC_CR_START_MASK ((7UL<<24))
|
||||
/** Select Start Mode */
|
||||
#define ADC_CR_START_MODE_SEL(SEL) ((SEL<<24))
|
||||
/** Start conversion now */
|
||||
#define ADC_CR_START_NOW ((1UL<<24))
|
||||
/** Start conversion when the edge selected by bit 27 occurs on P2.10/EINT0 */
|
||||
#define ADC_CR_START_EINT0 ((2UL<<24))
|
||||
/** Start conversion when the edge selected by bit 27 occurs on P1.27/CAP0.1 */
|
||||
#define ADC_CR_START_CAP01 ((3UL<<24))
|
||||
/** Start conversion when the edge selected by bit 27 occurs on MAT0.1 */
|
||||
#define ADC_CR_START_MAT01 ((4UL<<24))
|
||||
/** Start conversion when the edge selected by bit 27 occurs on MAT0.3 */
|
||||
#define ADC_CR_START_MAT03 ((5UL<<24))
|
||||
/** Start conversion when the edge selected by bit 27 occurs on MAT1.0 */
|
||||
#define ADC_CR_START_MAT10 ((6UL<<24))
|
||||
/** Start conversion when the edge selected by bit 27 occurs on MAT1.1 */
|
||||
#define ADC_CR_START_MAT11 ((7UL<<24))
|
||||
/** Start conversion on a falling edge on the selected CAP/MAT signal */
|
||||
#define ADC_CR_EDGE ((1UL<<27))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for ADC Global Data register
|
||||
**********************************************************************/
|
||||
/** When DONE is 1, this field contains result value of ADC conversion */
|
||||
#define ADC_GDR_RESULT(n) (((n>>4)&0xFFF))
|
||||
/** These bits contain the channel from which the LS bits were converted */
|
||||
#define ADC_GDR_CH(n) (((n>>24)&0x7))
|
||||
/** This bit is 1 in burst mode if the results of one or
|
||||
* more conversions was (were) lost */
|
||||
#define ADC_GDR_OVERRUN_FLAG ((1UL<<30))
|
||||
/** This bit is set to 1 when an A/D conversion completes */
|
||||
#define ADC_GDR_DONE_FLAG ((1UL<<31))
|
||||
|
||||
/** This bits is used to mask for Channel */
|
||||
#define ADC_GDR_CH_MASK ((7UL<<24))
|
||||
/*********************************************************************//**
|
||||
* Macro defines for ADC Interrupt register
|
||||
**********************************************************************/
|
||||
/** These bits allow control over which A/D channels generate
|
||||
* interrupts for conversion completion */
|
||||
#define ADC_INTEN_CH(n) ((1UL<<n))
|
||||
/** When 1, enables the global DONE flag in ADDR to generate an interrupt */
|
||||
#define ADC_INTEN_GLOBAL ((1UL<<8))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for ADC Data register
|
||||
**********************************************************************/
|
||||
/** When DONE is 1, this field contains result value of ADC conversion */
|
||||
#define ADC_DR_RESULT(n) (((n>>4)&0xFFF))
|
||||
/** These bits mirror the OVERRRUN status flags that appear in the
|
||||
* result register for each A/D channel */
|
||||
#define ADC_DR_OVERRUN_FLAG ((1UL<<30))
|
||||
/** This bit is set to 1 when an A/D conversion completes. It is cleared
|
||||
* when this register is read */
|
||||
#define ADC_DR_DONE_FLAG ((1UL<<31))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for ADC Status register
|
||||
**********************************************************************/
|
||||
/** These bits mirror the DONE status flags that appear in the result
|
||||
* register for each A/D channel */
|
||||
#define ADC_STAT_CH_DONE_FLAG(n) ((n&0xFF))
|
||||
/** These bits mirror the OVERRRUN status flags that appear in the
|
||||
* result register for each A/D channel */
|
||||
#define ADC_STAT_CH_OVERRUN_FLAG(n) (((n>>8)&0xFF))
|
||||
/** This bit is the A/D interrupt flag */
|
||||
#define ADC_STAT_INT_FLAG ((1UL<<16))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for ADC Trim register
|
||||
**********************************************************************/
|
||||
/** Offset trim bits for ADC operation */
|
||||
#define ADC_ADCOFFS(n) (((n&0xF)<<4))
|
||||
/** Written to boot code*/
|
||||
#define ADC_TRIM(n) (((n&0xF)<<8))
|
||||
|
||||
/* ------------------- CHECK PARAM DEFINITIONS ------------------------- */
|
||||
/** Check ADC parameter */
|
||||
#define PARAM_ADCx(n) (((uint32_t *)n)==((uint32_t *)LPC_ADC))
|
||||
|
||||
/** Check ADC state parameter */
|
||||
#define PARAM_ADC_START_ON_EDGE_OPT(OPT) ((OPT == ADC_START_ON_RISING)||(OPT == ADC_START_ON_FALLING))
|
||||
|
||||
/** Check ADC state parameter */
|
||||
#define PARAM_ADC_DATA_STATUS(OPT) ((OPT== ADC_DATA_BURST)||(OPT== ADC_DATA_DONE))
|
||||
|
||||
/** Check ADC rate parameter */
|
||||
#define PARAM_ADC_RATE(rate) ((rate>0)&&(rate<=200000))
|
||||
|
||||
/** Check ADC channel selection parameter */
|
||||
#define PARAM_ADC_CHANNEL_SELECTION(SEL) ((SEL == ADC_CHANNEL_0)||(ADC_CHANNEL_1)\
|
||||
||(SEL == ADC_CHANNEL_2)|(ADC_CHANNEL_3)\
|
||||
||(SEL == ADC_CHANNEL_4)||(ADC_CHANNEL_5)\
|
||||
||(SEL == ADC_CHANNEL_6)||(ADC_CHANNEL_7))
|
||||
|
||||
/** Check ADC start option parameter */
|
||||
#define PARAM_ADC_START_OPT(OPT) ((OPT == ADC_START_CONTINUOUS)||(OPT == ADC_START_NOW)\
|
||||
||(OPT == ADC_START_ON_EINT0)||(OPT == ADC_START_ON_CAP01)\
|
||||
||(OPT == ADC_START_ON_MAT01)||(OPT == ADC_START_ON_MAT03)\
|
||||
||(OPT == ADC_START_ON_MAT10)||(OPT == ADC_START_ON_MAT11))
|
||||
|
||||
/** Check ADC interrupt type parameter */
|
||||
#define PARAM_ADC_TYPE_INT_OPT(OPT) ((OPT == ADC_ADINTEN0)||(OPT == ADC_ADINTEN1)\
|
||||
||(OPT == ADC_ADINTEN2)||(OPT == ADC_ADINTEN3)\
|
||||
||(OPT == ADC_ADINTEN4)||(OPT == ADC_ADINTEN5)\
|
||||
||(OPT == ADC_ADINTEN6)||(OPT == ADC_ADINTEN7)\
|
||||
||(OPT == ADC_ADGINTEN))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup ADC_Public_Types ADC Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief ADC enumeration
|
||||
**********************************************************************/
|
||||
/** @brief Channel Selection */
|
||||
typedef enum
|
||||
{
|
||||
ADC_CHANNEL_0 = 0, /*!< Channel 0 */
|
||||
ADC_CHANNEL_1, /*!< Channel 1 */
|
||||
ADC_CHANNEL_2, /*!< Channel 2 */
|
||||
ADC_CHANNEL_3, /*!< Channel 3 */
|
||||
ADC_CHANNEL_4, /*!< Channel 4 */
|
||||
ADC_CHANNEL_5, /*!< Channel 5 */
|
||||
ADC_CHANNEL_6, /*!< Channel 6 */
|
||||
ADC_CHANNEL_7 /*!< Channel 7 */
|
||||
}ADC_CHANNEL_SELECTION;
|
||||
|
||||
/** @brief Type of start option */
|
||||
typedef enum
|
||||
{
|
||||
ADC_START_CONTINUOUS =0, /*!< Continuous mode */
|
||||
ADC_START_NOW, /*!< Start conversion now */
|
||||
ADC_START_ON_EINT0, /*!< Start conversion when the edge selected
|
||||
* by bit 27 occurs on P2.10/EINT0 */
|
||||
ADC_START_ON_CAP01, /*!< Start conversion when the edge selected
|
||||
* by bit 27 occurs on P1.27/CAP0.1 */
|
||||
ADC_START_ON_MAT01, /*!< Start conversion when the edge selected
|
||||
* by bit 27 occurs on MAT0.1 */
|
||||
ADC_START_ON_MAT03, /*!< Start conversion when the edge selected
|
||||
* by bit 27 occurs on MAT0.3 */
|
||||
ADC_START_ON_MAT10, /*!< Start conversion when the edge selected
|
||||
* by bit 27 occurs on MAT1.0 */
|
||||
ADC_START_ON_MAT11 /*!< Start conversion when the edge selected
|
||||
* by bit 27 occurs on MAT1.1 */
|
||||
} ADC_START_OPT;
|
||||
|
||||
|
||||
/** @brief Type of edge when start conversion on the selected CAP/MAT signal */
|
||||
typedef enum
|
||||
{
|
||||
ADC_START_ON_RISING = 0, /*!< Start conversion on a rising edge
|
||||
*on the selected CAP/MAT signal */
|
||||
ADC_START_ON_FALLING /*!< Start conversion on a falling edge
|
||||
*on the selected CAP/MAT signal */
|
||||
} ADC_START_ON_EDGE_OPT;
|
||||
|
||||
/** @brief* ADC type interrupt enum */
|
||||
typedef enum
|
||||
{
|
||||
ADC_ADINTEN0 = 0, /*!< Interrupt channel 0 */
|
||||
ADC_ADINTEN1, /*!< Interrupt channel 1 */
|
||||
ADC_ADINTEN2, /*!< Interrupt channel 2 */
|
||||
ADC_ADINTEN3, /*!< Interrupt channel 3 */
|
||||
ADC_ADINTEN4, /*!< Interrupt channel 4 */
|
||||
ADC_ADINTEN5, /*!< Interrupt channel 5 */
|
||||
ADC_ADINTEN6, /*!< Interrupt channel 6 */
|
||||
ADC_ADINTEN7, /*!< Interrupt channel 7 */
|
||||
ADC_ADGINTEN /*!< Individual channel/global flag done generate an interrupt */
|
||||
}ADC_TYPE_INT_OPT;
|
||||
|
||||
/** @brief ADC Data status */
|
||||
typedef enum
|
||||
{
|
||||
ADC_DATA_BURST = 0, /*Burst bit*/
|
||||
ADC_DATA_DONE /*Done bit*/
|
||||
}ADC_DATA_STATUS;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup ADC_Public_Functions ADC Public Functions
|
||||
* @{
|
||||
*/
|
||||
/* Init/DeInit ADC peripheral ----------------*/
|
||||
void ADC_Init(LPC_ADC_TypeDef *ADCx, uint32_t rate);
|
||||
void ADC_DeInit(LPC_ADC_TypeDef *ADCx);
|
||||
|
||||
/* Enable/Disable ADC functions --------------*/
|
||||
void ADC_BurstCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
void ADC_PowerdownCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
void ADC_StartCmd(LPC_ADC_TypeDef *ADCx, uint8_t start_mode);
|
||||
void ADC_ChannelCmd (LPC_ADC_TypeDef *ADCx, uint8_t Channel, FunctionalState NewState);
|
||||
|
||||
/* Configure ADC functions -------------------*/
|
||||
void ADC_EdgeStartConfig(LPC_ADC_TypeDef *ADCx, uint8_t EdgeOption);
|
||||
void ADC_IntConfig (LPC_ADC_TypeDef *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState);
|
||||
|
||||
/* Get ADC information functions -------------------*/
|
||||
uint16_t ADC_ChannelGetData(LPC_ADC_TypeDef *ADCx, uint8_t channel);
|
||||
FlagStatus ADC_ChannelGetStatus(LPC_ADC_TypeDef *ADCx, uint8_t channel, uint32_t StatusType);
|
||||
uint32_t ADC_GlobalGetData(LPC_ADC_TypeDef *ADCx);
|
||||
FlagStatus ADC_GlobalGetStatus(LPC_ADC_TypeDef *ADCx, uint32_t StatusType);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* LPC17XX_ADC_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@@ -1,872 +0,0 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc17xx_can.h 2010-06-18
|
||||
*//**
|
||||
* @file lpc17xx_can.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for CAN firmware library on LPC17xx
|
||||
* @version 3.0
|
||||
* @date 18. June. 2010
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2010, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup CAN CAN (Control Area Network)
|
||||
* @ingroup LPC1700CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef LPC17XX_CAN_H_
|
||||
#define LPC17XX_CAN_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC17xx.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup CAN_Public_Macros CAN Public Macros
|
||||
* @{
|
||||
*/
|
||||
#define MSG_ENABLE ((uint8_t)(0))
|
||||
#define MSG_DISABLE ((uint8_t)(1))
|
||||
#define CAN1_CTRL ((uint8_t)(0))
|
||||
#define CAN2_CTRL ((uint8_t)(1))
|
||||
#define PARAM_FULLCAN_IC(n) ((n==FULLCAN_IC0)||(n==FULLCAN_IC1))
|
||||
#define ID_11 1
|
||||
#define MAX_HW_FULLCAN_OBJ 64
|
||||
#define MAX_SW_FULLCAN_OBJ 32
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup CAN_Private_Macros CAN Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* --------------------- BIT DEFINITIONS -------------------------------------- */
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Mode Register
|
||||
**********************************************************************/
|
||||
/** CAN Reset mode */
|
||||
#define CAN_MOD_RM ((uint32_t)(1))
|
||||
/** CAN Listen Only Mode */
|
||||
#define CAN_MOD_LOM ((uint32_t)(1<<1))
|
||||
/** CAN Self Test mode */
|
||||
#define CAN_MOD_STM ((uint32_t)(1<<2))
|
||||
/** CAN Transmit Priority mode */
|
||||
#define CAN_MOD_TPM ((uint32_t)(1<<3))
|
||||
/** CAN Sleep mode */
|
||||
#define CAN_MOD_SM ((uint32_t)(1<<4))
|
||||
/** CAN Receive Polarity mode */
|
||||
#define CAN_MOD_RPM ((uint32_t)(1<<5))
|
||||
/** CAN Test mode */
|
||||
#define CAN_MOD_TM ((uint32_t)(1<<7))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Command Register
|
||||
**********************************************************************/
|
||||
/** CAN Transmission Request */
|
||||
#define CAN_CMR_TR ((uint32_t)(1))
|
||||
/** CAN Abort Transmission */
|
||||
#define CAN_CMR_AT ((uint32_t)(1<<1))
|
||||
/** CAN Release Receive Buffer */
|
||||
#define CAN_CMR_RRB ((uint32_t)(1<<2))
|
||||
/** CAN Clear Data Overrun */
|
||||
#define CAN_CMR_CDO ((uint32_t)(1<<3))
|
||||
/** CAN Self Reception Request */
|
||||
#define CAN_CMR_SRR ((uint32_t)(1<<4))
|
||||
/** CAN Select Tx Buffer 1 */
|
||||
#define CAN_CMR_STB1 ((uint32_t)(1<<5))
|
||||
/** CAN Select Tx Buffer 2 */
|
||||
#define CAN_CMR_STB2 ((uint32_t)(1<<6))
|
||||
/** CAN Select Tx Buffer 3 */
|
||||
#define CAN_CMR_STB3 ((uint32_t)(1<<7))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Global Status Register
|
||||
**********************************************************************/
|
||||
/** CAN Receive Buffer Status */
|
||||
#define CAN_GSR_RBS ((uint32_t)(1))
|
||||
/** CAN Data Overrun Status */
|
||||
#define CAN_GSR_DOS ((uint32_t)(1<<1))
|
||||
/** CAN Transmit Buffer Status */
|
||||
#define CAN_GSR_TBS ((uint32_t)(1<<2))
|
||||
/** CAN Transmit Complete Status */
|
||||
#define CAN_GSR_TCS ((uint32_t)(1<<3))
|
||||
/** CAN Receive Status */
|
||||
#define CAN_GSR_RS ((uint32_t)(1<<4))
|
||||
/** CAN Transmit Status */
|
||||
#define CAN_GSR_TS ((uint32_t)(1<<5))
|
||||
/** CAN Error Status */
|
||||
#define CAN_GSR_ES ((uint32_t)(1<<6))
|
||||
/** CAN Bus Status */
|
||||
#define CAN_GSR_BS ((uint32_t)(1<<7))
|
||||
/** CAN Current value of the Rx Error Counter */
|
||||
#define CAN_GSR_RXERR(n) ((uint32_t)((n&0xFF)<<16))
|
||||
/** CAN Current value of the Tx Error Counter */
|
||||
#define CAN_GSR_TXERR(n) ((uint32_t)(n&0xFF)<<24))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Interrupt and Capture Register
|
||||
**********************************************************************/
|
||||
/** CAN Receive Interrupt */
|
||||
#define CAN_ICR_RI ((uint32_t)(1))
|
||||
/** CAN Transmit Interrupt 1 */
|
||||
#define CAN_ICR_TI1 ((uint32_t)(1<<1))
|
||||
/** CAN Error Warning Interrupt */
|
||||
#define CAN_ICR_EI ((uint32_t)(1<<2))
|
||||
/** CAN Data Overrun Interrupt */
|
||||
#define CAN_ICR_DOI ((uint32_t)(1<<3))
|
||||
/** CAN Wake-Up Interrupt */
|
||||
#define CAN_ICR_WUI ((uint32_t)(1<<4))
|
||||
/** CAN Error Passive Interrupt */
|
||||
#define CAN_ICR_EPI ((uint32_t)(1<<5))
|
||||
/** CAN Arbitration Lost Interrupt */
|
||||
#define CAN_ICR_ALI ((uint32_t)(1<<6))
|
||||
/** CAN Bus Error Interrupt */
|
||||
#define CAN_ICR_BEI ((uint32_t)(1<<7))
|
||||
/** CAN ID Ready Interrupt */
|
||||
#define CAN_ICR_IDI ((uint32_t)(1<<8))
|
||||
/** CAN Transmit Interrupt 2 */
|
||||
#define CAN_ICR_TI2 ((uint32_t)(1<<9))
|
||||
/** CAN Transmit Interrupt 3 */
|
||||
#define CAN_ICR_TI3 ((uint32_t)(1<<10))
|
||||
/** CAN Error Code Capture */
|
||||
#define CAN_ICR_ERRBIT(n) ((uint32_t)((n&0x1F)<<16))
|
||||
/** CAN Error Direction */
|
||||
#define CAN_ICR_ERRDIR ((uint32_t)(1<<21))
|
||||
/** CAN Error Capture */
|
||||
#define CAN_ICR_ERRC(n) ((uint32_t)((n&0x3)<<22))
|
||||
/** CAN Arbitration Lost Capture */
|
||||
#define CAN_ICR_ALCBIT(n) ((uint32_t)((n&0xFF)<<24))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Interrupt Enable Register
|
||||
**********************************************************************/
|
||||
/** CAN Receive Interrupt Enable */
|
||||
#define CAN_IER_RIE ((uint32_t)(1))
|
||||
/** CAN Transmit Interrupt Enable for buffer 1 */
|
||||
#define CAN_IER_TIE1 ((uint32_t)(1<<1))
|
||||
/** CAN Error Warning Interrupt Enable */
|
||||
#define CAN_IER_EIE ((uint32_t)(1<<2))
|
||||
/** CAN Data Overrun Interrupt Enable */
|
||||
#define CAN_IER_DOIE ((uint32_t)(1<<3))
|
||||
/** CAN Wake-Up Interrupt Enable */
|
||||
#define CAN_IER_WUIE ((uint32_t)(1<<4))
|
||||
/** CAN Error Passive Interrupt Enable */
|
||||
#define CAN_IER_EPIE ((uint32_t)(1<<5))
|
||||
/** CAN Arbitration Lost Interrupt Enable */
|
||||
#define CAN_IER_ALIE ((uint32_t)(1<<6))
|
||||
/** CAN Bus Error Interrupt Enable */
|
||||
#define CAN_IER_BEIE ((uint32_t)(1<<7))
|
||||
/** CAN ID Ready Interrupt Enable */
|
||||
#define CAN_IER_IDIE ((uint32_t)(1<<8))
|
||||
/** CAN Transmit Enable Interrupt for Buffer 2 */
|
||||
#define CAN_IER_TIE2 ((uint32_t)(1<<9))
|
||||
/** CAN Transmit Enable Interrupt for Buffer 3 */
|
||||
#define CAN_IER_TIE3 ((uint32_t)(1<<10))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Bus Timing Register
|
||||
**********************************************************************/
|
||||
/** CAN Baudrate Prescaler */
|
||||
#define CAN_BTR_BRP(n) ((uint32_t)(n&0x3FF))
|
||||
/** CAN Synchronization Jump Width */
|
||||
#define CAN_BTR_SJM(n) ((uint32_t)((n&0x3)<<14))
|
||||
/** CAN Time Segment 1 */
|
||||
#define CAN_BTR_TESG1(n) ((uint32_t)(n&0xF)<<16))
|
||||
/** CAN Time Segment 2 */
|
||||
#define CAN_BTR_TESG2(n) ((uint32_t)(n&0xF)<<20))
|
||||
/** CAN Sampling */
|
||||
#define CAN_BTR_SAM(n) ((uint32_t)(1<<23))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Error Warning Limit Register
|
||||
**********************************************************************/
|
||||
/** CAN Error Warning Limit */
|
||||
#define CAN_EWL_EWL(n) ((uint32_t)(n&0xFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Status Register
|
||||
**********************************************************************/
|
||||
/** CAN Receive Buffer Status */
|
||||
#define CAN_SR_RBS ((uint32_t)(1))
|
||||
/** CAN Data Overrun Status */
|
||||
#define CAN_SR_DOS ((uint32_t)(1<<1))
|
||||
/** CAN Transmit Buffer Status 1 */
|
||||
#define CAN_SR_TBS1 ((uint32_t)(1<<2))
|
||||
/** CAN Transmission Complete Status of Buffer 1 */
|
||||
#define CAN_SR_TCS1 ((uint32_t)(1<<3))
|
||||
/** CAN Receive Status */
|
||||
#define CAN_SR_RS ((uint32_t)(1<<4))
|
||||
/** CAN Transmit Status 1 */
|
||||
#define CAN_SR_TS1 ((uint32_t)(1<<5))
|
||||
/** CAN Error Status */
|
||||
#define CAN_SR_ES ((uint32_t)(1<<6))
|
||||
/** CAN Bus Status */
|
||||
#define CAN_SR_BS ((uint32_t)(1<<7))
|
||||
/** CAN Transmit Buffer Status 2 */
|
||||
#define CAN_SR_TBS2 ((uint32_t)(1<<10))
|
||||
/** CAN Transmission Complete Status of Buffer 2 */
|
||||
#define CAN_SR_TCS2 ((uint32_t)(1<<11))
|
||||
/** CAN Transmit Status 2 */
|
||||
#define CAN_SR_TS2 ((uint32_t)(1<<13))
|
||||
/** CAN Transmit Buffer Status 2 */
|
||||
#define CAN_SR_TBS3 ((uint32_t)(1<<18))
|
||||
/** CAN Transmission Complete Status of Buffer 2 */
|
||||
#define CAN_SR_TCS3 ((uint32_t)(1<<19))
|
||||
/** CAN Transmit Status 2 */
|
||||
#define CAN_SR_TS3 ((uint32_t)(1<<21))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Receive Frame Status Register
|
||||
**********************************************************************/
|
||||
/** CAN ID Index */
|
||||
#define CAN_RFS_ID_INDEX(n) ((uint32_t)(n&0x3FF))
|
||||
/** CAN Bypass */
|
||||
#define CAN_RFS_BP ((uint32_t)(1<<10))
|
||||
/** CAN Data Length Code */
|
||||
#define CAN_RFS_DLC(n) ((uint32_t)((n&0xF)<<16)
|
||||
/** CAN Remote Transmission Request */
|
||||
#define CAN_RFS_RTR ((uint32_t)(1<<30))
|
||||
/** CAN control 11 bit or 29 bit Identifier */
|
||||
#define CAN_RFS_FF ((uint32_t)(1<<31))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Receive Identifier Register
|
||||
**********************************************************************/
|
||||
/** CAN 11 bit Identifier */
|
||||
#define CAN_RID_ID_11(n) ((uint32_t)(n&0x7FF))
|
||||
/** CAN 29 bit Identifier */
|
||||
#define CAN_RID_ID_29(n) ((uint32_t)(n&0x1FFFFFFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Receive Data A Register
|
||||
**********************************************************************/
|
||||
/** CAN Receive Data 1 */
|
||||
#define CAN_RDA_DATA1(n) ((uint32_t)(n&0xFF))
|
||||
/** CAN Receive Data 2 */
|
||||
#define CAN_RDA_DATA2(n) ((uint32_t)((n&0xFF)<<8))
|
||||
/** CAN Receive Data 3 */
|
||||
#define CAN_RDA_DATA3(n) ((uint32_t)((n&0xFF)<<16))
|
||||
/** CAN Receive Data 4 */
|
||||
#define CAN_RDA_DATA4(n) ((uint32_t)((n&0xFF)<<24))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Receive Data B Register
|
||||
**********************************************************************/
|
||||
/** CAN Receive Data 5 */
|
||||
#define CAN_RDB_DATA5(n) ((uint32_t)(n&0xFF))
|
||||
/** CAN Receive Data 6 */
|
||||
#define CAN_RDB_DATA6(n) ((uint32_t)((n&0xFF)<<8))
|
||||
/** CAN Receive Data 7 */
|
||||
#define CAN_RDB_DATA7(n) ((uint32_t)((n&0xFF)<<16))
|
||||
/** CAN Receive Data 8 */
|
||||
#define CAN_RDB_DATA8(n) ((uint32_t)((n&0xFF)<<24))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Transmit Frame Information Register
|
||||
**********************************************************************/
|
||||
/** CAN Priority */
|
||||
#define CAN_TFI_PRIO(n) ((uint32_t)(n&0xFF))
|
||||
/** CAN Data Length Code */
|
||||
#define CAN_TFI_DLC(n) ((uint32_t)((n&0xF)<<16))
|
||||
/** CAN Remote Frame Transmission */
|
||||
#define CAN_TFI_RTR ((uint32_t)(1<<30))
|
||||
/** CAN control 11-bit or 29-bit Identifier */
|
||||
#define CAN_TFI_FF ((uint32_t)(1<<31))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Transmit Identifier Register
|
||||
**********************************************************************/
|
||||
/** CAN 11-bit Identifier */
|
||||
#define CAN_TID_ID11(n) ((uint32_t)(n&0x7FF))
|
||||
/** CAN 11-bit Identifier */
|
||||
#define CAN_TID_ID29(n) ((uint32_t)(n&0x1FFFFFFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Transmit Data A Register
|
||||
**********************************************************************/
|
||||
/** CAN Transmit Data 1 */
|
||||
#define CAN_TDA_DATA1(n) ((uint32_t)(n&0xFF))
|
||||
/** CAN Transmit Data 2 */
|
||||
#define CAN_TDA_DATA2(n) ((uint32_t)((n&0xFF)<<8))
|
||||
/** CAN Transmit Data 3 */
|
||||
#define CAN_TDA_DATA3(n) ((uint32_t)((n&0xFF)<<16))
|
||||
/** CAN Transmit Data 4 */
|
||||
#define CAN_TDA_DATA4(n) ((uint32_t)((n&0xFF)<<24))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Transmit Data B Register
|
||||
**********************************************************************/
|
||||
/** CAN Transmit Data 5 */
|
||||
#define CAN_TDA_DATA5(n) ((uint32_t)(n&0xFF))
|
||||
/** CAN Transmit Data 6 */
|
||||
#define CAN_TDA_DATA6(n) ((uint32_t)((n&0xFF)<<8))
|
||||
/** CAN Transmit Data 7 */
|
||||
#define CAN_TDA_DATA7(n) ((uint32_t)((n&0xFF)<<16))
|
||||
/** CAN Transmit Data 8 */
|
||||
#define CAN_TDA_DATA8(n) ((uint32_t)((n&0xFF)<<24))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Sleep Clear Register
|
||||
**********************************************************************/
|
||||
/** CAN1 Sleep mode */
|
||||
#define CAN1SLEEPCLR ((uint32_t)(1<<1))
|
||||
/** CAN2 Sleep Mode */
|
||||
#define CAN2SLEEPCLR ((uint32_t)(1<<2))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CAN Wake up Flags Register
|
||||
**********************************************************************/
|
||||
/** CAN1 Sleep mode */
|
||||
#define CAN_WAKEFLAGES_CAN1WAKE ((uint32_t)(1<<1))
|
||||
/** CAN2 Sleep Mode */
|
||||
#define CAN_WAKEFLAGES_CAN2WAKE ((uint32_t)(1<<2))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Central transmit Status Register
|
||||
**********************************************************************/
|
||||
/** CAN Transmit 1 */
|
||||
#define CAN_TSR_TS1 ((uint32_t)(1))
|
||||
/** CAN Transmit 2 */
|
||||
#define CAN_TSR_TS2 ((uint32_t)(1<<1))
|
||||
/** CAN Transmit Buffer Status 1 */
|
||||
#define CAN_TSR_TBS1 ((uint32_t)(1<<8))
|
||||
/** CAN Transmit Buffer Status 2 */
|
||||
#define CAN_TSR_TBS2 ((uint32_t)(1<<9))
|
||||
/** CAN Transmission Complete Status 1 */
|
||||
#define CAN_TSR_TCS1 ((uint32_t)(1<<16))
|
||||
/** CAN Transmission Complete Status 2 */
|
||||
#define CAN_TSR_TCS2 ((uint32_t)(1<<17))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Central Receive Status Register
|
||||
**********************************************************************/
|
||||
/** CAN Receive Status 1 */
|
||||
#define CAN_RSR_RS1 ((uint32_t)(1))
|
||||
/** CAN Receive Status 1 */
|
||||
#define CAN_RSR_RS2 ((uint32_t)(1<<1))
|
||||
/** CAN Receive Buffer Status 1*/
|
||||
#define CAN_RSR_RB1 ((uint32_t)(1<<8))
|
||||
/** CAN Receive Buffer Status 2*/
|
||||
#define CAN_RSR_RB2 ((uint32_t)(1<<9))
|
||||
/** CAN Data Overrun Status 1 */
|
||||
#define CAN_RSR_DOS1 ((uint32_t)(1<<16))
|
||||
/** CAN Data Overrun Status 1 */
|
||||
#define CAN_RSR_DOS2 ((uint32_t)(1<<17))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Central Miscellaneous Status Register
|
||||
**********************************************************************/
|
||||
/** Same CAN Error Status in CAN1GSR */
|
||||
#define CAN_MSR_E1 ((uint32_t)(1))
|
||||
/** Same CAN Error Status in CAN2GSR */
|
||||
#define CAN_MSR_E2 ((uint32_t)(1<<1))
|
||||
/** Same CAN Bus Status in CAN1GSR */
|
||||
#define CAN_MSR_BS1 ((uint32_t)(1<<8))
|
||||
/** Same CAN Bus Status in CAN2GSR */
|
||||
#define CAN_MSR_BS2 ((uint32_t)(1<<9))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Acceptance Filter Mode Register
|
||||
**********************************************************************/
|
||||
/** CAN Acceptance Filter Off mode */
|
||||
#define CAN_AFMR_AccOff ((uint32_t)(1))
|
||||
/** CAN Acceptance File Bypass mode */
|
||||
#define CAN_AFMR_AccBP ((uint32_t)(1<<1))
|
||||
/** FullCAN Mode Enhancements */
|
||||
#define CAN_AFMR_eFCAN ((uint32_t)(1<<2))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Standard Frame Individual Start Address Register
|
||||
**********************************************************************/
|
||||
/** The start address of the table of individual Standard Identifier */
|
||||
#define CAN_STT_sa(n) ((uint32_t)((n&1FF)<<2))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Standard Frame Group Start Address Register
|
||||
**********************************************************************/
|
||||
/** The start address of the table of grouped Standard Identifier */
|
||||
#define CAN_SFF_GRP_sa(n) ((uint32_t)((n&3FF)<<2))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Extended Frame Start Address Register
|
||||
**********************************************************************/
|
||||
/** The start address of the table of individual Extended Identifier */
|
||||
#define CAN_EFF_sa(n) ((uint32_t)((n&1FF)<<2))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Extended Frame Group Start Address Register
|
||||
**********************************************************************/
|
||||
/** The start address of the table of grouped Extended Identifier */
|
||||
#define CAN_Eff_GRP_sa(n) ((uint32_t)((n&3FF)<<2))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for End Of AF Table Register
|
||||
**********************************************************************/
|
||||
/** The End of Table of AF LookUp Table */
|
||||
#define CAN_EndofTable(n) ((uint32_t)((n&3FF)<<2))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for LUT Error Address Register
|
||||
**********************************************************************/
|
||||
/** CAN Look-Up Table Error Address */
|
||||
#define CAN_LUTerrAd(n) ((uint32_t)((n&1FF)<<2))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for LUT Error Register
|
||||
**********************************************************************/
|
||||
/** CAN Look-Up Table Error */
|
||||
#define CAN_LUTerr ((uint32_t)(1))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Global FullCANInterrupt Enable Register
|
||||
**********************************************************************/
|
||||
/** Global FullCANInterrupt Enable */
|
||||
#define CAN_FCANIE ((uint32_t)(1))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for FullCAN Interrupt and Capture Register 0
|
||||
**********************************************************************/
|
||||
/** FullCAN Interrupt and Capture (0-31)*/
|
||||
#define CAN_FCANIC0_IntPnd(n) ((uint32_t)(1<<n))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for FullCAN Interrupt and Capture Register 1
|
||||
**********************************************************************/
|
||||
/** FullCAN Interrupt and Capture (0-31)*/
|
||||
#define CAN_FCANIC1_IntPnd(n) ((uint32_t)(1<<(n-32)))
|
||||
|
||||
|
||||
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
|
||||
/** Macro to determine if it is valid CAN peripheral or not */
|
||||
#define PARAM_CANx(x) ((((uint32_t*)x)==((uint32_t *)LPC_CAN1)) \
|
||||
||(((uint32_t*)x)==((uint32_t *)LPC_CAN2)))
|
||||
|
||||
/* Macro to determine if it is valid CANAF or not*/
|
||||
#define PARAM_CANAFx(x) (((uint32_t*)x)== ((uint32_t*)LPC_CANAF))
|
||||
|
||||
/* Macro to determine if it is valid CANAF RAM or not*/
|
||||
#define PARAM_CANAFRAMx(x) (((uint32_t*)x)== (uint32_t*)LPC_CANAF_RAM)
|
||||
|
||||
/* Macro to determine if it is valid CANCR or not*/
|
||||
#define PARAM_CANCRx(x) (((uint32_t*)x)==((uint32_t*)LPC_CANCR))
|
||||
|
||||
/** Macro to check Data to send valid */
|
||||
#define PARAM_I2S_DATA(data) ((data>=0)&&(data <= 0xFFFFFFFF))
|
||||
|
||||
/** Macro to check frequency value */
|
||||
#define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000))
|
||||
|
||||
/** Macro to check Frame Identifier */
|
||||
#define PARAM_ID_11(n) ((n>>11)==0) /*-- 11 bit --*/
|
||||
#define PARAM_ID_29(n) ((n>>29)==0) /*-- 29 bit --*/
|
||||
|
||||
/** Macro to check DLC value */
|
||||
#define PARAM_DLC(n) ((n>>4)==0) /*-- 4 bit --*/
|
||||
/** Macro to check ID format type */
|
||||
#define PARAM_ID_FORMAT(n) ((n==STD_ID_FORMAT)||(n==EXT_ID_FORMAT))
|
||||
|
||||
/** Macro to check Group identifier */
|
||||
#define PARAM_GRP_ID(x, y) ((x<=y))
|
||||
|
||||
/** Macro to check Frame type */
|
||||
#define PARAM_FRAME_TYPE(n) ((n==DATA_FRAME)||(n==REMOTE_FRAME))
|
||||
|
||||
/** Macro to check Control/Central Status type parameter */
|
||||
#define PARAM_CTRL_STS_TYPE(n) ((n==CANCTRL_GLOBAL_STS)||(n==CANCTRL_INT_CAP) \
|
||||
||(n==CANCTRL_ERR_WRN)||(n==CANCTRL_STS))
|
||||
|
||||
/** Macro to check CR status type */
|
||||
#define PARAM_CR_STS_TYPE(n) ((n==CANCR_TX_STS)||(n==CANCR_RX_STS) \
|
||||
||(n==CANCR_MS))
|
||||
/** Macro to check AF Mode type parameter */
|
||||
#define PARAM_AFMODE_TYPE(n) ((n==CAN_Normal)||(n==CAN_AccOff) \
|
||||
||(n==CAN_AccBP)||(n==CAN_eFCAN))
|
||||
|
||||
/** Macro to check Operation Mode */
|
||||
#define PARAM_MODE_TYPE(n) ((n==CAN_OPERATING_MODE)||(n==CAN_RESET_MODE) \
|
||||
||(n==CAN_LISTENONLY_MODE)||(n==CAN_SELFTEST_MODE) \
|
||||
||(n==CAN_TXPRIORITY_MODE)||(n==CAN_SLEEP_MODE) \
|
||||
||(n==CAN_RXPOLARITY_MODE)||(n==CAN_TEST_MODE))
|
||||
|
||||
/** Macro define for struct AF_Section parameter */
|
||||
#define PARAM_CTRL(n) ((n==CAN1_CTRL)|(n==CAN2_CTRL))
|
||||
|
||||
/** Macro define for struct AF_Section parameter */
|
||||
#define PARAM_MSG_DISABLE(n) ((n==MSG_ENABLE)|(n==MSG_DISABLE))
|
||||
|
||||
/**Macro to check Interrupt Type parameter */
|
||||
#define PARAM_INT_EN_TYPE(n) ((n==CANINT_RIE)||(n==CANINT_TIE1) \
|
||||
||(n==CANINT_EIE)||(n==CANINT_DOIE) \
|
||||
||(n==CANINT_WUIE)||(n==CANINT_EPIE) \
|
||||
||(n==CANINT_ALIE)||(n==CANINT_BEIE) \
|
||||
||(n==CANINT_IDIE)||(n==CANINT_TIE2) \
|
||||
||(n==CANINT_TIE3)||(n==CANINT_FCE))
|
||||
|
||||
/** Macro to check AFLUT Entry type */
|
||||
#define PARAM_AFLUT_ENTRY_TYPE(n) ((n==FULLCAN_ENTRY)||(n==EXPLICIT_STANDARD_ENTRY)\
|
||||
||(n==GROUP_STANDARD_ENTRY)||(n==EXPLICIT_EXTEND_ENTRY) \
|
||||
||(n==GROUP_EXTEND_ENTRY))
|
||||
|
||||
/** Macro to check position */
|
||||
#define PARAM_POSITION(n) (n<512)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup CAN_Public_Types CAN Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** CAN configuration structure */
|
||||
/***********************************************************************
|
||||
* CAN device configuration commands (IOCTL commands and arguments)
|
||||
**********************************************************************/
|
||||
/**
|
||||
* @brief CAN ID format definition
|
||||
*/
|
||||
typedef enum {
|
||||
STD_ID_FORMAT = 0, /**< Use standard ID format (11 bit ID) */
|
||||
EXT_ID_FORMAT = 1 /**< Use extended ID format (29 bit ID) */
|
||||
} CAN_ID_FORMAT_Type;
|
||||
|
||||
/**
|
||||
* @brief AFLUT Entry type definition
|
||||
*/
|
||||
typedef enum {
|
||||
FULLCAN_ENTRY = 0,
|
||||
EXPLICIT_STANDARD_ENTRY,
|
||||
GROUP_STANDARD_ENTRY,
|
||||
EXPLICIT_EXTEND_ENTRY,
|
||||
GROUP_EXTEND_ENTRY
|
||||
} AFLUT_ENTRY_Type;
|
||||
|
||||
/**
|
||||
* @brief Symbolic names for type of CAN message
|
||||
*/
|
||||
typedef enum {
|
||||
DATA_FRAME = 0, /**< Data frame */
|
||||
REMOTE_FRAME = 1 /**< Remote frame */
|
||||
} CAN_FRAME_Type;
|
||||
|
||||
/**
|
||||
* @brief CAN Control status definition
|
||||
*/
|
||||
typedef enum {
|
||||
CANCTRL_GLOBAL_STS = 0, /**< CAN Global Status */
|
||||
CANCTRL_INT_CAP, /**< CAN Interrupt and Capture */
|
||||
CANCTRL_ERR_WRN, /**< CAN Error Warning Limit */
|
||||
CANCTRL_STS /**< CAN Control Status */
|
||||
} CAN_CTRL_STS_Type;
|
||||
|
||||
/**
|
||||
* @brief Central CAN status type definition
|
||||
*/
|
||||
typedef enum {
|
||||
CANCR_TX_STS = 0, /**< Central CAN Tx Status */
|
||||
CANCR_RX_STS, /**< Central CAN Rx Status */
|
||||
CANCR_MS /**< Central CAN Miscellaneous Status */
|
||||
} CAN_CR_STS_Type;
|
||||
|
||||
/**
|
||||
* @brief FullCAN Interrupt Capture type definition
|
||||
*/
|
||||
typedef enum{
|
||||
FULLCAN_IC0, /**< FullCAN Interrupt and Capture 0 */
|
||||
FULLCAN_IC1 /**< FullCAN Interrupt and Capture 1 */
|
||||
}FullCAN_IC_Type;
|
||||
|
||||
/**
|
||||
* @brief CAN interrupt enable type definition
|
||||
*/
|
||||
typedef enum {
|
||||
CANINT_RIE = 0, /**< CAN Receiver Interrupt Enable */
|
||||
CANINT_TIE1, /**< CAN Transmit Interrupt Enable */
|
||||
CANINT_EIE, /**< CAN Error Warning Interrupt Enable */
|
||||
CANINT_DOIE, /**< CAN Data Overrun Interrupt Enable */
|
||||
CANINT_WUIE, /**< CAN Wake-Up Interrupt Enable */
|
||||
CANINT_EPIE, /**< CAN Error Passive Interrupt Enable */
|
||||
CANINT_ALIE, /**< CAN Arbitration Lost Interrupt Enable */
|
||||
CANINT_BEIE, /**< CAN Bus Error Inter rupt Enable */
|
||||
CANINT_IDIE, /**< CAN ID Ready Interrupt Enable */
|
||||
CANINT_TIE2, /**< CAN Transmit Interrupt Enable for Buffer2 */
|
||||
CANINT_TIE3, /**< CAN Transmit Interrupt Enable for Buffer3 */
|
||||
CANINT_FCE /**< FullCAN Interrupt Enable */
|
||||
} CAN_INT_EN_Type;
|
||||
|
||||
/**
|
||||
* @brief Acceptance Filter Mode type definition
|
||||
*/
|
||||
typedef enum {
|
||||
CAN_Normal = 0, /**< Normal Mode */
|
||||
CAN_AccOff, /**< Acceptance Filter Off Mode */
|
||||
CAN_AccBP, /**< Acceptance Fileter Bypass Mode */
|
||||
CAN_eFCAN /**< FullCAN Mode Enhancement */
|
||||
} CAN_AFMODE_Type;
|
||||
|
||||
/**
|
||||
* @brief CAN Mode Type definition
|
||||
*/
|
||||
typedef enum {
|
||||
CAN_OPERATING_MODE = 0, /**< Operating Mode */
|
||||
CAN_RESET_MODE, /**< Reset Mode */
|
||||
CAN_LISTENONLY_MODE, /**< Listen Only Mode */
|
||||
CAN_SELFTEST_MODE, /**< Seft Test Mode */
|
||||
CAN_TXPRIORITY_MODE, /**< Transmit Priority Mode */
|
||||
CAN_SLEEP_MODE, /**< Sleep Mode */
|
||||
CAN_RXPOLARITY_MODE, /**< Receive Polarity Mode */
|
||||
CAN_TEST_MODE /**< Test Mode */
|
||||
} CAN_MODE_Type;
|
||||
|
||||
/**
|
||||
* @brief Error values that functions can return
|
||||
*/
|
||||
typedef enum {
|
||||
CAN_OK = 1, /**< No error */
|
||||
CAN_OBJECTS_FULL_ERROR, /**< No more rx or tx objects available */
|
||||
CAN_FULL_OBJ_NOT_RCV, /**< Full CAN object not received */
|
||||
CAN_NO_RECEIVE_DATA, /**< No have receive data available */
|
||||
CAN_AF_ENTRY_ERROR, /**< Entry load in AFLUT is unvalid */
|
||||
CAN_CONFLICT_ID_ERROR, /**< Conflict ID occur */
|
||||
CAN_ENTRY_NOT_EXIT_ERROR /**< Entry remove outo AFLUT is not exit */
|
||||
} CAN_ERROR;
|
||||
|
||||
/**
|
||||
* @brief Pin Configuration structure
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t RD; /**< Serial Inputs, from CAN transceivers, should be:
|
||||
** For CAN1:
|
||||
- CAN_RD1_P0_0: RD pin is on P0.0
|
||||
- CAN_RD1_P0_21 : RD pin is on P0.21
|
||||
** For CAN2:
|
||||
- CAN_RD2_P0_4: RD pin is on P0.4
|
||||
- CAN_RD2_P2_7: RD pin is on P2.7
|
||||
*/
|
||||
uint8_t TD; /**< Serial Outputs, To CAN transceivers, should be:
|
||||
** For CAN1:
|
||||
- CAN_TD1_P0_1: TD pin is on P0.1
|
||||
- CAN_TD1_P0_22: TD pin is on P0.22
|
||||
** For CAN2:
|
||||
- CAN_TD2_P0_5: TD pin is on P0.5
|
||||
- CAN_TD2_P2_8: TD pin is on P2.8
|
||||
*/
|
||||
} CAN_PinCFG_Type;
|
||||
|
||||
/**
|
||||
* @brief CAN message object structure
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t id; /**< 29 bit identifier, it depend on "format" value
|
||||
- if format = STD_ID_FORMAT, id should be 11 bit identifier
|
||||
- if format = EXT_ID_FORMAT, id should be 29 bit identifier
|
||||
*/
|
||||
uint8_t dataA[4]; /**< Data field A */
|
||||
uint8_t dataB[4]; /**< Data field B */
|
||||
uint8_t len; /**< Length of data field in bytes, should be:
|
||||
- 0000b-0111b: 0-7 bytes
|
||||
- 1xxxb: 8 bytes
|
||||
*/
|
||||
uint8_t format; /**< Identifier Format, should be:
|
||||
- STD_ID_FORMAT: Standard ID - 11 bit format
|
||||
- EXT_ID_FORMAT: Extended ID - 29 bit format
|
||||
*/
|
||||
uint8_t type; /**< Remote Frame transmission, should be:
|
||||
- DATA_FRAME: the number of data bytes called out by the DLC
|
||||
field are send from the CANxTDA and CANxTDB registers
|
||||
- REMOTE_FRAME: Remote Frame is sent
|
||||
*/
|
||||
} CAN_MSG_Type;
|
||||
|
||||
/**
|
||||
* @brief FullCAN Entry structure
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t controller; /**< CAN Controller, should be:
|
||||
- CAN1_CTRL: CAN1 Controller
|
||||
- CAN2_CTRL: CAN2 Controller
|
||||
*/
|
||||
uint8_t disable; /**< Disable bit, should be:
|
||||
- MSG_ENABLE: disable bit = 0
|
||||
- MSG_DISABLE: disable bit = 1
|
||||
*/
|
||||
uint16_t id_11; /**< Standard ID, should be 11-bit value */
|
||||
} FullCAN_Entry;
|
||||
|
||||
/**
|
||||
* @brief Standard ID Frame Format Entry structure
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t controller; /**< CAN Controller, should be:
|
||||
- CAN1_CTRL: CAN1 Controller
|
||||
- CAN2_CTRL: CAN2 Controller
|
||||
*/
|
||||
uint8_t disable; /**< Disable bit, should be:
|
||||
- MSG_ENABLE: disable bit = 0
|
||||
- MSG_DISABLE: disable bit = 1
|
||||
*/
|
||||
uint16_t id_11; /**< Standard ID, should be 11-bit value */
|
||||
} SFF_Entry;
|
||||
|
||||
/**
|
||||
* @brief Group of Standard ID Frame Format Entry structure
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t controller1; /**< First CAN Controller, should be:
|
||||
- CAN1_CTRL: CAN1 Controller
|
||||
- CAN2_CTRL: CAN2 Controller
|
||||
*/
|
||||
uint8_t disable1; /**< First Disable bit, should be:
|
||||
- MSG_ENABLE: disable bit = 0)
|
||||
- MSG_DISABLE: disable bit = 1
|
||||
*/
|
||||
uint16_t lowerID; /**< ID lower bound, should be 11-bit value */
|
||||
uint8_t controller2; /**< Second CAN Controller, should be:
|
||||
- CAN1_CTRL: CAN1 Controller
|
||||
- CAN2_CTRL: CAN2 Controller
|
||||
*/
|
||||
uint8_t disable2; /**< Second Disable bit, should be:
|
||||
- MSG_ENABLE: disable bit = 0
|
||||
- MSG_DISABLE: disable bit = 1
|
||||
*/
|
||||
uint16_t upperID; /**< ID upper bound, should be 11-bit value and
|
||||
equal or greater than lowerID
|
||||
*/
|
||||
} SFF_GPR_Entry;
|
||||
|
||||
/**
|
||||
* @brief Extended ID Frame Format Entry structure
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t controller; /**< CAN Controller, should be:
|
||||
- CAN1_CTRL: CAN1 Controller
|
||||
- CAN2_CTRL: CAN2 Controller
|
||||
*/
|
||||
uint32_t ID_29; /**< Extend ID, shoud be 29-bit value */
|
||||
} EFF_Entry;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Group of Extended ID Frame Format Entry structure
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t controller1; /**< First CAN Controller, should be:
|
||||
- CAN1_CTRL: CAN1 Controller
|
||||
- CAN2_CTRL: CAN2 Controller
|
||||
*/
|
||||
uint8_t controller2; /**< Second Disable bit, should be:
|
||||
- MSG_ENABLE: disable bit = 0(default)
|
||||
- MSG_DISABLE: disable bit = 1
|
||||
*/
|
||||
uint32_t lowerEID; /**< Extended ID lower bound, should be 29-bit value */
|
||||
uint32_t upperEID; /**< Extended ID upper bound, should be 29-bit value */
|
||||
} EFF_GPR_Entry;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Acceptance Filter Section Table structure
|
||||
*/
|
||||
typedef struct {
|
||||
FullCAN_Entry* FullCAN_Sec; /**< The pointer point to FullCAN_Entry */
|
||||
uint8_t FC_NumEntry; /**< FullCAN Entry Number */
|
||||
SFF_Entry* SFF_Sec; /**< The pointer point to SFF_Entry */
|
||||
uint8_t SFF_NumEntry; /**< Standard ID Entry Number */
|
||||
SFF_GPR_Entry* SFF_GPR_Sec; /**< The pointer point to SFF_GPR_Entry */
|
||||
uint8_t SFF_GPR_NumEntry; /**< Group Standard ID Entry Number */
|
||||
EFF_Entry* EFF_Sec; /**< The pointer point to EFF_Entry */
|
||||
uint8_t EFF_NumEntry; /**< Extended ID Entry Number */
|
||||
EFF_GPR_Entry* EFF_GPR_Sec; /**< The pointer point to EFF_GPR_Entry */
|
||||
uint8_t EFF_GPR_NumEntry; /**< Group Extended ID Entry Number */
|
||||
} AF_SectionDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup CAN_Public_Functions CAN Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Init/DeInit CAN peripheral -----------*/
|
||||
void CAN_Init(LPC_CAN_TypeDef *CANx, uint32_t baudrate);
|
||||
void CAN_DeInit(LPC_CAN_TypeDef *CANx);
|
||||
|
||||
/* CAN messages functions ---------------*/
|
||||
Status CAN_SendMsg(LPC_CAN_TypeDef *CANx, CAN_MSG_Type *CAN_Msg);
|
||||
Status CAN_ReceiveMsg(LPC_CAN_TypeDef *CANx, CAN_MSG_Type *CAN_Msg);
|
||||
CAN_ERROR FCAN_ReadObj(LPC_CANAF_TypeDef* CANAFx, CAN_MSG_Type *CAN_Msg);
|
||||
|
||||
/* CAN configure functions ---------------*/
|
||||
void CAN_ModeConfig(LPC_CAN_TypeDef* CANx, CAN_MODE_Type mode,
|
||||
FunctionalState NewState);
|
||||
void CAN_SetAFMode(LPC_CANAF_TypeDef* CANAFx, CAN_AFMODE_Type AFmode);
|
||||
void CAN_SetCommand(LPC_CAN_TypeDef* CANx, uint32_t CMRType);
|
||||
|
||||
/* AFLUT functions ---------------------- */
|
||||
CAN_ERROR CAN_SetupAFLUT(LPC_CANAF_TypeDef* CANAFx, AF_SectionDef* AFSection);
|
||||
CAN_ERROR CAN_LoadFullCANEntry(LPC_CAN_TypeDef* CANx, uint16_t ID);
|
||||
CAN_ERROR CAN_LoadExplicitEntry(LPC_CAN_TypeDef* CANx, uint32_t ID,
|
||||
CAN_ID_FORMAT_Type format);
|
||||
CAN_ERROR CAN_LoadGroupEntry(LPC_CAN_TypeDef* CANx, uint32_t lowerID,
|
||||
uint32_t upperID, CAN_ID_FORMAT_Type format);
|
||||
CAN_ERROR CAN_RemoveEntry(AFLUT_ENTRY_Type EntryType, uint16_t position);
|
||||
|
||||
/* CAN interrupt functions -----------------*/
|
||||
void CAN_IRQCmd(LPC_CAN_TypeDef* CANx, CAN_INT_EN_Type arg, FunctionalState NewState);
|
||||
uint32_t CAN_IntGetStatus(LPC_CAN_TypeDef* CANx);
|
||||
|
||||
/* CAN get status functions ----------------*/
|
||||
IntStatus CAN_FullCANIntGetStatus (LPC_CANAF_TypeDef* CANAFx);
|
||||
uint32_t CAN_FullCANPendGetStatus (LPC_CANAF_TypeDef* CANAFx, FullCAN_IC_Type type);
|
||||
uint32_t CAN_GetCTRLStatus(LPC_CAN_TypeDef* CANx, CAN_CTRL_STS_Type arg);
|
||||
uint32_t CAN_GetCRStatus(LPC_CANCR_TypeDef* CANCRx, CAN_CR_STS_Type arg);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* LPC17XX_CAN_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@@ -1,406 +0,0 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc17xx_clkpwr.h 2010-05-21
|
||||
*//**
|
||||
* @file lpc17xx_clkpwr.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for Clock and Power Control firmware library on LPC17xx
|
||||
* @version 2.0
|
||||
* @date 21. May. 2010
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2010, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup CLKPWR CLKPWR (Clock Power)
|
||||
* @ingroup LPC1700CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef LPC17XX_CLKPWR_H_
|
||||
#define LPC17XX_CLKPWR_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC17xx.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Public Macros -------------------------------------------------------------- */
|
||||
/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**********************************************************************
|
||||
* Peripheral Clock Selection Definitions
|
||||
**********************************************************************/
|
||||
/** Peripheral clock divider bit position for WDT */
|
||||
#define CLKPWR_PCLKSEL_WDT ((uint32_t)(0))
|
||||
/** Peripheral clock divider bit position for TIMER0 */
|
||||
#define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2))
|
||||
/** Peripheral clock divider bit position for TIMER1 */
|
||||
#define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4))
|
||||
/** Peripheral clock divider bit position for UART0 */
|
||||
#define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6))
|
||||
/** Peripheral clock divider bit position for UART1 */
|
||||
#define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8))
|
||||
/** Peripheral clock divider bit position for PWM1 */
|
||||
#define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12))
|
||||
/** Peripheral clock divider bit position for I2C0 */
|
||||
#define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14))
|
||||
/** Peripheral clock divider bit position for SPI */
|
||||
#define CLKPWR_PCLKSEL_SPI ((uint32_t)(16))
|
||||
/** Peripheral clock divider bit position for SSP1 */
|
||||
#define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20))
|
||||
/** Peripheral clock divider bit position for DAC */
|
||||
#define CLKPWR_PCLKSEL_DAC ((uint32_t)(22))
|
||||
/** Peripheral clock divider bit position for ADC */
|
||||
#define CLKPWR_PCLKSEL_ADC ((uint32_t)(24))
|
||||
/** Peripheral clock divider bit position for CAN1 */
|
||||
#define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26))
|
||||
/** Peripheral clock divider bit position for CAN2 */
|
||||
#define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28))
|
||||
/** Peripheral clock divider bit position for ACF */
|
||||
#define CLKPWR_PCLKSEL_ACF ((uint32_t)(30))
|
||||
/** Peripheral clock divider bit position for QEI */
|
||||
#define CLKPWR_PCLKSEL_QEI ((uint32_t)(32))
|
||||
/** Peripheral clock divider bit position for PCB */
|
||||
#define CLKPWR_PCLKSEL_PCB ((uint32_t)(36))
|
||||
/** Peripheral clock divider bit position for I2C1 */
|
||||
#define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38))
|
||||
/** Peripheral clock divider bit position for SSP0 */
|
||||
#define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42))
|
||||
/** Peripheral clock divider bit position for TIMER2 */
|
||||
#define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44))
|
||||
/** Peripheral clock divider bit position for TIMER3 */
|
||||
#define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46))
|
||||
/** Peripheral clock divider bit position for UART2 */
|
||||
#define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48))
|
||||
/** Peripheral clock divider bit position for UART3 */
|
||||
#define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50))
|
||||
/** Peripheral clock divider bit position for I2C2 */
|
||||
#define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52))
|
||||
/** Peripheral clock divider bit position for I2S */
|
||||
#define CLKPWR_PCLKSEL_I2S ((uint32_t)(54))
|
||||
/** Peripheral clock divider bit position for RIT */
|
||||
#define CLKPWR_PCLKSEL_RIT ((uint32_t)(58))
|
||||
/** Peripheral clock divider bit position for SYSCON */
|
||||
#define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60))
|
||||
/** Peripheral clock divider bit position for MC */
|
||||
#define CLKPWR_PCLKSEL_MC ((uint32_t)(62))
|
||||
|
||||
/** Macro for Peripheral Clock Selection register bit values
|
||||
* Note: When CCLK_DIV_8, Peripheral’s clock is selected to
|
||||
* PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
|
||||
* when ’11’selects PCLK_xyz = CCLK/6 */
|
||||
/* Peripheral clock divider is set to 4 from CCLK */
|
||||
#define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0))
|
||||
/** Peripheral clock divider is the same with CCLK */
|
||||
#define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1))
|
||||
/** Peripheral clock divider is set to 2 from CCLK */
|
||||
#define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2))
|
||||
|
||||
|
||||
/********************************************************************
|
||||
* Power Control for Peripherals Definitions
|
||||
**********************************************************************/
|
||||
/** Timer/Counter 0 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
|
||||
/* Timer/Counter 1 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
|
||||
/** UART0 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
|
||||
/** UART1 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
|
||||
/** PWM1 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
|
||||
/** The I2C0 interface power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
|
||||
/** The SPI interface power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8))
|
||||
/** The RTC power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
|
||||
/** The SSP1 interface power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
|
||||
/** A/D converter 0 (ADC0) power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12))
|
||||
/** CAN Controller 1 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
|
||||
/** CAN Controller 2 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
|
||||
/** GPIO power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
|
||||
/** Repetitive Interrupt Timer power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16))
|
||||
/** Motor Control PWM */
|
||||
#define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17))
|
||||
/** Quadrature Encoder Interface power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
|
||||
/** The I2C1 interface power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
|
||||
/** The SSP0 interface power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
|
||||
/** Timer 2 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
|
||||
/** Timer 3 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
|
||||
/** UART 2 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
|
||||
/** UART 3 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
|
||||
/** I2C interface 2 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
|
||||
/** I2S interface power/clock control bit*/
|
||||
#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
|
||||
/** GP DMA function power/clock control bit*/
|
||||
#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
|
||||
/** Ethernet block power/clock control bit*/
|
||||
#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
|
||||
/** USB interface power/clock control bit*/
|
||||
#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* --------------------- BIT DEFINITIONS -------------------------------------- */
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Clock Source Select Register
|
||||
**********************************************************************/
|
||||
/** Internal RC oscillator */
|
||||
#define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00))
|
||||
/** Main oscillator */
|
||||
#define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01))
|
||||
/** RTC oscillator */
|
||||
#define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02))
|
||||
/** Clock source selection bit mask */
|
||||
#define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Clock Output Configuration Register
|
||||
**********************************************************************/
|
||||
/* Clock Output Configuration register definition */
|
||||
/** Selects the CPU clock as the CLKOUT source */
|
||||
#define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00))
|
||||
/** Selects the main oscillator as the CLKOUT source */
|
||||
#define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01))
|
||||
/** Selects the Internal RC oscillator as the CLKOUT source */
|
||||
#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02))
|
||||
/** Selects the USB clock as the CLKOUT source */
|
||||
#define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03))
|
||||
/** Selects the RTC oscillator as the CLKOUT source */
|
||||
#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04))
|
||||
/** Integer value to divide the output clock by, minus one */
|
||||
#define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4))
|
||||
/** CLKOUT enable control */
|
||||
#define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8))
|
||||
/** CLKOUT activity indication */
|
||||
#define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9))
|
||||
/** Clock source selection bit mask */
|
||||
#define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for PPL0 Control Register
|
||||
**********************************************************************/
|
||||
/** PLL 0 control enable */
|
||||
#define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01))
|
||||
/** PLL 0 control connect */
|
||||
#define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02))
|
||||
/** PLL 0 control bit mask */
|
||||
#define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for PPL0 Configuration Register
|
||||
**********************************************************************/
|
||||
/** PLL 0 Configuration MSEL field */
|
||||
#define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF))
|
||||
/** PLL 0 Configuration NSEL field */
|
||||
#define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000))
|
||||
/** PLL 0 Configuration bit mask */
|
||||
#define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF))
|
||||
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for PPL0 Status Register
|
||||
**********************************************************************/
|
||||
/** PLL 0 MSEL value */
|
||||
#define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF))
|
||||
/** PLL NSEL get value */
|
||||
#define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF))
|
||||
/** PLL status enable bit */
|
||||
#define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24))
|
||||
/** PLL status Connect bit */
|
||||
#define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25))
|
||||
/** PLL status lock */
|
||||
#define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for PPL0 Feed Register
|
||||
**********************************************************************/
|
||||
/** PLL0 Feed bit mask */
|
||||
#define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF)
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for PLL1 Control Register
|
||||
**********************************************************************/
|
||||
/** USB PLL control enable */
|
||||
#define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01))
|
||||
/** USB PLL control connect */
|
||||
#define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02))
|
||||
/** USB PLL control bit mask */
|
||||
#define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for PLL1 Configuration Register
|
||||
**********************************************************************/
|
||||
/** USB PLL MSEL set value */
|
||||
#define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F))
|
||||
/** USB PLL PSEL set value */
|
||||
#define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5))
|
||||
/** USB PLL configuration bit mask */
|
||||
#define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for PLL1 Status Register
|
||||
**********************************************************************/
|
||||
/** USB PLL MSEL get value */
|
||||
#define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F))
|
||||
/** USB PLL PSEL get value */
|
||||
#define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03))
|
||||
/** USB PLL status enable bit */
|
||||
#define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8))
|
||||
/** USB PLL status Connect bit */
|
||||
#define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9))
|
||||
/** USB PLL status lock */
|
||||
#define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for PLL1 Feed Register
|
||||
**********************************************************************/
|
||||
/** PLL1 Feed bit mask */
|
||||
#define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF)
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CPU Clock Configuration Register
|
||||
**********************************************************************/
|
||||
/** CPU Clock configuration bit mask */
|
||||
#define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for USB Clock Configuration Register
|
||||
**********************************************************************/
|
||||
/** USB Clock Configuration bit mask */
|
||||
#define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for IRC Trim Register
|
||||
**********************************************************************/
|
||||
/** IRC Trim bit mask */
|
||||
#define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Peripheral Clock Selection Register 0 and 1
|
||||
**********************************************************************/
|
||||
/** Peripheral Clock Selection 0 mask bit */
|
||||
#define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF))
|
||||
/** Peripheral Clock Selection 1 mask bit */
|
||||
#define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3))
|
||||
/** Macro to set peripheral clock of each type
|
||||
* p: position of two bits that hold divider of peripheral clock
|
||||
* n: value of divider of peripheral clock to be set */
|
||||
#define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n)
|
||||
/** Macro to mask peripheral clock of each type */
|
||||
#define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03)
|
||||
/** Macro to get peripheral clock of each type */
|
||||
#define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Power Mode Control Register
|
||||
**********************************************************************/
|
||||
/** Power mode control bit 0 */
|
||||
#define CLKPWR_PCON_PM0 ((uint32_t)(1<<0))
|
||||
/** Power mode control bit 1 */
|
||||
#define CLKPWR_PCON_PM1 ((uint32_t)(1<<1))
|
||||
/** Brown-Out Reduced Power Mode */
|
||||
#define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2))
|
||||
/** Brown-Out Global Disable */
|
||||
#define CLKPWR_PCON_BOGD ((uint32_t)(1<<3))
|
||||
/** Brown Out Reset Disable */
|
||||
#define CLKPWR_PCON_BORD ((uint32_t)(1<<4))
|
||||
/** Sleep Mode entry flag */
|
||||
#define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8))
|
||||
/** Deep Sleep entry flag */
|
||||
#define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9))
|
||||
/** Power-down entry flag */
|
||||
#define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10))
|
||||
/** Deep Power-down entry flag */
|
||||
#define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Power Control for Peripheral Register
|
||||
**********************************************************************/
|
||||
/** Power Control for Peripherals bit mask */
|
||||
#define CLKPWR_PCONP_BITMASK 0xEFEFF7DE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal);
|
||||
uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType);
|
||||
uint32_t CLKPWR_GetPCLK (uint32_t ClkType);
|
||||
void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState);
|
||||
void CLKPWR_Sleep(void);
|
||||
void CLKPWR_DeepSleep(void);
|
||||
void CLKPWR_PowerDown(void);
|
||||
void CLKPWR_DeepPowerDown(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* LPC17XX_CLKPWR_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@@ -1,154 +0,0 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc17xx_dac.h 2010-05-21
|
||||
*//**
|
||||
* @file lpc17xx_dac.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for Clock and Power Control firmware library on LPC17xx
|
||||
* @version 2.0
|
||||
* @date 21. May. 2010
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2010, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup DAC DAC (Digital-to-Analog Controller)
|
||||
* @ingroup LPC1700CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef LPC17XX_DAC_H_
|
||||
#define LPC17XX_DAC_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC17xx.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Public Macros -------------------------------------------------------------- */
|
||||
/** @defgroup DAC_Private_Macros DAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** After the selected settling time after this field is written with a
|
||||
new VALUE, the voltage on the AOUT pin (with respect to VSSA)
|
||||
is VALUE/1024 × VREF */
|
||||
#define DAC_VALUE(n) ((uint32_t)((n&0x3FF)<<6))
|
||||
/** If this bit = 0: The settling time of the DAC is 1 microsecond max,
|
||||
* and the maximum current is 700 microAmpere
|
||||
* If this bit = 1: The settling time of the DAC is 2.5 microsecond
|
||||
* and the maximum current is 350 microAmpere */
|
||||
#define DAC_BIAS_EN ((uint32_t)(1<<16))
|
||||
/** Value to reload interrupt DMA counter */
|
||||
#define DAC_CCNT_VALUE(n) ((uint32_t)(n&0xffff))
|
||||
|
||||
/** DCAR double buffering */
|
||||
#define DAC_DBLBUF_ENA ((uint32_t)(1<<1))
|
||||
/** DCAR Time out count enable */
|
||||
#define DAC_CNT_ENA ((uint32_t)(1<<2))
|
||||
/** DCAR DMA access */
|
||||
#define DAC_DMA_ENA ((uint32_t)(1<<3))
|
||||
/** DCAR DACCTRL mask bit */
|
||||
#define DAC_DACCTRL_MASK ((uint32_t)(0x0F))
|
||||
|
||||
/** Macro to determine if it is valid DAC peripheral */
|
||||
#define PARAM_DACx(n) (((uint32_t *)n)==((uint32_t *)LPC_DAC))
|
||||
|
||||
/** Macro to check DAC current optional parameter */
|
||||
#define PARAM_DAC_CURRENT_OPT(OPTION) ((OPTION == DAC_MAX_CURRENT_700uA)\
|
||||
||(OPTION == DAC_MAX_CURRENT_350uA))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup DAC_Public_Types DAC Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Current option in DAC configuration option */
|
||||
typedef enum
|
||||
{
|
||||
DAC_MAX_CURRENT_700uA = 0, /*!< The settling time of the DAC is 1 us max,
|
||||
and the maximum current is 700 uA */
|
||||
DAC_MAX_CURRENT_350uA /*!< The settling time of the DAC is 2.5 us
|
||||
and the maximum current is 350 uA */
|
||||
} DAC_CURRENT_OPT;
|
||||
|
||||
/**
|
||||
* @brief Configuration for DAC converter control register */
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint8_t DBLBUF_ENA; /**<
|
||||
-0: Disable DACR double buffering
|
||||
-1: when bit CNT_ENA, enable DACR double buffering feature
|
||||
*/
|
||||
uint8_t CNT_ENA; /*!<
|
||||
-0: Time out counter is disable
|
||||
-1: Time out conter is enable
|
||||
*/
|
||||
uint8_t DMA_ENA; /*!<
|
||||
-0: DMA access is disable
|
||||
-1: DMA burst request
|
||||
*/
|
||||
uint8_t RESERVED;
|
||||
|
||||
} DAC_CONVERTER_CFG_Type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup DAC_Public_Functions DAC Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void DAC_Init(LPC_DAC_TypeDef *DACx);
|
||||
void DAC_UpdateValue (LPC_DAC_TypeDef *DACx, uint32_t dac_value);
|
||||
void DAC_SetBias (LPC_DAC_TypeDef *DACx,uint32_t bias);
|
||||
void DAC_ConfigDAConverterControl (LPC_DAC_TypeDef *DACx,DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct);
|
||||
void DAC_SetDMATimeOut(LPC_DAC_TypeDef *DACx,uint32_t time_out);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* LPC17XX_DAC_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
|
||||
@@ -1,711 +0,0 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc17xx_emac.h 2010-05-21
|
||||
*//**
|
||||
* @file lpc17xx_emac.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for Ethernet MAC firmware library on LPC17xx
|
||||
* @version 2.0
|
||||
* @date 21. May. 2010
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2010, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup EMAC EMAC (Ethernet Media Access Controller)
|
||||
* @ingroup LPC1700CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef LPC17XX_EMAC_H_
|
||||
#define LPC17XX_EMAC_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC17xx.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#define MCB_LPC_1768
|
||||
//#define IAR_LPC_1768
|
||||
|
||||
/* Public Macros -------------------------------------------------------------- */
|
||||
/** @defgroup EMAC_Public_Macros EMAC Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* EMAC PHY status type definitions */
|
||||
#define EMAC_PHY_STAT_LINK (0) /**< Link Status */
|
||||
#define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
|
||||
#define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
|
||||
|
||||
/* EMAC PHY device Speed definitions */
|
||||
#define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
|
||||
#define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
|
||||
#define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
|
||||
#define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
|
||||
#define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup EMAC_Private_Macros EMAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* EMAC Memory Buffer configuration for 16K Ethernet RAM */
|
||||
#define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
|
||||
#define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
|
||||
#define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
|
||||
#define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
|
||||
|
||||
/* --------------------- BIT DEFINITIONS -------------------------------------- */
|
||||
/*********************************************************************//**
|
||||
* Macro defines for MAC Configuration Register 1
|
||||
**********************************************************************/
|
||||
#define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
|
||||
#define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
|
||||
#define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
|
||||
#define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
|
||||
#define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
|
||||
#define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
|
||||
#define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
|
||||
#define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
|
||||
#define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
|
||||
#define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
|
||||
#define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for MAC Configuration Register 2
|
||||
**********************************************************************/
|
||||
#define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
|
||||
#define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
|
||||
#define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
|
||||
#define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
|
||||
#define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
|
||||
#define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
|
||||
#define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
|
||||
#define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
|
||||
#define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
|
||||
#define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
|
||||
#define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
|
||||
#define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
|
||||
#define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Back-to-Back Inter-Packet-Gap Register
|
||||
**********************************************************************/
|
||||
/** Programmable field representing the nibble time offset of the minimum possible period
|
||||
* between the end of any transmitted packet to the beginning of the next */
|
||||
#define EMAC_IPGT_BBIPG(n) (n&0x7F)
|
||||
/** Recommended value for Full Duplex of Programmable field representing the nibble time
|
||||
* offset of the minimum possible period between the end of any transmitted packet to the
|
||||
* beginning of the next */
|
||||
#define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
|
||||
/** Recommended value for Half Duplex of Programmable field representing the nibble time
|
||||
* offset of the minimum possible period between the end of any transmitted packet to the
|
||||
* beginning of the next */
|
||||
#define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Non Back-to-Back Inter-Packet-Gap Register
|
||||
**********************************************************************/
|
||||
/** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
|
||||
#define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
|
||||
/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
|
||||
#define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
|
||||
/** Programmable field representing the optional carrierSense window referenced in
|
||||
* IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
|
||||
#define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
|
||||
/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
|
||||
#define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Collision Window/Retry Register
|
||||
**********************************************************************/
|
||||
/** Programmable field specifying the number of retransmission attempts following a collision before
|
||||
* aborting the packet due to excessive collisions */
|
||||
#define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
|
||||
/** Programmable field representing the slot time or collision window during which collisions occur
|
||||
* in properly configured networks */
|
||||
#define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
|
||||
/** Default value for Collision Window / Retry register */
|
||||
#define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Maximum Frame Register
|
||||
**********************************************************************/
|
||||
/** Represents a maximum receive frame of 1536 octets */
|
||||
#define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for PHY Support Register
|
||||
**********************************************************************/
|
||||
#define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
|
||||
//#define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Test Register
|
||||
**********************************************************************/
|
||||
#define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
|
||||
#define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
|
||||
#define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for MII Management Configuration Register
|
||||
**********************************************************************/
|
||||
#define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
|
||||
#define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
|
||||
#define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
|
||||
#define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
|
||||
#define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for MII Management Command Register
|
||||
**********************************************************************/
|
||||
#define EMAC_MCMD_READ 0x00000001 /**< MII Read */
|
||||
#define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
|
||||
|
||||
#define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
|
||||
#define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for MII Management Address Register
|
||||
**********************************************************************/
|
||||
#define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
|
||||
#define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for MII Management Write Data Register
|
||||
**********************************************************************/
|
||||
#define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for MII Management Read Data Register
|
||||
**********************************************************************/
|
||||
#define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for MII Management Indicators Register
|
||||
**********************************************************************/
|
||||
#define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
|
||||
#define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
|
||||
#define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
|
||||
#define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
|
||||
|
||||
/* Station Address 0 Register */
|
||||
/* Station Address 1 Register */
|
||||
/* Station Address 2 Register */
|
||||
|
||||
|
||||
/* Control register definitions --------------------------------------------------------------------------- */
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Command Register
|
||||
**********************************************************************/
|
||||
#define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
|
||||
#define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
|
||||
#define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
|
||||
#define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
|
||||
#define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
|
||||
#define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
|
||||
#define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
|
||||
#define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
|
||||
#define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
|
||||
#define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Status Register
|
||||
**********************************************************************/
|
||||
#define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
|
||||
#define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Transmit Status Vector 0 Register
|
||||
**********************************************************************/
|
||||
#define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
|
||||
#define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
|
||||
#define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
|
||||
#define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
|
||||
#define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
|
||||
#define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
|
||||
#define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
|
||||
#define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
|
||||
#define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
|
||||
#define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
|
||||
#define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
|
||||
#define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
|
||||
#define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
|
||||
#define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
|
||||
#define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
|
||||
#define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
|
||||
#define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Transmit Status Vector 1 Register
|
||||
**********************************************************************/
|
||||
#define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
|
||||
#define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Receive Status Vector Register
|
||||
**********************************************************************/
|
||||
#define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
|
||||
#define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
|
||||
#define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
|
||||
#define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
|
||||
#define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
|
||||
#define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
|
||||
#define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
|
||||
#define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
|
||||
#define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
|
||||
#define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
|
||||
#define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
|
||||
#define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
|
||||
#define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
|
||||
#define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
|
||||
#define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
|
||||
#define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Flow Control Counter Register
|
||||
**********************************************************************/
|
||||
#define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
|
||||
#define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Flow Control Status Register
|
||||
**********************************************************************/
|
||||
#define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
|
||||
|
||||
|
||||
/* Receive filter register definitions -------------------------------------------------------- */
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Receive Filter Control Register
|
||||
**********************************************************************/
|
||||
#define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
|
||||
#define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
|
||||
#define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
|
||||
#define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
|
||||
#define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
|
||||
#define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
|
||||
#define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
|
||||
#define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Receive Filter WoL Status/Clear Registers
|
||||
**********************************************************************/
|
||||
#define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
|
||||
#define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
|
||||
#define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
|
||||
#define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
|
||||
#define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
|
||||
#define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
|
||||
#define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
|
||||
#define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
|
||||
#define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
|
||||
|
||||
|
||||
/* Module control register definitions ---------------------------------------------------- */
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Interrupt Status/Enable/Clear/Set Registers
|
||||
**********************************************************************/
|
||||
#define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
|
||||
#define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
|
||||
#define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
|
||||
#define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
|
||||
#define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
|
||||
#define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
|
||||
#define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
|
||||
#define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
|
||||
#define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
|
||||
#define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Power Down Register
|
||||
**********************************************************************/
|
||||
#define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
|
||||
|
||||
/* Descriptor and status formats ---------------------------------------------------- */
|
||||
/*********************************************************************//**
|
||||
* Macro defines for RX Descriptor Control Word
|
||||
**********************************************************************/
|
||||
#define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
|
||||
#define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for RX Status Hash CRC Word
|
||||
**********************************************************************/
|
||||
#define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
|
||||
#define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for RX Status Information Word
|
||||
**********************************************************************/
|
||||
#define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
|
||||
#define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
|
||||
#define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
|
||||
#define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
|
||||
#define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
|
||||
#define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
|
||||
#define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
|
||||
#define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
|
||||
#define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
|
||||
#define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
|
||||
#define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
|
||||
#define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
|
||||
#define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
|
||||
#define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
|
||||
#define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
|
||||
#define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
|
||||
EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for TX Descriptor Control Word
|
||||
**********************************************************************/
|
||||
#define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
|
||||
#define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
|
||||
#define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
|
||||
#define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
|
||||
#define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
|
||||
#define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
|
||||
#define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for TX Status Information Word
|
||||
**********************************************************************/
|
||||
#define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
|
||||
#define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
|
||||
#define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
|
||||
#define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
|
||||
#define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
|
||||
#define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
|
||||
#define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
|
||||
#define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
|
||||
|
||||
#ifdef MCB_LPC_1768
|
||||
/* DP83848C PHY definition ------------------------------------------------------------ */
|
||||
|
||||
/** PHY device reset time out definition */
|
||||
#define EMAC_PHY_RESP_TOUT 0x100000UL
|
||||
|
||||
/* ENET Device Revision ID */
|
||||
#define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DP83848C PHY Registers
|
||||
**********************************************************************/
|
||||
#define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
|
||||
#define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
|
||||
#define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
|
||||
#define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
|
||||
#define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
|
||||
#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
|
||||
#define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
|
||||
#define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
|
||||
#define EMAC_PHY_REG_LPNPA 0x08
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for PHY Extended Registers
|
||||
**********************************************************************/
|
||||
#define EMAC_PHY_REG_STS 0x10 /**< Status Register */
|
||||
#define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
|
||||
#define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
|
||||
#define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
|
||||
#define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
|
||||
#define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
|
||||
#define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
|
||||
#define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
|
||||
#define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
|
||||
#define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
|
||||
#define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
|
||||
#define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for PHY Basic Mode Control Register
|
||||
**********************************************************************/
|
||||
#define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
|
||||
#define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
|
||||
#define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
|
||||
#define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
|
||||
#define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
|
||||
#define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
|
||||
#define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
|
||||
#define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for PHY Basic Mode Status Status Register
|
||||
**********************************************************************/
|
||||
#define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
|
||||
#define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
|
||||
#define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
|
||||
#define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
|
||||
#define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
|
||||
#define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
|
||||
#define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
|
||||
#define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
|
||||
#define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
|
||||
#define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for PHY Status Register
|
||||
**********************************************************************/
|
||||
#define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
|
||||
#define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
|
||||
#define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
|
||||
#define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
|
||||
#define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
|
||||
#define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
|
||||
#define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
|
||||
|
||||
#define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
|
||||
#define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
|
||||
#define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
|
||||
#define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
|
||||
#define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
|
||||
|
||||
#define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
|
||||
#define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
|
||||
|
||||
#define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
|
||||
#define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
|
||||
#define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
|
||||
|
||||
#elif defined(IAR_LPC_1768)
|
||||
/* KSZ8721BL PHY definition ------------------------------------------------------------ */
|
||||
/** PHY device reset time out definition */
|
||||
#define EMAC_PHY_RESP_TOUT 0x100000UL
|
||||
|
||||
/* ENET Device Revision ID */
|
||||
#define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for KSZ8721BL PHY Registers
|
||||
**********************************************************************/
|
||||
#define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
|
||||
#define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
|
||||
#define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
|
||||
#define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
|
||||
#define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
|
||||
#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
|
||||
#define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
|
||||
#define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
|
||||
#define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
|
||||
#define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
|
||||
#define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
|
||||
#define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for PHY Basic Mode Control Register
|
||||
**********************************************************************/
|
||||
#define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
|
||||
#define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
|
||||
#define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
|
||||
#define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
|
||||
#define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
|
||||
#define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
|
||||
#define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
|
||||
#define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
|
||||
#define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
|
||||
#define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for PHY Basic Mode Status Register
|
||||
**********************************************************************/
|
||||
#define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
|
||||
#define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
|
||||
#define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
|
||||
#define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
|
||||
#define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
|
||||
#define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
|
||||
#define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
|
||||
#define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
|
||||
#define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
|
||||
#define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
|
||||
#define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
|
||||
#define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for PHY Identifier
|
||||
**********************************************************************/
|
||||
/* PHY Identifier 1 bitmap definitions */
|
||||
#define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
|
||||
|
||||
/* PHY Identifier 2 bitmap definitions */
|
||||
#define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for Auto-Negotiation Advertisement
|
||||
**********************************************************************/
|
||||
#define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
|
||||
#define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
|
||||
#define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
|
||||
#define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
|
||||
#define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
|
||||
#define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
|
||||
#define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
|
||||
#define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
|
||||
#define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
|
||||
|
||||
#define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
|
||||
#define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
|
||||
#define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
|
||||
#define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
|
||||
#define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
|
||||
|
||||
#define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
|
||||
#define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
|
||||
|
||||
#define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
|
||||
#define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup EMAC_Public_Types EMAC Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Descriptor and status formats ---------------------------------------------- */
|
||||
|
||||
/**
|
||||
* @brief RX Descriptor structure type definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Packet; /**< Receive Packet Descriptor */
|
||||
uint32_t Ctrl; /**< Receive Control Descriptor */
|
||||
} RX_Desc;
|
||||
|
||||
/**
|
||||
* @brief RX Status structure type definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Info; /**< Receive Information Status */
|
||||
uint32_t HashCRC; /**< Receive Hash CRC Status */
|
||||
} RX_Stat;
|
||||
|
||||
/**
|
||||
* @brief TX Descriptor structure type definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Packet; /**< Transmit Packet Descriptor */
|
||||
uint32_t Ctrl; /**< Transmit Control Descriptor */
|
||||
} TX_Desc;
|
||||
|
||||
/**
|
||||
* @brief TX Status structure type definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Info; /**< Transmit Information Status */
|
||||
} TX_Stat;
|
||||
|
||||
|
||||
/**
|
||||
* @brief TX Data Buffer structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t ulDataLen; /**< Data length */
|
||||
uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
|
||||
} EMAC_PACKETBUF_Type;
|
||||
|
||||
/**
|
||||
* @brief EMAC configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
|
||||
- EMAC_MODE_AUTO
|
||||
- EMAC_MODE_10M_FULL
|
||||
- EMAC_MODE_10M_HALF
|
||||
- EMAC_MODE_100M_FULL
|
||||
- EMAC_MODE_100M_HALF
|
||||
*/
|
||||
uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
|
||||
of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
|
||||
*/
|
||||
} EMAC_CFG_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup EMAC_Public_Functions EMAC Public Functions
|
||||
* @{
|
||||
*/
|
||||
/* Init/DeInit EMAC peripheral */
|
||||
Status EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
|
||||
void EMAC_DeInit(void);
|
||||
|
||||
/* PHY functions --------------*/
|
||||
int32_t EMAC_CheckPHYStatus(uint32_t ulPHYState);
|
||||
int32_t EMAC_SetPHYMode(uint32_t ulPHYMode);
|
||||
int32_t EMAC_UpdatePHYStatus(void);
|
||||
|
||||
/* Filter functions ----------*/
|
||||
void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState);
|
||||
void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState);
|
||||
|
||||
/* EMAC Packet Buffer functions */
|
||||
void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
|
||||
void EMAC_ReadPacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
|
||||
|
||||
/* EMAC Interrupt functions -------*/
|
||||
void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState);
|
||||
IntStatus EMAC_IntGetStatus(uint32_t ulIntType);
|
||||
|
||||
/* EMAC Index functions -----------*/
|
||||
Bool EMAC_CheckReceiveIndex(void);
|
||||
Bool EMAC_CheckTransmitIndex(void);
|
||||
void EMAC_UpdateRxConsumeIndex(void);
|
||||
void EMAC_UpdateTxProduceIndex(void);
|
||||
|
||||
FlagStatus EMAC_CheckReceiveDataStatus(uint32_t ulRxStatType);
|
||||
uint32_t EMAC_GetReceiveDataSize(void);
|
||||
FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* LPC17XX_EMAC_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@@ -1,155 +0,0 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc17xx_exti.h 2010-05-21
|
||||
*//**
|
||||
* @file lpc17xx_exti.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for External interrupt firmware library on LPC17xx
|
||||
* @version 2.0
|
||||
* @date 21. May. 2010
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2010, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup EXTI EXTI (External Interrupt)
|
||||
* @ingroup LPC1700CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef LPC17XX_EXTI_H_
|
||||
#define LPC17XX_EXTI_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC17xx.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||
* @{
|
||||
*/
|
||||
/*********************************************************************//**
|
||||
* Macro defines for EXTI control register
|
||||
**********************************************************************/
|
||||
#define EXTI_EINT0_BIT_MARK 0x01
|
||||
#define EXTI_EINT1_BIT_MARK 0x02
|
||||
#define EXTI_EINT2_BIT_MARK 0x04
|
||||
#define EXTI_EINT3_BIT_MARK 0x08
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup EXTI_Public_Types EXTI Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief EXTI external interrupt line option
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXTI_EINT0, /*!< External interrupt 0, P2.10 */
|
||||
EXTI_EINT1, /*!< External interrupt 0, P2.11 */
|
||||
EXTI_EINT2, /*!< External interrupt 0, P2.12 */
|
||||
EXTI_EINT3 /*!< External interrupt 0, P2.13 */
|
||||
} EXTI_LINE_ENUM;
|
||||
|
||||
/**
|
||||
* @brief EXTI mode option
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXTI_MODE_LEVEL_SENSITIVE, /*!< Level sensitivity is selected */
|
||||
EXTI_MODE_EDGE_SENSITIVE /*!< Edge sensitivity is selected */
|
||||
} EXTI_MODE_ENUM;
|
||||
|
||||
/**
|
||||
* @brief EXTI polarity option
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXTI_POLARITY_LOW_ACTIVE_OR_FALLING_EDGE, /*!< Low active or falling edge sensitive
|
||||
depending on pin mode */
|
||||
EXTI_POLARITY_HIGH_ACTIVE_OR_RISING_EDGE /*!< High active or rising edge sensitive
|
||||
depending on pin mode */
|
||||
} EXTI_POLARITY_ENUM;
|
||||
|
||||
/**
|
||||
* @brief EXTI Initialize structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
EXTI_LINE_ENUM EXTI_Line; /*!<Select external interrupt pin (EINT0, EINT1, EINT 2, EINT3) */
|
||||
|
||||
EXTI_MODE_ENUM EXTI_Mode; /*!< Choose between Level-sensitivity or Edge sensitivity */
|
||||
|
||||
EXTI_POLARITY_ENUM EXTI_polarity; /*!< If EXTI mode is level-sensitive: this element use to select low or high active level
|
||||
if EXTI mode is polarity-sensitive: this element use to select falling or rising edge */
|
||||
|
||||
}EXTI_InitTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup EXTI_Public_Functions EXTI Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void EXTI_Init(void);
|
||||
void EXTI_DeInit(void);
|
||||
|
||||
void EXTI_Config(EXTI_InitTypeDef *EXTICfg);
|
||||
void EXTI_SetMode(EXTI_LINE_ENUM EXTILine, EXTI_MODE_ENUM mode);
|
||||
void EXTI_SetPolarity(EXTI_LINE_ENUM EXTILine, EXTI_POLARITY_ENUM polarity);
|
||||
void EXTI_ClearEXTIFlag(EXTI_LINE_ENUM EXTILine);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* LPC17XX_EXTI_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
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Reference in New Issue
Block a user