fix issue with bcm2711 caching issue by ading ISB() after dwc2_dcd_int_enable90
also add hwcfg_list for reference
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@@ -56,11 +56,25 @@
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// MACRO TYPEDEF CONSTANT ENUM
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//--------------------------------------------------------------------+
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// DWC2 registers
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#define DWC2_REG(_port) ((dwc2_regs_t*) DWC2_REG_BASE)
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// Debug level for DWC2
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#define DWC2_DEBUG 2
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#ifndef dcache_clean
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#define dcache_clean(_addr, _size)
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#endif
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#ifndef dcache_invalidate
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#define dcache_invalidate(_addr, _size)
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#endif
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#ifndef dcache_clean_invalidate
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#define dcache_clean_invalidate(_addr, _size)
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#endif
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static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
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typedef struct {
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@@ -71,7 +85,7 @@ typedef struct {
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uint8_t interval;
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} xfer_ctl_t;
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xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
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static xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
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#define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir])
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// EP0 transfers are limited to 1 packet - larger sizes has to be split
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