add lpcopen lpc11u6x files
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hathach
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/*
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* @brief LPC11U6X System clock control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#include "chip.h"
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/*****************************************************************************
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* Private types/enumerations/variables
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****************************************************************************/
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/* Inprecise clock rates for the watchdog oscillator */
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STATIC const uint32_t wdtOSCRate[WDTLFO_OSC_4_60 + 1] = {
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0, /* WDT_OSC_ILLEGAL */
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600000, /* WDT_OSC_0_60 */
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1050000, /* WDT_OSC_1_05 */
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1400000, /* WDT_OSC_1_40 */
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1750000, /* WDT_OSC_1_75 */
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2100000, /* WDT_OSC_2_10 */
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2400000, /* WDT_OSC_2_40 */
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2700000, /* WDT_OSC_2_70 */
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3000000, /* WDT_OSC_3_00 */
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3250000, /* WDT_OSC_3_25 */
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3500000, /* WDT_OSC_3_50 */
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3750000, /* WDT_OSC_3_75 */
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4000000, /* WDT_OSC_4_00 */
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4200000, /* WDT_OSC_4_20 */
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4400000, /* WDT_OSC_4_40 */
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4600000 /* WDT_OSC_4_60 */
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};
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/*****************************************************************************
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* Public types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Private functions
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****************************************************************************/
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/* Compute a WDT rate */
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STATIC uint32_t Chip_Clock_GetWDTRate(uint32_t reg)
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{
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uint32_t div;
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CHIP_WDTLFO_OSC_T clk;
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/* Get WDT oscillator settings */
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clk = (CHIP_WDTLFO_OSC_T) ((reg >> 5) & 0xF);
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div = reg & 0x1F;
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/* Compute clock rate and divided by divde value */
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return wdtOSCRate[clk] / ((div + 1) << 1);
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}
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/* Compute a PLL frequency */
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STATIC uint32_t Chip_Clock_GetPLLFreq(uint32_t PLLReg, uint32_t inputRate)
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{
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uint32_t msel = ((PLLReg & 0x1F) + 1);
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return inputRate * msel;
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}
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/*****************************************************************************
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* Public functions
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****************************************************************************/
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/* Get USART 1/2/3/4 UART base rate */
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uint32_t Chip_Clock_GetUSARTNBaseClockRate(void)
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{
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uint64_t inclk;
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uint32_t div;
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div = (uint32_t) Chip_Clock_GetUSARTNBaseClockDiv();
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if (div == 0) {
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/* Divider is 0 so UART clock is disabled */
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inclk = 0;
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}
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else {
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uint32_t mult, divf;
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/* Input clock into FRG block is the divided main system clock */
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inclk = (uint64_t) (Chip_Clock_GetMainClockRate() / div);
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divf = Chip_Clock_GetUSARTNFRGDivider();
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if (divf == 0xFF) {
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/* Fractional part is enabled, get multiplier */
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mult = (uint32_t) Chip_Clock_GetUSARTNFRGMultiplier();
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/* Get fractional error */
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inclk = (inclk * 256) / (uint64_t) (256 + mult);
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}
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}
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return (uint32_t) inclk;
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}
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/* Set USART 1/2/3/4 UART base rate */
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uint32_t Chip_Clock_SetUSARTNBaseClockRate(uint32_t rate, bool fEnable)
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{
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uint32_t div, inclk;
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/* Input clock into FRG block is the main system clock */
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inclk = Chip_Clock_GetMainClockRate();
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/* Get integer divider for coarse rate */
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div = inclk / rate;
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if (div == 0) {
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div = 1;
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}
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/* Approximated rate with only integer divider */
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Chip_Clock_SetUSARTNBaseClockDiv((uint8_t) div);
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if (fEnable) {
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uint32_t uart_fra_multiplier;
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/* Reset FRG */
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Chip_SYSCTL_PeriphReset(RESET_FRG);
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/* Enable fractional divider */
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Chip_Clock_SetUSARTNFRGDivider(0xFF);
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/* Compute the fractional divisor (the lower byte is the
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fractional portion) */
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uart_fra_multiplier = ((inclk / div) * 256) / rate;
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/* ...just the fractional portion (the lower byte) */
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Chip_Clock_SetUSARTNFRGMultiplier((uint8_t) uart_fra_multiplier);
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}
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else {
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/* Disable fractional generator and use integer divider only */
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Chip_Clock_SetUSARTNFRGDivider(0);
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}
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return Chip_Clock_GetUSARTNBaseClockRate();
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}
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/* Set System PLL clock source */
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void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
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{
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LPC_SYSCTL->SYSPLLCLKSEL = (uint32_t) src;
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LPC_SYSCTL->SYSPLLCLKUEN = 0;
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LPC_SYSCTL->SYSPLLCLKUEN = 1;
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}
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/* Bypass System Oscillator and set oscillator frequency range */
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void Chip_Clock_SetPLLBypass(bool bypass, bool highfr)
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{
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uint32_t ctrl = 0;
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if (bypass) {
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ctrl |= (1 << 0);
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}
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if (highfr) {
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ctrl |= (1 << 1);
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}
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LPC_SYSCTL->SYSOSCCTRL = ctrl;
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}
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/* Set USB PLL clock source */
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void Chip_Clock_SetUSBPLLSource(CHIP_SYSCTL_USBPLLCLKSRC_T src)
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{
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LPC_SYSCTL->USBPLLCLKSEL = (uint32_t) src;
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LPC_SYSCTL->USBPLLCLKUEN = 0;
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LPC_SYSCTL->USBPLLCLKUEN = 1;
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}
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/* Set main system clock source */
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void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src)
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{
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LPC_SYSCTL->MAINCLKSEL = (uint32_t) src;
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LPC_SYSCTL->MAINCLKUEN = 0;
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LPC_SYSCTL->MAINCLKUEN = 1;
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}
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/* Set USB clock source and divider */
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void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div)
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{
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LPC_SYSCTL->USBCLKSEL = (uint32_t) src;
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LPC_SYSCTL->USBCLKUEN = 0;
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LPC_SYSCTL->USBCLKUEN = 1;
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LPC_SYSCTL->USBCLKDIV = div;
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}
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/* Set CLKOUT clock source and divider */
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void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div)
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{
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LPC_SYSCTL->CLKOUTSEL = (uint32_t) src;
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LPC_SYSCTL->CLKOUTUEN = 0;
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LPC_SYSCTL->CLKOUTUEN = 1;
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LPC_SYSCTL->CLKOUTDIV = div;
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}
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/* Return estimated watchdog oscillator rate */
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uint32_t Chip_Clock_GetWDTOSCRate(void)
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{
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return Chip_Clock_GetWDTRate(LPC_SYSCTL->WDTOSCCTRL);
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}
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/* Return System PLL input clock rate */
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uint32_t Chip_Clock_GetSystemPLLInClockRate(void)
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{
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uint32_t clkRate;
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switch ((CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->SYSPLLCLKSEL & 0x3)) {
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case SYSCTL_PLLCLKSRC_IRC:
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clkRate = Chip_Clock_GetIntOscRate();
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break;
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case SYSCTL_PLLCLKSRC_MAINOSC:
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clkRate = Chip_Clock_GetMainOscRate();
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break;
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case SYSCTL_PLLCLKSRC_RTC32K:
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clkRate = Chip_Clock_GetRTCOscRate();
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break;
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default:
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clkRate = 0;
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}
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return clkRate;
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}
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/* Return System PLL output clock rate */
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uint32_t Chip_Clock_GetSystemPLLOutClockRate(void)
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{
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return Chip_Clock_GetPLLFreq(LPC_SYSCTL->SYSPLLCTRL,
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Chip_Clock_GetSystemPLLInClockRate());
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}
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/* Return USB PLL input clock rate */
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uint32_t Chip_Clock_GetUSBPLLInClockRate(void)
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{
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uint32_t clkRate;
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switch ((CHIP_SYSCTL_USBPLLCLKSRC_T) (LPC_SYSCTL->USBPLLCLKSEL & 0x3)) {
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case SYSCTL_PLLCLKSRC_IRC:
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clkRate = Chip_Clock_GetIntOscRate();
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break;
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case SYSCTL_PLLCLKSRC_MAINOSC:
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clkRate = Chip_Clock_GetMainOscRate();
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break;
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default:
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clkRate = 0;
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}
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return clkRate;
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}
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/* Return USB PLL output clock rate */
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uint32_t Chip_Clock_GetUSBPLLOutClockRate(void)
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{
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return Chip_Clock_GetPLLFreq(LPC_SYSCTL->USBPLLCTRL,
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Chip_Clock_GetUSBPLLInClockRate());
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}
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/* Return main clock rate */
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uint32_t Chip_Clock_GetMainClockRate(void)
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{
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uint32_t clkRate = 0;
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switch ((CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL & 0x3)) {
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case SYSCTL_MAINCLKSRC_IRC:
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clkRate = Chip_Clock_GetIntOscRate();
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break;
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case SYSCTL_MAINCLKSRC_PLLIN:
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clkRate = Chip_Clock_GetSystemPLLInClockRate();
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break;
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case SYSCTL_MAINCLKSRC_WDTOSC:
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clkRate = Chip_Clock_GetWDTOSCRate();
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break;
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case SYSCTL_MAINCLKSRC_PLLOUT:
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clkRate = Chip_Clock_GetSystemPLLOutClockRate();
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break;
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}
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return clkRate;
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}
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/* Return system clock rate */
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uint32_t Chip_Clock_GetSystemClockRate(void)
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{
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/* No point in checking for divide by 0 */
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return Chip_Clock_GetMainClockRate() / LPC_SYSCTL->SYSAHBCLKDIV;
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}
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