diff --git a/demos/device/device_os_none/.cproject b/demos/device/device_os_none/.cproject
index 350f67d2..72f3110e 100644
--- a/demos/device/device_os_none/.cproject
+++ b/demos/device/device_os_none/.cproject
@@ -211,7 +211,7 @@
-
+
-
+
@@ -247,7 +247,7 @@
-
+
@@ -473,86 +473,73 @@
<?xml version="1.0" encoding="UTF-8"?>
<TargetConfig>
-<Properties property_0="" property_2="LPC18x7_43x7_2x512_BootA.cfx" property_3="NXP" property_4="LPC4357" property_count="5" version="1"/>
-<infoList vendor="NXP"><info chip="LPC4357" flash_driver="LPC18x7_43x7_2x512_BootA.cfx" match_id="0x0" name="LPC4357" resetscript="LPC18LPC43InternalFLASHBootResetscript.scp" stub="crt_emu_lpc18_43_nxp"><chip><name>LPC4357</name>
-<family>LPC43xx</family>
+<Properties property_0="" property_3="NXP" property_4="LPC1769" property_count="5" version="1"/>
+<infoList vendor="NXP"><info chip="LPC1769" match_id="0x26113F37" name="LPC1769" package="lpc17_lqfp100.xml"><chip><name>LPC1769</name>
+<family>LPC17xx</family>
<vendor>NXP (formerly Philips)</vendor>
<reset board="None" core="Real" sys="Real"/>
<clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/>
<memory can_program="true" id="Flash" is_ro="true" type="Flash"/>
<memory id="RAM" type="RAM"/>
<memory id="Periph" is_volatile="true" type="Peripheral"/>
-<memoryInstance derived_from="Flash" id="MFlashA512" location="0x1a000000" size="0x80000"/>
-<memoryInstance derived_from="Flash" id="MFlashB512" location="0x1b000000" size="0x80000"/>
+<memoryInstance derived_from="Flash" id="MFlash512" location="0x0" size="0x80000"/>
<memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/>
-<memoryInstance derived_from="RAM" id="RamLoc40" location="0x10080000" size="0xa000"/>
-<memoryInstance derived_from="RAM" id="RamAHB32" location="0x20000000" size="0x8000"/>
-<memoryInstance derived_from="RAM" id="RamAHB16" location="0x20008000" size="0x4000"/>
-<memoryInstance derived_from="RAM" id="RamAHB_ETB16" location="0x2000c000" size="0x4000"/>
-<prog_flash blocksz="0x2000" location="0x1a000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/>
-<prog_flash blocksz="0x10000" location="0x1a010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/>
-<prog_flash blocksz="0x2000" location="0x1b000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/>
-<prog_flash blocksz="0x10000" location="0x1b010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/>
-<peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/>
-<peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/>
-<peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/>
-<peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/>
-<peripheralInstance derived_from="SCT" id="SCT" location="0x40000000"/>
-<peripheralInstance derived_from="GPDMA" id="GPDMA" location="0x40002000"/>
-<peripheralInstance derived_from="SPIFI" id="SPIFI" location="0x40003000"/>
-<peripheralInstance derived_from="SDMMC" id="SDMMC" location="0x40004000"/>
-<peripheralInstance derived_from="EMC" id="EMC" location="0x40005000"/>
-<peripheralInstance derived_from="USB0" id="USB0" location="0x40006000"/>
-<peripheralInstance derived_from="USB1" id="USB1" location="0x40007000"/>
-<peripheralInstance derived_from="LCD" id="LCD" location="0x40008000"/>
-<peripheralInstance derived_from="EEPROM" id="EEPROM" location="0x4000e000"/>
-<peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x40010000"/>
-<peripheralInstance derived_from="ATIMER" id="ATIMER" location="0x40040000"/>
-<peripheralInstance derived_from="REGFILE" id="REGFILE" location="0x40041000"/>
-<peripheralInstance derived_from="PMC" id="PMC" location="0x40042000"/>
-<peripheralInstance derived_from="CREG" id="CREG" location="0x40043000"/>
-<peripheralInstance derived_from="EVENTROUTER" id="EVENTROUTER" location="0x40044000"/>
-<peripheralInstance derived_from="RTC" id="RTC" location="0x40046000"/>
-<peripheralInstance derived_from="CGU" id="CGU" location="0x40050000"/>
-<peripheralInstance derived_from="CCU1" id="CCU1" location="0x40051000"/>
-<peripheralInstance derived_from="CCU2" id="CCU2" location="0x40052000"/>
-<peripheralInstance derived_from="RGU" id="RGU" location="0x40053000"/>
-<peripheralInstance derived_from="WWDT" id="WWDT" location="0x40080000"/>
-<peripheralInstance derived_from="USART0" id="USART0" location="0x40081000"/>
-<peripheralInstance derived_from="USART2" id="USART2" location="0x400c1000"/>
-<peripheralInstance derived_from="USART3" id="USART3" location="0x400c2000"/>
-<peripheralInstance derived_from="UART1" id="UART1" location="0x40082000"/>
-<peripheralInstance derived_from="SSP0" id="SSP0" location="0x40083000"/>
-<peripheralInstance derived_from="SSP1" id="SSP1" location="0x400c5000"/>
-<peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40084000"/>
-<peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40085000"/>
-<peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x400c3000"/>
-<peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x400c4000"/>
-<peripheralInstance derived_from="SCU" id="SCU" location="0x40086000"/>
-<peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x40087000"/>
-<peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x40088000"/>
-<peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40089000"/>
-<peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400a0000"/>
-<peripheralInstance derived_from="I2C0" id="I2C0" location="0x400a1000"/>
-<peripheralInstance derived_from="I2C1" id="I2C1" location="0x400e0000"/>
-<peripheralInstance derived_from="I2S0" id="I2S0" location="0x400a2000"/>
-<peripheralInstance derived_from="I2S1" id="I2S1" location="0x400a3000"/>
-<peripheralInstance derived_from="C-CAN1" id="C-CAN1" location="0x400a4000"/>
-<peripheralInstance derived_from="RITIMER" id="RITIMER" location="0x400c0000"/>
-<peripheralInstance derived_from="QEI" id="QEI" location="0x400c6000"/>
-<peripheralInstance derived_from="GIMA" id="GIMA" location="0x400c7000"/>
-<peripheralInstance derived_from="DAC" id="DAC" location="0x400e1000"/>
-<peripheralInstance derived_from="C-CAN0" id="C-CAN0" location="0x400e2000"/>
-<peripheralInstance derived_from="ADC0" id="ADC0" location="0x400e3000"/>
-<peripheralInstance derived_from="ADC1" id="ADC1" location="0x400e4000"/>
-<peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x400f4000"/>
-<peripheralInstance derived_from="SPI" id="SPI" location="0x40100000"/>
-<peripheralInstance derived_from="SGPIO" id="SGPIO" location="0x40101000"/>
+<memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/>
+<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/>
+<prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/>
+<peripheralInstance derived_from="LPC17_NVIC" id="NVIC" location="0xE000E000"/>
+<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM0&0x1" id="TIMER0" location="0x40004000"/>
+<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM1&0x1" id="TIMER1" location="0x40008000"/>
+<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM2&0x1" id="TIMER2" location="0x40090000"/>
+<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM3&0x1" id="TIMER3" location="0x40094000"/>
+<peripheralInstance derived_from="LPC17_RIT" enable="SYSCTL.PCONP.PCRIT&0x1" id="RIT" location="0x400B0000"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO0" location="0x2009C000"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO1" location="0x2009C020"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO2" location="0x2009C040"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO3" location="0x2009C060"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO4" location="0x2009C080"/>
+<peripheralInstance derived_from="LPC17_I2S" enable="SYSCTL.PCONP&0x08000000" id="I2S" location="0x400A8000"/>
+<peripheralInstance derived_from="LPC17_SYSCTL" id="SYSCTL" location="0x400FC000"/>
+<peripheralInstance derived_from="LPC17_DAC" enable="PCB.PINSEL1.P0_26&0x2=2" id="DAC" location="0x4008C000"/>
+<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART0&0x1" id="UART0" location="0x4000C000"/>
+<peripheralInstance derived_from="LPC17xx_UART_MODEM" enable="SYSCTL.PCONP.PCUART1&0x1" id="UART1" location="0x40010000"/>
+<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART2&0x1" id="UART2" location="0x40098000"/>
+<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART3&0x1" id="UART3" location="0x4009C000"/>
+<peripheralInstance derived_from="SPI" enable="SYSCTL.PCONP.PCSPI&0x1" id="SPI" location="0x40020000"/>
+<peripheralInstance derived_from="LPC17_SSP" enable="SYSCTL.PCONP.PCSSP0&0x1" id="SSP0" location="0x40088000"/>
+<peripheralInstance derived_from="LPC17_SSP" enable="SYSCTL.PCONP.PCSSP1&0x1" id="SSP1" location="0x40030000"/>
+<peripheralInstance derived_from="LPC17_ADC" enable="SYSCTL.PCONP.PCAD&0x1" id="ADC" location="0x40034000"/>
+<peripheralInstance derived_from="LPC17_USBINTST" enable="USBCLKCTL.USBClkCtrl&0x12" id="USBINTSTAT" location="0x400fc1c0"/>
+<peripheralInstance derived_from="LPC17_USB_CLK_CTL" id="USBCLKCTL" location="0x5000cff4"/>
+<peripheralInstance derived_from="LPC17_USBDEV" enable="USBCLKCTL.USBClkSt&0x12=0x12" id="USBDEV" location="0x5000C200"/>
+<peripheralInstance derived_from="LPC17_PWM" enable="SYSCTL.PCONP.PWM1&0x1" id="PWM" location="0x40018000"/>
+<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C0&0x1" id="I2C0" location="0x4001C000"/>
+<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C1&0x1" id="I2C1" location="0x4005C000"/>
+<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C2&0x1" id="I2C2" location="0x400A0000"/>
+<peripheralInstance derived_from="LPC17_DMA" enable="SYSCTL.PCONP.PCGPDMA&0x1" id="DMA" location="0x50004000"/>
+<peripheralInstance derived_from="LPC17_ENET" enable="SYSCTL.PCONP.PCENET&0x1" id="ENET" location="0x50000000"/>
+<peripheralInstance derived_from="CM3_DCR" id="DCR" location="0xE000EDF0"/>
+<peripheralInstance derived_from="LPC17_PCB" id="PCB" location="0x4002c000"/>
+<peripheralInstance derived_from="LPC17_QEI" enable="SYSCTL.PCONP.PCQEI&0x1" id="QEI" location="0x400bc000"/>
+<peripheralInstance derived_from="LPC17_USBHOST" enable="USBCLKCTL.USBClkSt&0x11=0x11" id="USBHOST" location="0x5000C000"/>
+<peripheralInstance derived_from="LPC17_USBOTG" enable="USBCLKCTL.USBClkSt&0x1c=0x1c" id="USBOTG" location="0x5000C000"/>
+<peripheralInstance derived_from="LPC17_RTC" enable="SYSCTL.PCONP.PCRTC&0x1" id="RTC" location="0x40024000"/>
+<peripheralInstance derived_from="MPU" id="MPU" location="0xE000ED90"/>
+<peripheralInstance derived_from="LPC1x_WDT" id="WDT" location="0x40000000"/>
+<peripheralInstance derived_from="LPC17_FLASHCFG" id="FLASHACCEL" location="0x400FC000"/>
+<peripheralInstance derived_from="GPIO_INT" id="GPIOINTMAP" location="0x40028080"/>
+<peripheralInstance derived_from="LPC17_CANAFR" enable="SYSCTL.PCONP.PCCAN1&0x1|SYSCTL.PCONP.PCCAN2&0x1" id="CANAFR" location="0x4003C000"/>
+<peripheralInstance derived_from="LPC17_CANCEN" enable="SYSCTL.PCONP.PCCAN1&0x1|SYSCTL.PCONP.PCCAN2&0x1" id="CANCEN" location="0x40040000"/>
+<peripheralInstance derived_from="LPC17_CANWAKESLEEP" id="CANWAKESLEEP" location="0x400FC110"/>
+<peripheralInstance derived_from="LPC17_CANCON" enable="SYSCTL.PCONP.PCCAN1&0x1" id="CANCON1" location="0x40044000"/>
+<peripheralInstance derived_from="LPC17_CANCON" enable="SYSCTL.PCONP.PCCAN2&0x1" id="CANCON2" location="0x40048000"/>
+<peripheralInstance derived_from="LPC17_MCPWM" enable="SYSCTL.PCONP.PCMCPWM&0x1" id="MCPWM" location="0x400B8000"/>
+<peripheralInstance derived_from="LPC17_FMC" id="FMC" location="0x40084000"/>
</chip>
-<processor><name gcc_name="cortex-m4">Cortex-M4</name>
+<processor><name gcc_name="cortex-m3">Cortex-M3</name>
<family>Cortex-M</family>
</processor>
-<link href="nxp_lpc43xx_peripheral.xme" show="embed" type="simple"/>
+<link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/>
</info>
</infoList>
</TargetConfig>
diff --git a/demos/device/src/tusb_config.h b/demos/device/src/tusb_config.h
index 27809357..512d2399 100644
--- a/demos/device/src/tusb_config.h
+++ b/demos/device/src/tusb_config.h
@@ -82,11 +82,11 @@
#define TUSB_CFG_DEVICE_FULLSPEED 1 // TODO refractor, remove
//------------- CLASS -------------//
-#define TUSB_CFG_DEVICE_HID_KEYBOARD 0
-#define TUSB_CFG_DEVICE_HID_MOUSE 0
+#define TUSB_CFG_DEVICE_HID_KEYBOARD 1
+#define TUSB_CFG_DEVICE_HID_MOUSE 1
#define TUSB_CFG_DEVICE_HID_GENERIC 0
#define TUSB_CFG_DEVICE_MSC 1
-#define TUSB_CFG_DEVICE_CDC 0
+#define TUSB_CFG_DEVICE_CDC 1
//--------------------------------------------------------------------+
// COMMON CONFIGURATION
diff --git a/tinyusb/device/dcd_lpc175x_6x.c b/tinyusb/device/dcd_lpc175x_6x.c
index a7a43da6..058891e5 100644
--- a/tinyusb/device/dcd_lpc175x_6x.c
+++ b/tinyusb/device/dcd_lpc175x_6x.c
@@ -58,11 +58,8 @@ typedef struct {
volatile ATTR_ALIGNED(128) dcd_dma_descriptor_t* udca[DCD_QHD_MAX];
dcd_dma_descriptor_t dd[DCD_QTD_MAX][2]; // each endpoints can have up to 2 DD queued at a time TODO 0-1 are not used, offset to reduce memory
-// uint8_t ddat[DCD_QHD_MAX]; ///< DMA Descriptor Allocation Table. A fixed DD will be allocated for a UDCA pointer up on endpoint open
uint8_t class_code[DCD_QHD_MAX];
-// volatile uint32_t ioc_dd; ///< each bit for each DD
-
struct {
uint8_t* p_data;
uint16_t remaining_bytes;
@@ -104,30 +101,6 @@ static inline void edpt_set_max_packet_size(uint8_t ep_id, uint16_t max_packet_s
}
-// retval UINT8_MAX: invalid
-//static inline uint8_t dd_find_free(void) ATTR_PURE ATTR_ALWAYS_INLINE;
-//static inline uint8_t dd_find_free(void)
-//{
-// for(uint8_t i=0; iis_next_valid) ? (&dcd_data.dd[ep_id][1]) : p_fixed_dd;
+ dcd_dma_descriptor_t* const p_first_dd = &dcd_data.dd[ep_id][0];
+ dcd_dma_descriptor_t* const p_last_dd = dcd_data.dd[ep_id] + (p_first_dd->is_next_valid ? 1 : 0); // Maximum is 2 QTD are queued in an endpoint
// only handle when Controller already finished the last DD
if ( dcd_data.udca[ep_id] == p_last_dd )
{
- dcd_data.udca[ep_id] = p_fixed_dd; // UDCA currently points to the last DD, change to the fixed DD
- p_fixed_dd->buffer_length = 0; // buffer length is used to determined if fixed dd is queued in pipe xfer function
-
-// if (p_fixed_dd->is_next_valid)
-// { // last_dd is not fixed_dd --> need to free
-// p_last_dd->used = 0;
-// }
+ dcd_data.udca[ep_id] = p_first_dd; // UDCA currently points to the last DD, change to the fixed DD
+ p_first_dd->buffer_length = 0; // buffer length is used to determined if first dd is queued in pipe xfer function
if ( p_last_dd->int_on_complete )
{
-// dcd_data.ioc_dd = BIT_CLR_(dcd_data.ioc_dd, dd_get_index(p_last_dd) );
-
endpoint_handle_t edpt_hdl =
{
.coreid = 0,
@@ -200,7 +165,7 @@ static void endpoint_non_control_isr(uint32_t eot_int)
};
tusb_event_t event = (p_last_dd->status == DD_STATUS_NORMAL || p_last_dd->status == DD_STATUS_DATA_UNDERUN) ? TUSB_EVENT_XFER_COMPLETE : TUSB_EVENT_XFER_ERROR;
- usbd_xfer_isr(edpt_hdl, event, p_last_dd->present_count); // only number of bytes in the IOC qtd
+ usbd_xfer_isr(edpt_hdl, event, p_last_dd->present_count); // report only xferred bytes in the IOC qtd
}
}
}
@@ -233,18 +198,12 @@ static void endpoint_control_isr(void)
else
{
dcd_data.control_dma.remaining_bytes = 0;
-// if ( ep_id == 0 )
-// { // always need to read from OUT endpoint in interrupt handler
-// pipe_control_xfer(ep_id, dcd_data.control_dma.p_data, dcd_data.control_dma.remaining_bytes);
-// }
if ( BIT_TEST_(dcd_data.control_dma.int_on_complete, ep_id) )
{
endpoint_handle_t edpt_hdl = { .coreid = 0, .class_code = 0 };
dcd_data.control_dma.int_on_complete = 0;
-// dcd_data.ioc_dd = BIT_CLR_(dcd_data.ioc_dd, ep_id);
-
// FIXME xferred_byte for control xfer is not needed now !!!
usbd_xfer_isr(edpt_hdl, TUSB_EVENT_XFER_COMPLETE, 0);
}
@@ -437,10 +396,9 @@ tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, void *
//------------- Status Phase (opposite direct to Data) -------------//
if (dir == TUSB_DIR_HOST_TO_DEV)
- { // only write for CONTROL OUT, CONTROL IN data will be retrieved in dcd_isr
+ { // only write for CONTROL OUT, CONTROL IN data will be retrieved in dcd_isr // TODO ????
ASSERT_STATUS ( pipe_control_write(NULL, 0) );
}
-// ASSERT_STATUS ( pipe_control_xfer(ep_status, NULL, 0) );
return TUSB_ERROR_NONE;
}
@@ -462,14 +420,9 @@ endpoint_handle_t dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const
//------------- Realize Endpoint with Max Packet Size -------------//
edpt_set_max_packet_size(ep_id, p_endpoint_desc->wMaxPacketSize.size);
-
- //------------- fixed DD prepare -------------//
-// uint8_t const dd_idx = dd_find_free();
-// ASSERT(dd_idx != UINT8_MAX, null_handle);
-
-// dcd_data.ddat[ep_id] = dd_idx; // fixed this DD to UDCA for this endpoint
dcd_data.class_code[ep_id] = class_code;
+ //------------- first DD prepare -------------//
dcd_dma_descriptor_t* const p_dd = &dcd_data.dd[ep_id][0];
memclr_(p_dd, sizeof(dcd_dma_descriptor_t));
@@ -522,54 +475,45 @@ void dd_xfer_init(dcd_dma_descriptor_t* p_dd, void* buffer, uint16_t total_bytes
tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint16_t total_bytes)
{ // NOTE for sure the qhd has no dds
- dcd_dma_descriptor_t* const p_fixed_dd = &dcd_data.dd[edpt_hdl.index][0]; // qhd_get_fixed_dd(edpt_hdl.index); // always queue with the fixed DD
+ dcd_dma_descriptor_t* const p_fixed_dd = &dcd_data.dd[edpt_hdl.index][0]; // always queue with the fixed DD
dd_xfer_init(p_fixed_dd, buffer, total_bytes);
p_fixed_dd->is_retired = 1;
p_fixed_dd->int_on_complete = 0;
-// dcd_data.ioc_dd = BIT_CLR_(dcd_data.ioc_dd, edpt_hdl.index);
-
return TUSB_ERROR_NONE;
}
tusb_error_t dcd_pipe_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint16_t total_bytes, bool int_on_complete)
{
- dcd_dma_descriptor_t* const p_fixed_dd = &dcd_data.dd[edpt_hdl.index][0];
+ dcd_dma_descriptor_t* const p_first_dd = &dcd_data.dd[edpt_hdl.index][0];
//------------- fixed DD is already queued a xfer -------------//
- if ( p_fixed_dd->buffer_length )
+ if ( p_first_dd->buffer_length )
{
- //------------- setup new dd -------------//
-// uint8_t dd_idx = dd_find_free();
-// ASSERT( dd_idx != UINT8_MAX, TUSB_ERROR_DCD_NOT_ENOUGH_QTD);
-
+ // setup new dd
dcd_dma_descriptor_t* const p_dd = &dcd_data.dd[ edpt_hdl.index ][1];
memclr_(p_dd, sizeof(dcd_dma_descriptor_t));
dd_xfer_init(p_dd, buffer, total_bytes);
- p_dd->max_packet_size = p_fixed_dd->max_packet_size;
- p_dd->is_isochronous = p_fixed_dd->is_isochronous;
- p_dd->int_on_complete = int_on_complete;
+ p_dd->max_packet_size = p_first_dd->max_packet_size;
+ p_dd->is_isochronous = p_first_dd->is_isochronous;
+ p_dd->int_on_complete = int_on_complete;
- //------------- hook to fixed dd -------------//
- p_fixed_dd->next = (uint32_t) p_dd;
- p_fixed_dd->is_next_valid = 1;
+ // hook to fixed dd
+ p_first_dd->next = (uint32_t) p_dd;
+ p_first_dd->is_next_valid = 1;
}
//------------- fixed DD is free -------------//
else
{
- dd_xfer_init(p_fixed_dd, buffer, total_bytes);
- p_fixed_dd->int_on_complete = int_on_complete;
-// dcd_data.ioc_dd = int_on_complete ? BIT_SET_(dcd_data.ioc_dd, dcd_data.ddat[edpt_hdl.index]) :
-// BIT_CLR_(dcd_data.ioc_dd, dcd_data.ddat[edpt_hdl.index]);
+ dd_xfer_init(p_first_dd, buffer, total_bytes);
+ p_first_dd->int_on_complete = int_on_complete;
}
- p_fixed_dd->is_retired = 0;
-
- dcd_data.udca[edpt_hdl.index] = p_fixed_dd;
-
+ p_first_dd->is_retired = 0; // activate xfer
+ dcd_data.udca[edpt_hdl.index] = p_first_dd;
LPC_USB->USBEpDMAEn = BIT_(edpt_hdl.index);
if ( edpt_hdl.index % 2 )