nxp tdi: hcd_init() reset and set host mode
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hathach
@@ -32,9 +32,6 @@
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//--------------------------------------------------------------------+
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// INCLUDE
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//--------------------------------------------------------------------+
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#include "common/tusb_common.h"
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#include "device/dcd.h"
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#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
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#include "fsl_device_registers.h"
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#else
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@@ -42,6 +39,10 @@
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#include "chip.h"
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#endif
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#include "common/tusb_common.h"
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#include "device/dcd.h"
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#include "common_transdimension.h"
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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#define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr
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#else
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@@ -60,15 +61,6 @@ enum {
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ENDPTCTRL_ENABLE = TU_BIT(7)
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};
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// USBCMD
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enum {
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USBCMD_RUN_STOP = TU_BIT(0),
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USBCMD_RESET = TU_BIT(1),
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USBCMD_SETUP_TRIPWIRE = TU_BIT(13),
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USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14) ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
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};
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// Interrupt Threshold bit 23:16
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// USBSTS, USBINTR
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enum {
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INTR_USB = TU_BIT(0),
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@@ -80,96 +72,6 @@ enum {
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INTR_NAK = TU_BIT(16)
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};
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// PORTSC1
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#define PORTSC1_PORT_SPEED_POS 26
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enum {
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PORTSC1_CURRENT_CONNECT_STATUS = TU_BIT(0),
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PORTSC1_FORCE_PORT_RESUME = TU_BIT(6),
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PORTSC1_SUSPEND = TU_BIT(7),
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PORTSC1_FORCE_FULL_SPEED = TU_BIT(24),
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PORTSC1_PORT_SPEED = TU_BIT(26) | TU_BIT(27)
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};
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// OTGSC
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enum {
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OTGSC_VBUS_DISCHARGE = TU_BIT(0),
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OTGSC_VBUS_CHARGE = TU_BIT(1),
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// OTGSC_HWASSIST_AUTORESET = TU_BIT(2),
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OTGSC_OTG_TERMINATION = TU_BIT(3), ///< Must set to 1 when OTG go to device mode
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OTGSC_DATA_PULSING = TU_BIT(4),
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OTGSC_ID_PULLUP = TU_BIT(5),
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// OTGSC_HWASSIT_DATA_PULSE = TU_BIT(6),
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// OTGSC_HWASSIT_BDIS_ACONN = TU_BIT(7),
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OTGSC_ID = TU_BIT(8), ///< 0 = A device, 1 = B Device
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OTGSC_A_VBUS_VALID = TU_BIT(9),
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OTGSC_A_SESSION_VALID = TU_BIT(10),
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OTGSC_B_SESSION_VALID = TU_BIT(11),
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OTGSC_B_SESSION_END = TU_BIT(12),
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OTGSC_1MS_TOGGLE = TU_BIT(13),
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OTGSC_DATA_BUS_PULSING_STATUS = TU_BIT(14),
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};
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// USBMode
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enum {
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USBMODE_CM_DEVICE = 2,
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USBMODE_CM_HOST = 3,
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USBMODE_SLOM = TU_BIT(3),
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USBMODE_SDIS = TU_BIT(4),
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USBMODE_VBUS_POWER_SELCT = TU_BIT(5), // Enable for LPC18XX/43XX in host most only
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};
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// Device Registers
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typedef struct
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{
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//------------- ID + HW Parameter Registers-------------//
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__I uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX
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//------------- Capability Registers-------------//
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__I uint8_t CAPLENGTH; ///< Capability Registers Length
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__I uint8_t TU_RESERVED[1];
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__I uint16_t HCIVERSION; ///< Host Controller Interface Version
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__I uint32_t HCSPARAMS; ///< Host Controller Structural Parameters
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__I uint32_t HCCPARAMS; ///< Host Controller Capability Parameters
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__I uint32_t TU_RESERVED[5];
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__I uint16_t DCIVERSION; ///< Device Controller Interface Version
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__I uint8_t TU_RESERVED[2];
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__I uint32_t DCCPARAMS; ///< Device Controller Capability Parameters
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__I uint32_t TU_RESERVED[6];
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//------------- Operational Registers -------------//
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__IO uint32_t USBCMD; ///< USB Command Register
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__IO uint32_t USBSTS; ///< USB Status Register
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__IO uint32_t USBINTR; ///< Interrupt Enable Register
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__IO uint32_t FRINDEX; ///< USB Frame Index
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__I uint32_t TU_RESERVED;
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__IO uint32_t DEVICEADDR; ///< Device Address
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__IO uint32_t ENDPTLISTADDR; ///< Endpoint List Address
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__I uint32_t TU_RESERVED;
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__IO uint32_t BURSTSIZE; ///< Programmable Burst Size
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__IO uint32_t TXFILLTUNING; ///< TX FIFO Fill Tuning
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uint32_t TU_RESERVED[4];
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__IO uint32_t ENDPTNAK; ///< Endpoint NAK
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__IO uint32_t ENDPTNAKEN; ///< Endpoint NAK Enable
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__I uint32_t TU_RESERVED;
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__IO uint32_t PORTSC1; ///< Port Status & Control
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__I uint32_t TU_RESERVED[7];
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__IO uint32_t OTGSC; ///< On-The-Go Status & control
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__IO uint32_t USBMODE; ///< USB Device Mode
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__IO uint32_t ENDPTSETUPSTAT; ///< Endpoint Setup Status
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__IO uint32_t ENDPTPRIME; ///< Endpoint Prime
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__IO uint32_t ENDPTFLUSH; ///< Endpoint Flush
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__I uint32_t ENDPTSTAT; ///< Endpoint Status
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__IO uint32_t ENDPTCOMPLETE; ///< Endpoint Complete
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__IO uint32_t ENDPTCTRL[8]; ///< Endpoint Control 0 - 7
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} dcd_registers_t;
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// Queue Transfer Descriptor
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typedef struct
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{
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@@ -279,7 +181,7 @@ CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048)
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static dcd_data_t _dcd_data;
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//--------------------------------------------------------------------+
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// CONTROLLER API
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// Controller API
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//--------------------------------------------------------------------+
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/// follows LPC43xx User Manual 23.10.3
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