RP2040 support
This commit is contained in:
graham sanderson
@@ -0,0 +1,549 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "tusb_option.h"
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#if TUSB_OPT_HOST_ENABLED && CFG_TUSB_MCU == OPT_MCU_RP2040
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#include "pico.h"
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#include "rp2040_usb.h"
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//--------------------------------------------------------------------+
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// INCLUDE
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//--------------------------------------------------------------------+
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#include "osal/osal.h"
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#include "host/hcd.h"
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#include "host/usbh.h"
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#include "host/usbh_hcd.h"
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#define ROOT_PORT 0
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//--------------------------------------------------------------------+
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// Low level rp2040 controller functions
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//--------------------------------------------------------------------+
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#ifndef PICO_USB_HOST_INTERRUPT_ENDPOINTS
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#define PICO_USB_HOST_INTERRUPT_ENDPOINTS (USB_MAX_ENDPOINTS - 1)
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#endif
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static_assert(PICO_USB_HOST_INTERRUPT_ENDPOINTS <= USB_MAX_ENDPOINTS, "");
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// Host mode uses one shared endpoint register for non-interrupt endpoint
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struct hw_endpoint eps[1 + PICO_USB_HOST_INTERRUPT_ENDPOINTS];
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#define epx (eps[0])
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#define usb_hw_set hw_set_alias(usb_hw)
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#define usb_hw_clear hw_clear_alias(usb_hw)
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// Used for hcd pipe busy.
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// todo still a bit wasteful
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// top bit set if valid
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uint8_t dev_ep_map[CFG_TUSB_HOST_DEVICE_MAX][1 + PICO_USB_HOST_INTERRUPT_ENDPOINTS][2];
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// Flags we set by default in sie_ctrl (we add other bits on top)
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static uint32_t sie_ctrl_base = USB_SIE_CTRL_SOF_EN_BITS |
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USB_SIE_CTRL_KEEP_ALIVE_EN_BITS |
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USB_SIE_CTRL_PULLDOWN_EN_BITS |
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USB_SIE_CTRL_EP0_INT_1BUF_BITS;
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static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr)
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{
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uint8_t num = tu_edpt_number(ep_addr);
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if (num == 0) {
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return &epx;
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}
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uint8_t in = (ep_addr & TUSB_DIR_IN_MASK) ? 1 : 0;
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uint mapping = dev_ep_map[dev_addr-1][num][in];
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pico_trace("Get dev addr %d ep %d = %d\n", dev_addr, ep_addr, mapping);
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return mapping >= 128 ? eps + (mapping & 0x7fu) : NULL;
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}
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static void set_dev_ep(uint8_t dev_addr, uint8_t ep_addr, struct hw_endpoint *ep)
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{
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uint8_t num = tu_edpt_number(ep_addr);
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uint8_t in = (ep_addr & TUSB_DIR_IN_MASK) ? 1 : 0;
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uint32_t index = ep - eps;
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hard_assert(index < count_of(eps));
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// todo revisit why dev_addr can be 0 here
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if (dev_addr) {
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dev_ep_map[dev_addr-1][num][in] = 128u | index;
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}
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pico_trace("Set dev addr %d ep %d = %d\n", dev_addr, ep_addr, index);
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}
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static inline uint8_t dev_speed(void)
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{
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return (usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS) >> USB_SIE_STATUS_SPEED_LSB;
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}
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static bool need_pre(uint8_t dev_addr)
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{
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// If this device is different to the speed of the root device
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// (i.e. is a low speed device on a full speed hub) then need pre
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return hcd_port_speed_get(0) != tuh_device_get_speed(dev_addr);
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}
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static void hw_xfer_complete(struct hw_endpoint *ep, xfer_result_t xfer_result)
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{
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// Mark transfer as done before we tell the tinyusb stack
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uint8_t dev_addr = ep->dev_addr;
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uint8_t ep_addr = ep->ep_addr;
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uint total_len = ep->total_len;
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hw_endpoint_reset_transfer(ep);
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hcd_event_xfer_complete(dev_addr, ep_addr, total_len, xfer_result, true);
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}
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static void _handle_buff_status_bit(uint bit, struct hw_endpoint *ep)
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{
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usb_hw_clear->buf_status = bit;
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bool done = _hw_endpoint_xfer_continue(ep);
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if (done)
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{
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hw_xfer_complete(ep, XFER_RESULT_SUCCESS);
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}
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}
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static void hw_handle_buff_status(void)
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{
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uint32_t remaining_buffers = usb_hw->buf_status;
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pico_trace("buf_status 0x%08x\n", remaining_buffers);
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// Check EPX first
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uint bit = 0b1;
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if (remaining_buffers & bit)
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{
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remaining_buffers &= ~bit;
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struct hw_endpoint *ep = &epx;
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_handle_buff_status_bit(bit, ep);
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}
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// Check interrupt endpoints
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for (uint i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS && remaining_buffers; i++)
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{
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// EPX is bit 0
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// IEP1 is bit 2
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// IEP2 is bit 4
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// IEP3 is bit 6
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// etc
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bit = 1 << (i*2);
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if (remaining_buffers & bit)
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{
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remaining_buffers &= ~bit;
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_handle_buff_status_bit(bit, &eps[i]);
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}
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}
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if (remaining_buffers)
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{
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panic("Unhandled buffer %d\n", remaining_buffers);
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}
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}
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static void hw_trans_complete(void)
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{
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struct hw_endpoint *ep = &epx;
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assert(ep->active);
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if (ep->sent_setup)
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{
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pico_trace("Sent setup packet\n");
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hw_xfer_complete(ep, XFER_RESULT_SUCCESS);
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}
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else
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{
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// Don't care. Will handle this in buff status
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return;
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}
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}
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static void hcd_rp2040_irq(void)
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{
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uint32_t status = usb_hw->ints;
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uint32_t handled = 0;
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if (status & USB_INTS_HOST_CONN_DIS_BITS)
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{
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handled |= USB_INTS_HOST_CONN_DIS_BITS;
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if (dev_speed())
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{
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hcd_event_device_attach(ROOT_PORT, true);
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}
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else
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{
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hcd_event_device_remove(ROOT_PORT, true);
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}
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// Clear speed change interrupt
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usb_hw_clear->sie_status = USB_SIE_STATUS_SPEED_BITS;
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}
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if (status & USB_INTS_TRANS_COMPLETE_BITS)
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{
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handled |= USB_INTS_TRANS_COMPLETE_BITS;
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usb_hw_clear->sie_status = USB_SIE_STATUS_TRANS_COMPLETE_BITS;
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hw_trans_complete();
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}
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if (status & USB_INTS_BUFF_STATUS_BITS)
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{
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handled |= USB_INTS_BUFF_STATUS_BITS;
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hw_handle_buff_status();
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}
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if (status & USB_INTS_STALL_BITS)
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{
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// We have rx'd a stall from the device
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pico_trace("Stall REC\n");
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handled |= USB_INTS_STALL_BITS;
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usb_hw_clear->sie_status = USB_SIE_STATUS_STALL_REC_BITS;
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hw_xfer_complete(&epx, XFER_RESULT_STALLED);
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}
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if (status & USB_INTS_ERROR_RX_TIMEOUT_BITS)
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{
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handled |= USB_INTS_ERROR_RX_TIMEOUT_BITS;
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usb_hw_clear->sie_status = USB_SIE_STATUS_RX_TIMEOUT_BITS;
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}
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if (status & USB_INTS_ERROR_DATA_SEQ_BITS)
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{
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usb_hw_clear->sie_status = USB_SIE_STATUS_DATA_SEQ_ERROR_BITS;
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panic("Data Seq Error \n");
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}
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if (status ^ handled)
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{
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panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled));
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}
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}
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static struct hw_endpoint *_next_free_interrupt_ep(void)
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{
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struct hw_endpoint *ep = NULL;
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for (uint i = 1; i < count_of(eps); i++)
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{
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ep = &eps[i];
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if (!ep->configured)
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{
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// Will be configured by _hw_endpoint_init / _hw_endpoint_allocate
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ep->interrupt_num = i - 1;
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return ep;
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}
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}
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return ep;
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}
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static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type)
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{
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struct hw_endpoint *ep = NULL;
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if (transfer_type == TUSB_XFER_INTERRUPT)
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{
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ep = _next_free_interrupt_ep();
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pico_info("Allocate interrupt ep %d\n", ep->interrupt_num);
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assert(ep);
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ep->buffer_control = &usbh_dpram->int_ep_buffer_ctrl[ep->interrupt_num].ctrl;
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ep->endpoint_control = &usbh_dpram->int_ep_ctrl[ep->interrupt_num].ctrl;
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// 0x180 for epx
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// 0x1c0 for intep0
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// 0x200 for intep1
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// etc
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ep->hw_data_buf = &usbh_dpram->epx_data[64 * (ep->interrupt_num + 1)];
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}
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else
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{
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ep = &epx;
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ep->buffer_control = &usbh_dpram->epx_buf_ctrl;
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ep->endpoint_control = &usbh_dpram->epx_ctrl;
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ep->hw_data_buf = &usbh_dpram->epx_data[0];
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}
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return ep;
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}
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static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t ep_addr, uint wMaxPacketSize, uint8_t transfer_type, uint8_t bmInterval)
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{
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// Already has data buffer, endpoint control, and buffer control allocated at this point
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assert(ep->endpoint_control);
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assert(ep->buffer_control);
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assert(ep->hw_data_buf);
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uint8_t num = tu_edpt_number(ep_addr);
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bool in = ep_addr & TUSB_DIR_IN_MASK;
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ep->ep_addr = ep_addr;
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ep->dev_addr = dev_addr;
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ep->in = in;
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// For host, IN to host == RX, anything else rx == false
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ep->rx = in == true;
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ep->num = num;
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// Response to a setup packet on EP0 starts with pid of 1
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ep->next_pid = num == 0 ? 1u : 0u;
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ep->wMaxPacketSize = wMaxPacketSize;
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ep->transfer_type = transfer_type;
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pico_trace("hw_endpoint_init dev %d ep %d %s xfer %d\n", ep->dev_addr, ep->num, ep_dir_string[ep->in], ep->transfer_type);
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pico_trace("dev %d ep %d %s setup buffer @ 0x%p\n", ep->dev_addr, ep->num, ep_dir_string[ep->in], ep->hw_data_buf);
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uint dpram_offset = hw_data_offset(ep->hw_data_buf);
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// Bits 0-5 should be 0
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assert(!(dpram_offset & 0b111111));
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// Fill in endpoint control register with buffer offset
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uint32_t ep_reg = EP_CTRL_ENABLE_BITS
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| EP_CTRL_INTERRUPT_PER_BUFFER
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| (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB)
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| dpram_offset;
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ep_reg |= bmInterval ? (bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB : 0;
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*ep->endpoint_control = ep_reg;
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pico_trace("endpoint control (0x%p) <- 0x%x\n", ep->endpoint_control, ep_reg);
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ep->configured = true;
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if (bmInterval)
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{
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// This is an interrupt endpoint
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// so need to set up interrupt endpoint address control register with:
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// device address
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// endpoint number / direction
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// preamble
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uint32_t reg = dev_addr | (ep->num << USB_ADDR_ENDP1_ENDPOINT_LSB);
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// Assert the interrupt endpoint is IN_TO_HOST
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assert(ep->in);
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if (need_pre(dev_addr))
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{
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reg |= USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS;
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}
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usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = reg;
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// Finally, enable interrupt that endpoint
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usb_hw_set->int_ep_ctrl = 1 << (ep->interrupt_num + 1);
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// If it's an interrupt endpoint we need to set up the buffer control
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// register
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}
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}
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static void hw_endpoint_init(uint8_t dev_addr, const tusb_desc_endpoint_t *ep_desc)
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{
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// Allocated differently based on if it's an interrupt endpoint or not
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struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
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_hw_endpoint_init(ep,
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dev_addr,
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ep_desc->bEndpointAddress,
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ep_desc->wMaxPacketSize.size,
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ep_desc->bmAttributes.xfer,
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ep_desc->bInterval);
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// Map this struct to ep@device address
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set_dev_ep(dev_addr, ep_desc->bEndpointAddress, ep);
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}
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//--------------------------------------------------------------------+
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// HCD API
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//--------------------------------------------------------------------+
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bool hcd_init(void)
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{
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pico_trace("hcd_init\n");
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// Reset any previous state
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rp2040_usb_init();
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irq_set_exclusive_handler(USBCTRL_IRQ, hcd_rp2040_irq);
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// clear epx and interrupt eps
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memset(&eps, 0, sizeof(eps));
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// Enable in host mode with SOF / Keep alive on
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usb_hw->main_ctrl = USB_MAIN_CTRL_CONTROLLER_EN_BITS | USB_MAIN_CTRL_HOST_NDEVICE_BITS;
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usb_hw->sie_ctrl = sie_ctrl_base;
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usb_hw->inte = USB_INTE_BUFF_STATUS_BITS |
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USB_INTE_HOST_CONN_DIS_BITS |
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USB_INTE_HOST_RESUME_BITS |
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USB_INTE_STALL_BITS |
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USB_INTE_TRANS_COMPLETE_BITS |
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USB_INTE_ERROR_RX_TIMEOUT_BITS |
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USB_INTE_ERROR_DATA_SEQ_BITS ;
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return true;
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}
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void hcd_port_reset(uint8_t rhport)
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{
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pico_trace("hcd_port_reset\n");
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assert(rhport == 0);
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// TODO: Nothing to do here yet. Perhaps need to reset some state?
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}
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bool hcd_port_connect_status(uint8_t rhport)
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{
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pico_trace("hcd_port_connect_status\n");
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assert(rhport == 0);
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return usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS;
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}
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tusb_speed_t hcd_port_speed_get(uint8_t rhport)
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{
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pico_trace("hcd_port_speed_get\n");
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assert(rhport == 0);
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// TODO: Should enumval this register
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switch (dev_speed())
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{
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case 1:
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return TUSB_SPEED_LOW;
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case 2:
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return TUSB_SPEED_FULL;
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default:
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panic("Invalid speed\n");
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}
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}
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// Close all opened endpoint belong to this device
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void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
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{
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pico_trace("hcd_device_close %d\n", dev_addr);
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}
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void hcd_int_enable(uint8_t rhport)
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{
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assert(rhport == 0);
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irq_set_enabled(USBCTRL_IRQ, true);
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}
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void hcd_int_disable(uint8_t rhport)
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{
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// todo we should check this is disabling from the correct core; note currently this is never called
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assert(rhport == 0);
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irq_set_enabled(USBCTRL_IRQ, false);
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}
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bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
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{
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pico_info("hcd_edpt_xfer dev_addr %d, ep_addr 0x%x, len %d\n", dev_addr, ep_addr, buflen);
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// Get appropriate ep. Either EPX or interrupt endpoint
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struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
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if (ep_addr != ep->ep_addr)
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{
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// Direction has flipped so re init it but with same properties
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_hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, ep->transfer_type, 0);
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}
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// True indicates this is the start of the transfer
|
||||
_hw_endpoint_xfer(ep, buffer, buflen, true);
|
||||
|
||||
// If a normal transfer (non-interrupt) then initiate using
|
||||
// sie ctrl registers. Otherwise interrupt ep registers should
|
||||
// already be configured
|
||||
if (ep == &epx) {
|
||||
// That has set up buffer control, endpoint control etc
|
||||
// for host we have to initiate the transfer
|
||||
usb_hw->dev_addr_ctrl = dev_addr | ep->num << USB_ADDR_ENDP_ENDPOINT_LSB;
|
||||
uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | sie_ctrl_base;
|
||||
flags |= ep->rx ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS;
|
||||
// Set pre if we are a low speed device on full speed hub
|
||||
flags |= need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0;
|
||||
usb_hw->sie_ctrl = flags;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
|
||||
{
|
||||
pico_info("hcd_setup_send dev_addr %d\n", dev_addr);
|
||||
|
||||
// Copy data into setup packet buffer
|
||||
memcpy((void*)&usbh_dpram->setup_packet[0], setup_packet, 8);
|
||||
|
||||
// Configure EP0 struct with setup info for the trans complete
|
||||
struct hw_endpoint *ep = _hw_endpoint_allocate(0);
|
||||
// EP0 out
|
||||
_hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0);
|
||||
assert(ep->configured);
|
||||
assert(ep->num == 0 && !ep->in);
|
||||
ep->total_len = 8;
|
||||
ep->transfer_size = 8;
|
||||
ep->active = true;
|
||||
ep->sent_setup = true;
|
||||
|
||||
// Set device address
|
||||
usb_hw->dev_addr_ctrl = dev_addr;
|
||||
// Set pre if we are a low speed device on full speed hub
|
||||
uint32_t flags = sie_ctrl_base | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS;
|
||||
flags |= need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0;
|
||||
usb_hw->sie_ctrl = flags;
|
||||
return true;
|
||||
}
|
||||
|
||||
uint32_t hcd_uframe_number(uint8_t rhport)
|
||||
{
|
||||
// Microframe number is (125us) but we are max full speed so return miliseconds * 8
|
||||
return usb_hw->sof_rd * 8;
|
||||
}
|
||||
|
||||
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
|
||||
{
|
||||
pico_trace("hcd_edpt_open dev_addr %d, ep_addr %d\n", dev_addr, ep_desc->bEndpointAddress);
|
||||
hw_endpoint_init(dev_addr, ep_desc);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
|
||||
{
|
||||
// EPX is shared, so multiple device addresses and endpoint addresses share that
|
||||
// so if any transfer is active on epx, we are busy. Interrupt endpoints have their own
|
||||
// EPX so ep->active will only be busy if there is a pending transfer on that interrupt endpoint
|
||||
// on that device
|
||||
pico_trace("hcd_edpt_busy dev addr %d ep_addr 0x%x\n", dev_addr, ep_addr);
|
||||
struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
|
||||
assert(ep);
|
||||
bool busy = ep->active;
|
||||
pico_trace("busy == %d\n", busy);
|
||||
return busy;
|
||||
}
|
||||
|
||||
bool hcd_edpt_stalled(uint8_t dev_addr, uint8_t ep_addr)
|
||||
{
|
||||
panic("hcd_pipe_stalled");
|
||||
}
|
||||
|
||||
bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
|
||||
{
|
||||
panic("hcd_clear_stall");
|
||||
return true;
|
||||
}
|
||||
|
||||
bool hcd_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete)
|
||||
{
|
||||
pico_trace("hcd_pipe_xfer dev_addr %d, ep_addr 0x%x, total_bytes %d, int_on_complete %d\n",
|
||||
dev_addr, ep_addr, total_bytes, int_on_complete);
|
||||
|
||||
// Same logic as hcd_edpt_xfer as far as I am concerned
|
||||
hcd_edpt_xfer(0, dev_addr, ep_addr, buffer, total_bytes);
|
||||
|
||||
return true;
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user