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refractor ehci_data_t

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separate tests for pipe open & pipe xfer
This commit is contained in:
hathach
2013-03-06 14:25:26 +07:00
parent 97a4a41b82
commit ef1cef5019
4 changed files with 215 additions and 92 deletions
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tinyusb/host/ehci/ehci.c
+3 -3
View File
@@ -101,13 +101,13 @@ STATIC_ INLINE_ uint8_t hostid_to_data_idx(uint8_t hostid)
STATIC_ INLINE_ ehci_qhd_t* const get_async_head(uint8_t hostid) ATTR_ALWAYS_INLINE ATTR_PURE ATTR_WARN_UNUSED_RESULT;
STATIC_ INLINE_ ehci_qhd_t* const get_async_head(uint8_t hostid)
{
return &ehci_data.controller.async_head[hostid_to_data_idx(hostid)];
return &ehci_data.async_head[ hostid_to_data_idx(hostid) ];
}
STATIC_ INLINE_ ehci_qhd_t* const get_period_head(uint8_t hostid) ATTR_ALWAYS_INLINE ATTR_PURE ATTR_WARN_UNUSED_RESULT;
STATIC_ INLINE_ ehci_qhd_t* const get_period_head(uint8_t hostid)
{
return &ehci_data.controller.period_head[hostid_to_data_idx(hostid)];
return &ehci_data.period_head[ hostid_to_data_idx(hostid) ];
}
tusb_error_t hcd_controller_init(uint8_t hostid) ATTR_WARN_UNUSED_RESULT;
@@ -337,7 +337,7 @@ static inline ehci_qhd_t* const get_control_qhd(uint8_t dev_addr)
static inline ehci_qtd_t* get_control_qtds(uint8_t dev_addr)
{
return (dev_addr == 0) ?
ehci_data.controller.addr0_qtd :
ehci_data.addr0.qtd :
ehci_data.device[ dev_addr ].control.qtd;
}
tinyusb/host/ehci/ehci.h
+13 -7
View File
@@ -435,21 +435,27 @@ typedef volatile struct {
// EHCI Data Organization
//--------------------------------------------------------------------+
typedef struct {
//------------- Static Async/Period List Head, Each for one controller -------------//
ehci_qhd_t async_head[CONTROLLER_HOST_NUMBER]; /// head qhd of async list, also is used as control endpoint for address 0
ehci_qhd_t period_head[CONTROLLER_HOST_NUMBER];
//------------- Data for Address 0 -------------//
struct {
// qhd: addr0 use async head (dummy) as Queue Head
ehci_qtd_t qtd[3];
tusb_std_request_t request;
} addr0;
struct {
ehci_qhd_t async_head[CONTROLLER_HOST_NUMBER]; /// head qhd of async list, also is used as control endpoint for address 0
ehci_qhd_t period_head[CONTROLLER_HOST_NUMBER];
ehci_qtd_t addr0_qtd[3];
}controller; ///< Static Interrupt Queue Head
struct {
// ehci_itd_t itd[EHCI_MAX_ITD] ; ///< Iso Transfer Pool
struct {
ehci_qhd_t qhd;
ehci_qtd_t qtd[3];
tusb_std_request_t request;
}control;
ehci_qhd_t qhd[EHCI_MAX_QHD] ; ///< Queue Head Pool
ehci_qtd_t qtd[EHCI_MAX_QTD] ; ///< Queue Element Transfer Pool
// ehci_itd_t itd[EHCI_MAX_ITD] ; ///< Iso Transfer Pool
// ehci_sitd_t sitd[EHCI_MAX_SITD] ; ///< Split (FS) Isochronous Transfer Pool
}device[TUSB_CFG_HOST_DEVICE_MAX];