cleanup SUBTASK macros
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@@ -378,11 +378,11 @@ void dcd_pipe_control_stall(uint8_t coreid)
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sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+0, 1, SIE_SET_ENDPOINT_STALLED_MASK | SIE_SET_ENDPOINT_CONDITION_STALLED_MASK);
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}
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tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
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bool dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
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{
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(void) coreid;
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ASSERT( !(length != 0 && p_buffer == NULL), TUSB_ERROR_INVALID_PARA);
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VERIFY( !(length != 0 && p_buffer == NULL) );
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// determine Endpoint where Data & Status phase occurred (IN or OUT)
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uint8_t const ep_data = (dir == TUSB_DIR_DEV_TO_HOST) ? 1 : 0;
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@@ -397,16 +397,16 @@ tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, uint8_t
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dcd_data.control_dma.remaining_bytes = length;
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// lpc17xx already received the first DATA OUT packet by now
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ASSERT_STATUS ( pipe_control_xfer(ep_data, p_buffer, length) );
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VERIFY_STATUS ( pipe_control_xfer(ep_data, p_buffer, length), false );
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}
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//------------- Status Phase (opposite direct to Data) -------------//
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if (dir == TUSB_DIR_HOST_TO_DEV)
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{ // only write for CONTROL OUT, CONTROL IN data will be retrieved in dcd_isr // TODO ????
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ASSERT_STATUS ( pipe_control_write(NULL, 0) );
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VERIFY_STATUS ( pipe_control_write(NULL, 0), false );
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}
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return TUSB_ERROR_NONE;
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return true;
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}
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//--------------------------------------------------------------------+
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