c557bf7b2e
Implement dynamic FIFO RAM allocation according to configuration desc.
2020-08-03 19:48:05 +02:00
acde49ccc9
enable pull-up in dcd_init() instead of usbd
2020-08-01 20:14:58 +07:00
c3b0389f10
Fix synopsys size check for ISO endpoint
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Constraint was incorrect for ISO endpoint as stated in TODO.
2020-07-31 15:52:21 +02:00
10a8ef7614
fix nested extern declaration of 'SystemCoreClock' [-Werror=nested-externs]
2020-07-29 17:04:47 +07:00
01903a4a6d
Implement dynamic reallocation of RX and TX fifos for EP0.
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Tested with EP0 size 8/16/32/64.
2020-07-27 21:03:20 +02:00
5e3f90cd6e
add 'set_EP0_max_pkt_size(...)' and fix EP0 size to 64 bytes after reset
2020-07-26 19:21:30 +02:00
0fd074afd8
change REDUCE_SPEED=0/1 to explicitly SPEED=high/full
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update readme, boards.md to add link to new stm boards
2020-07-08 16:29:48 +07:00
a192d99bf0
Merge pull request #457 from UweBonnes/add-stm-hs
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Add stm hs
2020-07-05 14:07:08 +07:00
fd38178189
STM32/OTG_HS: Allow OTG_HS port to run at FS speed.
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Add "REDUCE_SPEED=1" to the compile options.
2020-07-03 10:52:57 +02:00
ad5ae8c31d
update per review
2020-07-03 14:50:39 +07:00
a09a86d299
fix NVIC disable typo
2020-07-03 01:19:02 +07:00
4cec866994
correct HSE_VALUE in hal_conf
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- although it is define in CFLAGS, it is worth to correct to be
consistent with other build
- extract set_speed()
2020-07-02 14:57:00 +07:00
9a290febcd
change default port some stm bsp
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- f769disco default port is highspeed port1
- remove PORT0 on stlink since the board only populated HS connector
2020-07-02 11:58:40 +07:00
4966fb2e13
clean up
2020-07-02 01:25:21 +07:00
c2289777f7
Merge branch 'add-stm-hs' of github.com:hathach/tinyusb into add-stm-hs
2020-07-01 23:53:33 +07:00
196bdbc702
st/synopsys/dcd_synopsys.c: Remove USBC PHY PLL stabilization delay for now
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While the ST code has a 2 ms stabilization delay for the USBC PHY PLL,
running without this delay showed no problem for at leat 10 USB un/replug
cycles. Observe for problems!
2020-07-01 14:45:07 +02:00
d2450abaaf
only set turnaround in reset complete
2020-07-01 18:51:04 +07:00
e3974d6869
correctly set turn around according to cpu clock
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help to run with low speed mcu
2020-07-01 18:44:52 +07:00
a512a31c9d
Merge branch 'master' into add-stm-hs
2020-07-01 17:58:02 +07:00
ed1b670c55
clean up code
2020-07-01 17:57:37 +07:00
378e6aab8c
Clear ep0_pending if rx short packet
2020-06-30 17:56:25 +02:00
9e35ef73f7
Fix receiving of short packet data (ep out)
2020-06-30 12:55:39 +02:00
30a18e2605
stm32f723disco: USB HS enumerates.
2020-06-30 11:07:53 +02:00
05bfd9ac4a
dcd_synopsys: Handle HS and FS IP in one device
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FIXME: Allow run-time selection to allow to handle both HS and FS with
one file
F746 HS port enumerates with error
config 1 interface 2 altsetting 0 bulk endpoint 0x3 has invalid maxpacket 64
2020-06-30 11:02:41 +02:00
ab75998316
Merge branch 'master' into add-stm-hs
2020-06-30 01:55:57 +07:00
268ab9eaa8
Merge pull request #399 from duempel/redesign_synopsys_receive
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Improvements to Synopsys EP OUT
2020-06-29 16:02:40 +07:00
99df7789a7
Add author name to dcd_synopsys.c
2020-06-29 10:55:03 +02:00
4f69bcea7e
Remove EP0 remaining bytes manipulation
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Renaming edpt_xact to edpt_schedule_packets
2020-06-26 17:18:25 +02:00
067287ef91
Add transaction (edpt_xact) as sub transfer
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A transfer can have one or multiple transactions.
Usually only EP0 splits one xfer into multiple xact.
2020-06-18 17:18:28 +02:00
9ffb9b69a4
Disable SOF in dcd_stm32_fsdev
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Signed-off-by: Mengsk <admin@hifiphile.com >
2020-06-18 14:18:00 +02:00
57b553e023
Fix IAR warnings.
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Pa039 : use of address of unaligned structure member.
Pe188: enumerated type mixed with another type.
2020-06-17 10:08:33 +02:00
667eaa6dd6
fix stm32h743 priority with freeRTOS
2020-06-16 00:03:52 +07:00
2dd1be13e5
Enhance EP FIFO allocation for both Fullspeed and Highspeed
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- Update shared RX FIFO calculation with FS/HS
- IN FIFO EP
- Interrupt -> use EPSize
- Bulk/ISO -> use max(EPSize, remaining-fifo / non-opened-EPIN)
2020-06-15 23:17:49 +07:00
4399dd1b06
cherry pick PR399 commit : Interrupt time improvements
2020-06-14 19:13:31 +07:00
f438aedccb
overwrite setup packet
2020-06-14 18:29:38 +07:00
710c54f8cb
allow hs ep open with 512 bytes
2020-06-01 01:36:09 +07:00
f771afe6af
fixed EP0 size to 64 since LS is not supported in device mode
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- set turn-around and report actual speed in Enum Done
- add dcd_event_bus_reset() helper to report speed
2020-05-31 23:43:29 +07:00
5ffba8536d
able to detect as hs
2020-05-31 19:41:22 +07:00
d4bf777c94
try to get synopsys work with OTG HS + external PHY
2020-05-27 11:01:33 +07:00
947c3eb10d
multiple port support for global otg base
2020-05-26 16:07:48 +07:00
b7ab60aa44
suporting multiple port (OTG FS + HS) for stm32
2020-05-26 15:52:02 +07:00
42edbc0006
Allow EP0 to use xfer sizes larger than one packet
2020-05-15 22:26:14 +02:00
28696de390
Interrupt time improvements
2020-05-15 18:21:44 +02:00
3401e0f6ff
Synopsys OUT EP improvements:
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- Use register based XFRSIZ to determine transfer complete
(xfer->queued_len and xfer->short_packet were deleted)
- Pop out as many RxFIFO data entries as available within a IRQ call
- less application interruption due to XFRC calls
2020-05-08 18:10:48 +02:00
fd69cc3dcc
clean up
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renaming function and variables
changing indent size
2020-05-04 07:59:13 +02:00
59ff208c65
Changed switch into if statements
2020-04-29 12:37:29 +02:00
3e6feb7f6d
Redesign of Synopsys device transmission
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Changes:
- checking if tx buffer empty interrupt is masked
- process more than one packet in isr
- mask tx buffer empty just after all bytes were written
- use of transmit_fifo_packet instead of transmit_packet
2020-04-29 11:32:22 +02:00
958b5510cb
added comment for hw clearing TXFE
2020-04-27 13:17:47 +07:00
e785b09118
TXFE is read only bit
2020-04-27 12:06:14 +07:00
8d18d6077b
turn off TX FIFO Empty for EPIN if all bytes are written
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fix dcd synopsys issue with usbnet #289
2020-04-26 22:14:59 +07:00
Reinhard Panhuber